JP2011197023A - Reticle layout generating method, program and reticle layout generating device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a reticle layout generating method for increasing the effective number of chips.SOLUTION: A design support device creates, when patterns of a plurality of chips are formed in a shot area 42 of one reticle, a wafer map 23 on the basis of the shot area 42. Then, an ineffective area 43 outside a wafer effective area 52 is extracted from the shot area 42 of the wafer map 23, and the chips are arranged according to distribution of the ineffective area 43 to the shot area 42 to create a reticle layout and the wafer map 23.

Description

  The present invention relates to a reticle layout generation method, a program, and a reticle layout generation apparatus.

  In the manufacture of semiconductor devices, for example, a reticle (photomask) is used to form figures (patterns) such as elements and wirings on a substrate such as silicon. The reticle includes a substrate on which an IC (chip) pattern is formed. The pattern formed on the reticle is projected onto a substrate (for example, a wafer) on which a semiconductor device is formed by an exposure apparatus (for example, a stepper). A plurality of one type of chips are formed on one wafer.

  In the manufacturing process, the outer peripheral edge of the wafer is likely to come into contact with the wafer transfer device or dust generated in the manufacturing process adheres, and the yield tends to be lower than the central portion of the wafer. For this reason, a circular effective area is set for the wafer, and chips are formed in the effective area.

  In the manufacturing process, in order to increase production efficiency, it is preferable to arrange as many chips as possible in the effective area. For this reason, a shot area for exposing a chip pattern is set so that the number of chips included in the area is maximized (see, for example, Patent Documents 1 and 2).

  However, in the conventional method, the number of chips that can be shipped (effective number) manufactured from one wafer is determined according to the number of shot areas in the effective area. ) There were less cases. In such a case, it is necessary to separately specify the number of wafers to be input into the manufacturing process.

JP-A-5-217834 JP 2004-157327 A

  Unlike general mass-produced products, when manufacturing low-volume chips with different chip types in terms of device characteristics and chip size, etc., it depends on how many chips of different chip types on the reticle are placed on the wafer. The number of inserted wafers may change.

  According to one aspect of the present invention, there is provided a reticle layout generation method in which a design support apparatus generates a reticle layout in which a plurality of types of chip patterns are arranged on a single reticle that describes a pattern on a substrate on which chips are formed. Generating a map indicating the position of the shot area relative to the substrate based on the shot area of the reticle and the effective area of the substrate; and from the map, the effective area of the substrate or the ineffective area of the shot area A region extracting step of extracting a region; and a first layout processing step of generating reticle layout data by arranging each chip in accordance with the distribution information of the extracted region and the type of the chip.

  According to one aspect of the present invention, the effective number of chips can be increased.

It is a schematic block diagram of a design support apparatus. It is explanatory drawing of chip data. It is a flowchart of a layout data creation process. (A) (b) is explanatory drawing of shot size. It is explanatory drawing of a wafer map creation process. It is explanatory drawing of a multichip. (A) and (b) are explanatory drawings of invalid area distribution information. It is explanatory drawing of multiple invalid area | region overlap. It is explanatory drawing of the superimposition of a shot area | region and an invalid area | region distribution. It is explanatory drawing of layout examination. It is a yield expectation figure. It is explanatory drawing of yield determination. It is explanatory drawing of a yield area | region. It is explanatory drawing of layout examination. It is explanatory drawing of the wafer map after offset. It is explanatory drawing of chip data. It is explanatory drawing of shot size calculation. It is explanatory drawing of the superimposition of a shot area | region and an invalid area | region distribution. It is explanatory drawing of layout examination. It is explanatory drawing of layout examination. It is explanatory drawing of a multilayer reticle. It is explanatory drawing of the superimposition of a shot area | region and an invalid area | region distribution. It is explanatory drawing of layout examination. It is explanatory drawing of yield determination.

Hereinafter, an embodiment will be described.
As shown in FIG. 1, the design support device 11 functions as a data creation device for creating reticle layout data used for exposing a pattern of a manufacturing object on a substrate. The substrate is a material capable of manufacturing a manufacturing object (for example, a device) by forming a pattern formed on the reticle, and is, for example, a wafer or a glass plate.

  The design support device 11 is, for example, a general design support device (CAD: Computer Aided Design), a central processing unit (hereinafter referred to as CPU) 12, a memory 13, a storage device 14, a display device 15, an input device 16, The drive unit 17 is connected to each other via a bus 18.

  The CPU 12 executes a program using the memory 13 and realizes necessary processing such as layout design of the semiconductor device. The program is for causing the CPU 12 to function as various means as a design support apparatus that generates drawing data. The memory 13 stores programs and data necessary for providing various processes. The memory 13 usually includes a cache memory, a system memory, and a display memory.

  The display device 15 is used for displaying a pattern display, a parameter input screen, and the like, and for this, a CRT, LCD, PDP or the like is used. The input device 16 is used for inputting requests, instructions, patterns, and parameters from the user, and for this, a keyboard and a mouse device (not shown) are used.

The design support device 11 can also cause the display device 15 to display a pattern (figure) formed on the semiconductor device based on the layout data, a reticle pattern, a wafer map, and the like.
The storage device 14 usually includes a magnetic disk device, an optical disk device, and a magneto-optical disk device. The storage device 14 stores a file containing program data for designing a semiconductor device (semiconductor integrated circuit device). The CPU 12 transfers a program responding to an instruction from the input device 16 to the memory 13. Run it.

  In the design support apparatus 11, the storage device 14 stores files 21 to 27 shown in FIG. These files 21 to 27 store various data used for manufacturing the semiconductor device and various data created by the CPU 12 in each process shown in FIG. The data stored in the files 21 to 27 will be described later. The design support apparatus 11 reads data stored in the file of the storage device 14 and creates design data (for example, layout data) of the semiconductor device based on the data. Then, the design support apparatus 11 stores a file including the created data in the storage device 14.

  Program data executed by the CPU 12 is provided on the recording medium 19. The drive device 17 drives the recording medium 19 and accesses the stored contents. The CPU 12 reads program data from the recording medium 19 via the drive device 17 and installs it in the storage device 14.

  As the recording medium 19, any computer-readable recording such as magnetic tape (MT), memory card, flexible disk, optical disk (CD-ROM, DVD-ROM,...), Magneto-optical disk (MO, MD,...) Media can be used. The program and data described above can be stored in this recording medium 19 and loaded into the memory 13 for use as required.

  The recording medium 19 includes a medium and a disk device that record program data uploaded or downloaded via a communication medium. Furthermore, not only a recording medium that records a program that can be directly executed by a computer, but also a recording medium that records a program that can be executed once installed on another recording medium (such as a hard disk), or an encrypted program In addition, a recording medium on which a compressed program is recorded is also included.

  Next, data stored in the files 21 to 27 and processing executed by the design support apparatus 11 will be described. The data stored in each file will be described using the same reference numerals as the file.

  The file 21 shown in FIG. 3 stores the chip data 21 shown in FIG. The chip data 21 includes information on chips to be mounted on one reticle. This chip data information includes the chip name, the requested number of chips, and the chip size (X size and Y size). In the present embodiment, the size of the chip includes the size of an area (for example, a scribe area) necessary for manufacturing. The chip data 21 may include process conditions (for example, technology information such as line width) for each chip.

  In step 31 (reticle shot size calculation step), the design support apparatus 11 calculates a shot size necessary for exposing all the chips based on the chip size read from the chip data 21. For example, the design support apparatus 11 calculates the minimum shot size by arranging chips of the same size together. The design support apparatus 11 stores the calculated shot size in the file 22.

  In the case of the data shown in FIG. 2, since all the chips A to T have the same size, the design support apparatus 11 generates an initial layout in which all the chips are arranged in a matrix as shown in FIG. To do. Then, the design support apparatus 11 calculates the size of the rectangle including each chip A to T from the chip size of each chip A to T in the initial layout, and calculates the size of the rectangle as the shot size (SX = 20 mm, SY = 16 mm) and stored in the file 22. By this process, as shown in FIG. 4B, a shot region 42 in which patterns of a plurality of chips A to T are formed on the reticle 41 is determined.

  Next, in step 32 (wafer map creation process), the design support apparatus 11 creates a wafer map based on the size of the wafer, the size of the effective area of the wafer, and the shot size 22 described above. Store in file 23. The size of the wafer and the size of the wafer effective area are read from a file (not shown) or set by operating the input device 16 shown in FIG.

  As shown in FIG. 5, the size of the wafer 51 is set by, for example, a diameter (300 mm). The wafer effective area 52 is set, for example, by removing a portion set by a predetermined size (for example, 4.5 mm) from the wafer edge 51a. That is, the wafer effective area 52 is set as an inner portion of a circle having a radius smaller than the wafer size. FIG. 5 shows the size of the wafer, the wafer effective area 52, and the size of each of the shot area 42 and the area other than the wafer effective area 52 in order to facilitate understanding. The size, dimensions, ratio, etc. are not shown.

  An area outside the wafer effective area 52 and inside the edge 51a of the wafer 51 is an outer periphery of the substrate on which the holding claws or the like provided for handling the wafer 51 are arranged in the semiconductor device manufacturing process. This is a region where chips cannot be formed. In an exposure method in which the pattern of one chip is exposed on the wafer in one shot, if the shot area overlaps with the chip non-formation area, the chip formed by the shot area does not have a part of the pattern formed normally. Therefore, it is not counted as a valid chip. On the other hand, when using a reticle in which a plurality of chip patterns are formed in one shot area, among the chips included in the shot area, all the patterns of the chips exposed in the wafer effective area 52 are normal. Therefore, it is counted as an effective chip. That is, the effective number of chips increases.

  The design support apparatus 11 sets a circle for setting the wafer effective area 52 as an area boundary line 52a. Then, the design support apparatus 11 arranges the calculated shot region 42 on the entire surface of the wafer 51 along two predetermined axes (in the drawing, the X axis (horizontal direction) and the Y axis (vertical direction)). Thus, the wafer map 23 shown in FIG. 6 is generated.

  In creating this wafer map 23, the design support apparatus 11, as shown in FIG. 5, makes an end in a predetermined direction with respect to the region boundary line 52 a of the wafer effective region 52 (in the drawing, the minimum coordinate in the X-axis direction). A position (coordinate position) offset by a predetermined amount α in the axial direction from the point) is set as a reference position, and the shot area 42 is arranged from the reference position. The predetermined amount α is a value that is arbitrarily set according to the size of the wafer 51.

  The data of the wafer map 23 includes information on the wafer 51 (size, reference position (center coordinates)), information on the wafer effective area 52 (size, reference position), the size of the shot area 42 arranged, and a reference point of the shot area 42 ( For example, the coordinate value for arranging the lower left corner) is included. The design support apparatus 11 stores this data in the file 23 shown in FIG.

  Next, the design support apparatus 11 extracts an invalid area for the shot area 42 based on the wafer map 23 in step 33 (invalid area extraction step). The design support apparatus 11 divides the wafer 51 into four as shown in FIG. The invalid region is a portion that overlaps the region 51b between the region boundary line 52a and the wafer edge 51a in the arranged shot region 42, that is, a region that is not formed as a chip.

  The design support apparatus 11 extracts, as the invalid area 43 in each shot area 42, the area remaining after subtracting the wafer effective area 52 from the shot area 42 for each rectangular shot area 42. The information indicating the invalid area 43 (invalid area data) includes identification information and boundary information. The identification information is information for distinguishing the shot area 42 that does not include the invalid area 43 and the shot area 42 that includes the invalid area 43 from each other. When these shot areas are described separately, the shot area 42 that does not include the invalid area 43 is referred to as the entire effective shot area 42a, and the shot area 42 that includes the invalid area 43 is referred to as the partial effective shot area 42b.

  As the identification information, for example, a coordinate value of a reference point of the partial effective shot area 42b, a flag attached to each shot area 42, and the like are used. The boundary information is information divided into a portion where the shot area 42 and the wafer effective area 52 overlap (chip effective area) and a portion where the shot area 42 and the invalid area 43 overlap (chip invalid area). As the boundary information, for example, information (coordinate values or the like) representing a line segment (arc) included in the corresponding shot region 42 in the circular region boundary line 52a shown in FIG. 5 is used.

  The wafer map 23 shown in FIG. 6 is arranged so as to overlap the position information of all 50 effective shot areas 42a arranged in the wafer effective area 52 and the shot area 42 including the invalid area 43, that is, the area boundary line 52a. The positional information of the ten partial effective shot areas 42b that have been set is included.

  Next, the design support apparatus 11 stores the invalid area distribution map generated based on the invalid area 43 extracted in step 33 in the file 24 in step 34 (invalid area distribution map creation step). The design support apparatus 11 generates the invalid area distribution diagram 24 shown in FIG. 7A by superimposing the shot areas 42 including the invalid area 43 extracted in step 33 on each other. That is, the design support apparatus 11 arranges the extracted invalid area 43 in a rectangle having the same size (shot size) as that of one shot area 42. In this invalid area distribution diagram 24, the area indicated by hatching is the invalid area 43 extracted in each shot area 42. The design support apparatus 11 counts the number of invalid areas 43 that overlap each other in the shot area 42.

  FIG. 7B shows a line segment (arc) 52b included in the shot area 42b among the line segments forming the invalid area 43, that is, the area boundary line 52a shown in FIG. The design support apparatus 11 counts the number of invalid areas 43 that overlap each other for the partitioned areas a to x that divide the shot area 42 by each line segment. The count result is shown in FIG. In each partitioned area a to x, the number of invalid areas 43 in which the overlap number (count value) overlaps each other.

  Next, in step 35 (reticle layout review process: first layout process step), the design support apparatus 11 generates a reticle layout and a yield prediction map based on the invalid area distribution map 24, the shot size 22, and the chip data 21. Generate. Then, the design support apparatus 11 stores the reticle layout in the file 25 and stores the expected yield map in the file 26.

  For example, the design support apparatus 11 arranges in order from a chip with a small number of requests, from a partition area with a large number of overlaps to a partition area with a small number of overlaps. Specifically, as shown in FIG. 9, the design support apparatus 11 superimposes the invalid area distribution map 24 and the initial layout 25a. The initial layout 25a is information (data) indicating the position where the chip is arranged when calculating the shot size 22, that is, information (data) indicating the arrangement state shown in FIG. Next, the design support apparatus 11 pays attention to a partitioned area with a large number of overlapping areas to a partitioned area with a small number of overlapping areas. And the design support apparatus 11 arrange | positions a chip | tip with few request | requirements with respect to the partition area | region which paid its attention.

  The invalid area 43 is an edge side of the wafer 51 from the wafer effective area 52 (see FIG. 6) in the partial effective shot area 42b, and is an area where chips cannot be formed. Therefore, the number of chips formed by the wafer 51 is smaller than the number of times the reticle is shot with respect to the wafer 51 by the overlapping number of the partition regions overlapping with the chips. In other words, it is possible to increase the number of chips formed by the wafer 51 by disposing the chips in the partition region where the plurality of overlaps is small.

  Note that the design support apparatus 11 changes the chip arrangement so that the size of the shot area does not change, that is, the size of the shot area calculated in step 31 of FIG. 3 is maintained. For example, in the case of the chip data 21 shown in FIG. 2, the chip sizes of all the chips A to T are the same value. Therefore, the size of the shot area 42 does not change even if the chips are replaced.

  An example of the layout review processing result, that is, the reticle layout 25b is shown in FIG. In the reticle layout 25b, the chip T having the largest number of requests and the chips A, B, and C having the next largest number of requests are overlapped with the partitioned region i having the least number of overlaps (= 0).

  Then, the design support apparatus 11 creates a yield prediction diagram 26 shown in FIG. 11 based on the reticle layout 25b created by the above processing and the wafer map 23. In FIG. 11, for the partial effective shot area 42b, chips in the wafer effective area 52, that is, valid chips are shown, and invalid chips are not shown. Further, all the chips are omitted from the entire effective shot area 42a.

Next, the design support apparatus 11 determines whether or not the required number of chips is cleared in step 36 (first determination step).
Specifically, the design support apparatus 11 calculates the effective number of each chip A to T created from one wafer 51 based on the yield prediction diagram 26, and the effective number is a request for each chip A to T, respectively. Determine whether the number is greater than or equal to. Then, the design support apparatus 11 determines that the required number of chips has been cleared when the effective number is greater than or equal to the required number for all chips, and proceeds to step 40. On the other hand, when the effective number is less than the required number for at least one chip, the design support apparatus 11 determines that the required number of chips has not been cleared, and proceeds to step 37.

An example of calculating the effective number will be described.
As shown in FIG. 13, the design support apparatus 11 calculates the effective number of each chip A to T based on the yield areas 53 a to 53 c for the wafer 51. The setting data for the yield areas 53a to 53c is stored in a file (not shown).

  The yield areas 53a to 53c are areas indicating the range of yield in the wafer 51, and are set according to the ratio of the number of chips determined to be non-defective to the number of chips in the area. The yield areas 53a to 53c are set concentrically with respect to the center of the wafer 51, for example. For example, the yield ratios of the yield areas 53a to 53c are 99.9%, 99%, and 96%, respectively, and the yield ratio outside the range of the yield area 53c and within the range of the wafer effective area 52 is 89%. . Therefore, the wafer effective area 52 is set as a yield area 53d indicating a predetermined yield ratio.

  The design support apparatus 11 extracts chips included in the respective yield areas 53a to 53d based on the yield prediction diagram 26, and based on the number of extractions and the yield ratios of the respective yield areas 53a to 53d, the effectiveness of each chip is extracted. Calculate the number.

  For example, as shown in FIG. 12, the number of chips A included in each of the yield areas 53a to 53d is 4, 16, 19, and 19. In FIG. 12, the yield areas 53a to 53d are shown as a to d, respectively. For example, for chip A, the percentage of the yield area 53a is indicated as “a 99.9%”, and the number of chips in the yield area 53a is indicated as “a 4”.

The effective number of chips A is calculated by the sum of the multiplication results of the number of chips included in each of the areas 53a to 53d and the yield ratio of each of the areas 53a to 53d. In other words, the design support apparatus 11 has the following formula:
4 × 0.999 + 16 × 0.99 + 19 × 0.96 + 19 × 0.89 = 54.986
Thus, the effective number 54.986 of chip A is calculated.

  The effective number of chips A (= 54.986) is larger than the required number of chips A (= 50). Therefore, the design support apparatus 11 determines that the required number of chips is cleared (OK) for the chip A. Similarly, the design support apparatus 11 calculates the effective number for each of the chips B to T, compares the effective number with the required number, and determines each chip (see FIG. 12). Although not shown, it is determined that the chip number for which the valid number is smaller than the required number is not cleared (NG).

  Then, the design support apparatus 11 proceeds to step 40 when the effective number clears the required number of conditions for all chips (OK). On the other hand, the design support apparatus 11 proceeds to Step 37 when the effective number does not satisfy the requirement number requirement (NG) for at least one chip.

  Next, in step 37 (reticle layout review process: second layout process step), the design support apparatus 11 changes the chip arrangement position or invalid area for the reticle layout 25 so that the effective number of chips increases. The position of the distribution map 24 is relatively changed. In step 36, the design support apparatus 11 changes the relative position so that the chip determined to be NG is included in the partitioned area with a small number of overlaps.

  For example, in the reticle layout 25 shown in FIG. 10, it is assumed that the effective number of chips T is smaller than the required number. In this case, as illustrated in FIG. 14, the design support apparatus 11 shifts the shot area 42 and the invalid area distribution map 24 so that the chip T is included in the partitioned area i having the smallest overlapping number. For example, the design support apparatus 11 may arrange the apex of the chip T on the line segment based on the arrangement position and chip size of the chip T and the coordinate value of the line segment forming the partition region i. Calculate the shift amount.

  Then, when the arrangement position of the chip is changed, the design support apparatus 11 generates a reticle layout 25 corresponding thereto. In addition, the design support apparatus 11 changes the wafer map 23 based on the relative positions of the reticle layout 25 and the invalid area distribution diagram 24. That is, the design support apparatus 11 is based on the relative position difference between the reticle layout 25 and the invalid area distribution diagram 24, and the wafer map 23 in which the position of the shot area 42 shown in FIG. 11 is offset by the position difference (see FIG. 15). ) Is generated.

  In FIG. 15, a shot area indicated by a one-dot chain line (only an outline line including the shot area is shown) indicates a position of a shot area group before offset. That is, FIG. 3 shows a wafer map generated when the requested number of chips is cleared in step 38 of FIG. FIG. 15 shows the deviation between the shot area before offset (indicated by the alternate long and short dash line) and the shot area after offset (indicated by the solid line) in an easily understandable manner. This deviation amount (offset amount) is shown in FIG. It does not correspond to the offset amount shown. In FIG. 15, point O1 represents the center point of the wafer 51, point O2 represents the center point of the shot region group before offset, and point O3 represents the center point of the shot region group after offset.

  Next, in step 38 (second determination step), the design support apparatus 11 determines whether or not the effective number of all chips has cleared the requirement number condition, as in step 36. Then, the design support apparatus 11 proceeds to step 40 when the effective number clears the requirement number requirement (OK), and proceeds to step 40 when the effective number does not clear the requirement number requirement (NG). Migrate to

  Next, in step 39 (reticle layout process: third layout process step), the design support apparatus 11 changes the wafer size or sets the number of wafers to be input to the manufacturing process in order to satisfy the required number of chips. change. As a result of increasing the number of wafers, when the required number is satisfied regardless of the arrangement position of each chip, the design support apparatus 11 performs the reticle layout based on the arrangement standard of the file 27 and the created reticle layout data is stored in the file. 25. In the arrangement standard, dicing priority, chip density, and technology are set as elements. The design support apparatus 11 arranges chips according to at least one element.

  The dicing priority is to collect the chips of the same size and arrange them linearly so that the wafer 51 can be easily diced, do not generate a T-shaped branch by internal scribe, or arrange chips of the same scribe width. In the chip density, the chips are arranged so that the density distribution of each chip is uniform so that variations in reticle manufacturing accuracy do not occur. The technology is to uniformly arrange chips of the same technology so that the production specifications of the reticle can be leveled.

The design support apparatus 11 stores reticle layout data in which chips are arranged according to the above elements in the file 25.
Next, in step 40 (wafer map re-creation), the design support apparatus 11 generates final wafer map data based on the reticle layout data determined in steps 35, 37, and 39, and stores this data in the file 23. To do.

  As described above, when the patterns of the plurality of chips A to T are formed in the shot area 42 of one reticle 41, the wafer map 23 is created based on the shot area 42. Then, an invalid area 43 outside the wafer effective area 52 is extracted from the shot area 42 of the wafer map 23, and chips A to T are arranged according to the distribution of the invalid area 43 with respect to the shot area 42, and the reticle layout 25 and the wafer map 23. Was created. Therefore, since the chips formed in the shot area 42 (partial effective shot area 42b) overlapping the area boundary line 52a between the shot area 42 and the wafer effective area 52 can be validated, the effective number of each chip A to T is Can be increased. Further, by arranging the pattern of the chip having a large number of requests in a portion where the overlap of the invalid area 43 is small, the effective number of the chips having the large number of requests is increased, and the number of wafers to be processed can be reduced. .

Next, processing based on another chip data will be described.
As shown in FIG. 16, the chip data 21 includes the required number of chips A to T and the chip size (X, Y). In this example, chips of different sizes are included.

  The design support apparatus 11 calculates the shot size 22 based on the sizes of the chips A to T read from the chip data 21 (step 31 in FIG. 3). In the case of the chip data shown in FIG. 16, the chips A, B, F to L, and Q to S have the same size, the chips C to E have the same size, and the chips M to P have the same size. Therefore, the design support apparatus 11 calculates the minimum shot size 22 by collecting chips of the same size as shown in FIG. In this case, the design support apparatus 11 calculates the shot size 22 as SX = 20.4 mm and SY = 16 mm from the chip size shown in FIG.

  Next, the design support apparatus 11 creates a wafer map in which the shot area 42 is arranged based on the size of the wafer, the size of the effective area of the wafer, and the shot size 22 (FIG. 3, step 32).

Next, the design support apparatus 11 extracts the invalid area 43 in the shot area 42 (FIG. 3, step 33), and generates an invalid area distribution diagram 24 (FIG. 3, step 34).
Next, the design support apparatus 11 counts the number of invalid areas 43 that overlap each other in the partitioned area of the invalid area distribution map 24, and superimposes the invalid area distribution chart 24 and the shot area 42 as shown in FIG. The chips A to T are arranged as shown in FIG. 19 according to the overlapping number of the divided areas (FIG. 3, step 35).

Next, the design support apparatus 11 determines whether or not the required number of chips has been cleared (step 36 in FIG. 3).
Now, assume that chip C has not cleared the required number of chips. In this case, as shown in FIG. 20, the design support apparatus 11 changes the position of the chip or changes the position of the invalid area distribution map 24 relative to the reticle layout 25 so that the effective number of chips C increases. (Step 37 in FIG. 3). At this time, when at least a part of the chip T deviates from the partition region i, the arrangement position of the chip T may be shifted so that the overlapping number is included in the partition region i with the smallest number. This is because the area of the chip T is smaller than other chips and there is an empty area around the chip T.

Then, the design support apparatus 11 creates a wafer map according to the arrangement positions of the chips A to T and the shift amount (offset) between the shot area 42 and the invalid area distribution diagram.
As described above, the chips A to T are also created for the chips having different chip sizes by creating the reticle layout data and the wafer map 23 in which the chips A to T are arranged in the shot area 42 in the same manner as described above. The effective number of can be increased. Further, by arranging the pattern of the chip having a large number of requests in a portion where the overlap of the invalid area 43 is small, the effective number of the chips having the large number of requests is increased, and the number of wafers to be processed can be reduced. .

Next, processing for another reticle will be described.
As shown in FIG. 21, reticle 71 includes a plurality (four in the figure) of shot areas 71a to 71d. In each of the shot areas 71a to 71d, patterns for forming different layers in the plurality of chips A to L are formed. That is, the patterns A1 to L1 for the first layer formed in the chips A to L are formed in the first shot region 71a. Of the patterns formed on the chips A to L, a pattern for a second layer different from the first layer is formed in the second shot region 71b. Similarly, patterns for the third layer and the fourth layer are formed in the third and fourth shot regions 71c and 71d, respectively. Such a reticle 71 is called a multi-layer reticle. By forming a pattern of a plurality of layers on one reticle 71, the number of reticles used in the manufacturing process is reduced, which is advantageous in terms of cost and management.

  A reticle layout and a wafer map are created for one area (for example, the first shot area 71a) among the plurality of shot areas 71a to 71d in the same manner as described above. That is, the initial layout 25a in which the patterns A1 to L1 in one layer of the chips A to L are arranged is created.

  Next, a wafer map is created based on the shot area 71a. Next, an invalid area distribution map 24 (see FIG. 22) is created based on the invalid area extracted from the wafer map, and a reticle layout 25b is generated based on the invalid area distribution chart 24. In FIG. 24, for the sake of convenience, the same invalid area distribution diagram as that described above is used. Further, the layout is the same as the initial layout 25a shown in FIG. Further, in FIG. 22, the chip name is simply displayed in order to handle the chip unit for the arrangement.

  Next, as shown in FIG. 23, relative alignment of the reticle layout 25b and the invalid area distribution diagram 24 is performed so that a chip having a large number of requests (chip E in the figure) is within the area i (see FIG. 7B). Offset and create a yield forecast.

  Then, based on the yield prediction diagram, it is determined whether or not the required number of chips has been cleared. FIG. 24 shows a determination process for chips A to L (the chip names are indicated as A1 to L1 since the pattern is for one layer). Although not shown in the figure, the chips C1 to K1 are also determined OK.

As described above, when the number of valid chips is cleared for all the chips A1 to L1, a wafer map is created based on the reticle layout 25b.
As described above, the multi-layer reticle 71 can be processed in the same manner to increase the effective number of chips A to L. Further, by arranging the pattern of the chip having a large number of requests in a portion where the overlap of the invalid area 43 is small, the effective number of the chips having the large number of requests is increased, and the number of wafers to be processed can be reduced. .

As described above, according to the present embodiment, the following effects can be obtained.
(1) The design support apparatus 11 creates the wafer map 23 based on the shot area 42 when forming patterns of a plurality of chips A to T in the shot area 42 of one reticle 41. Then, an invalid area 43 outside the wafer effective area 52 is extracted from the shot area 42 of the wafer map 23, and chips A to T are arranged according to the distribution of the invalid area 43 with respect to the shot area 42, and the reticle layout 25 and the wafer map 23. Was created. Therefore, since the chips formed in the shot area 42 (partial effective shot area 42b) overlapping the area boundary line 52a between the shot area 42 and the wafer effective area 52 can be validated, the effective number of each chip A to T is Can be increased.

  (2) Based on the invalid area distribution diagram 24, the design support apparatus 11 arranges the pattern of the chip having a large number of requests in a portion where the overlapping of the invalid area 43 is small, so that the effective number of the chips having the large number of requests is obtained. It is possible to increase the number of chips with a large number of requests from one wafer. For this reason, the number of wafers to be processed can be reduced.

In addition, you may implement each said embodiment in the following aspects.
In step 35, the information necessary for placing chips and the order of placement may be changed as appropriate.

  For example, from the partition area with a small number of overlaps to the partition area with a large number of overlaps, the chips with the largest number of requests are arranged in order. Even with such an arrangement, it is possible to increase the effective number of chips having a large number of requests, that is, to reliably form chips having a large number of requests, and to reduce the number of wafers.

  Further, the arrangement order may be changed according to the area of the partition area. For example, the position where the number of chips formed by one wafer 51 is the largest, that is, the area of the partition region (region i in FIG. 7B) with the smallest number of overlaps, and the area of each chip are calculated. Then, when the area of the partition region is smaller than the minimum area of the chip, the chip is arranged from the outer periphery of the reticle according to the size of the chip. By arranging the chips in this way, the effective number of each chip can be increased, that is, a plurality of chips can be surely formed, by arranging according to the shape (size) of the chips having the same or similar required number. The number of requested chips can be cleared. As a result, the number of wafers can be reduced.

  On the other hand, when the area of the partition area is larger than the minimum area of the chip, the chip is arranged according to the size with the partition area as the center. By arranging the chips in this way, the effective number of each chip can be increased, that is, a plurality of chips can be surely formed, by arranging according to the shape (size) of the chips having the same or similar required number. The number of requested chips can be cleared. As a result, the number of wafers can be reduced.

  The chips may be arranged according to information other than the chip size, for example, information set according to the chip configuration. In the case of the same technology, a chip in which the area ratio of input / output circuits (I / O), power supply circuits, pads (PAD), etc. is larger than the area ratio of logic circuits, etc., has an I / O area ratio of logic circuits, etc. Compared with chips smaller than the area ratio, the yield rate is high. In addition, the yield rate of a chip mounted with a memory region such as a RAM decreases as the area ratio of the memory region increases. Note that the yield rate varies depending on the configuration of the memory area (for example, the presence or absence of a redundant circuit or an error correction circuit).

  Therefore, information indicating the configuration and type of the chip is stored in, for example, the file 21 of FIG. 3, and the yield rate is set or calculated according to the information read from the file, and the chips with the higher yield rate are sequentially ordered according to the yield rate. , From the partitioned area having a large number of overlaps to the partitioned area having a small number of overlaps. By this arrangement process, the number of chips formed from one wafer increases, so the effective number of each chip increases and the required number of chips can be cleared. As a result, the number of wafers can be reduced.

As a method for calculating the effective number in step 36, the number may be calculated for each yield area. That is, the effective number of chips A can be obtained by converting the multiplication result of each term into an integer in the above formula. For example, in the case of chip A shown in FIG. 10, since the number of chips in the yield area 53a shown in FIG. 13 is 4, the number of chips (= 4) is multiplied by the yield ratio (99.9%) of the yield area 53a. As a result, the effective number of chips A is 3. Similarly, the effective numbers in the yield areas 53b to 53d are 15, 18, and 16, respectively. Therefore, the effective number of chips A on the wafer 51 is
3 + 15 + 18 + 16 = 52
It becomes.

  In step 37, the amount by which the invalid area distribution map 24 is shifted with respect to the reticle layout 25 is calculated. On the other hand, the amount of deviation may be input from the outside. For example, the design support device 11 displays the arrangement result shown in FIG. 10 on the display device 15 in FIG. 1 and inputs a deviation amount based on the operation of the input device 16 by the operator (for example, the designer). Further, the design support apparatus 11 displays the arrangement result shown in FIG. 10 on the display device 15 in FIG. 1, and the operator operates the input device 16 to display the graphic displayed on the display device 15 on the display device 15. By moving it, the shift amount may be calculated based on the operation amount or the position of the displayed graphic.

  As the boundary information, a linear line segment may be used instead of the arc-shaped line segment 52b (see FIG. 7B). That is, two intersection points where the outline of the shot area 42 and the circular area boundary line 52a shown in FIG. 5 intersect may be calculated, and a straight line (line segment) connecting these intersection points may be used as boundary information. Thus, even if the invalid area distribution map 24 is created, the same effect as described above can be obtained.

-Arrange layout data of the same type of chip on one reticle according to the number of requests.
-Limit shot areas from which invalid areas are extracted. For example, the extraction of the invalid area for the shot area in which no chip can be formed is canceled according to the length of the boundary line of the shot area included in the wafer effective area and the size of the chip. Further, the ratio of the area of the area surrounded by the line segment included in the wafer effective area of the boundary lines of the shot area and the boundary line of the wafer effective area and the area of the shot area is a predetermined value (for example, 1: 4). ) Cancel invalid area extraction for the following shot areas. The predetermined value may be changed based on the size of the shot area and the size of the chip arranged in the shot area. Moreover, you may make it determine combining said conditions.

  In each of the above embodiments, the invalid area where the chip is invalid is extracted, and the chip is arranged based on the invalid area distribution map. On the other hand, an area where the chip is effective (effective area) may be extracted, and the chip may be arranged according to the distribution of the effective area with respect to the shot area. That is, the design support apparatus 11 extracts an effective area in the flowchart shown in FIG. 3 (step 33), and creates an effective area distribution map (step 34). Then, the layout of the chip on the reticle is examined based on the effective area distribution chart (step 35). As described above, by arranging the chips according to the effective area, it is possible to increase the effective number of chips as in the above-described embodiments, and to reduce the number of wafers to be processed.

The following notes are disclosed regarding the above embodiments.
(Appendix 1)
A reticle layout generation method for generating, by a design support apparatus, a reticle layout in which a plurality of types of chip patterns are arranged on a single reticle that describes a pattern on a substrate on which a chip is formed,
A map creating step for generating a map indicating a position of the shot area with respect to the substrate based on a shot area of the reticle and an effective area of the substrate;
An area extraction step for extracting an effective area or an invalid area in the shot area from the map,
A first layout processing step of generating reticle layout data by arranging each chip in accordance with the distribution information of the extracted region and the type of the chip;
A reticle layout generation method including:
(Appendix 2)
Including an area distribution map creating step of generating an area distribution map by arranging the areas so that the shot areas including the extracted areas overlap with each other;
2. The reticle layout generation method according to appendix 1, wherein the number of overlapping regions is counted based on the region distribution chart, the count value is used as distribution information, and chips are arranged according to the distribution information.
(Appendix 3)
The type of the chip is set by at least the number of requested chips being different,
The reticle layout generation method according to appendix 1 or 2, wherein, in the first layout processing step, each chip is arranged according to the distribution information and the required number of each chip.
(Appendix 4)
A shot size that reads the sizes of multiple types of chips that place a pattern on a single reticle from chip data, and calculates the minimum shot size required to expose all chips based on the size of each chip The reticle layout generation method according to any one of appendices 1 to 3, further comprising a calculation step.
(Appendix 5)
The chip data includes the number of requests for each chip,
A first yield prediction map is generated based on the generated reticle layout and wafer map, and an effective number of chips in one wafer is calculated based on the yield prediction map, and the effective number of each chip and the request are calculated. 5. The method according to claim 1, further comprising a first determination step of comparing the number with a number to determine whether the reticle layout has cleared a required number of chips. Reticle layout generation method.
(Appendix 6)
In the first determination step, when it is determined that the required number of chips has not been cleared, the invalid area distribution map and the shot area are relative to each other based on the invalid area distribution map and the chip size. And a second layout processing step of generating a reticle layout in accordance with the offset amount to be shifted and generating a second yield prediction diagram in which the shot area for the wafer is shifted in accordance with the offset amount. 6. The reticle layout generation method according to 5.
(Appendix 7)
In the second layout processing step, among the plurality of types of chips, the arrangement position of the chip having a small area is changed according to the position of the invalid area distribution diagram and the shot area which are relatively shifted, The reticle layout generation method according to appendix 6, which is a feature.
(Appendix 8)
A second determination step of determining whether or not the reticle layout generated by the second layout processing step has cleared the required number of chips;
A third layout processing step of generating a reticle layout in which a plurality of types of chips are arranged according to the arrangement standard when it is determined in the second determination step that the required number of chips has not been cleared;
The reticle layout generation method according to appendix 6 or 7, characterized by comprising:
(Appendix 9)
In the first layout processing step, the area of the high yield area is compared with the area of the minimum chip to be arranged in the shot area based on the invalid area distribution map, and according to the comparison result, 9. The reticle layout generation method according to any one of appendices 1 to 8, wherein a chip is arranged.
(Appendix 10)
The reticle according to any one of appendices 1 to 9, wherein in the first layout processing step, the arrangement is examined in an order corresponding to device characteristics of each chip arranged in the shot region. Layout generation method.
(Appendix 11)
A program executed by an apparatus for generating a reticle layout in which a plurality of types of chip patterns are arranged on a single reticle that describes a pattern on a substrate on which chips are formed,
Generating a map indicating the position of the shot area relative to the substrate based on the shot area of the reticle and the effective area of the substrate;
Extracting an effective area or an invalid area in the shot area from the map;
A step of generating reticle layout data by arranging each chip according to the distribution information of the extracted region and the type of the chip;
Including programs.
(Appendix 12)
A reticle layout generation apparatus for generating a reticle layout in which a plurality of types of chip patterns are arranged on a single reticle that describes a pattern on a substrate on which chips are formed,
Generating a map indicating the position of the shot area relative to the substrate based on the shot area of the reticle and the effective area of the substrate;
Extracting an effective area or an invalid area in the shot area from the map;
A step of generating reticle layout data by arranging each chip according to the distribution information of the extracted region and the type of the chip;
A reticle layout generation device for executing

21 Chip data 22 Shot size 23 Wafer map 24 Invalid area distribution chart 25 Reticle layout 26 Yield prediction chart 27 Placement reference 41 Reticle 42 Shot area 43 Invalid area 51 Wafer 52 Wafer effective area 52a Area boundary line A to T chips

Claims (5)

A reticle layout generation method for generating, by a design support apparatus, a reticle layout in which a plurality of types of chip patterns are arranged on a single reticle that describes a pattern on a substrate on which a chip is formed,
A map creating step for generating a map indicating a position of the shot area with respect to the substrate based on a shot area of the reticle and an effective area of the substrate;
An area extraction step for extracting an effective area or an invalid area in the shot area from the map,
A first layout processing step of generating reticle layout data by arranging each chip in accordance with the distribution information of the extracted region and the type of the chip;
A reticle layout generation method including: Including an area distribution map creating step of generating an area distribution map by arranging the areas so that the shot areas including the extracted areas overlap with each other;
2. The reticle layout generation method according to claim 1, wherein the number of overlapping areas is counted based on the area distribution chart, the count value is used as distribution information, and chips are arranged according to the distribution information. The type of the chip is set by at least the number of requested chips being different,
3. The reticle layout generation method according to claim 1, wherein, in the first layout processing step, each chip is arranged according to the distribution information and the required number of each chip. A program executed by an apparatus for generating a reticle layout in which a plurality of types of chip patterns are arranged on a single reticle that describes a pattern on a substrate on which chips are formed,
Generating a map indicating the position of the shot area relative to the substrate based on the shot area of the reticle and the effective area of the substrate;
Extracting an effective area or an invalid area in the shot area from the map;
A step of generating reticle layout data by arranging each chip according to the distribution information of the extracted region and the type of the chip;
Including programs. A reticle layout generation apparatus for generating a reticle layout in which a plurality of types of chip patterns are arranged on a single reticle that describes a pattern on a substrate on which chips are formed,
Generating a map indicating the position of the shot area relative to the substrate based on the shot area of the reticle and the effective area of the substrate;
Extracting an effective area or an invalid area in the shot area from the map;
A step of generating reticle layout data by arranging each chip according to the distribution information of the extracted region and the type of the chip;
A reticle layout generation device for executing

Images