JP2014182829A5 - - Google Patents

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Publication number
JP2014182829A5
JP2014182829A5 JP2014051609A JP2014051609A JP2014182829A5 JP 2014182829 A5 JP2014182829 A5 JP 2014182829A5 JP 2014051609 A JP2014051609 A JP 2014051609A JP 2014051609 A JP2014051609 A JP 2014051609A JP 2014182829 A5 JP2014182829 A5 JP 2014182829A5
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JP
Japan
Prior art keywords
instruction
source
dependent
dependent instruction
nested
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JP2014051609A
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English (en)
Japanese (ja)
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JP6148191B2 (ja
JP2014182829A (ja
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Priority claimed from US13/836,392 external-priority patent/US9424041B2/en
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Publication of JP6148191B2 publication Critical patent/JP6148191B2/ja
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JP2014051609A 2013-03-15 2014-03-14 直接依存命令及びネストされた依存命令のためのスケジューラー内の推測的ソース準備をリセットする効果的な方法 Active JP6148191B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/836,392 US9424041B2 (en) 2013-03-15 2013-03-15 Efficient way to cancel speculative ‘source ready’ in scheduler for direct and nested dependent instructions
US13/836,392 2013-03-15

Publications (3)

Publication Number Publication Date
JP2014182829A JP2014182829A (ja) 2014-09-29
JP2014182829A5 true JP2014182829A5 (enExample) 2017-03-09
JP6148191B2 JP6148191B2 (ja) 2017-06-14

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ID=51419119

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014051609A Active JP6148191B2 (ja) 2013-03-15 2014-03-14 直接依存命令及びネストされた依存命令のためのスケジューラー内の推測的ソース準備をリセットする効果的な方法

Country Status (5)

Country Link
US (1) US9424041B2 (enExample)
JP (1) JP6148191B2 (enExample)
KR (1) KR101985377B1 (enExample)
CN (1) CN104049952B (enExample)
DE (1) DE102014103282A1 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180038793A (ko) * 2016-10-07 2018-04-17 삼성전자주식회사 영상 데이터 처리 방법 및 장치
CN106909343B (zh) * 2017-02-23 2019-01-29 北京中科睿芯科技有限公司 一种基于数据流的指令调度方法及装置
CN111124492B (zh) * 2019-12-16 2022-09-20 成都海光微电子技术有限公司 指令生成方法、装置、指令执行方法、处理器及电子设备
CN111399912B (zh) * 2020-03-26 2022-11-22 超睿科技(长沙)有限公司 一种面向多周期指令的指令调度方法、系统及介质
US20220206793A1 (en) * 2020-12-24 2022-06-30 Intel Corporation Methods, systems, and apparatuses for a scalable reservation station implementing a single unified speculation state propagation and execution wakeup matrix circuit in a processor
US11934834B2 (en) * 2021-10-19 2024-03-19 Ampere Computing Llc Instruction scheduling in a processor using operation source parent tracking
US20230315446A1 (en) * 2022-03-30 2023-10-05 Fujitsu Limited Arithmetic processing apparatus and method for arithmetic processing
US20250306999A1 (en) * 2024-03-30 2025-10-02 Advanced Micro Devices, Inc. Apparatuses, systems, and methods for scheduling processor operations

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5778210A (en) 1996-01-11 1998-07-07 Intel Corporation Method and apparatus for recovering the state of a speculatively scheduled operation in a processor which cannot be executed at the speculated time
US6065105A (en) 1997-01-08 2000-05-16 Intel Corporation Dependency matrix
US6792524B1 (en) * 1998-08-20 2004-09-14 International Business Machines Corporation System and method cancelling a speculative branch
EP1122639A3 (en) * 1998-08-24 2002-02-13 Advanced Micro Devices, Inc. Mechanism for load block on store address generation and universal dependency vector/queue entry
US6988185B2 (en) 2002-01-22 2006-01-17 Intel Corporation Select-free dynamic instruction scheduling
US7130990B2 (en) 2002-12-31 2006-10-31 Intel Corporation Efficient instruction scheduling with lossy tracking of scheduling information
US20070043932A1 (en) 2005-08-22 2007-02-22 Intel Corporation Wakeup mechanisms for schedulers
US7721071B2 (en) * 2006-02-28 2010-05-18 Mips Technologies, Inc. System and method for propagating operand availability prediction bits with instructions through a pipeline in an out-of-order processor
US7600103B2 (en) 2006-06-30 2009-10-06 Intel Corporation Speculatively scheduling micro-operations after allocation
JP4230504B2 (ja) * 2006-11-30 2009-02-25 株式会社日立製作所 データプロセッサ
JP2009181163A (ja) * 2008-01-29 2009-08-13 Kyoto Univ マイクロプロセッサならびにビット・ベクタのエンコーディング方法およびビット・ベクタの生成方法
US8239661B2 (en) 2008-08-28 2012-08-07 International Business Machines Corporation System and method for double-issue instructions using a dependency matrix
US9262171B2 (en) 2009-06-30 2016-02-16 Oracle America, Inc. Dependency matrix for the determination of load dependencies
US9286075B2 (en) * 2009-09-30 2016-03-15 Oracle America, Inc. Optimal deallocation of instructions from a unified pick queue
CN101833435A (zh) * 2010-04-19 2010-09-15 天津大学 基于传输触发架构可配置处理器指令冗余消除方法
US9256428B2 (en) * 2013-02-06 2016-02-09 International Business Machines Corporation Load latency speculation in an out-of-order computer processor

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