CN104049952B - 直接和嵌套依赖指令的调度器中重置推测源就绪的方法 - Google Patents

直接和嵌套依赖指令的调度器中重置推测源就绪的方法 Download PDF

Info

Publication number
CN104049952B
CN104049952B CN201410087003.3A CN201410087003A CN104049952B CN 104049952 B CN104049952 B CN 104049952B CN 201410087003 A CN201410087003 A CN 201410087003A CN 104049952 B CN104049952 B CN 104049952B
Authority
CN
China
Prior art keywords
instruction
source
relying
nested
cancellation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201410087003.3A
Other languages
English (en)
Chinese (zh)
Other versions
CN104049952A (zh
Inventor
拉维·伊因加尔
布莱德利·杰尼·伯杰斯
桑迪普·库马尔·杜贝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN104049952A publication Critical patent/CN104049952A/zh
Application granted granted Critical
Publication of CN104049952B publication Critical patent/CN104049952B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181Instruction operation extension or modification
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838Dependency mechanisms, e.g. register scoreboarding
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842Speculative instruction execution
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
CN201410087003.3A 2013-03-15 2014-03-11 直接和嵌套依赖指令的调度器中重置推测源就绪的方法 Active CN104049952B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/836,392 US9424041B2 (en) 2013-03-15 2013-03-15 Efficient way to cancel speculative ‘source ready’ in scheduler for direct and nested dependent instructions
US13/836,392 2013-03-15

Publications (2)

Publication Number Publication Date
CN104049952A CN104049952A (zh) 2014-09-17
CN104049952B true CN104049952B (zh) 2018-10-16

Family

ID=51419119

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410087003.3A Active CN104049952B (zh) 2013-03-15 2014-03-11 直接和嵌套依赖指令的调度器中重置推测源就绪的方法

Country Status (5)

Country Link
US (1) US9424041B2 (enExample)
JP (1) JP6148191B2 (enExample)
KR (1) KR101985377B1 (enExample)
CN (1) CN104049952B (enExample)
DE (1) DE102014103282A1 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180038793A (ko) * 2016-10-07 2018-04-17 삼성전자주식회사 영상 데이터 처리 방법 및 장치
CN106909343B (zh) * 2017-02-23 2019-01-29 北京中科睿芯科技有限公司 一种基于数据流的指令调度方法及装置
CN111124492B (zh) * 2019-12-16 2022-09-20 成都海光微电子技术有限公司 指令生成方法、装置、指令执行方法、处理器及电子设备
CN111399912B (zh) * 2020-03-26 2022-11-22 超睿科技(长沙)有限公司 一种面向多周期指令的指令调度方法、系统及介质
US20220206793A1 (en) * 2020-12-24 2022-06-30 Intel Corporation Methods, systems, and apparatuses for a scalable reservation station implementing a single unified speculation state propagation and execution wakeup matrix circuit in a processor
US11934834B2 (en) * 2021-10-19 2024-03-19 Ampere Computing Llc Instruction scheduling in a processor using operation source parent tracking
US20230315446A1 (en) * 2022-03-30 2023-10-05 Fujitsu Limited Arithmetic processing apparatus and method for arithmetic processing
US20250306999A1 (en) * 2024-03-30 2025-10-02 Advanced Micro Devices, Inc. Apparatuses, systems, and methods for scheduling processor operations

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6792524B1 (en) * 1998-08-20 2004-09-14 International Business Machines Corporation System and method cancelling a speculative branch
CN101833435A (zh) * 2010-04-19 2010-09-15 天津大学 基于传输触发架构可配置处理器指令冗余消除方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5778210A (en) 1996-01-11 1998-07-07 Intel Corporation Method and apparatus for recovering the state of a speculatively scheduled operation in a processor which cannot be executed at the speculated time
US6065105A (en) 1997-01-08 2000-05-16 Intel Corporation Dependency matrix
EP1122639A3 (en) * 1998-08-24 2002-02-13 Advanced Micro Devices, Inc. Mechanism for load block on store address generation and universal dependency vector/queue entry
US6988185B2 (en) 2002-01-22 2006-01-17 Intel Corporation Select-free dynamic instruction scheduling
US7130990B2 (en) 2002-12-31 2006-10-31 Intel Corporation Efficient instruction scheduling with lossy tracking of scheduling information
US20070043932A1 (en) 2005-08-22 2007-02-22 Intel Corporation Wakeup mechanisms for schedulers
US7721071B2 (en) * 2006-02-28 2010-05-18 Mips Technologies, Inc. System and method for propagating operand availability prediction bits with instructions through a pipeline in an out-of-order processor
US7600103B2 (en) 2006-06-30 2009-10-06 Intel Corporation Speculatively scheduling micro-operations after allocation
JP4230504B2 (ja) * 2006-11-30 2009-02-25 株式会社日立製作所 データプロセッサ
JP2009181163A (ja) * 2008-01-29 2009-08-13 Kyoto Univ マイクロプロセッサならびにビット・ベクタのエンコーディング方法およびビット・ベクタの生成方法
US8239661B2 (en) 2008-08-28 2012-08-07 International Business Machines Corporation System and method for double-issue instructions using a dependency matrix
US9262171B2 (en) 2009-06-30 2016-02-16 Oracle America, Inc. Dependency matrix for the determination of load dependencies
US9286075B2 (en) * 2009-09-30 2016-03-15 Oracle America, Inc. Optimal deallocation of instructions from a unified pick queue
US9256428B2 (en) * 2013-02-06 2016-02-09 International Business Machines Corporation Load latency speculation in an out-of-order computer processor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6792524B1 (en) * 1998-08-20 2004-09-14 International Business Machines Corporation System and method cancelling a speculative branch
CN101833435A (zh) * 2010-04-19 2010-09-15 天津大学 基于传输触发架构可配置处理器指令冗余消除方法

Also Published As

Publication number Publication date
JP6148191B2 (ja) 2017-06-14
US9424041B2 (en) 2016-08-23
JP2014182829A (ja) 2014-09-29
CN104049952A (zh) 2014-09-17
DE102014103282A1 (de) 2014-09-18
KR20140113303A (ko) 2014-09-24
KR101985377B1 (ko) 2019-06-03
US20140281431A1 (en) 2014-09-18

Similar Documents

Publication Publication Date Title
CN104049952B (zh) 直接和嵌套依赖指令的调度器中重置推测源就绪的方法
CN112534403B (zh) 微处理器中存储指令融合的系统和方法
US8650554B2 (en) Single thread performance in an in-order multi-threaded processor
US7721071B2 (en) System and method for propagating operand availability prediction bits with instructions through a pipeline in an out-of-order processor
US9405548B2 (en) Prioritizing instructions based on the number of delay cycles
CN101133391B (zh) 多线程微处理器中的二分化线程调度器
US9606806B2 (en) Dependence-based replay suppression
US9104399B2 (en) Dual issuing of complex instruction set instructions
US20120023314A1 (en) Paired execution scheduling of dependent micro-operations
US20060149931A1 (en) Runahead execution in a central processing unit
US9274829B2 (en) Handling interrupt actions for inter-thread communication
EP2997462A1 (en) Dynamic optimization of pipelined software
US6988185B2 (en) Select-free dynamic instruction scheduling
US7711934B2 (en) Processor core and method for managing branch misprediction in an out-of-order processor pipeline
US11829767B2 (en) Register scoreboard for a microprocessor with a time counter for statically dispatching instructions
US20100306513A1 (en) Processor Core and Method for Managing Program Counter Redirection in an Out-of-Order Processor Pipeline
US20140258697A1 (en) Apparatus and Method for Transitive Instruction Scheduling
US20070043932A1 (en) Wakeup mechanisms for schedulers
US10387162B2 (en) Effective address table with multiple taken branch handling for out-of-order processors
US12001843B2 (en) Microprocessor including a decode unit that performs pre-execution of load constant micro-operations
US20130019085A1 (en) Efficient Recombining for Dual Path Execution
US10514925B1 (en) Load speculation recovery
CN120179296B (zh) 基于分支跳转的伪乱序指令调度方法
US12169716B2 (en) Microprocessor with a time counter for statically dispatching extended instructions
WO2007084202A2 (en) Processor core and method for managing branch misprediction in an out-of-order processor pipeline

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant