DE102014103282A1 - Effizienter Weg zum Zurücksetzen eines spekulativen "Source Ready" in einem Scheduler für direkte und verschachtelte, abhängige Anweisungen - Google Patents

Effizienter Weg zum Zurücksetzen eines spekulativen "Source Ready" in einem Scheduler für direkte und verschachtelte, abhängige Anweisungen Download PDF

Info

Publication number
DE102014103282A1
DE102014103282A1 DE102014103282.9A DE102014103282A DE102014103282A1 DE 102014103282 A1 DE102014103282 A1 DE 102014103282A1 DE 102014103282 A DE102014103282 A DE 102014103282A DE 102014103282 A1 DE102014103282 A1 DE 102014103282A1
Authority
DE
Germany
Prior art keywords
dependent
source
instruction
abort
statement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE102014103282.9A
Other languages
German (de)
English (en)
Inventor
Ravi Iyengar
Bradley Gene Burgess
Sandeep Kumar DUBEY
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of DE102014103282A1 publication Critical patent/DE102014103282A1/de
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
DE102014103282.9A 2013-03-15 2014-03-12 Effizienter Weg zum Zurücksetzen eines spekulativen "Source Ready" in einem Scheduler für direkte und verschachtelte, abhängige Anweisungen Pending DE102014103282A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/836,392 US9424041B2 (en) 2013-03-15 2013-03-15 Efficient way to cancel speculative ‘source ready’ in scheduler for direct and nested dependent instructions
US13/836,392 2013-03-15

Publications (1)

Publication Number Publication Date
DE102014103282A1 true DE102014103282A1 (de) 2014-09-18

Family

ID=51419119

Family Applications (1)

Application Number Title Priority Date Filing Date
DE102014103282.9A Pending DE102014103282A1 (de) 2013-03-15 2014-03-12 Effizienter Weg zum Zurücksetzen eines spekulativen "Source Ready" in einem Scheduler für direkte und verschachtelte, abhängige Anweisungen

Country Status (5)

Country Link
US (1) US9424041B2 (enExample)
JP (1) JP6148191B2 (enExample)
KR (1) KR101985377B1 (enExample)
CN (1) CN104049952B (enExample)
DE (1) DE102014103282A1 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180038793A (ko) * 2016-10-07 2018-04-17 삼성전자주식회사 영상 데이터 처리 방법 및 장치
CN106909343B (zh) * 2017-02-23 2019-01-29 北京中科睿芯科技有限公司 一种基于数据流的指令调度方法及装置
CN111124492B (zh) * 2019-12-16 2022-09-20 成都海光微电子技术有限公司 指令生成方法、装置、指令执行方法、处理器及电子设备
CN111399912B (zh) * 2020-03-26 2022-11-22 超睿科技(长沙)有限公司 一种面向多周期指令的指令调度方法、系统及介质
US20220206793A1 (en) * 2020-12-24 2022-06-30 Intel Corporation Methods, systems, and apparatuses for a scalable reservation station implementing a single unified speculation state propagation and execution wakeup matrix circuit in a processor
US11934834B2 (en) * 2021-10-19 2024-03-19 Ampere Computing Llc Instruction scheduling in a processor using operation source parent tracking
US20230315446A1 (en) * 2022-03-30 2023-10-05 Fujitsu Limited Arithmetic processing apparatus and method for arithmetic processing
US20250306999A1 (en) * 2024-03-30 2025-10-02 Advanced Micro Devices, Inc. Apparatuses, systems, and methods for scheduling processor operations

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5778210A (en) 1996-01-11 1998-07-07 Intel Corporation Method and apparatus for recovering the state of a speculatively scheduled operation in a processor which cannot be executed at the speculated time
US6065105A (en) 1997-01-08 2000-05-16 Intel Corporation Dependency matrix
US6792524B1 (en) * 1998-08-20 2004-09-14 International Business Machines Corporation System and method cancelling a speculative branch
WO2000011548A1 (en) * 1998-08-24 2000-03-02 Advanced Micro Devices, Inc. Mechanism for load block on store address generation and universal dependency vector
US6988185B2 (en) 2002-01-22 2006-01-17 Intel Corporation Select-free dynamic instruction scheduling
US7130990B2 (en) 2002-12-31 2006-10-31 Intel Corporation Efficient instruction scheduling with lossy tracking of scheduling information
US20070043932A1 (en) 2005-08-22 2007-02-22 Intel Corporation Wakeup mechanisms for schedulers
US7721071B2 (en) * 2006-02-28 2010-05-18 Mips Technologies, Inc. System and method for propagating operand availability prediction bits with instructions through a pipeline in an out-of-order processor
US7600103B2 (en) 2006-06-30 2009-10-06 Intel Corporation Speculatively scheduling micro-operations after allocation
JP4230504B2 (ja) * 2006-11-30 2009-02-25 株式会社日立製作所 データプロセッサ
JP2009181163A (ja) * 2008-01-29 2009-08-13 Kyoto Univ マイクロプロセッサならびにビット・ベクタのエンコーディング方法およびビット・ベクタの生成方法
US8239661B2 (en) 2008-08-28 2012-08-07 International Business Machines Corporation System and method for double-issue instructions using a dependency matrix
US9262171B2 (en) 2009-06-30 2016-02-16 Oracle America, Inc. Dependency matrix for the determination of load dependencies
US9286075B2 (en) * 2009-09-30 2016-03-15 Oracle America, Inc. Optimal deallocation of instructions from a unified pick queue
CN101833435A (zh) * 2010-04-19 2010-09-15 天津大学 基于传输触发架构可配置处理器指令冗余消除方法
US9256428B2 (en) * 2013-02-06 2016-02-09 International Business Machines Corporation Load latency speculation in an out-of-order computer processor

Also Published As

Publication number Publication date
JP2014182829A (ja) 2014-09-29
US9424041B2 (en) 2016-08-23
JP6148191B2 (ja) 2017-06-14
KR101985377B1 (ko) 2019-06-03
US20140281431A1 (en) 2014-09-18
CN104049952A (zh) 2014-09-17
KR20140113303A (ko) 2014-09-24
CN104049952B (zh) 2018-10-16

Similar Documents

Publication Publication Date Title
DE102014103282A1 (de) Effizienter Weg zum Zurücksetzen eines spekulativen "Source Ready" in einem Scheduler für direkte und verschachtelte, abhängige Anweisungen
DE112004002506B4 (de) Vorrichtung und Verfahren für Energieleistungsüberwachungsgeräte zur Programmanpassung auf einen geringen Energieverbrauch
DE10297596B4 (de) Verfahren und Vorrichtung zum Suspendieren der Ausführung eines Threads, bis ein spezifizierter Speicherzugriff auftritt
DE69228600T2 (de) Kleinleistungs-rechnerarchitektur und verfahren
DE102012212639B4 (de) Temporäre SIMT-Ausführungs-Optimierung
DE102014003799A1 (de) Systeme und Verfahren zur Übertragungseliminierung mit Bypass-Mehrfachinstanziierungstabelle
DE102014003798B4 (de) Verfahren zum Booten eines heterogenen Systems und Präsentieren einer symmetrischen Kernansicht
TW559729B (en) Instruction for multithreaded parallel processor
DE69904083T2 (de) Anordnung und verfahren zum etikettieren und ungültig-erklären von spekulativ ausgeführten befehlen
DE102012216565A1 (de) Decodierzeit-computeranweisungsoptimierung
DE112011100715T5 (de) Hardware-hilfs-thread
DE112017000721T5 (de) Verfahren, einrichtung und befehle für thread-aussetzung auf benutzerebene
DE112018006124B4 (de) ZUSAMMENFÜHREN VON EINTRÄGEN GLOBALER ABSCHLUSSTABELLEN IN EINEM OoO-PROZESSOR
DE19506435C2 (de) Verfahren und Einrichtung zum Vermeiden von Rückschreibkonflikten zwischen einen gemeinsamen Rückschreibpfad verwendenden Ausführungseinheiten
DE112017003340T5 (de) Unterbrechungsfähige und neustartfähige matrix-multiplikationsinstruktionen, prozessoren, verfahren, und systeme
DE102014003671A1 (de) Prozessoren, verfahren und systeme zum entspannen der synchronisation von zugriffen auf einen gemeinsam genutzten speicher
DE112010004963T5 (de) Synchronisieren von SIMD Vektoren
DE102012216571A1 (de) Nutzung einer architekturdefinierten letztverwendungs-operandenangabe in einem computersystem-operandenressourcenpool
DE102010052680A1 (de) Ein Befehl, um einen Prozessor-Wartezustand zu ermöglichen
DE102014003399A1 (de) Systeme und Verfahren zur Implementierung transaktionalen Speichers
DE102018005105A1 (de) Befehle für entfernte atomare operationen
DE112011101086T5 (de) Optimieren von Energieverbrauch und Anwendungsleistung in einem Multithread-Mehrkernprozessorsystem
DE102014000384A1 (de) ZUWEISEN VON RESSOURCEN ZU THREADS AUF DER BASIS VON SPEKULATIONSMESSGRÖßEN
DE102007045496A1 (de) Anweisung und Logik zum Bearbeiten von Textstrings
DE102012217970A1 (de) Computeranweisungen zum Aktivieren und Deaktivieren von Operanden

Legal Events

Date Code Title Description
R082 Change of representative

Representative=s name: KUHNEN & WACKER PATENT- UND RECHTSANWALTSBUERO, DE

R012 Request for examination validly filed