JP2014182812A - データ記憶装置 - Google Patents

データ記憶装置 Download PDF

Info

Publication number
JP2014182812A
JP2014182812A JP2014044947A JP2014044947A JP2014182812A JP 2014182812 A JP2014182812 A JP 2014182812A JP 2014044947 A JP2014044947 A JP 2014044947A JP 2014044947 A JP2014044947 A JP 2014044947A JP 2014182812 A JP2014182812 A JP 2014182812A
Authority
JP
Japan
Prior art keywords
memory
data
solid state
control circuit
interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2014044947A
Other languages
English (en)
Japanese (ja)
Other versions
JP2014182812A5 (https=
Inventor
Dale Murphy Robert
ロバート・デイル・マーフィー
Edward Moon John
ジョン・エドワード・ムーン
Keeler Stanton
スタントン・キーラー
Esten Bohn Richard
リチャード・エステン・ボーン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seagate Technology LLC
Original Assignee
Seagate Technology LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US14/028,528 external-priority patent/US20160011965A1/en
Application filed by Seagate Technology LLC filed Critical Seagate Technology LLC
Publication of JP2014182812A publication Critical patent/JP2014182812A/ja
Publication of JP2014182812A5 publication Critical patent/JP2014182812A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2014044947A 2013-03-15 2014-03-07 データ記憶装置 Pending JP2014182812A (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201361790978P 2013-03-15 2013-03-15
US61/790,978 2013-03-15
US14/028,528 2013-09-16
US14/028,528 US20160011965A1 (en) 2013-03-15 2013-09-16 Pass through storage devices

Publications (2)

Publication Number Publication Date
JP2014182812A true JP2014182812A (ja) 2014-09-29
JP2014182812A5 JP2014182812A5 (https=) 2015-03-26

Family

ID=51701386

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014044947A Pending JP2014182812A (ja) 2013-03-15 2014-03-07 データ記憶装置

Country Status (2)

Country Link
JP (1) JP2014182812A (https=)
KR (1) KR101569049B1 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107025190A (zh) * 2016-02-02 2017-08-08 爱思开海力士有限公司 系统及其操作方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102396441B1 (ko) * 2015-08-11 2022-05-10 삼성전자주식회사 통신 중단시 데이터 손실을 방지하도록 동작하는 스토리지 장치

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09297659A (ja) * 1996-04-30 1997-11-18 Toshiba Corp 不揮発性記憶装置およびその制御方法
JP2007193440A (ja) * 2006-01-17 2007-08-02 Toshiba Corp 不揮発性キャッシュメモリを用いる記憶装置とその制御方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011005249A1 (en) 2009-07-07 2011-01-13 Lsi Corporation Systems and methods for tiered non-volatile storage

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09297659A (ja) * 1996-04-30 1997-11-18 Toshiba Corp 不揮発性記憶装置およびその制御方法
JP2007193440A (ja) * 2006-01-17 2007-08-02 Toshiba Corp 不揮発性キャッシュメモリを用いる記憶装置とその制御方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107025190A (zh) * 2016-02-02 2017-08-08 爱思开海力士有限公司 系统及其操作方法

Also Published As

Publication number Publication date
KR20140113370A (ko) 2014-09-24
KR101569049B1 (ko) 2015-11-20

Similar Documents

Publication Publication Date Title
US9304901B2 (en) System and method for handling I/O write requests
US8850114B2 (en) Storage array controller for flash-based storage devices
KR101480659B1 (ko) 2-레벨 시스템 메인 메모리
US8683131B2 (en) Direct memory address for solid-state drives
CN103262054B (zh) 用于自动提交存储器的装置、系统和方法
US9824041B2 (en) Dual access memory mapped data structure memory
US9075729B2 (en) Storage system and method of controlling data transfer in storage system
US11893269B2 (en) Apparatus and method for improving read performance in a system
US20160011965A1 (en) Pass through storage devices
US20150339058A1 (en) Storage system and control method
TWI782847B (zh) 用來在儲存伺服器中進行基於管線的存取管理的方法及設備
US12386565B2 (en) Method and device for data storage based on redundant array of independent disks
US9547460B2 (en) Method and system for improving cache performance of a redundant disk array controller
US20130086308A1 (en) Storage device and method of accessing copy destination data
US9542284B2 (en) Buffered automated flash controller connected directly to processor memory bus
TW201608469A (zh) 有效率釋出序列輸入輸出串流的方法及裝置
US20210255794A1 (en) Optimizing Data Write Size Using Storage Device Geometry
JP2014182812A (ja) データ記憶装置
WO2021048709A1 (en) Dynamically switching between memory copy and memory mapping to optimize 1/o performance

Legal Events

Date Code Title Description
A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20150204

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20150204

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20160118

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20160126

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20160425

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20160712

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20161011

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20161117

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20170110

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20170323

A911 Transfer of reconsideration by examiner before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20170404

A912 Removal of reconsideration by examiner before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A912

Effective date: 20170428

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20180418