JP2014179895A - Pipelined a/d converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a pipelined A/D converter that suppresses a linear error due to a relative error in a capacitance value of unit capacitors of switched capacitor circuits.SOLUTION: The pipelined A/D converter includes: a group of a plurality of unit capacitors C1'-C8' of the same capacitance value; an operational amplifier O1 having an input end connected with one end of the unit capacitor group; and a selection circuit S1 for selecting a voltage to be connected to the other end of the unit capacitor group from a positive reference voltage, a negative reference voltage or an analog common voltage. Each stage has a sub A/D converter built therein. Prior to and subsequently to a change in an output value of the sub A/D converter of one stage, one unit capacitor of the unit capacitor group C1'-C8' of the stage next to the stage to be connected with the positive reference voltage or the negative reference voltage is selected from different unit capacitors.

Description

  The present invention relates to a pipeline type A / D converter, and more particularly, to suppress a linear error caused by a relative error in the capacitance value of a unit capacitor of a switched capacitor circuit constituting the pipeline type A / D converter. The present invention relates to a pipelined A / D converter.

  In general, pipelined A / D converters implement sample / hold, signal amplification, and D / A functions for adding / subtracting a reference voltage using a switched capacitor circuit using an operational amplifier. In this switched capacitor circuit, there are a plurality of unit capacitors designed to have the same capacitance value, and some unit capacitors are used for feedback of the operational amplifier, and the ratio of the unit capacitors connected to the reference voltage is appropriately set. By switching, the expected transfer characteristics are realized.

The operation of the switched capacitor circuit of the conventional pipeline type A / D converter will be described with reference to FIGS.
FIG. 4 is a diagram showing a conventional pipeline type A / D converter composed of N stages. In the pipeline type A / D converter A1, N stages from STAGE 1 to STAGE, each incorporating a 2.5-bit A / D converter, are connected in series, and A / D conversion from each stage is performed. The digital output signals DO_1 to DO_N are input to the encoder E11, and the encoder E11 outputs an output value ADO obtained by calculating them. The operation of each stage consists of a sample period for sampling the analog output signal from the previous stage and a hold period that is amplified by an operational amplifier and output to the next stage, and this period is an inverted phase relationship between adjacent stages. It is in.

  FIG. 5 is a configuration diagram of a certain stage in the pipeline type A / D converter of FIG. FIG. 5 shows unit capacitors C1 to C4 having the same capacitance value, switches sw1s to sw4s, sw1h to sw4h, sw9, an operational amplifier O1, a 2.5-bit sub A / D converter, and a sub A / D converter. A selection circuit S1 that selects a reference voltage + Vr, 0 (analog ground), and −Vr for connection to a unit capacitor by an output DO_i is included. Here, the reference voltage Vr is a voltage satisfying Vr = A / 2 where A is the input range of the A / D converter.

Next, the operation of STAGEi will be described.
Now, assume that the sub-A / D converter operates with the two-phase clock shown in FIG. 6, and that STAGEi is a sample period when φ1 is high level, and a hold period when φ2 is high level. When φ1 is at high level, the switches SW1s to sw4s and sw9 of STAGEi are short-circuited, and sw1h to sw4h are opened, and the output signal Vo_i-1 from the previous stage STAGEi-1 is sampled by all the unit capacitors C1 to C4.

  Further, the sub A / D converter performs A / D conversion on the output signal Vo_i−1 from the previous stage STAGEi−1 to 7 values of 0 to 6. When φ2 becomes high level, the switches sw1s to sw4s and sw9 are opened, and sw1h to sw4h are short-circuited. The unit capacitor C1 is connected to the output Vo_i of the operational amplifier O1 to form a negative feedback. The unit capacitors C2 to C4 One of the reference voltages + Vr, 0, and −Vr is selected and connected according to the output value of the sub A / D converter.

FIG. 7 is a diagram showing the output value of the sub A / D converter and the connection destination connected to the unit capacitor during the hold period. As is apparent from FIG. 5, the unit capacitor C1 is always connected to the output Vo_i of the operational amplifier O1 regardless of the output value of the sub A / D converter.
FIG. 8 is a diagram showing the input / output characteristics of STAGE, and shows the input / output characteristics of STAGEi. The horizontal axis represents the input voltage to STAGEi, and the vertical axis represents the output voltage from STAGEi (= input voltage to STAGEi + 1). The correspondence with the output value of the sub A / D converter is also shown. Before and after the output value of the sub A / D converter is switched, a voltage corresponding to the reference voltage Vr is added or subtracted so as not to exceed the input range of the next stage. Further, the analog voltage added and subtracted here is wrinkled by adding and subtracting a digital value corresponding to the reference voltage by the encoder E11 of FIG.

  By the way, for the purpose of increasing the number of output bits of the pipeline A / D converter A1 and sharing the reference voltage with the ground and the power source, a configuration as in Patent Document 1 has been proposed. According to Patent Document 1, the number of output bits of the pipeline A / D converter A1 can be increased without tightening the thermal noise from the switch and the DC gain of the operational amplifier, and the reference voltage can be set to the power source or the ground. By using the common, there is an advantage that a buffer for generating a reference voltage becomes unnecessary.

Next, the operation of the switched capacitor circuit of the pipeline type A / D converter A1 disclosed in Patent Document 1 will be described with reference to FIGS.
FIG. 9 is a diagram showing a pipeline type A / D converter composed of N stages described in Patent Document 1. In FIG. As in FIG. 4 and the circuit, N stages from STAGE 1 to STAGE, each incorporating a 2.5-bit A / D converter, are connected in cascade, and A / D converted digital output signals from each stage DO_1 to DO_N are input to the encoder E21, and the encoder E21 outputs an output value ADO obtained by calculating them.

  FIG. 10 is a configuration diagram of a certain stage in the pipeline type A / D converter of FIG. FIG. 10 shows unit capacitors C1 ′ to C8 ′ having the same capacitance value, switches sw1s to sw8s, sw1h to sw8h, sw9, an operational amplifier O1, a 2.5-bit sub A / D converter, and a sub A / D. A selection circuit S1 for selecting connection to the unit capacitor from the reference voltage +2 Vr, 0 (analog ground), and −2 Vr according to the output DO_i of the converter is included. Here, the capacitance values of the unit capacitors C1 ′ to C8 ′ are half of the capacitance values of the unit capacitors C1 to C4 in FIG. 5 (that is, C1 ′ = C2 ′ =... = C8 ′ = 0.5C1). The reference voltage Vr is equal to Vr in FIG. 5 (that is, Vr = A / 2).

Next, the operation of STAGEi will be described.
Now, assume that the sub-A / D converter operates with the two-phase clock shown in FIG. 6, and that STAGEi is a sample period when φ1 is high level, and a hold period when φ2 is high level. When φ1 is high, the switches SW1s to sw8s and sw9 of STAGEi are short-circuited, and sw1h to sw8h are opened, and the output signal Vo_i-1 from the previous stage STAGEi-1 is sampled by all unit capacitors C1 'to C8'. To do.

  Further, the sub A / D converter performs A / D conversion on the output signal Vo_i−1 from the previous stage STAGEi−1 to 7 values of 0 to 6. When φ2 becomes high level, the switches sw1s to sw8s and sw9 are opened, and sw1h to sw8h are short-circuited. 'To C8' are connected to the analog ground, and the unit capacitors C3 to C5 are selected and connected to any one of the reference voltages + 2Vr, 0, and -2Vr according to the output value of the sub A / D converter. .

FIG. 11 is a diagram showing the output value of the sub A / D converter and the connection destination connected to the unit capacitor during the hold period. As is clear from FIG. 10, the unit capacitors C1 ′ and C2 ′ are always connected to the output Vo_i of the operational amplifier O1 regardless of the output value of the sub A / D converter, and the unit capacitors C6 ′ to C8 ′ are always Connected to analog ground.
The input / output characteristics of STAGEi at this time are shown in FIG. 8 as in the prior art of FIG. However, in the configuration of Patent Document 1, there is a unit capacitor that is always connected to the analog ground during the hold period, and using these, the reference voltages 0 and ± 2 Vr are connected according to the output value of the sub A / D converter. By doing so, a wider number of conversion bits can be obtained. In addition, since the reference voltage is doubled, the reference voltage can be shared with the power supply and the ground.

JP 2011-229128 A

  However, a unit capacitor used in an actual switched capacitor circuit includes a relative error due to manufacturing variations, and this relative error generates an error voltage in the voltage of the output signal, resulting in a linearity error in A / D conversion. Has occurred. In particular, in the circuit configuration of Patent Document 1, when the output value of the sub A / D converter is switched, the capacitance value of the unit capacitor involved in adding / subtracting the reference voltage 2Vr is half that of the configuration of FIG. large.

The influence of the relative error of the capacitance values of these unit capacitors on the linearity error will be described using mathematical expressions. For the sake of simplicity, assuming that the unit capacitor of STAGEi has a relative error, and the capacitance values of the unit capacitors of the operational amplifier and other stages are ideal, the relative error of the unit capacitor of STAGEi is sub-A of STAGEi-1. The amount of error generated before and after switching of the output of the / D converter can be derived as follows.
First, in the case of the conventional circuit configuration shown in FIG. 4, the output of STAGE i-1 is −0.5 Vr and +0.5 Vr, respectively, before and after the decision value switching of the sub-A / D converter of STAGE i−1. The output values Vo1 and Vo2 of STAGEi when these are input to STAGEi are expressed as follows.

  Therefore, the difference ΔVo of the output of STAGE i before and after the switching of the determination value of the sub A / D converter of STAGE i−1 is expressed by the following equation.

  In an ideal case, ΔVo is 0, but if the unit capacitor has a relative error, ΔVo does not become 0, and this is a linear error. The error ε_total is calculated by calculating the amount of error appearing in the output difference ΔVo assuming that the error ε of each unit capacitor is uncorrelated, using the fact that the error of each unit capacitor is uncorrelated. Is obtained by the following formula.

  Next, in the case of the circuit configuration of Patent Document 1 shown in FIG. 9, the output of STAGEi-1 is −0.5 Vr and +0.5 Vr, respectively, before and after switching of the determination value of the sub-A / D converter of STAGEi−1. Become. The output values Vo1 and Vo2 of STAGE i when these are input to STAGEi are expressed as follows.

  Therefore, the difference ΔVo of the output of STAGE i before and after the switching of the determination value of the sub A / D converter of STAGE i−1 is expressed by the following equation.

  In an ideal case, ΔVo is 0, but if the unit capacitor has a relative error, ΔVo does not become 0, and this is a linear error. The error ε_total ′ is calculated by calculating the amount of error appearing in the output difference ΔVo assuming that the error ε ′ is assumed for each unit capacitor by using the fact that the error of each unit capacitor is uncorrelated. What is necessary is just to take the square root of multiplication, and it is represented by the following formula.

  However, the capacitance value of the unit capacitor having the configuration of Patent Document 1 is half the capacitance value of the unit capacitor of FIG. In general, since the error is inversely proportional to the square root of the capacitance value, the relationship between the error ε ′ of the unit capacitor disclosed in Patent Document 1 and the error ε of the unit capacitor of FIG.

  Therefore, when the error ε_total ′ of Patent Document 1 is represented by the error ε of the unit capacitor of FIG. 4 which is the prior art, it is expressed as follows.

As is clear from the comparison between Equation 4 and Equation 10, the configuration of Patent Document 1 has a linearity of √3 times relative to the relative error of the capacitance value of the unit capacitor compared to the configuration of FIG. The impact on errors is large. If we try to cover this only by increasing the capacitance value of the unit capacitor, it is necessary to triple the size of the unit capacitor, which not only greatly increases the area, but also significantly increases the power consumption of the operational amplifier that drives it. End up.
The present invention has been made in view of such problems, and its object is that the capacitance value of the unit capacitor of the switched capacitor circuit constituting the pipeline A / D converter has a relative error. It is an object of the present invention to provide a pipeline type A / D converter that suppresses linear errors.

  The present invention has been made to achieve such an object, and the invention according to claim 1 is a pipeline type A in which a plurality of stages each having a switched capacitor circuit are connected in cascade. In the / D converter (A1), a plurality of unit capacitor groups (C1 ′ to C8 ′) having the same capacitance value and an operational amplifier (O1) in which one end of each of the unit capacitor groups (C1 ′ to C8 ′) is connected to the input end And a selection circuit (S1) for selecting a voltage connected to the other end of the unit capacitor group (C1 ′ to C8 ′) from a positive reference voltage, a negative reference voltage, or an analog common voltage, The stage incorporates a sub A / D converter, and before and after the output value of the sub A / D converter of a certain stage of the stage is switched, Or unit capacitor group of the next stage of the stage negative reference voltage is connected to the unit capacitor certain of (C1'~C8 '), and selecting from the different units capacitor.

According to a second aspect of the present invention, there is provided the encoder according to the first aspect, further comprising an encoder (E1) for inputting an A / D converted digital output signal from each of the stages. .
The invention according to claim 3 is the invention according to claim 1 or 2, wherein the unit capacitor group (C1 ′ to C8 ′) is connected to the inverting input terminal (−) of the operational amplifier (O1). A part of the unit capacitor groups (C1 ′ to C8 ′) is connected to the output terminal of the operational amplifier (O1) directly or via a switch.

  According to the present invention, even in the circuit configuration described in Patent Document 1 described above, it is possible to realize a converter that suppresses the influence of the relative error of the capacitance value of the capacitor and a pipeline A / D converter having the converter. .

It is a figure which shows the pipeline type A / D converter comprised from N stages. It is a figure which shows the structure of a certain STAGE in the pipeline type A / D converter of FIG. It is a figure which shows the output value of a sub A / D converter, and the connection place connected to a unit capacitor at the time of a hold period. It is a figure which shows the pipeline type A / D converter comprised from the conventional N stage. FIG. 5 is a configuration diagram of a certain stage in the pipeline type A / D converter of FIG. 4. It is a waveform diagram for operating with a two-phase clock of the A / D converter. It is the figure which showed the output value of a sub A / D converter, and the connecting point connected to a unit capacitor at the time of a hold period. It is a figure which shows the input / output characteristic of STAGE. It is a figure which shows the pipeline type A / D converter comprised from the N stage described in patent document 1. FIG. FIG. 10 is a configuration diagram of a certain stage in the pipeline type A / D converter of FIG. 9. It is a figure which shows the output value of a sub A / D converter, and the connection place connected to a unit capacitor at the time of a hold period.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram showing a pipeline type A / D converter composed of N stages. FIG. 2 is a diagram showing a configuration of a certain stage in the pipeline type A / D converter of FIG. FIG. 3 is a diagram illustrating an output value of the sub A / D converter and a connection destination connected to the unit capacitor during the hold period.

The pipeline type A / D converter of the present invention is a pipeline type A / D converter A1 in which a plurality of stages each having a switched capacitor circuit in each stage are connected in cascade.
Further, the pipeline type A / D converter of the present invention includes a plurality of unit capacitor groups C1 ′ to C8 ′ having the same capacitance value, and an operational amplifier O1 in which one end of each of the unit capacitor groups C1 ′ to C8 ′ is connected to an input end. And a selection circuit S1 for selecting a voltage connected to the other end of the unit capacitor groups C1 ′ to C8 ′ from either a positive reference voltage, a negative reference voltage, or an analog common voltage.

Each stage incorporates a sub A / D converter, and before and after the output value of the sub A / D converter of a certain stage is switched, the next stage of the stage to which the positive reference voltage or the negative reference voltage is connected. A certain unit capacitor in the unit capacitor groups C1 ′ to C8 ′ is selected from different unit capacitors.
In addition, an encoder E1 for inputting the A / D converted digital output signal from each stage is provided. The unit capacitor groups C1 ′ to C8 ′ are connected to the inverting input terminal (−) of the operational amplifier O1, and among the unit capacitor groups C1 ′ to C8 ′, C1 ′ and C2 ′ are connected to the operational amplifier O1 via a switch. Is connected to the output terminal.

The operation of the switched capacitor circuit of the pipeline type A / D converter to which the present invention is applied will be described below with reference to FIGS.
In FIG. 1, a pipeline type A / D converter A1 includes N stages from STAGE 1 to STAGE, each incorporating a 2.5-bit sub A / D converter, connected in series. The digital output signals DO_1 to DO_N subjected to the / D conversion are input to the encoder E1, and the encoder E1 outputs an output value ADO obtained by calculating them. The operation of each stage consists of a sample period for sampling the analog output signal from the previous stage and a hold period for amplifying the sampled signal with an operational amplifier and outputting it to the next stage, and this period is inverted between adjacent stages. Are in a phase relationship.

  In FIG. 2, unit capacitors C1 ′ to C8 ′ having equal capacitance values, switches sw1s to sw8s, sw1h to sw8h, sw9, an operational amplifier O1, a 2.5-bit sub A / D converter, and a sub A / D A selection circuit S1 for selecting connection to the unit capacitor from the reference voltage +2 Vr, 0 (analog ground), and −2 Vr according to the output DO_i of the converter is included. Here, the unit capacitors C1 'to C8' are equal to the capacitance value of the unit capacitor of FIG. 10 which is the circuit configuration diagram of Patent Document 1 described above, and the same applies to the reference voltage 2Vr.

Next, the operation of STAGEi will be described.
Now, assume that the sub-A / D converter operates with the two-phase clock shown in FIG. 6, and that STAGEi is a sample period when φ1 is high level, and a hold period when φ2 is high level. When φ1 is high, the switches SW1s to sw8s and sw9 of STAGEi are short-circuited, and sw1h to sw8h are opened, and the output signal Vo_i-1 from the previous stage STAGEi-1 is sampled by all unit capacitors C1 'to C8'. To do. Further, the sub A / D converter performs A / D conversion on the output signal Vo_i−1 from the previous stage STAGEi−1 to 7 values of 0 to 6. When φ2 becomes high level, the switches sw1s to sw8s and sw9 are opened, the sw1h to sw8h are short-circuited, and the unit capacitors C1 ′ and C2 ′ are connected to the output Vo_i of the operational amplifier O1 to form a negative feedback, and the unit capacitor C3 “˜C8” is selected and connected to one of the reference voltages +2 Vr, 0, and −2 Vr according to the output value of the sub A / D converter.

In FIG. 3, as is clear from FIG. 2, the unit capacitors C1 ′ and C2 ′ are always connected to the output Vo_i of the operational amplifier O1, regardless of the output value of the sub A / D converter. The difference from FIG. 11, which is the connection destination of Patent Document 1 described above, is that when the output of the sub A / D converter is 1 or 5, the unit capacitor to which +2 Vr is connected is different from the unit capacitor to which −2 Vr is connected. This is the unit capacitor.
The input / output characteristics of STAGEi at this time are as shown in FIG. 8, similar to the configuration of FIG.

Next, the influence of the relative error of the capacitance value of the unit capacitor in the configuration using the present invention on the linearity error will be described using mathematical expressions. For the sake of simplicity, if only the unit capacitor of STAGE i has a relative error, and the capacitance values of the unit capacitors of the operational amplifier and other stages are ideal, the relative error of the unit capacitor of STAGEi is the sub-stage of STAGEi-1. The amount of error generated before and after switching of the output of the A / D converter can be derived as follows.
In the case of the circuit configuration using the present invention shown in FIG. 1, the output of STAGEi-1 becomes −0.5 Vr and +0.5 Vr, respectively, before and after the decision value switching of the sub-A / D converter of STAGEi−1. . The output values Vo1 and Vo2 of STAGE i when these are input to STAGEi are expressed as follows.

  Therefore, the difference ΔVo of the output of STAGE i before and after switching of the determination value of the sub A / D converter of STAGE i−1 is expressed by the following equation.

  In an ideal case, ΔVo is 0, but if the unit capacitor has a relative error, ΔVo does not become 0, and this is a linear error. This error ε_total ″ is calculated by calculating the amount of error appearing in the output difference ΔVo assuming that the error ε ″ is assumed for each unit capacitor by utilizing the fact that the error of each unit capacitor is uncorrelated. It is sufficient to take the square root of the sum of squares of and is expressed by the following equation.

  However, the capacitance value of the unit capacitor having the configuration using the present invention is half of the capacitance value of the unit capacitor of FIG. Generally, since the error is inversely proportional to the square root of the capacitance value, the relationship between the error ε ″ of the unit capacitor having the configuration using the present invention and the error ε of the unit capacitor of FIG. Is done.

  Therefore, when the error ε_total ″ of the configuration using the present invention is expressed by the error ε of the unit capacitor of FIG.

As is clear from the comparison between Equation 4 and Equation 16, the influence of the relative error of the unit capacitor on the linearity error is not different from that of the prior art of FIG. Nevertheless, in the configuration of the present invention, as in Patent Document 1, there is a unit capacitor that is always connected to the analog ground during the hold period, and depending on the output value of the sub A / D converter using these units By connecting the reference voltages 0 and ± 2 Vr, it is possible to obtain a wider number of conversion bits, and the reference voltage is doubled, so that the reference voltage is shared with the power supply and the ground. Is possible.
As described above, according to the present invention, the pipeline type A / D that suppresses the linear error caused by the relative error in the capacitance value of the unit capacitor of the switched capacitor circuit constituting the pipeline type A / D converter A1. A D converter can be realized.

A1 Pipeline A / D converter E1, E11, E21 Encoder O1 Operational amplifier S1 selection circuit

Claims (3)

In a pipeline type A / D converter in which a plurality of stages each having a switched capacitor circuit in each stage are connected in cascade,
A plurality of unit capacitor groups having the same capacitance value;
An operational amplifier in which one end of the unit capacitor group is connected to an input end;
A selection circuit for selecting a voltage connected to the other end of the unit capacitor group from either a positive reference voltage, a negative reference voltage or an analog common voltage;
Each of the stages has a built-in sub A / D converter,
The unit capacitor group of the next stage of the certain stage to which the positive reference voltage or the negative reference voltage is connected before and after the output value of the sub A / D converter of a certain stage of the stage is switched. A pipeline type A / D converter, wherein a unit capacitor is selected from different unit capacitors.   2. The pipeline type A / D converter according to claim 1, further comprising an encoder for inputting an A / D converted digital output signal from each stage.   The unit capacitor group is connected to an inverting input terminal of the operational amplifier, and a part of the unit capacitor group is connected to the output terminal of the operational amplifier directly or through a switch. The pipeline type A / D converter according to claim 1 or 2.

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