JP2014179711A - Image processing apparatus, image processing method and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow the same hardware to be used in an A3 copier and a wide-width copier without degradation of the transfer speed of the wide-width copier in comparison with the A3 copier in an image processing apparatus for processing images with different main scanning sizes.SOLUTION: An image processing apparatus comprises: a main scanning size recognition unit 120a which recognizes the magnitude of data in the main scanning size of an image to be processed; memory control units 132, 134, 136 which perform changeover control of data processing to an internal memory and a DDR3 in accordance with the magnitude of the data in the main scanning size recognized by the main scanning size recognition unit 120a: and data processing units 131, 133, 135 which perform writing and reading of data by using the internal memory or the DDR3 changed over by the memory control units.

Description

  The present invention relates to an image processing apparatus, an image processing method, and a program.

  2. Description of the Related Art Conventionally, image processing apparatuses such as copiers and multifunction peripherals have been individually developed depending on the size of image data to be processed. In this case, there is a problem that development of hardware and software is wasteful, and development time and development cost are high. For example, a narrow multifunction peripheral having a paper size of A3, A4 or the like and a wide multifunction peripheral having a paper size of A0 or the like perform characteristic correction specific to the scanner unit on the read image data read by the scanner unit. After that, the image processing module performs image processing such as filter processing, color correction processing, scaling processing, and gradation processing, and performs output processing such as storage in memory, transfer output to other devices, and print output. Yes.

  However, in an image processing apparatus that processes images having different sizes in the main scanning direction, such as a narrow-width multifunction peripheral and a wide-width multifunction peripheral, the main image data to be handled is processed in spite of performing the same image processing in the image processing module. The data size in the scanning direction is different. In this case, since the required memory amount is different, conventionally, the hardware and software of the image processing module are individually developed. When hardware and software are individually developed in this way, there is a problem that the development of hardware and software is wasteful, and development time and development cost increase.

  For this reason, with respect to the image processing ASIC installed in the multifunction peripheral, it is possible to use the same ASIC for the A3 multifunction peripheral and the wide (A0) multifunction peripheral. Therefore, development at low cost and low man-hour is required. ASIC is an abbreviation for Application Specific Integrated Circuit.

  For example, in Patent Document 1, it is possible to use the same ASIC for an A3 multifunction peripheral and a wide (A0) multifunction peripheral for an image processing ASIC mounted on the multifunction peripheral. In this wide (A0) multi-function peripheral, image processing is realized by the configuration of a plurality of ASICs.

  A processing example of a conventional controller image processing unit will be described here. The upper part of FIG. 11 is a block diagram showing image processing parameter setting processing of the controller image processing unit 10, and the lower part of FIG. 11 is a block diagram showing image processing according to the image processing parameters. The controller image processing unit 10 includes ASICs 11a, b, and c. The ASICs 11a, b, and c have image processing registers 13a, b, and c, activation registers 14a, b, and c, and register I / Fs 15a, b, and c, respectively.

  First, as shown in the upper part of FIG. 11, the CPU that controls the entire multi-function peripheral writes image parameters to the controller image processing unit 10, and a write access is entered in the register I / F 15c of the ASIC 11c (arrow [1] ). Further, the register I / F 15c performs write access to the image processing register 13c or write access to the image processing register 13b (arrow [2]), and write access enters the register I / F 15b (arrow [3]). The register I / F 15b performs write access to the image processing register 13b or write access to the image processing register 13a (arrow [4]), and write access enters the register I / F 15a (arrow [5]). The register I / F 15a performs write access to the image processing register 13a (arrow [6]). In this manner, image parameters are set in the image processing registers 13a, b, and c of the ASICs 11a, b, and c.

  Next, when register setting is completed, as shown in the lower part of FIG. 11, the CPU performs write access to the activation register and write access to the register I / F 15c to the controller image processing unit 10 (arrow [1]). . The register I / F 15c performs a write access to the activation register 14c and the register I / F 15b (arrow [2]), and a write access enters the register I / F 15b (arrow [3]). The register I / F 15b performs write access to the activation register 14b and the register I / F 15a (arrow [4]), and write access enters the register I / F 15a (arrow [5]). The register I / F 15a performs write access to the activation register 14a (arrow [6]). At this point, the preparation for DMA transfer with the input from the scanner image processing unit (not shown) as the transfer source and the CPU as the transfer destination is completed.

  Next, as shown in the lower part of FIG. 11, image data is input to the ASIC 11a (arrow [7]). The ASIC 11a performs filter processing and color correction assigned by the various image processing units 12a, and outputs the result to the ASIC 11b (arrow [8]). The ASIC 11b performs a scaling process on the image data sent from the ASIC 11a and sends it to the ASIC 11c (arrow [9]). The ASIC 11c performs gradation processing on the image data sent from the ASIC 11b and transfers it to the CPU (arrow [10]).

  However, in the conventional technique as described above, since it is configured by a plurality of ASICs (hardware) as compared to the case of being configured by a single ASIC (hardware), the interrupt notification speed and the image processing There has been a problem that the transmission speed of the control signal between the modules becomes slow.

  The present invention has been made in view of the above, and in an image processing apparatus for processing images having different main scanning sizes, the transfer speed of a wide-width copying machine does not deteriorate as compared with an A3 copying machine. The purpose is to make it possible to use the same hardware for a wide-width copying machine.

  In order to solve the above-described problems and achieve the object, the present invention is recognized by a main scanning size recognition unit for recognizing the size of main scanning size data of an image to be processed, and the main scanning size recognition unit. A memory control unit that performs switching control of data processing to an internal memory and an external memory according to the data size of the main scanning size, and writing and writing data using the internal memory or the external memory switched by the memory control unit And a data processing unit that performs reading.

  The present invention has an effect that the same hardware can be used when processing images having different main scanning sizes, such as a narrow copying machine and a wide copying machine.

FIG. 1 is a block diagram showing the overall configuration of the image forming apparatus according to the present embodiment. FIG. 2 is a block diagram illustrating a configuration of the controller image processing unit. FIG. 3 is a block diagram showing a configuration of a memory control unit in various image processing blocks. FIG. 4A is a flowchart illustrating the operation (1) when the main scanning size is the A3 size. FIG. 4B is a flowchart illustrating the operation (2) when the main scanning size is the A3 size. FIG. 5A is a flowchart illustrating a memory control method (1) when the main scanning size is A0 size. FIG. 5B is a flowchart of the memory control method (2) when the main scanning size is A0. FIG. 6 is a block diagram showing the configuration of the SRAM_A control unit inside the memory control unit. FIG. 7 is a block diagram showing the configuration of the SRAM_C control unit inside the memory control unit. FIG. 8A is a flowchart illustrating the operation (1) of the main control unit of the SRAM_A control unit. FIG. 8B is a flowchart illustrating the operation (2) of the main control unit of the SRAM_A control unit. FIG. 9A is a flowchart illustrating the operation (1) of the main control unit of the SRAM_C control unit. FIG. 9-2 is a flowchart illustrating the operation (2) of the main control unit of the SRAM_C control unit. FIG. 10A is a block diagram showing an outline of operation when functioning as an A3 copying machine, and FIG. 10B when operating as a wide-width copying machine. FIG. 11 is a block diagram showing image processing parameter setting processing of a conventional controller image processing unit.

  Exemplary embodiments of an image processing apparatus, an image processing method, and a program according to the present invention will be explained below in detail with reference to the accompanying drawings.

(Embodiment)
The present invention has the following characteristics in the memory control of an image processing apparatus that processes images having different main scanning sizes with the same apparatus, such as an A3 multifunction apparatus and a wide multifunction apparatus. The SRAM used as the line memory in the A3 multifunction peripheral is divided into two in the wide multifunction peripheral and used as a toggle buffer for writing to or reading from the external DDR. Note that DDR is an abbreviation of Double-Data-Rate, and is a kind of DRAM (Dynamic Random Access Memory) standard composed of semiconductor integrated circuits. It is used for a main storage device of a computer.

  In the present specification, A3 is an A size having a paper size of 297 × 420 mm, and A0 is an A size having a paper size of 841 × 1189 mm, and will be simply referred to as A3 and A0 hereinafter. In this embodiment, A3 (297 mm) is assumed in the main scanning direction of the narrow-width multifunction peripheral, and a resolution of 600 dpi is taken as an example. In this embodiment, an A3 size is taken as an example of a narrow-width multifunction peripheral and an A0 size is taken as an example of a wide-width multifunction peripheral, but the present invention is not limited to this size.

  FIG. 1 is a block diagram showing an overall configuration of an image forming apparatus 100 according to the present embodiment. The scanner 101 is a device that optically reads a document to be imaged. As the scanner 101, a color image scanner or the like is used. The original is scanned in the main and sub-scans, the image of the original is read at a predetermined resolution, and RGB color image signals are output to the scanner image processing unit 102.

  Due to the difference in characteristics of a CCD (Charge Coupled Device) used in the reading apparatus, the characteristics of data entering the scanner image processing unit 102 are various. The scanner characteristic correcting unit 103 of the scanner image processing unit 102 performs processing for correcting this characteristic. For example, shading correction, γ conversion, filter processing, color conversion, and the like. The color conversion performed here is conversion from RGB (R (red), G (green), B (blue)) to CMYK (C (cyan), M (magenta), Y (yellow), K (black))). Rather, it is a conversion from RGB to RGB. The scanner image processing unit 102 includes a DMA controller (not shown). The scanner image processing unit 102 includes an output control unit (PCIe End Point) 104 that outputs data. DMA is an abbreviation for Direct Memory Access.

  The controller image processing unit 105 includes an input control unit 106, an image processing unit 107, a storage control unit 108, and a CPU IF 109. An input control unit (PCIe Root Complex) 106 receives data from the scanner image processing unit 102. The image processing unit 107 performs various image processing suitable for the output form. The accumulation control unit 108 performs accumulation in an HDD (Hard Disk Drive) 110 and reading from the HDD 110. A CPU (Central Processing Unit) IF (PCIe End Point) 109 controls the entire image transfer. The controller image processing unit 105 is composed of a single ASIC. Alternatively, at least the image processing unit 107 is configured by a single ASIC.

  The image processing unit 107 has file processing, scaling processing, and gradation processing functions. Each controller includes a DMA controller (not shown). The image output from the controller image processing unit 105 is output from the CPU 111 to the plotter 119 via the plotter image processing unit 116 corresponding to the configuration of the plotter 119 in the case of copying. The image output from the controller image processing unit 105 can be directly output from the CPU 111 to the network in the case of the use of the scanner 101.

  A ROM 113, a RAM 114, and a main memory 115 are connected to the CPU 111. Further, the CPU 111 is provided with a PCIe Root 112 a connected to the CPU IF 109 and a PCIe Root 112 b connected to the PCIe Endp 118 of the plotter image processing unit 116.

  The plotter image processing unit 116 includes a plurality of output control units 117 that transmit CMYK images to the plotter 119 at different timings. Each output control unit 117 includes a DMA controller (not shown).

  The plotter 119 is, for example, a color laser printer in which units based on an electrophotographic process are arranged, and forms a color image on a recording sheet in accordance with image data sent from the plotter image processing unit 116.

  FIG. 2 is a block diagram illustrating a configuration of the controller image processing unit 105. The controller image processing unit 105 includes an input control unit 120, a filter processing unit 121, a scaling processing unit 122, a gradation processing unit 123, a memory arbiter 124, and a DDR3 controller 125. The controller image processing unit 105 includes an image processing data DMAC 126, a bus arbiter 127, a CPU IF (PCIe End Point) 128, an accumulated data DMAC 129, and an HDD IF 130.

  An input control unit (PCIe Root Complex) 120 receives data from the scanner image processing unit 102. The HDD I / F 130 controls the HDD 110 that is a storage device. Note that PCIe is an abbreviation for PCI (Peripheral Component Interconnect) express.

  The input control unit 120 exchanges image data with the scanner image processing unit 102 connected via PCI Express. The input control unit 120 receives a signal capable of recognizing whether the main scanning size is A3 size or A0 size. The input control unit 120 includes a main scanning size recognition unit 120a that recognizes whether the main scanning size is A3 size or A0 size based on the signal.

  As the main scanning size recognition, a function of “automatic size detection” or “size designation” on an operation unit (not shown) can be used. Alternatively, the main scanning size may be recognized from information input by the size detection sensor when the scanner 101 reads an original. Alternatively, a mode setting terminal for inputting a mode setting signal of A0 size / A3 size may be provided in the controller image processing unit 105 for recognition of the main scanning size.

  As a signal capable of recognizing the main scanning size, for example, there is data added to the image data sent from the scanner image processing unit 102. The size signal includes a signal based on size detection by the scanner 101, a signal based on manual input from an input key of an operation unit (not shown), and the like. In the case where the image forming apparatus is connected to an external device such as a PC and prints image data sent from the external device, a size signal is included together with the image data.

  The image processing data DMAC 126 and the accumulated data DMAC 129 write image data to the CPU 111 via a bus arbiter 127 and a CPU IF (PCIe End Point) 128 as a bus master. A CPU IF (PCIe End Point) 128 transmits and receives image data to and from the CPU 111 connected via PCI Express.

  The filter processing unit 121 performs processing such as smoothing and edge enhancement on the input image data, and performs image correction suitable for each of the character part and the picture part. The scaling processing unit 122 enlarges / reduces input image data in the main scanning direction or the sub-scanning direction. The gradation processing unit 123 performs gradation processing on the input CMYK image data and outputs it.

  The filter processing unit 121 includes a data processing unit 131 that performs operations for image correction processing and deformation processing, and an SRAM (external DDR3) with built-in ASIC or a memory control unit 132 that controls an external memory. The scaling processing unit 122 is also a data processing unit 133 that performs calculations for executing image data correction processing and deformation processing, an ASIC built-in SRAM, or a memory that controls an external memory (external DDR3). A control unit 134 is included. Also, the gradation processing unit 123 is a memory that controls the data processing unit 135 that performs operations for executing correction processing and deformation processing of image data, SRAM that includes the ASIC, or external memory (external DDR3). A control unit 136 is included. SRAM is an abbreviation for Static Random Access Memory.

  In order to perform image processing such as the filter processing unit 121, the scaling processing unit 122, and the gradation processing unit 123, a line buffer corresponding to the main scanning size is required. When performing wide (A0) size image processing, a wide (A0) size line buffer is required. In this case, each image processing unit has only an A3 size memory capacity, and DDR3 connected to the outside of the controller image processing unit 105 via the memory arbiter 124 and the DDR3 controller 125 is used as a line buffer. .

  Note that DDR3 is an abbreviation for Double-Data-Rate3. DDR3 is a kind of DRAM standard composed of a semiconductor integrated circuit called DDR3 SDRAM (Synchronous Dynamic Access Memory).

  FIG. 3 is a block diagram showing a configuration of a memory control unit in various image processing blocks. Although the filter processing unit 121 is described in FIG. 3, the scaling processing unit 122 and the gradation processing unit 123 have the same configuration. The memory control unit 132 is a block that controls a line buffer corresponding to the main scanning size necessary for image processing. Three line buffers of A3 size are built in the memory control unit 132. The SRAM_A1, A2, B2, C1, and C2 SRAMs in FIG. 3 are half the size of the A3 size, and the total size of the SRAM_A1, A2, B2, C1, and C2 SRAMs is three lines. Each SRAM is controlled in line units. That is, SRAM_A1 and A2 are controlled by the SRAM_A control unit 140, SRAM_B1 and B2 are controlled by the SRAM_B control unit 141, and SRAM_C1 and C2 are controlled by the SRAM_C control unit 142.

  Before describing each SRAM control unit 140, 141, 142, how to use the memory when the main scanning size is A3 size or A0 size will be described. That is, a description will be given of write / read processing of image data of each built-in SRAM and external DDR3.

  Here, how to use the memory will be described by taking as an example a filter process that refers to three pixels in the sub-scanning direction. 4A and 4B are flowcharts illustrating the operation when the main scanning size is the A3 size. This operation is executed by the SRAM control units 140, 141, and 142 constituting the memory control unit 132 shown in FIG. First, the SRAM control unit 140 stores the image data of the first line in the SRAM_A1 and the SRAM_A2 (Step S1). Next, the SRAM control unit 141 stores the image data of the second line in the SRAM_B1 and the SRAM_B2 (Step S2). Next, the SRAM control unit 142 stores the image data of the third line in the SRAM_C1 and the SRAM_C2. At the same time, the SRAM control unit 142 reads the stored first line image data (SRAM_A1 and SRAM_A2) and the second line image data (SRAM_B1 and SRAM_B2). The read image data of the first line and the second line are used for calculation together with the image data of the third line inputted simultaneously (step S3).

  When the image data for the fourth line is input, the image data for the second line (SRAM_B1 and SRAM_B2) and the image data for the third line (SRAM_C1 and SRAM_C2) that have already been stored are read at the same time as they are stored in SRAM_A1 and SRAM_A2. The read image data of the second line and the third line are used for the calculation together with the image data of the fourth line inputted simultaneously (step S4). When inputting the image data for the fifth line, the image data for the third line (SRAM_C1 and SRAM_C2) and the image data for the fourth line (SRAM_A1 and SRAM_A2) that have already been stored are read at the same time they are stored in SRAM_B1 and SRAM_B2. The read image data of the third line and the fourth line are used for the calculation together with the image data of the fifth line inputted simultaneously (step S5). For subsequent lines, the operations from step S3 to step S5 are repeated.

  Similarly, FIG. 5 shows how to use the memory when the main scanning size is the wide (A0) size. In FIG. 4 described above, when the main scanning size is A3, three line data are stored in the SRAM built in the memory control unit 132. On the other hand, at the time of the wide (A0) size, the three line data are stored in the DDR 3 connected to the outside of the controller image processing unit 105. When the main scanning size is A3 size, the SRAM of the memory control unit 132 used as a line buffer is used, and when the main scanning size is wide (A0) size, a buffer for writing or reading access to the external DDR3 is provided. Used as a toggle buffer. In FIG. 5, SRAM_A1, A2 and SRAM_B1, B2 are DDR read-only SRAMs, and SRAM_C1, C2 are DDR write-only SDRAMs.

  5A and 5B are flowcharts illustrating a memory control method when the main scanning size is A0 size. This operation is executed by the SRAM control units 140, 141, and 142 constituting the memory control unit 132 shown in FIG. As shown in FIGS. 5A and 5B, memory read DMACs 145 and 146 and a memory write DMAC 147 are provided in the preceding stage of the memory arbiter 124. DMAC is an abbreviation for Direct Memory Access Controller.

  First, the image data of the first line is written to SRAM_A1 and SRAM_C1 (step S11). Next, when all the areas of SRAM_A1 and SRAM_C1 have been written, the image data is written to SRAM_C2, and at the same time, the image data stored in SRAM_C1 is read and written to external DDR3 (step S12). The SRAM read processing is executed via the memory read DMACs 145 and 146, and the DDR3 write processing is executed via the memory write DMAC 147. Here, the reason why image data is stored not only in SRAM_C1 but also in SRAM_A1 in step S11 is as follows. This is because the memory read data at the head of the first line is prepared in the SRAM in advance in order to shorten the read access time to the external DDR3 at the time of memory read at the head of the first line.

  When writing to the entire area of the SRAM_C2 is completed, the image data is written to the SRAM_C1, and at the same time, the image data stored in the SRAM_C2 is read and written to the external DDR3 (step S13). Three times the A3 size is the A0 size, and as described above, the total size of the SRAM_C1 and the SRAM_C2 is the A3 size. Therefore, when step S12 → step S13 → step S12 is subsequently performed, the input of the image data for the first line of A0 size is completed.

  Next, the image data of the second line is written to SRAM_B1 and SRAM_C1, and at the same time, the image data stored in SRAM_C2 is read and written to the external DDR3 (step S14). Here, the reason why image data is stored not only in SRAM_C1 but also in SRAM_B1 in step S14 is as follows. This is because the memory read data at the head of the second line is prepared in the SRAM in advance in order to shorten the read access time to the external DDR3 at the time of memory read at the head of the second line.

  Thereafter, when step S12 → step S13 → step S12 → step S13 → step S14 is executed, the input of the image data for the second line of A0 size is completed.

  Next, the image data of the third line is written to the SRAM_C1, and at the same time, the image data stored in the SRAM_C2 is read and written to the external DDR3. At the same time, the image data stored in the SRAM_A1 and the SRAM_B1 are read. The read image data of SRAM_A1 and SRAM_B1 (that is, the image data of the first line and the second line) is used for calculation together with the image data of the third line that is input simultaneously. At the same time, the image data stored in the external DDR3 is read and written to SRAM_A2 and SRAM_B2 (step S15). A series of processing of DDR read and SRAM write is performed via the memory read DMACs 145 and 146.

  When the entire area of SRAM_C1 is written, the image data is written to SRAM_C2, and at the same time, the image data stored in SRAM_C1 is read and written to external DDR3. At the same time, the image data stored in the SRAM_A2 and the SRAM_B2 are read. The read image data of SRAM_A2 and SRAM_B2 (that is, the image data of the first line and the second line) is used for calculation together with the image data of the third line that is input simultaneously. At the same time, the image data stored in the external DDR3 is read and written to SRAM_A1 and SRAM_B1 (step S16).

  Thereafter, when step S15 → step S16 → step S15 → step S16 is performed, the input of the image data of the third line of A0 size is completed. Similarly, the fourth and subsequent lines are repeatedly executed in steps S15 and S16.

  FIG. 6 is a block diagram showing a configuration of the SRAM_A control unit 140 inside the memory control unit 132. The SRAM_B control unit 141 has the same configuration. The SRAM_A control unit 140 is a block that performs write / read access control to the SRAMs built in the SRAM_A 1 and A 2 or the external DDR 3 in response to a memory write / read request from the data processing unit 131. The SRAM_A control unit 140 includes a main control unit 145, a memory read DMAC 146, and selectors (sel) 147 and 148.

  In FIG. 6, the SRAM_A1 write signal from the memory read DMAC 146 and the SRAM_A1 read signal from the main control unit 145 are input to the selector 147. The selector 148 receives an SRAM_A2 write signal from the memory read DMAC 146 and an SRAM_A2 read signal from the main control unit 145. The selectors 147 and 148 output data to the SRAM_A1 and A1 via the SRAM_A1I / F and SRAM_A2I / F according to the above signals.

  As described above, when the main scanning size handled by the image processing unit 107 is A3 size, since the built-in SRAM functions as a line memory, the SRAM_A control unit 140 controls the SRAM_A1 and A2 as line memories. On the other hand, when the main scanning size handled by the image processing unit 107 is a wide (A0) size, the line memory is provided in the external DDR3, so the built-in SRAM serves as a speed buffer buffer for read access to the external DDR3. Function. The memory read DMAC 146 performs DMA transfer from the external DDR3 to the SRAM in which the SRAM_A1 and A2 are built, and controls the memory read DMAC 146 and data transfer between the data processing unit 131 and the built-in SRAM. 145 controls.

  FIG. 7 is a block diagram showing a configuration of the SRAM_C control unit 142 inside the memory control unit 132. The SRAM_C control unit 142 includes a main control unit 150, a memory write DMAC 151, and selectors (sel) 152 and 153.

  In FIG. 7, an SRAM_C1 read signal from the memory write DMAC 151 and an SRAM_C1 write signal from the main control unit 145 are input to the selector 152. The selector 153 receives the SRAM_C2 read signal from the memory write DMAC 151 and the SRAM_C2 write signal from the main control unit 145. The selectors 152 and 153 output data to the SRAM_C1 and C1 via the SRAM_C1I / F and SRAM_C2I / F according to the above signals. Further, the main control unit 150 outputs an SRAM_A1 write signal to the SRAM_A1 I / F and an SRAM_B1 write signal to the SRAM_B1 I / F. The SRAM_C control unit 142 outputs data to each DDR3, SRAM_C1, C2, A1, and B1 by outputting the above signal to each I / F.

  The SRAM_C control unit 142 is a block that performs write / read access control to the SRAMs in the SRAM_C 1 and C 2 or the external DDR 3 in response to a memory write / read request from the data processing unit 131. As described above, when the main scanning size handled by the image processing unit 107 is A3 size, since the built-in SRAM functions as a line memory, the SRAM_C control unit 142 controls the SRAM_C1 and C2 as line memories. When the main scanning size handled by the image processing unit 107 is wide (A0) size, the line memory is provided in the external DDR3, so that the built-in SRAM functions as a speed buffer buffer for write access to the external DDR3. . The memory write DMAC 151 performs DMA transfer from the SRAM in which the SRAM_C1 and C2 are built to the external DDR3, and controls the memory write DMAC 151 and data transfer between the data processing unit 131 and the built-in SRAM. 150 controls.

  8A and 8B are flowcharts illustrating the operation of the main control unit 145 of the SRAM_A control unit 140. The operation of the SRAM_B control unit 141 is performed in the same manner as this control. 8A, first, in step S21, the presence or absence of an SRAM read request is determined (standby) (step S21-1). If there is an SRAM read request, the SRAM_A1 is read (step S21-2), and the memory read DMAC 146 is activated to perform the transfer source: area [1-3] -2 and the transfer destination SRAM_A2 (step S21). -3). These processes are executed until completion of reading of SRAM_A1 for 3508 words and completion of DMA transfer (step S21-4).

  Note that the above 3508 words are 7016 pixels in terms of A3 (297 mm, resolution 600 dpi), which means that the word size of one SRAM is half that of 3508 words.

  Subsequently, when the reading of SRAM_A1 and the DMA transfer are completed, in step S22, reading of SRAM_A2 and DMA transfer (transfer source: area [1-3] -3, transfer destination SRAM_A1) are performed (step S22-). 1-4). Subsequently, when the reading of SRAM_A2 and the DMA transfer are completed, in step S23, the reading of SRAM_A2 and the DMA transfer (transfer source: area [1-3] -4, transfer destination SRAM_A2) are performed (step S23-). 1-4).

  Subsequently, when the reading of the SRAM_A2 and the DMA transfer are completed, in the step S24, the reading of the SRAM_A2 and the DMA transfer (transfer source: area [1-3] -5, transfer destination SRAM_A1) are performed (step S24-). 1-4). Subsequently, when the reading of the SRAM_A2 is completed and the DMA transfer is completed, the reading of the SRAM_A1 and the DMA transfer (transfer source: area [1-3] -6, transfer destination SRAM_A2) are performed in step S25 (step S25-). 1-4). Subsequently, when the reading of SRAM_A1 and the DMA transfer are completed, in step S26, reading of SRAM_A2 and DMA transfer (transfer source: area [1-3] -1, transfer destination SRAM_A1) are performed (step S26-). 1-4).

  As described above, the main control unit 145 of the SRAM_A control unit 140 sequentially executes the DDR3 read-> SRAM write operation.

  9A and 9B are flowcharts illustrating the operation of the main control unit 150 of the SRAM_C control unit 142. In FIG. 9A, first, the presence / absence of an SRAM write request is determined (standby) (step S31). If there is an SRAM write request, it is next determined whether or not the SRAM 1 is the first write (first line input) (step S32). If it is the first write (input of the first line) of the SRAM 1 in step S32 (determination Yes), the processes of steps S34 and S37 are executed. On the other hand, if it is not the first write (first line input) of the SRAM 1 in step S32 (determination No), it is further determined whether it is the first write (second line input) of the SRAM 2 (step S33). Here, when it is the first write (input of the second line) of the SRAM 2 (determination Yes), steps S35 and S37 are executed. On the other hand, if it is not the first write (second line input) of the SRAM 2 in step S33 (determination No), the processes of steps S36 and S37 are executed.

  In step S34, write processing of SRAM_C1 and SRAM_A1 is executed. In step S35, write processing of SRAM_C1 and SRAM_B1 is executed. In step S36, SRAM_C1 write processing is executed. In step S37, the memory write DMAC 151 is activated and transferred (transfer source: SRAM_C2, transfer destination: area [1-3] -6).

  After executing Steps S34 and S37, it is determined whether writing of 3508 words of SRAM_C1 and 3508 words of SRAM_A1 has been completed (Step S38). After executing steps S35 and S37, it is determined whether 3508 word SRAM_C1 write, 3508 word SRAM_B1 write, and DMA transfer have been completed (step S39). After executing step S36, it is determined whether 3508 words of SRAM_C1 write and DMA transfer have been completed (step S40). When the respective processes are completed in steps S38, S39, and S40 (determination Yes), the following steps S41, S42, S43, S44, and S45 are executed in order.

  In step S41, the following steps S41-1 to S4-4 are executed. It is determined (standby) whether there is an SRAM write request (step S41-1). Next, when there is an SRAM write request, the SRAM_C2 is written (step S41-2) and the memory write DMAC 151 is activated to perform transfer (transfer source: SRAM_C1, transfer destination 1-3] -1) (step S41). -3). These processes are executed until 3508 word SRAM_C2 write completion and DMA transfer are completed (step S41-4).

  Subsequently, in step S42, the following steps S42-1 to S4-4 are executed. It is determined (standby) whether there is an SRAM write request (step S42-1). Next, when there is an SRAM write request, the SRAM_C1 is written (step S42-2), and the memory write DMAC 151 is activated and transferred (transfer source: SRAM_C2, transfer destination: area [1-3] -2). (Step S42-3). These processes are executed until 3508 words of SRAM_C1 are written and DMA transfer is completed (step S42-4).

  Subsequently, in step S43, the following steps S43-1 to S4-4 are executed. It is determined (standby) whether there is an SRAM write request (step S43-1). Next, when there is an SRAM write request, the SRAM_C2 is written (step S43-2), and the memory write DMAC 151 is activated and transferred (transfer source: SRAM_C1, transfer destination: area [1-3] -3). (Step S43-3). These processes are executed until 3508 words of SRAM_C2 are written and DMA transfer is completed (step S43-4).

  Subsequently, in step S44, the following steps S44-1 to S4-4 are executed. It is determined (standby) whether there is an SRAM write request (step S44-1). Next, when there is an SRAM write request, the SRAM_C1 is written (step S44-2), and the memory write DMAC 151 is activated and transferred (transfer source: SRAM_C2, transfer destination: area [1-3] -4). (Step S44-3). These processes are executed until 3508 words of SRAM_C1 are written and DMA transfer is completed (step S44-4).

  Subsequently, in step S45, the following steps S45-1 to S45-4 are executed. It is determined (standby) whether there is an SRAM write request (step S45-1). Next, when there is an SRAM write request, the SRAM_C2 is written (step S45-2), and the memory write DMAC 151 is activated and transferred (transfer source: SRAM_C1, transfer destination: area [1-3] -5). (Step S44-3). These processes are executed until 3508 words of SRAM_C2 are written and DMA transfer is completed (step S45-4).

  According to the embodiment described above, the following effects can be obtained. This effect will be described with reference to FIG. FIG. 10A shows an outline of the operation when functioning as an A3 copying machine, and FIG. 10B shows the operation when functioning as a wide-width multifunction peripheral. As described above, the controller image processing unit 105 is composed of the same ASIC. Therefore, the same ASIC can be used for the A3 multifunction peripheral and the wide multifunction peripheral, and the transfer speed of the wide (A0) multifunction peripheral can have the same performance as the A3 multifunction peripheral. Further, the line memory access method from the image processing core unit 201 is SRAM access in which both the A3 multifunction peripheral and the wide-width multifunction peripheral are built, and the circuit of the image processing core unit 201 can be shared.

  In addition, the SRAM used as the line memory in the A3 copying machine is divided into two in the wide-width multifunction peripheral and used as a toggle buffer for writing to or reading from the external DDR3. Therefore, the transfer speed of the wide (A0) multifunction device can have the same performance as the A3 multifunction device.

  In addition, the image processing core unit 201 and the SRAM control unit 202 are separated, and the access control to the external DDR 3 is performed by the SRAM control unit 202. For this reason, the line memory access method from the image processing core unit 201 is to access the SRAM incorporated in both the A3 multifunction peripheral and the wide multifunction peripheral, and the circuit of the image processing core unit 201 can be shared.

  Accordingly, the same hardware can be used when processing images having different main scanning sizes, such as a narrow-width multifunction device such as A3 size and a wide-width multifunction device such as A0 size, and the wide-width multifunction device. The transfer speed can be equivalent to that of a narrow multifunction peripheral.

  By the way, the program executed in the present embodiment is provided by being incorporated in the ROM 113 in advance, but is not limited to this. The program executed in this embodiment may be recorded on a computer-readable recording medium and provided as a computer program product. For example, an installable or executable file is recorded and provided on a computer-readable recording medium such as a CD-ROM, a flexible disk (FD), a CD-R, or a DVD (Digital Versatile Disk). Also good.

  Further, the program executed in the present embodiment may be provided by being stored on a computer connected to a network such as the Internet and downloaded via the network. In addition, the program executed in the present embodiment may be configured to be provided or distributed via a network such as the Internet.

  The program executed in the present embodiment has a module configuration including the main scanning size recognition unit 120a, the data processing units 131, 133, and 135, and the memory control units 132, 134, and 136 described above. As actual hardware, the CPU 111 (processor) reads out the program from the recording medium and executes the program, so that the respective units are loaded onto the main storage device such as the RAM 114. A main scanning size recognition unit 120a, data processing units 131, 133, and 135, and memory control units 132, 134, and 136 are generated on the main storage device.

  In the above-described embodiment, the image forming apparatus has been described as an example. However, the present invention is not limited to this, and another apparatus may be used.

DESCRIPTION OF SYMBOLS 100 Image forming apparatus 105 Controller image processing part 111 CPU
113 ROM
114 RAM
120 Input Control Unit 120a Main Scan Size Recognition Unit 121 Filter Processing Unit 122 Scaling Processing Unit 123 Gradation Processing Unit 124 Memory Arbiter 125 DDR3 Controller 131, 133, 135 Data Processing Unit 132, 134, 136 Memory Control Unit 140 SRAM_A Control Unit 141 SRAM_B control unit 142 SRAM_C control unit 145 Main control unit 146 Memory read DMAC
150 Main control unit 151 Memory write DMAC

JP 2010-147815 A

Claims (6)

A main scanning size recognition unit for recognizing the size of data of the main scanning size of the image to be processed;
A memory control unit that performs switching control of data processing to an internal memory and an external memory according to the size of data of the main scanning size recognized by the main scanning size recognition unit;
A data processing unit for writing and reading data using an internal memory or an external memory switched by the memory control unit;
An image processing apparatus comprising:   The memory control unit switches whether the internal memory is controlled as a line memory or a buffer buffer, and the data processing unit stores the internal memory in a line memory regardless of the main scanning size of an image to be processed. The image processing apparatus according to claim 1, wherein the image processing apparatus is controlled as follows.   When the internal memory is controlled as a speed buffer, the memory control unit stores line data in the external memory and simultaneously stores image data at the head of the line in the internal memory. The image processing apparatus according to claim 1.   3. The image processing apparatus according to claim 1, wherein the internal memory includes two memories each storing half line data with respect to data having a predetermined main scanning size. 4. A main scanning size recognition step for recognizing the data size of the main scanning size of the image to be processed;
A memory control step for controlling switching of data processing to an internal memory and an external memory in accordance with the size of data of the main scanning size recognized by the main scanning size recognition step;
A data processing step of writing and reading data using an internal memory or an external memory switched by the memory control step;
An image processing method comprising: A main scanning size recognition step for recognizing the data size of the main scanning size of the image to be processed;
A memory control step for controlling the switching of data processing to the internal memory and the external memory in accordance with the size of the data of the main scanning size recognized by the main scanning size recognition step;
A data processing step of writing and reading data using an internal memory or an external memory switched by the memory control step;
A program that causes a computer to execute.

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