JP2014175643A - Method for testing semiconductor transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a test method, which makes it easy to, in a test in which a high voltage is applied to a semiconductor transistor, specify a factor causing a failure and an occurrence location of the failure.SOLUTION: A test voltage application circuit 15 including a capacitor 17 is connected to a test device that supplies a test voltage for application to a drain terminal 13 of a transistor 10 to be tested, and one end (node A) of the capacitor 17 is charged to the test voltage. Following this, when a predetermined gate voltage, drain voltage, and source voltage, at which the transistor 10 to be tested assumes an off state, are respectively applied to a gate terminal 11, drain terminal 13, and source terminal 12 of the transistor 10 to be tested, the drain voltage is applied by cutting off the connection between the test voltage application circuit 15 and the test device and connecting one end of the capacitor 17 charged to the test voltage to the drain terminal 13.

Description

  The present invention relates to a test method for a semiconductor transistor, and more particularly to a test method that facilitates identification of a cause of failure by physical analysis after a test in a wafer test or package test of a high-voltage semiconductor transistor such as a power device.

  In a semiconductor circuit having a high voltage withstand voltage specification such as a power device, since a test is performed by applying a high voltage, a high voltage is applied and a large current flows when a short circuit failure occurs. As a result, when the device is in a high power state, the transistor under test and the test jig are significantly destroyed, so that it becomes impossible to easily identify the factor causing the failure and the location where the failure occurs.

  For this reason, the reduction of destruction damage has become an important issue in product development. As a method for reducing the destruction damage, a method is generally used in which a current is limited on the test apparatus side and a current flowing through the transistor under test or the test jig is limited by setting a clamp current value.

  FIG. 8 shows a state of connection between a test apparatus and a transistor under test in a high voltage application test of a general power device. FIG. 9 shows a timing chart when a defect occurs during the high voltage application test. As shown in FIG. 8, each of the drain terminal 13, the source terminal 12, and the gate terminal 11 of the transistor under test 10 is connected to a test apparatus, and each of the drain terminal 13, the source terminal 12, and the gate terminal 11 is connected to the transistor under test. Apply a voltage that turns off. FIG. 9A shows the drain-source voltage waveform, FIG. 9B shows the gate-source voltage waveform, and FIG. 9C shows the drain current waveform.

  If the transistor under test is in an off state, even if a high voltage (for example, several hundred volts or more) is applied between the drain and source, the drain current flows only about several μA as a normal off-leakage current. On the other hand, when a short circuit failure occurs in a state where a high voltage is applied to the drain terminal 13, the current limit of the test apparatus connected to the drain terminal works, and the drain voltage drops. The drain current flows up to a value (clamp current value Iclamp: about several mA) with a current limit, but no more current flows. As a result, the generation of high voltage and large current, which are the cause of the destruction damage, is suppressed, and the destruction damage is reduced.

  However, with the suppression of abnormal current by current clamp, the clamp current value cannot be set smaller than the normal current, and the parasitic capacitance and parasitic inductance of the test jig and wiring between the test equipment and the transistor under test Therefore, the current flowing through the transistor under test cannot be suppressed, and the sufficient destruction damage cannot be reduced. In the above method, it is difficult to suppress the destruction location (occurrence of failure) in the chip to a size of several μm. In order to reduce the destruction damage, it is necessary to interrupt or suppress the current between several tens of nanoseconds to several hundred nanoseconds when a defect occurs.

  There is a method described in Patent Document 1 as a method for reducing breakage damage due to current caused by parasitic capacitance and parasitic inductance between the test apparatus and the transistor under test while completely interrupting the current from the test apparatus. In Patent Document 1, when a transistor switch is provided between the test apparatus and the transistor under test and the abnormality detection unit detects an abnormality, the transistor under test is disconnected from the test apparatus, and the current flowing through the test apparatus flows into the transistor under test. And turning on a transistor connected in parallel with the transistor under test to shunt the current that flows into the transistor under test, thereby preventing excessive current from flowing through the transistor under test. .

JP 2012-127813 A

  However, in order to reduce the breakage damage at abnormal points and realize soft breakage, it is necessary to prevent current from flowing into the transistor under test immediately after the breakage (after several tens of nanoseconds to several hundred nanoseconds) However, it was difficult to realize in tests other than the avalanche test in which abnormal voltage is generated immediately when a defect occurs.

  For example, in the drain leak test, which is a representative item of the high voltage test, an abnormal voltage often does not occur in the drain voltage when a failure occurs. In the technique of Patent Document 1, the transistor connected in parallel with the transistor under test is turned on and tested. A transistor switch attached between the device and the transistor under test cannot be turned off. In order to reduce destruction damage and realize soft destruction, it is important how to reduce the amount of charge flowing into the destruction portion.

  In view of the above situation, the present invention provides a current from a test apparatus that is generated when a semiconductor device such as a power device is subjected to a failure, or a parasitic of a test jig or wiring between the test apparatus and a transistor under test. It is an object of the present invention to provide a test method that suppresses the flow of current due to capacitance and parasitic inductance into a broken portion and makes it easy to identify the factor causing the failure and the location where the failure has occurred.

A test method according to the present invention for achieving the above object is a test method for detecting a reliability defect in a wafer test or a package test of a semiconductor transistor,
Connecting a test voltage application circuit comprising a capacitor to a test device for supplying a test voltage to be applied to the drain terminal of the transistor under test, and charging one end of the capacitor to the test voltage;
A second step of applying a first gate voltage, a first drain voltage, and a first source voltage that turn off the predetermined transistor under test to the gate terminal, the drain terminal, and the source terminal of the transistor under test, respectively; ,
After the second step, a third step of detecting a voltage of the drain terminal or a drain current flowing through the drain terminal,
In the second step, the first drain voltage is applied by disconnecting the connection between the test voltage application circuit and the test apparatus and connecting the one end of the charged capacitor to the drain terminal. First feature.

The test method according to the first aspect of the present invention further includes:
In the third step, the test apparatus and the drain terminal are directly connected, and a predetermined transistor under test is turned off at each of the gate terminal, the drain terminal, and the source terminal of the transistor under test. A second feature is a step of applying a two-gate voltage, a second drain voltage, and a second source voltage and detecting a drain current flowing in the drain terminal of the transistor under test.

The test method according to the second aspect of the present invention further includes:
The voltage difference between the first drain voltage applied to the transistor under test in the second step and the first source voltage is equal to the second drain voltage applied to the transistor under test in the third step. A third feature is that the difference is equal to or greater than the voltage difference between the second source voltages.

The test method according to the third aspect of the present invention further includes:
After the third step, the method includes a fourth step of disconnecting the connection between the test apparatus and the drain terminal of the transistor under test.
The first to fourth steps are repeatedly performed a plurality of times,
The fourth feature is that the voltage difference between the first drain voltage and the first source voltage applied to the transistor under test is gradually increased in the plurality of second steps.

The test method according to the present invention having any one of the first to third features further includes:
The test voltage application circuit includes a resistor,
When the first drain voltage is applied in the second step, the one end of the charged capacitor and the drain terminal of the transistor under test are connected via the resistor,
At the time of applying the first drain voltage in the second step,
When the transistor under test is a good product, the first drain voltage rises to a constant voltage determined by the test voltage. When the transistor under test is a defective product, the first drain voltage rises to the constant voltage. A fifth feature is that the resistance value of the resistor is set so that the first drain voltage starts to decrease in the middle of the rise of the voltage.

The test method according to the present invention having any one of the first to fifth features further includes:
A switch for switching the connection between the test device and the drain terminal via the test voltage application circuit or a direct connection without going through the test voltage application circuit;
It is preferable to use the switch to change the supply destination of the test voltage applied to the drain terminal from the capacitor of the test voltage application circuit to the test apparatus.

The test method according to the present invention having any one of the first to fifth features further includes:
The test voltage application circuit includes a discharge transistor whose drain terminal side is connected to the one end of the capacitor,
It is preferable that the discharge transistor is turned on after a lapse of a predetermined period from the start of application of the first drain voltage in the second step.

  According to the present invention, by applying a voltage to the drain terminal of the transistor under test through a precharged capacitor, the charge flowing from the test apparatus side when a failure occurs in the transistor under test during the high voltage test. The amount can be minimized. As a result, it is possible to prevent the destruction damage from expanding from the location where the failure occurs, and to easily identify the factor causing the failure and the location where the failure occurs when the failure occurs.

The flowchart which shows the structural example of the test method of the reliability failure based on one Embodiment of this invention. In the test method according to an embodiment of the present invention, a timing chart showing changes in the voltage of the gate terminal, the terminal voltage of the capacitor, and the voltage between the source and drain terminals during the test when the transistor under test is a non-defective product In the test method according to an embodiment of the present invention, a timing chart showing changes in the voltage of the gate terminal, the terminal voltage of the capacitor, and the voltage between the source and drain terminals during the test when the transistor under test is a defective product The figure which shows the mode of the connection of the voltage application circuit which applies a high voltage to a drain terminal in the test method which concerns on one Embodiment of this invention. The flowchart which shows an example in the case of performing the high voltage application test method of this invention as one item of a normal wafer test The figure which shows the mode of the change of the voltage applied to a drain terminal in the test method which concerns on one Embodiment of this invention. The flowchart which shows the other example at the time of performing the high voltage application test method of this invention as one item of a normal wafer test Diagram showing the connection between the test equipment and the transistor under test in a high voltage application test for a general power device Timing chart showing changes over time in source-drain voltage, gate-source voltage, and drain current when a failure occurs during a conventional high-voltage application test

<First Embodiment>
Hereinafter, the configuration of a reliability failure test method according to an embodiment of the present invention (hereinafter referred to as “the present invention method 1” as appropriate) will be described in detail with reference to the drawings. A flowchart showing an example of the configuration of the method 1 of the present invention is shown in FIG. In the method of the present invention, a timing chart during a high voltage application test when the transistor under test is a non-defective product is shown in FIG. 2, and a timing chart during a high voltage application test when the transistor under test is a defective product is shown in FIG. . The method 1 of the present invention assumes a reliability test of a power transistor made of a compound semiconductor such as GaN or SiC. However, the method 1 of the present invention is not limited to this. Further, the method 1 of the present invention is not limited to the method shown in the flowchart of FIG.

  FIG. 4 shows a state of connection between a test apparatus and a transistor under test in a high voltage application test of a power device in the method 1 of the present invention.

  In the method 1 of the present invention, first, each of the drain terminal 13, the source terminal 12, and the gate terminal 11 of the transistor under test 10 is connected to the test devices 30a to 30c for each terminal. At this time, the test voltage application circuit 15 is connected between the drain terminal 13 of the transistor under test 10 and the test apparatus 30c (step S100).

  As shown in FIG. 4, a test voltage application circuit 15 is connected via switches 16 and 19 between the drain terminal 13 of the transistor under test 10 and the test apparatus 30 c. The test voltage application circuit 15 includes a capacitor 17, a discharge transistor 18, and a resistor 20. Further, the test apparatus 30 c can be directly connected by the drain terminal 13 of the transistor under test 10 and the switch 21 without going through the test voltage application circuit 15.

  The capacitor 17 has one end (node A in FIG. 4) connected to the output terminal of the test apparatus 30c for supplying a test voltage to be applied to the drain terminal 13 of the transistor under test 10 via the switch 16, and the other end. Is connected to a fixed potential (here, ground potential) lower than the test voltage. The capacitance of the capacitor 17 is minimized to about several pF in accordance with the DC characteristics (Id, Qgd, etc.) of the transistor under test.

  The discharge transistor 18 has a drain terminal connected to the one end (node A) of the capacitor 17 and a source terminal connected to a fixed potential (here, a ground potential) lower than the test voltage. One end of the resistor 20 is connected to the drain terminal 13 of the transistor under test 10 via the switch 19, and the other end is connected to the one end of the capacitor 17 (and the one end of the discharge transistor 18). That is, in the test voltage application circuit 15, the capacitor 17 and the discharge transistor 18 are connected in parallel, and one end on the high voltage side is connected to the test apparatus 30 c via the switch 16, and the switch 19 and the resistor 20. To the drain terminal 13 of the transistor under test 10.

Referring to FIGS. 2 and 3, at time T1, with the test voltage application circuit 15 connected as described above, the switches 19 and 21 are turned off and the switch 16 is turned on (step S101). Thus, the test voltage application circuit 15 is connected to the test apparatus, and the connection between the test apparatus and the transistor under test 10 and the connection between the test voltage application circuit 15 and the transistor under test 10 are disconnected. One end (node A) of the capacitor is charged to a test voltage V ₁ (for example, 600 V) supplied from the test apparatus. A control signal for turning off the discharge transistor 18 is applied to the gate terminal of the discharge transistor 18 via the test apparatus 30d.

  Thereafter, at time T2, a predetermined gate voltage for turning off the transistor under test is applied to the gate terminal 11, and then at time T3, the transistor under test is turned off to the drain terminal 13 and the source terminal 12, respectively. A predetermined drain voltage and source voltage are applied. At this time, the drain voltage is applied to the drain terminal 13 by turning off the switch 16 and turning on the switch 19 so that the connection between the test voltage application device 15 and the test device is disconnected. A charging voltage (node A voltage) is applied (step S102).

At this time, since the resistor 21 is provided between the drain terminal 13 and the capacitor 17, the voltage applied to the drain terminal 13 is slowly increased as shown in FIG. 2 (c) and FIG. 3 (c). Rises and is supplied to the drain terminal 13. By setting the resistance value of the resistor to about 10 kΩ to 100 kΩ, the voltage applied to the drain terminal 13 slowly rises with a time constant of about several hundred nanoseconds. When the transistor under test 10 is a good product, the voltage applied to the drain terminal 13 is constant depending on the capacitance C ₀ of the capacitor 17 and the parasitic capacitance C ₁ of the transistor under test 10 at time T 4 in FIG. The voltage reaches a voltage V ₁ ′ (˜ (C ₁ / (C ₁ + C ₀ )) V ₁ ) in the vicinity of the test voltage V ₁ , and then maintains a constant voltage V ₁ ′. The time constant depends on the capacitance C ₀ of the capacitor 17 (as described above, about several pF), the parasitic capacitance C _{1 of} the transistor under test 10, and the resistance value of the resistor 20.

On the other hand, when a failure occurs in the transistor under test 10, a leak current starts to flow from the broken portion, and the voltage of the drain terminal 13 starts to decrease accordingly. However, since the leakage current is generated by discharging the charge charged in the capacitor 17, the current does not flow beyond the amount of charge charged in the capacitor 17. Since the capacitance of the capacitor 17 is about several pF, the voltage of the drain terminal 13 immediately drops to the same potential as the voltage of the source terminal 12 in a short time of about several tens of nanoseconds to several hundred nanoseconds. To do. Therefore, as shown after time T5 in FIG. 3, the drain voltage applied to the drain terminal 13 does not increase to the constant voltage V ₁ ′, but starts to decrease in the middle of the rise.

Therefore, a voltage drop from V ₁ ′ is applied by applying a voltage to the transistor under test 10 through the capacitor 17 for a predetermined time (about 1 μsec) and detecting the voltage at the drain terminal 13 after the time T4 has elapsed. If the amount is below the set value, it is a non-defective product, and if the voltage drops from V ₁ ′ above the set value, it can be determined as a defective product. When detecting the voltage, for example, the voltage on the path between the resistor 20 and the switch 19 may be detected with the switch 21 turned off.

The resistance value of the resistor 20 rises in the middle of the rise of the voltage at which the voltage at the drain terminal 13 rises to V ₁ ′ when the voltage at the drain terminal 13 slowly rises to V ₁ ′ and a defect occurs. It is set so that a voltage drop occurs immediately. That is, the resistance value of the resistor 21 is set so that a voltage drop occurs immediately when the voltage at the drain terminal 13 reaches a voltage at which breakdown occurs. As a result, it is possible to prevent an excessive voltage equal to or higher than the voltage at which breakdown has occurred from being applied to the transistor under test, and to minimize the breakdown damage at the defective portion. If the resistance value is small, the voltage change at the drain terminal 13 becomes abrupt. Therefore, even if breakdown occurs at 550 V, for example, a voltage of 550 V or more (for example, 600 V) may be applied to the transistor under test 10. This will cause the destruction damage of the defective part to be enlarged. Applying an excessive voltage higher than the voltage at which breakdown occurs to the transistor under test is one of the reasons why it is impossible to suppress damage at a defective portion. However, in Method 1 of the present invention, this can be prevented.

  After applying a voltage to the transistor under test 10 via the capacitor 17 for a predetermined time (about 1 μsec), at time T6 after time T4 has elapsed, the discharge transistor 18 is turned on via the test device 30d, and the capacitor 17 is turned on. The charged charge and the charge stored in the parasitic capacitance 14 of the transistor under test 10 and the parasitic capacitance of the wiring of the test path are discharged (step S103). As a result, the voltage at the drain terminal 13 drops to the same potential as the voltage at the source terminal 12. In the case of a defective product, the voltage drop at the drain terminal 13 has already started from the time when the failure occurred, but it is preferable to turn on the discharge transistor 18 at time T6. There is a case where the discharge of the capacitor 17 is incomplete at time T6 and the voltage of the drain terminal 13 is not completely lowered. In that case, the remaining electric charge stored in the capacitor 17 is released through the discharge transistor 18, whereby the leakage current flowing through the transistor under test 10 is reduced, and as a result, the destruction damage is reduced. In parallel, the test devices 30a and 30b stop the supply of the gate voltage applied to the gate terminal 11 and the supply of the source voltage applied to the source terminal 12, and end the high voltage application test at time T7.

  In FIG. 5, the high voltage application test described above is executed as one item of a normal wafer test, the damage damage of defective products of the high voltage test that occurs during the wafer test execution is reduced, and the wafer test failure analysis is facilitated. An example of a test flow is shown. The soft destructive test process (step S203: process A) in FIG. 5 corresponds to steps S101 to S103 of the method 1 of the present invention.

  Usually, in the wafer test, after the Kelvin test (contact confirmation process: step S201) is performed, an off-leak test with a low voltage (about 10 V) is performed (step S202). Thereafter, a high voltage is applied between the source terminal 12 and the drain terminal 13 while the transistor under test 10 is maintained in the OFF state, and a soft breakdown test (step S203: step A) is performed. In this soft breakdown test, as described above, the test voltage application circuit 15 is connected between the test apparatus 30c and the drain terminal of the transistor under test 10, and a predetermined high voltage (for example, 600V) is passed through the charged capacitor 17. Is applied to the drain terminal 13 of the transistor under test 10.

  Thereafter, the low-voltage off-leak test is performed again (step S204: step B). At this time, the switch 19 of the test voltage application circuit 15 is turned off, the switch 21 is turned on, and the test device 30c and the drain terminal of the transistor under test 10 are directly connected. Then, while applying a low voltage of about 10 V between the source terminal 12 and the drain terminal 13, the transistor under test 10 is set to an off state, and the test apparatus 30c generates a drain current that flows through the drain terminal 13 of the transistor under test 10. Detect. By detecting the magnitude of the drain current at this time, it can be determined whether a defect has occurred in the immediately preceding soft breakdown test step.

  If the drain current is normal in step S204, then, in step S205 and subsequent steps, normal wafer tests such as a Vth test (a step for checking whether the threshold voltage is within the set range) and a Yfs test (a step for checking the gain) are continued. Implement the item. By continuously executing these normal wafer test items and the high voltage application test according to the present invention, it is possible to reduce the destruction damage of defective products of the high voltage application test that occur during the wafer test execution.

  As described above, in the method 1 of the present invention, a high voltage application test is performed by applying a voltage to the drain terminal 13 of the transistor under test 10 through the capacitor 17 charged in advance. As a result, the amount of charge flowing from the test apparatus side when a failure occurs in the transistor under test 10 can be suppressed. As a result, it is possible to prevent the destruction damage from expanding from the failure occurrence location, and to easily identify the factor causing the failure and the failure occurrence location when the failure occurs.

  Further, as described above, by appropriately setting the resistance value of the resistor 20, when a breakdown occurs, it is possible to prevent an excessive voltage higher than the voltage at which the breakdown has occurred from being applied to the transistor under test. The destruction damage of the defective part can be minimized.

  Further, the discharge transistor 18 is connected to the charged capacitor 17 so that the charge charged in the capacitor 17 is discharged and does not flow into the transistor under test 10. As a result, the amount of charge flowing into the transistor under test 10 can be limited to be equal to or less than the charge amount of the capacitor 17.

Second Embodiment
Hereinafter, the configuration of a reliability failure test method according to an embodiment of the present invention (hereinafter referred to as “the present invention method 2” as appropriate) will be described in detail with reference to the drawings. The method 2 according to the present invention is different from the method 1 according to the present invention in that the test voltage application circuit 15 shown in FIG. .

  FIG. 6 shows a change in voltage applied to the drain terminal 13 of the transistor under test 10 in the method 2 of the present invention. In this case, an excessive voltage is applied to the transistor under test by increasing the applied voltage in a predetermined voltage step (for example, +10 V) instead of applying a high voltage (for example, 600 V) to the drain terminal 13 from the beginning. It is not applied.

  As shown in FIG. 6, in the method 2 of the present invention, the step of applying a voltage to the drain terminal 13 of the transistor under test 10 has two steps, A and B, and the steps A and B are alternately performed. Run repeatedly. The process A is the same as steps S101 to S103 of the method 1 of the present invention. The test voltage application circuit 15 is connected between the test device 30c and the drain terminal of the transistor under test 10 and predetermined through the charged capacitor 17. Is applied to the drain terminal 13 of the transistor under test 10.

  After step A, in step B, the switch 19 of the test voltage application circuit 15 is turned off, the switch 21 is turned on, and the test device 30c and the drain terminal of the transistor under test 10 are directly connected. Then, while applying a low voltage of about 10 V between the source terminal 12 and the drain terminal 13, the transistor under test 10 is set to an off state, and the test apparatus 30c generates a drain current that flows through the drain terminal 13 of the transistor under test 10. Detect. By detecting the magnitude of this drain current, it is confirmed whether or not a defect (destruction) has occurred in the process A. If the drain current is abnormal, it is determined that a defect has occurred and the test is terminated.

If no defect (destruction) has occurred, the switch 21 is turned off, and the connection between the test apparatus and the drain terminal 13 of the transistor under test 10 is disconnected. Thereafter, the switch 16 is turned on and the process A is performed again. That is, a predetermined high voltage is applied to the drain terminal 13 of the transistor under test 10 via the charged capacitor 17. At this time, the test voltages V ₁ to be applied to charge the capacitor 17, to be higher than the test voltages V ₁ in the immediately preceding step A, is gradually increased at a predetermined voltage step. As a result, when the process A is executed a plurality of times, the voltage applied between the source terminal 12 and the drain terminal 13 of the transistor under test 10 in each process A is, for example, from 10 V to 600 V, as shown in FIG. It gradually increases in increments of + 10V. On the other hand, the voltage applied between the source terminal 12 and the drain terminal 13 of the transistor under test 10 in the process B is a constant voltage in the plurality of processes B and is equal to or lower than the applied voltage in the process A.

  Thus, in step A, the voltage applied through the capacitor 17 is delayed by the resistor 20 by gradually increasing the high voltage applied between the source terminal 12 and the drain terminal 13 of the transistor under test 10. There is no need. In this case, the resistor 20 may be a small value of 10Ω or less. Alternatively, the resistor 20 may not be provided.

FIG. 7 shows an example of a test flow when the high voltage application test of the method 2 of the present invention is executed as one item of a normal wafer test. After execution of the Kelvin test (contact confirmation step: step S301) and the off-leak test (step S302) of low voltage (about 10V),
Setting the initial value of the test voltages V ₁ to be applied with a high voltage application test (step S303). Thereafter, while maintaining the transistor under test 10 in the OFF state, a high voltage is applied between the source terminal 12 and the drain terminal 13 via the charged capacitor 17 to perform a soft breakdown test (step S304: corresponding to step A). To implement. This step is the same as step S203 in FIG.

  Thereafter, the low-voltage off-leak test is performed again (step S305: corresponding to step B). This process is the same as step S204 in FIG. While applying a low voltage of about 10 V between the source terminal 12 and the drain terminal 13, the transistor under test 10 is set to the OFF state, and the test apparatus 30 c detects the drain current flowing through the drain terminal 13 of the transistor under test 10. Then, the presence / absence of failure (destruction) of the transistor under test 10 is determined. When the transistor under test 10 is defective, the subsequent test process is not executed.

If the drain current is normal in step S305, subsequently, the voltage step of the set value of the predetermined test voltage _{V 1} (e.g., + 10V) by increasing (step S307), the process returns to step S304, the test voltage of higher voltage by using the V _1, again to perform a soft destruction test.

Thus multiple soft breakdown test (step S304) and the low voltage offleak test (the step S305) are alternately repeated while increasing the test voltage V _1. Test voltage _{V 1} is equal to or greater than a predetermined upper limit set value (branch YES content in step S306), and terminates the high-voltage application test, followed by Vth test (step S308), and Yfs test (gain confirmation process), etc. Conduct normal wafer test items.

  Other configurations of the method 2 of the present invention (for example, the operation of the discharge transistor 18) are the same as those of the method 1 of the present invention, and a detailed description thereof is omitted.

  As described above, in the method 2 of the present invention, similarly to the method 1 of the present invention, a voltage is applied to the drain terminal 13 of the transistor under test 10 through the capacitor 17 which has been charged in advance, and a high voltage application test is performed. When a failure occurs in the transistor 10, the amount of charge flowing from the test apparatus side can be suppressed. As a result, it is possible to prevent the destruction damage from expanding from the failure occurrence location, and to easily identify the factor causing the failure and the failure occurrence location when the failure occurs.

  In addition, a breakdown occurred when a breakdown occurred by performing a plurality of high voltage application tests while gradually increasing the high voltage applied to the drain terminal 13 of the transistor under test 10 via the capacitor 17. It is possible to prevent an excessive voltage higher than the voltage from being applied to the transistor under test, and to minimize the destruction damage of the defective portion.

  In the above embodiment, the charge stored in the capacitor 17 and the charge stored in the parasitic capacitance 14 of the transistor under test 10 are calculated at step S103 in FIG. 1 and time T6 in FIG. 2 (FIG. 3). In this configuration, discharge is performed using the discharge transistor 18 provided in the test voltage application circuit 15. However, instead of using the discharge transistor 18, the switch 19 is turned off and the switch 21 is turned on at time T6, and the same potential as that of the source terminal 12 is applied to the drain terminal 13 of the transistor under test 10 via the test device 30c. A configuration is also conceivable in which the charge stored in the parasitic capacitance 14 of the test transistor 10 is discharged.

Therefore, in the above-described embodiment, the discharge transistor is provided in the test voltage application circuit 15, but it may be provided in the test apparatus 30c. In this case, by turning off the switch 19 and turning on the switch 21 at time T6, the capacitor 17 is not discharged, and the state of charge at time T6 is maintained after time T6. Thereafter, when performing the soft breakdown test again, the switch 16 is turned on again, the capacitor 17 is recharged to the test voltage V _1.

  The present invention can be used as a test method for a semiconductor device, and in particular, can be suitably used as a reliability test method for a semiconductor transistor having a high breakdown voltage specification such as a power device made of a compound semiconductor.

1: Test method according to an embodiment of the present invention (method of the present invention)
10: Transistor under test 11: Gate terminal 12: Source terminal 13: Drain terminal 14: Parasitic capacitance of transistor under test 15: Test voltage application circuit 16, 19, 21: Switch 17: Capacitor 18: Discharge transistor 20: Resistor 30a ˜30d: Test apparatus

Claims (5)

A test method for detecting a reliability defect in a wafer test or a package test of a semiconductor transistor,
Connecting a test voltage application circuit comprising a capacitor to a test device for supplying a test voltage to be applied to the drain terminal of the transistor under test, and charging one end of the capacitor to the test voltage;
A second step of applying a first gate voltage, a first drain voltage, and a first source voltage that turn off the predetermined transistor under test to the gate terminal, the drain terminal, and the source terminal of the transistor under test, respectively; ,
After the second step, a third step of detecting a voltage of the drain terminal or a drain current flowing through the drain terminal,
In the second step, the first drain voltage is applied by disconnecting the connection between the test voltage application circuit and the test apparatus and connecting the one end of the charged capacitor to the drain terminal. Characteristic test method.   In the third step, the test apparatus and the drain terminal are directly connected, and a predetermined transistor under test is turned off at each of the gate terminal, the drain terminal, and the source terminal of the transistor under test. 2. The test method according to claim 1, comprising applying a two-gate voltage, a second drain voltage, and a second source voltage, and detecting a drain current flowing through the drain terminal of the transistor under test. .   The voltage difference between the first drain voltage applied to the transistor under test in the second step and the first source voltage is equal to the second drain voltage applied to the transistor under test in the third step. The test method according to claim 2, wherein the voltage difference is greater than or equal to a voltage difference between the second source voltages. After the third step, the method includes a fourth step of disconnecting the connection between the test apparatus and the drain terminal of the transistor under test.
The first to fourth steps are repeatedly performed a plurality of times,
4. The test according to claim 3, wherein in the plurality of second steps, a voltage difference between the first drain voltage and the first source voltage applied to the transistor under test is gradually increased. Method. The test voltage application circuit includes a resistor,
When the first drain voltage is applied in the second step, the one end of the charged capacitor and the drain terminal of the transistor under test are connected via the resistor,
At the time of applying the first drain voltage in the second step,
When the transistor under test is a good product, the first drain voltage rises to a constant voltage determined by the test voltage. When the transistor under test is a defective product, the first drain voltage rises to the constant voltage. 5. The test method according to claim 1, wherein a resistance value of the resistor is set so that the first drain voltage starts to decrease in the middle of a voltage rise. 6. .

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