JP2014160990A - D/a converter and delta-sigma d/a converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a low distortion and high S/N ratio D/A converter.SOLUTION: During a first period, each input segment unit (IU1m (m=1-N)) outputs current signals depending on input digital data (Dm), and terminals (Iout+, Iout-) are connected to an inverting input terminal and a non-inverting input terminal of a differential operational amplifier (100) and the terminals (Iout+, Iout-) are disconnected from each other to produce differential analog signals that are the sums of the current signals output from each input segment unit. During a second period, the current signal outputs are stopped, the terminals (Iout+, Iout-) are disconnected from the inverting input terminal and non-inverting input terminal of the differential operational amplifier (100) and the terminals (Iout+, Iout-) are connected to each other, so that capacitive elements (Cfb1, Cfb2) connected between a non-inverting output terminal and the inverting input terminal and between an inverting output terminal and the non-inverting input terminal of the differential operational amplifier (100) hold signal values of the differential analog signals at the same values as in the first period.

Description

  The present invention relates to a D / A (digital / analog) converter and a delta-sigma type D / A converter for converting a given digital signal into an analog signal, which is an analog signal having a low distortion and a high S / N ratio. The present invention relates to an output D / A converter and a delta-sigma D / A converter.

  Conventionally, a processing unit that performs dynamic element matching processing on a multi-bit digital signal and a plurality of elements corresponding to each bit of the digital signal subjected to dynamic element matching processing by the processing unit are operated. A multi-bit D / A converter including a D / A converter that outputs an analog signal has been proposed (see, for example, Patent Document 1).

In such a multi-bit D / A converter, for example, a D / A converter (50) having a circuit configuration shown in FIG. 7 is used.
The D / A converter (50) includes an input stage (51) and an output stage (52).
The input stage (51) includes a plurality of input segment units (IU51 to IU5N). Since these input segment units (IU51 to IU5N) have the same configuration, the configuration of the input segment unit (IU5m (m = 1 to N)) will be described here.

  In the input segment unit (IU5m), one end is a current source (IPm) connected to a reference voltage source (VREFP) and one end is a reference voltage source (VREFN) (D / A converter (50) shown in FIG. 7) Input switch that connects or disconnects the current source (INm) connected to the ground potential, the other end of the current source (IPm), and the terminal (Iout +) that is one output terminal of the input segment unit (IU5m). (SAm), an input switch (SBm) for connecting or disconnecting the other end of the current source (IPm) and the other output terminal (Iout−) of the input segment unit (IU5m), and a current source (INm) An input switch (SCm) for connecting or disconnecting the other end of the current source and the terminal (Iout−), and an input switch for connecting or disconnecting the other end of the current source (INm) and the terminal (Iout +). Comprising Tsu and switch (SDm), the.

The current source (IPm) and the current source (INm) supply currents having the same current value but different polarities.
The input switches (SAm) and (SCm) operate in accordance with input digital data (Dm) provided corresponding to each input segment unit (IU51 to IU5N). The input switches (SBm) and (SDm) operate according to the inverted signal (DmB) of the applied input digital data.
The terminals (Iout +) and the terminals (Iout−) of the plurality of input segment units (IU51 to IU5N) are connected in common.

  The output stage (52) includes an inverting input terminal commonly connected to the terminal (Iout +), a non-inverting input terminal commonly connected to the terminal (Iout−), a non-inverting output terminal (Vout +), and an inverting output terminal ( And a differential operational amplifier (500) that outputs a differential analog signal. Further, the output stage (52) includes a capacitive element (Cfb1) connected between the terminal (Iout +) and the non-inverting output terminal (Vout +) of the differential operational amplifier (500), and a differential between the terminal (Iout−) and the output stage (52). A capacitor (Cfb2) connected between the inverting output terminal (Vout−) of the operational amplifier (500) and a capacitor between the terminal (Iout +) and the non-inverting output terminal (Vout +) of the differential operational amplifier (500). A resistance element (Rfb1) connected in parallel to the element (Cfb1), and a capacitor (Cfb2) connected in parallel between the terminal (Iout−) and the inverting output terminal (Vout−) of the differential operational amplifier (500) A resistance element (Rfb2).

  Here, in the input segment unit (IU51 to IU5N), an input switch (SA1) for connecting and disconnecting the other end of the current source (IP1 to IPN) and one terminal (Iout +), one end of which is connected to the reference voltage source (VREFP). ˜SAN) is turned on when the polarity of the input digital data (D1 to DN) is “+1”, and connects the other end of the current source (IP1 to IPN) and the terminal (Iout +) to input digital data ( When the polarity of D1 to DN) is “−1”, it is turned off and the other end of the current source (IP1 to IPN) and the terminal (Iout +) are disconnected.

  On the other hand, the input switches (SB1 to SBN) for connecting and disconnecting the other end of the current source (IP1 to IPN) and the terminal (Iout−) having one end connected to the reference voltage source (VREFP) are input digital data (D1). To DN) when the polarity of the inversion signal (D1B to DNB) is “+1”, the signal is turned on and the other end of the current source (IP1 to IPN) is connected to the terminal (Iout−) to invert the input digital data. When the polarity of the signals (D1B to DNB) is “−1”, the signal is turned off and the other end of the current sources (IP1 to IPN) and the terminal (Iout−) are disconnected.

  Further, in the input segment unit (IU51 to IU5N), an input switch (SC1) for connecting and disconnecting the other end of the current source (IN1 to INN) having one end connected to the reference voltage source (VREFN) and the terminal (Iout−). ˜SCN) is turned on when the polarity of the input digital data (D1 to DN) is “+1”, and connects the other end of the current source (IN1 to INN) and the terminal (Iout−) to input digital data. When the polarity of (D1 to DN) is “−1”, it is turned off and the other end of the current source (IN1 to INN) and the terminal (Iout−) are disconnected.

  On the other hand, the input switches (SD1 to SDN) for connecting and disconnecting the other end of the current source (IN1 to INN) and the terminal (Iout +) whose one end is connected to the reference voltage source (VREFN) are input digital data (D1 to DDN). When the polarity of the inverted signal (D1B to DNB) of “DN” is “+1”, the signal is turned on to connect the other end of the current source (IN1 to INN) and the terminal (Iout +), and the inverted signal (D1B to DNB). When the polarity is “−1”, the current source (IN1 to INN) is disconnected from the other end and the terminal (Iout +).

Next, the operation of the D / A converter (50) shown in FIG. 7 will be described.
In the plurality of input segment units (IU51 to IU5N), the input digital data (D1 to DN) is determined according to the input digital data (D1 to DN) and the inverted signals (D1B to DNB) of the input digital data given to each unit. ) In response to a pair of input switches (SA1 to SAN) and input switches (SC1 to SCN), and input switches (SB1 to SBN) and input switches (SD1) to operate in response to inverted signals (D1B to DNB). ˜SDN), one of the pairs is turned on and the other pair is turned off. Thereby, each of the plurality of input segment units (IU51 to IU5N) outputs current to the terminal (Iout +) and the terminal (Iout−), and in the output stage (52), the differential operational amplifier (500) is connected to each input segment unit. The terminal (Iout +) and terminal (Iout−) currents corresponding to the sum of the currents output from (IU51 to IU5N) are input, and a differential analog signal is output.

FIG. 8 is a diagram for explaining the problems of the conventional D / A converter (50) shown in FIG.
Here, for simplicity, only the input segment unit (IU 51) is focused.
In FIG. 8, (a) is a reference clock (CLK), (b) is input digital data (D1), (c) is an inverted signal (D1B) of the input digital data, and (d) is an input segment unit (IU51). ) From the input segment unit (IU51) to the ideal current waveform (Iout + (A)) and (e) when the rise time and the fall time of the current output from the input segment unit (IU51) are zero. The actual current waveform (Iout + (B)) and (f) of the current output to (Iout +) is the current output from the input segment unit (IU51) to the terminal (Iout +) when the RTZ method described later is adopted. The waveform (Iout + (C)) is represented.

The input segment unit (IU51) is provided with input digital data (D1) and an inverted signal (D1B) of the input digital data for each reference clock (CLK) having a period T.
A pair of the input switch (SA1) and the input switch (SC1) or the input switch (SB1) and the input switch (in accordance with the input digital data (D1) and the inverted signal (D1B) of the input digital data. One of the pair with SD1) is turned on and the other pair is turned off, so that the current source (IP1) having the current value “+ Iref” or the current value “−Iref” is obtained. The current of the current source (IN1) is output to the terminal (Iout +) and the terminal (Iout−).

The rise time and rise time of the current output from the input segment unit (IU51) to the terminal (Iout +) according to the input digital data (D1) and the inverted signal (D1B) of the input digital data given in the example of FIG. An ideal current waveform (Iout + (A)) in which the fall time is zero is shown in FIG.
However, the current (Iout + (B)) actually output to the terminal (Iout +) has a finite rise time and fall time, and the rise time and the fall time do not completely match. For example, a current waveform as shown in FIG.

Here, the operation method of the D / A converter that outputs a signal as shown in current (Iout + (A)) (FIG. 8 (d)), (Iout + (B)) (FIG. 8 (e)) is defined as Non Return. to Zero (NRTZ) method.
In the ideal current waveform (Iout + (A)), the current area in the T1 period is “+ Iref × T”, the current area in the T2 period is “+ Iref × T”, and the current areas in the T1 and T2 periods are the same. To do. On the other hand, in the actual current waveform (Iout + (B)), the current area during the period T1 is “+ Iref × T−ΔQ1 + ΔQ2”, the current area during the period T2 is “+ Iref × T−2ΔQ1 + ΔQ2”, and the period between T1 and T2 Current areas do not match.

ΔQ1 represents a current area corresponding to a shortage of current that did not flow due to the rise time. ΔQ2 represents a current area corresponding to the excess current that has flowed due to the fall time.
As described above, when the D / A converter (50) is operated by the above-described NRTZ method, the rise time and the fall time of the finite output signal are provided, and the rise time and the fall time are completely set. Because of the mismatch, the current area output during the current (Nth) reference clock (CLK) is equal to the current value output at the previous (N−1) th reference clock (CLK) and the next (N + 1). Depends on the current value output by the reference clock (CLK). Such a phenomenon is generally called intersymbol interference. Due to the influence of this intersymbol interference, the output current waveform has non-linearity and distortion occurs in the differential analog signal.

For this reason, the conventional D / A converter (50) employs a Return to Zero (RTZ) system having a fixed period of one reference clock period and a period in which no current is output as a countermeasure against intersymbol interference. Yes.
A current waveform (Iout + (C)) when the RTZ method is adopted is the waveform shown in FIG.

  In this example, the current waveform (Iout + (C)) outputs a current of “+ Iref” or “−Iref” during a period in which the reference clock (CLK) is “+1” which is half of one cycle. In other periods of “−1”, no current is output (current value “0”). As shown in FIG. 8F, in the RTZ method, by having a period in which no current is output for each period of the reference clock (CLK), the current area in the period T1 in the current waveform (Iout + (C)). And the current area during the period T2. That is, it is possible to avoid distortion in the output signal due to the influence of intersymbol interference.

JP 2000-78015 A

However, in the above-described RTZ method, distortion to the output signal due to the influence of intersymbol interference can be avoided. However, since there is a period during which no signal is output, the S / N ratio is degraded by lowering the level of the output signal. There is a problem of end.
The present invention has been made to solve the above-described conventional problems, and does not cause distortion due to the influence of intersymbol interference in the output signal, and does not cause deterioration in the S / N ratio due to a decrease in the output signal level. An object of the present invention is to provide a D / A converter having a distortion and a high S / N ratio.

  One embodiment of the present invention is a D / A converter that converts a digital signal composed of one or more input digital data (for example, input digital data D1 shown in FIG. 2C), which is a 1-bit signal, into an analog signal. For example, a D / A converter 10 illustrated in FIG. 1, which includes a first current source (for example, current sources IP <b> 1 to IPN illustrated in FIG. 1) and a second current source (for example, current source illustrated in FIG. 1). IN1 to INN) and a first input switch (for example, FIG. 1) that connects or disconnects the first current source and a first output terminal (for example, terminal Iout + shown in FIG. 1) according to the input digital data. The first current source and the second output terminal (for example, FIG. 2) according to the input switches SA1 to SAN) and the inverted signal of the input digital data (for example, the inverted signal D1B illustrated in FIG. 2 (e)). 1, terminal I ut−) is connected to or disconnected from the second input switch (for example, input switches SB1 to SBN shown in FIG. 1), the second current source and the second output terminal according to the input digital data, A third input switch (for example, input switches SC1 to SCN shown in FIG. 1), and the second current source and the first output terminal according to an inverted signal of the input digital data. Input segment units (for example, input segment units IU11 to IU1N shown in FIG. 1) having fourth input switches (for example, input switches SD1 to SDN shown in FIG. 1) to be connected or disconnected are connected to the input digital data. And an input stage in which the first output terminals and the second output terminals of the input segment unit are connected in common (for example, FIG. 1), a differential operational amplifier (for example, the differential operational amplifier 100 shown in FIG. 1), and a first capacitor connected between the inverting input terminal and the non-inverting output terminal of the differential operational amplifier. An element (for example, the capacitive element Cfb1 shown in FIG. 1) and a second capacitive element (for example, the capacitive element Cfb2 shown in FIG. 1) connected between the non-inverting input terminal and the inverting output terminal of the differential operational amplifier. And a first resistance element (for example, resistance element Rfb1 shown in FIG. 1) connected in parallel with the first capacitance element between the first output terminal and the non-inverting output terminal of the differential operational amplifier. And a second resistance element (for example, resistance element Rfb2 shown in FIG. 1) connected in parallel with the second capacitance element between the second output terminal and the inverting output terminal of the differential operational amplifier. The first output terminal and the differential operational amplifier A first output switch (for example, output switch SO1 shown in FIG. 1) that connects or disconnects the inverting input terminal of the first output switch, and a second output terminal that connects or disconnects the non-inverting input terminal of the differential operational amplifier. A second output switch (for example, output switch SO2 shown in FIG. 1) and a third output switch (for example, an output shown in FIG. 1) that connects or disconnects the first output end and the second output end. And the differential operational amplifier includes an output stage (for example, the output stage 12 shown in FIG. 1) that outputs a differential analog signal corresponding to the digital signal. In a first period (for example, period T10 shown in FIG. 2) which is a front period of one cycle, each of the input segment units is in response to the input digital data. The third input switch, or any one pair of the second input switch and the fourth input switch is turned on and the other pair is turned off, and the first output switch and the second input switch are turned on. The third output switch is turned on and the third output switch is turned off, and a second period (for example, shown in FIG. 2) is a remaining period following the first period in one cycle of the input digital data. In the period T11), in each of the input segment units, the first, second, third and fourth input switches are turned off, and the first output switch and the second output switch are turned off. The D / A converter is characterized in that the third output switch is turned on.

  The input segment unit includes a fifth input switch (for example, input switches SE1 to SEN shown in FIG. 3) that connects or disconnects the output side of the first current source and the input side of the second current source. And the fifth input switch is turned off in the first period, and the fifth input switch is turned on in the second period.

  Another aspect of the present invention is a D / A converter that converts a digital signal composed of one or a plurality of input digital data (for example, input digital data D1 shown in FIG. 2C), which is a 1-bit signal, into an analog signal. (For example, the D / A converter 30 shown in FIG. 4), and the first current source (for example, current sources IP <b> 1 to IPN shown in FIG. 4) and the second current source (for example, current shown in FIG. 4). Source IN1 to INN) and a first input switch (for example, shown in FIG. 4) that connects or disconnects the first current source and an output terminal (for example, terminal Iout shown in FIG. 4) according to the input digital data. , Input switches SA1 to SAN) and the second current source and the output terminal are connected or disconnected in accordance with an inverted signal of the input digital data (for example, inverted signal D1B shown in FIG. 2E). 2 input slots Input segment units (for example, input segment units IU31 to IU3N shown in FIG. 4) for each of the input digital data, the input digital data including the input switches SB1 to SBN shown in FIG. An input stage (for example, input stage 31 shown in FIG. 4), an operational amplifier (for example, differential operational amplifier 300 shown in FIG. 4), and an inverting input terminal of the operational amplifier, in which the output ends of the segment units are connected in common A capacitive element (for example, the capacitive element Cfb shown in FIG. 4) connected between the output terminal and a resistive element (for example, connected in parallel with the capacitive element between the output terminal and the output terminal of the operational amplifier). 4, a first output switch (for example, FIG. 4) that connects or disconnects the resistance element Rfb) and the output terminal and the inverting input terminal of the operational amplifier. And a second output switch (for example, output switch SO2 shown in FIG. 4) for connecting or disconnecting the output terminal and a reference potential (for example, common voltage source VCM shown in FIG. 4). The operational amplifier includes an output stage (for example, the output stage 32 shown in FIG. 4) that outputs an analog signal corresponding to the digital signal, and a front period of one cycle of the input digital data In the first period, each input segment unit has one of the first input switch and the second input switch turned on and the other turned off according to the input digital data, and The first output switch is turned on and the second output switch is turned off, and continues to the first period of one cycle of the input digital data. In the second period, which is the remaining period, in each input segment unit, the first and second input switches are turned off, and the first output switch is turned off and the second output switch is A D / A converter characterized by being turned on.

The input segment unit includes third input switches (for example, input switches SE1 to SEN shown in FIG. 5) that connect or disconnect the output side of the first current source and the input side of the second current source. The third input switch may be in an off state during the first period, and the third input switch may be in an on state during the second period.
The first current source and the second current source may supply currents having different polarities and equal current values.
A plurality of the input segment units may be provided, and the current values of the first current sources and the second current sources may be equal between the input segment units.

A plurality of the input segment units may be provided, and the first current source and the second current source may be set so that the current value doubles in order between the input segment units.
Another aspect of the present invention includes the D / A converter according to any one of the above aspects, and a digital delta sigma modulator (for example, a 15-level digital delta sigma modulator 720 shown in FIG. 6), and the D The / A converter is a delta sigma type D / A converter that converts the digital signal processed through the digital delta sigma modulator into an analog signal.

  Other aspects of the invention include a D / A converter according to any of the preceding aspects, a digital delta sigma modulator (eg, a 15-level digital delta sigma modulator 720 shown in FIG. 6), and dynamic element matching. A circuit (eg, a DWA dynamic element matching circuit 730 shown in FIG. 6), and the D / A converter is processed via the digital delta-sigma modulator and the dynamic element matching circuit. A delta-sigma type D / A converter characterized by converting a digital signal into an analog signal.

  Another aspect of the present invention is a D / A converter that converts a digital signal composed of one or a plurality of input digital data (for example, input digital data D1 shown in FIG. 2C), which is a 1-bit signal, into an analog signal. (For example, the D / A converter 10 shown in FIG. 1), which is provided for each input digital data, and a current signal corresponding to the given input digital data is supplied to a first output terminal (for example, FIG. 1). 1 and input segment units (for example, input segment units IU11 to IU1N shown in FIG. 1) that output to a second output terminal (for example, terminal Iout− shown in FIG. 1). An input stage (for example, input stage 11 shown in FIG. 1) in which the first output terminals and the second output terminals of the unit are connected in common; (For example, the differential operational amplifier 100 shown in FIG. 1) and a first capacitive element (for example, the capacitive element Cfb1 shown in FIG. 1) connected between the inverting input terminal and the non-inverting output terminal of the differential operational amplifier. ), A second capacitive element (for example, capacitive element Cfb2 shown in FIG. 1) connected between the non-inverting input terminal and the inverting output terminal of the differential operational amplifier, and the difference between the first output terminal and the difference A first resistive element (for example, a resistive element Rfb1 shown in FIG. 1) connected in parallel with the first capacitive element between the non-inverting output terminal of the dynamic operational amplifier, the second output terminal, and the difference A second resistive element (for example, a resistive element Rfb2 shown in FIG. 1) connected in parallel with the second capacitive element between the inverting output terminal of the dynamic operational amplifier, the first output terminal, and the differential Connect or disconnect the inverting input terminal of the operational amplifier A first output switch (for example, output switch SO1 shown in FIG. 1) and a second output switch (for example, in FIG. 1) that connects or disconnects the second output terminal and the non-inverting input terminal of the differential operational amplifier. Output switch SO2), and a third output switch (for example, output switch SO3 shown in FIG. 1) for connecting or disconnecting the first output terminal and the second output terminal, and An output stage (for example, the output stage 12 shown in FIG. 1) that outputs a differential analog signal corresponding to the digital signal, and a first period (a front period of one cycle of the input digital data) For example, in the period T10) shown in FIG. 2, each of the input segment units outputs a current signal corresponding to the input digital data, and the first output switch and the second output switch are in an ON state. And the third output switch is turned off, and in the second period (for example, period T11 shown in FIG. 2), which is the remaining period following the first period in one cycle of the input digital data, Each input segment unit stops outputting a current signal, and the first output switch and the second output switch are turned off and the third output switch is turned on. A converter.

  According to the present invention, a D / A converter and a delta-sigma D / A converter having a low distortion and a high S / N ratio can be realized.

It is a block diagram which shows an example of the D / A converter which concerns on 1st Embodiment of this invention. It is a time chart which shows an example of the signal of each part of a D / A converter. It is a block diagram which shows an example of the D / A converter which concerns on 2nd Embodiment of this invention. It is a block diagram which shows an example of the D / A converter which concerns on 3rd Embodiment of this invention. It is a block diagram which shows an example of the D / A converter which concerns on 4th Embodiment of this invention. It is an example of a block diagram at the time of using the D / A converter of this invention with the delta-sigma type D / A converter. It is a figure which shows the structure of the conventional D / A converter. It is a time chart which shows an example of the signal of each part of the conventional D / A converter.

  Hereinafter, embodiments of the D / A converter of the present invention will be described in detail with reference to the drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted.

(First embodiment)
First, the configuration of the D / A converter (10) according to the first embodiment of the present invention will be described with reference to FIG.
The D / A converter (10) according to the first embodiment is a D / A converter that converts an N-bit digital signal into an analog signal. Here, each bit data of the N-bit digital signal is set as input digital data (D1 to DN).
The D / A converter (10) includes an input stage (11), an output stage (12), a clock supply unit (13), and a switch control unit (14).

The input stage (11) and the output stage (12) are the same except that the input stage (51) and the output stage (52) in the D / A converter (50) shown in FIG. Therefore, the same parts are denoted by the same reference numerals, and detailed description thereof is omitted.
The input stage (11) includes a plurality of input segment units (IU11 to IU1N).
The input segment units (IU11 to IU1N) are provided corresponding to each bit of the digital signal to be converted. That is, in the case of an N-bit digital signal, N input segment units are provided.
Since the input segment units (IU11 to IU1N) have the same configuration, the input segment unit (IU1m (m = 1 to N)) will be described here.

The input segment unit (IU1m) has a current source (IPm) having one end connected to a reference voltage source (VREFP) and a reference voltage source (VREFN) (one end of the D / A converter (10) shown in FIG. 1). Input switch for connecting or disconnecting the current source (INm) connected to the ground potential, the other end of the current source (IPm), and the terminal (Iout +) which is one output terminal of the input segment unit (IU1m) (SAm), an input switch (SBm) for connecting or disconnecting the other end of the current source (IPm) and the other output terminal (Iout-) of the input segment unit (IU1m), and a current source (INm) An input switch (SCm) for connecting or disconnecting the other end of the current source and the terminal (Iout−), and an input switch for connecting or disconnecting the other end of the current source (INm) and the terminal (Iout +). Comprising Tsu and switch (SDm), the.
The current source (IPm) and the current source (INm) supply currents having different polarities and equal current values.

  The input switches (SAm) and (SCm) are switch signals (φD1) based on input digital data (D1 to DN) given to each input segment unit (IU11 to IU1N) and a clock signal (Φ1) described later. ~ ΦDN). The input switches (SBm) and (SDm) operate according to the switch signals (φD1B to φDNB) based on the inverted signals (D1B to DNB) and the clock signal (Φ1) of the applied input digital data (D1 to DN). To do.

The terminals (Iout +) and the terminals (Iout−) of the plurality of input segment units (IU11 to IU1N) are connected in common.
The output stage (12) has a non-inverting input terminal, an inverting input terminal, a non-inverting output terminal (Vout +), and an inverting output terminal (Vout−), and is composed of a fully differential operational amplifier that outputs a differential analog signal. A differential operational amplifier (100) is provided. Further, the output stage (12) includes a capacitive element (Cfb1) connected between the inverting input terminal and the non-inverting output terminal (Vout +) of the differential operational amplifier (100), and the non-inverting of the differential operational amplifier (100). A capacitor (Cfb2) connected between the input terminal and the inverting output terminal (Vout−) and a capacitor (Cfb1) connected in parallel between the terminal (Iout +) and the non-inverting output terminal (Vout +). And a resistance element (Rfb2) connected in parallel with the capacitor element (Cfb2) between the terminal (Iout−) and the inverting output terminal (Vout−).

  Further, the output stage (12) includes an output switch (SO1) for connecting or disconnecting the terminal (Iout +) and the inverting input terminal of the differential operational amplifier (100), a terminal (Iout−), and the differential operational amplifier (100). An output switch (SO2) for connecting or disconnecting the non-inverting input terminal and an output switch (SO3) for connecting or disconnecting the terminal (Iout +) and the terminal (Iout−) are provided. The output switch (SO1) includes a connection point between one end of the resistance element (Rfb1) and the inverting input terminal of the differential operational amplifier (100), one end of the capacitive element (Cfb1), and an inverting input terminal of the differential operational amplifier (100). It is connected between the connection points. Similarly, the output switch (SO2) includes a connection point between one end of the resistance element (Rfb2) and the non-inverting input terminal of the differential operational amplifier (100), one end of the capacitive element (Cfb2), and the differential operational amplifier (100). It is connected between the connection point with the non-inverting input terminal. One end of the output switch (SO3) is connected to a connection point between one end of the resistance element (Rfb1) and the inverting input terminal of the differential operational amplifier (100), and the other end is connected to one end of the resistance element (Rfb2) and the differential operational amplifier. It is connected to the connection point with the non-inverting input terminal of (100).

These output switches (SO1, SO2) operate according to the clock signal (Φ1). The output switch (SO3) operates according to the clock signal (Φ2).
The clock supply unit (13) supplies the above-described two types of clock signals (Φ1, Φ2).
The two types of clock signals (Φ1, Φ2) supplied from the clock supply unit (13) repeat a low level and a high level at predetermined intervals as shown in FIGS. 2 (a) and 2 (b). This is a clock signal and has characteristics opposite to each other.

The clock signal (Φ1) is a signal corresponding to the reference clock (CLK) shown in FIG. 8A, and the input digital data (D1 to DN) is the clock signal (Φ1) as shown in FIG. 8C. ) To synchronize with the rise timing.
The switch control unit (14) receives input digital data (D1 to DN) and a clock signal (Φ1) output from the clock supply unit (13), and based on these, the switch signal (φD1 to φDN). ) And switch signals (φD1B to φDNB). Then, the switch signals (φD1 to φDN) are output to the input switches (SA1 to SAN) and the input switches (SC1 to SCN), and the switch signals (φD1B to φDNB) are output to the input switches (SB1 to SBN) and the input switches (SB1 to SBN). SD1 to SDN).

As shown in FIG. 2D, the switch signal (φD1) becomes the value of the input digital data (D1) (FIG. 2C) at the rising edge of the clock signal (Φ1), and becomes “−1” at the falling edge. The switch signals (φD2 to φDN) are similarly generated.
Similarly, as shown in FIG. 2 (f), the switch signal (φD1B) becomes the value of the inverted signal (D1B) (FIG. 2 (e)) of the input digital data at the rise of the clock signal (Φ1) and falls. The switch signal (φD2B to φDNB) is similarly generated.

  Here, in the input segment unit (IU11 to IU1N), an input switch (SA1) for connecting or disconnecting the other end of the current source (IP1 to IPN) having one end connected to the reference voltage source (VREFP) and the terminal (Iout +). To SAN) are turned on when the polarity of the switch signals (φD1 to φDN) generated based on the input digital data (D1 to DN) is “+1”, and the other ends of the current sources (IP1 to IPN) and the terminals ( Iout +) is connected, and when the polarity of the switch signal (φD1 to φDN) is “−1”, it is turned off and the other end of the current source (IP1 to IPN) and the terminal (Iout +) are disconnected.

  On the other hand, the input switches (SB1 to SBN) for connecting or disconnecting the other end of the current sources (IP1 to IPN) whose one end is connected to the reference voltage source (VREFP) and the terminal (Iout−) are inverted in the input digital data. When the polarity of the switch signal (φD1B to φDNB) generated based on the signal (D1B to DNB) is “+1”, the switch is turned on and the other end of the current source (IP1 to IPN) is connected to the terminal (Iout−). When the polarity of the switch signals (φD1B to φDNB) is “−1”, the switch is turned off and the other end of the current source (IP1 to IPN) and the terminal (Iout−) are disconnected.

  Further, in the input segment unit (IU11 to IU1N), an input switch (SC1) for connecting or disconnecting the other end of the current source (IN1 to INN) whose one end is connected to the reference voltage source (VREFN) and the terminal (Iout−). To SCN) are turned on when the polarity of the switch signals (φD1 to φDN) generated based on the input digital data (D1 to DN) is “+1”, and the other ends of the current sources (IN1 to INN) and the terminals ( Iout−) is connected, and when the polarity of the switch signal (φD1 to φDN) is “−1”, the switch is turned off and the other end of the current source (IN1 to INN) and the terminal (Iout−) are disconnected.

  On the other hand, the input switches (SD1 to SDN) for connecting or disconnecting the other end of the current source (IN1 to INN) and the terminal (Iout +) having one end connected to the reference voltage source (VREFN) are inverted signals of the input digital data. When the polarity of the switch signal (φD1B to φDNB) generated based on (D1B to DNB) is “+1”, the switch is turned on to connect the other end of the current source (IN1 to INN) and the terminal (Iout +), and switch When the polarity of the signal (φD1B to φDNB) is “−1”, the signal is turned off and the other end of the current source (IN1 to INN) and the terminal (Iout +) are disconnected.

That is, these input switches (SA1 to SAN, SB1 to SBN, SC1 to SCN, SD1 to SDN) operate in the RTZ system based on the switch signal (φD1 to φDN) and the switch signal (φD1B to φDNB).
The output switch (SO1) and the output switch (SO2) are turned on when the clock signal (Φ1) is at a high level, and are turned off at other times.
The output switch (SO3) is turned on when the clock signal (Φ2) is at a high level, and is turned off at other times.

Next, the operation of the D / A converter (10) shown in FIG. 1 will be described with reference to FIG.
As shown at time t11 in FIGS. 2A and 2B, when the clock signal (Φ1) is at a high level, the clock signal (Φ2) is at a low level. Therefore, in the output stage (12), the output switch (SO1) that operates according to the clock signal (Φ1) is turned on, and the terminal (Iout +) and the inverting input terminal of the differential operational amplifier (100) are connected. Similarly, the output switch (SO2) is turned on, and the terminal (Iout−) is connected to the non-inverting input terminal of the differential operational amplifier (100). On the other hand, the output switch (SO3) that operates according to the clock signal (Φ2) is turned off, and the terminal (Iout +) and the terminal (Iout−) are disconnected.

  In the input stage (11), in the plurality of input segment units (IU11 to IU1N), according to the input digital data (D1 to DN) given for each unit and the inverted signals (D1B to DNB) of the input digital data, One of the pair of the input switch (SA1 to SAN) and the input switch (SC1 to SCN) and the pair of the input switch (SB1 to SBN) and the input switch (SD1 to SDN) is in the on state. And the other pair is turned off.

Each of the plurality of input segment units (IU11 to IU1N) outputs a current to the terminal (Iout +) and the terminal (Iout−), and the sum of the currents output from the input segment units (IU11 to IU1N) It is output from each of the terminal (Iout +) and the terminal (Iout−).
In the output stage (12), the current signal output from each of the terminal (Iout +) and the terminal (Iout−) is input to the inverting input terminal and the non-inverting input terminal of the differential operational amplifier (100). 100) outputs a differential analog signal.

  When the clock signal (Φ1) becomes low level and the clock signal (Φ2) changes to high level at the time t12 from the state where the clock signal (Φ1) is high level, the input digital data (D1 to DN) and its inverted signal ( Regardless of D1B to DNB, the switch signals (φD1 to φDN) and (φD1B to φDNB) are switched to “−1”. Therefore, the input switch (SA1 to SAN), the input switch (SB1 to SBN), the input switch (SC1 to SCN), and the input switch (SD1 to SDN) are turned off, and the other end of the current source (IP1 to IPN). And the other ends of the current sources (IN1 to INN) are disconnected from the terminal (Iout +) and the terminal (Iout−).

  The output switch (SO1) that operates according to the clock signal (Φ1) is turned off, the terminal (Iout +) and the inverting input terminal of the differential operational amplifier (100) are disconnected, and similarly, the output switch (SO2) is turned off. The terminal (Iout−) and the non-inverting input terminal of the differential operational amplifier (100) are disconnected. On the other hand, the output switch (SO3) operating in response to the clock signal (Φ2) is turned on to connect the terminal (Iout +) and the terminal (Iout−).

  In the period in which the clock signal (Φ1) is at a low level, that is, as shown in FIG. 2, in the period T11 in which the clock signal (Φ2) is at a high level, the differential analog signal output by the differential operational amplifier (100) is FIG. 2 shows a signal output immediately before the clock signal (Φ1) is switched from the high level to the low level by the differential operational amplifier (100), the capacitive element (Cfb1), and the capacitive element (Cfb2). At the time t12 shown, the same voltage value as that of the signal output in the period T10 immediately before the clock signal (Φ1) switches from the high level to the low level is held.

  Then, from the state where the clock signal (Φ1) is at the low level and the clock signal (Φ2) is at the high level, the clock signal (Φ2) becomes the low level again at time t13 and the clock signal (Φ1) switches to the high level. The output switch (SO1) is turned on to connect the terminal (Iout +) and the inverting input terminal of the differential operational amplifier (100). Similarly, the output switch (SO2) is turned on, and the terminal (Iout−) is connected to the non-inverting input terminal of the differential operational amplifier (100). Further, the output switch (SO3) is turned off, and the terminal (Iout +) and the terminal (Iout−) are disconnected.

  Further, in the plurality of input segment units (IU11 to IU1N), new input digital data (D1-NEXT to DN-NEXT) given for each unit and new input digital data inverted signal (D1B-NEXT to DNB-). NEXT), a pair of input switch (SA1 to SAN) and input switch (SC1 to SCN), or a pair of input switch (SB1 to SBN) and input switch (SD1 to SDN) One pair is on and the other pair is off.

Each of the plurality of input segment units (IU11 to IU1N) outputs a current to the terminal (Iout +) and the terminal (Iout−), and the differential operational amplifier (100) in the output stage (12) has a new difference. A dynamic analog signal is output.
Thus, in the D / A converter (10), the input segment units (IU11 to IU1N) are connected to the terminal (Iout +) and the terminal (Iout−) during the period when the clock signal (Φ2) is at the high level. The differential analog signal output from the differential operational amplifier (100) is output immediately before the clock signal (Φ1) becomes the low level last time, even though the above-described RTZ method of not outputting current is adopted. It is possible to maintain the same voltage value as that of the signal that has been generated.

  In other words, the D / A converter (10) in the first embodiment can avoid distortion to the output signal due to the influence of intersymbol interference by adopting the RTZ method, and also when the RTZ method is adopted. It is possible to avoid the deterioration of the S / N ratio due to the decrease in the voltage level of the differential analog signal, which was a problem.

(Second Embodiment)
Next, the configuration of the D / A converter (20) according to the second embodiment of the present invention will be described with reference to FIG.
The D / A converter (20) according to the second embodiment, like the D / A converter (10) according to the first embodiment, converts the N-bit digital signal into an analog signal. It is a vessel. Here, each bit data of the N-bit digital signal is set as input digital data (D1 to DN).
The D / A converter (20) includes an input stage (21), an output stage (22), a clock supply unit (23), and a switch control unit (24).

The input stage (21) and the output stage (22) are partially different from the input stage (11) and the output stage (12) in the D / A converter (10) of the first embodiment shown in FIG. Since it is the same except for this, the same code | symbol is provided to the same part and the detailed description is abbreviate | omitted.
The input stage (21) includes a plurality of input segment units (IU21 to IU2N). The input segment units (IU21 to IU2N) are provided corresponding to each bit of the digital signal to be converted. That is, in the case of an N-bit digital signal, N input segment units are provided.
Since the input segment units (IU21 to IU2N) have the same configuration, the input segment unit (IU2m (m = 1 to N)) will be described here.

  In the input segment unit (IU2m), one end is a current source (IPm) connected to a reference voltage source (VREFP) and one end is a reference voltage source (VREFN) (D / A converter (20) shown in FIG. 3). Input switch for connecting or disconnecting the current source (INm) connected to the ground potential, the other end of the current source (IPm), and the terminal (Iout +) which is one output terminal of the input segment unit (IU2m) (SAm), an input switch (SBm) for connecting or disconnecting the other end of the current source (IPm) and the other output terminal (Iout-) of the input segment unit (IU2m), and a current source (INm) An input switch (SCm) for connecting or disconnecting the other end of the current source and the terminal (Iout−), and an input switch for connecting or disconnecting the other end of the current source (INm) and the terminal (Iout +). Comprising Tsu and switch (SDm), the.

Further, the input segment unit (IU2m) has the other end of the current source (IPm) whose one end is connected to the reference voltage source (VREFP) and the current source (INm) whose one end is connected to the reference voltage source (VREFN). An input switch (SEm) for connecting or disconnecting the end is provided.
The current source (IPm) and the current source (INm) supply currents having the same current value but different polarities.

The input switches (SAm) and (SCm) are switch signals (φD1 to φDN) based on input digital data (D1 to DN) and a clock signal (Φ1) given to the input segment units (IU21 to IU2N). ). The input switches (SBm) and (SDm) operate according to the switch signals (φD1B to φDNB) based on the inverted signals (D1B to DNB) and the clock signal (Φ1) of the applied input digital data (D1 to DN). To do. The input switch (SEm) operates according to the clock signal (Φ2).
The terminals (Iout +) and the terminals (Iout−) of the plurality of input segment units (IU21 to IU2N) are connected in common.

  The output stage (22) has a non-inverting input terminal, an inverting input terminal, a non-inverting output terminal (Vout +), and an inverting output terminal (Vout−), and is a fully differential operational amplifier that outputs a differential analog signal. A differential operational amplifier (200). Further, the output stage (22) includes a capacitive element (Cfb1) connected between the inverting input terminal and the non-inverting output terminal (Vout +) of the differential operational amplifier (200), and the non-inverting of the differential operational amplifier (200). A capacitor (Cfb2) connected between the input terminal and the inverting output terminal (Vout−) and a capacitor (Cfb1) connected in parallel between the terminal (Iout +) and the non-inverting output terminal (Vout +). And a resistance element (Rfb2) connected in parallel with the capacitor element (Cfb2) between the terminal (Iout−) and the inverting output terminal (Vout−).

  Further, the output stage (22) includes an output switch (SO1) for connecting or disconnecting the terminal (Iout +) and the inverting input terminal of the differential operational amplifier (200), a terminal (Iout−), and the differential operational amplifier (200). An output switch (SO2) for connecting or disconnecting the non-inverting input terminal and an output switch (SO3) for connecting or disconnecting the terminal (Iout +) and the terminal (Iout−) are provided. The output switch (SO1) has a connection point between one end of the resistance element (Rfb1) and the inverting input terminal of the differential operational amplifier (200), one end of the capacitive element (Cfb1), and an inverting input terminal of the differential operational amplifier (200). It is connected between the connection points. Similarly, the output switch (SO2) includes a connection point between one end of the resistance element (Rfb2) and the non-inverting input terminal of the differential operational amplifier (200), one end of the capacitive element (Cfb2), and the differential operational amplifier (200). It is connected between the connection point with the non-inverting input terminal. One end of the output switch (SO3) is connected to a connection point between one end of the resistance element (Rfb1) and the inverting input terminal of the differential operational amplifier (200), and the other end is connected to one end of the resistance element (Rfb2) and the differential operational amplifier. (200) is connected to the connection point with the non-inverting input terminal.

The output switches (SO1, SO2) operate according to the clock signal (Φ1). The output switch (SO3) operates according to the clock signal (Φ2).
The clock supply unit (23) supplies the two types of clock signals (Φ1, Φ2) shown in FIG.
As shown in FIG. 2, the two types of clock signals (Φ1, Φ2) supplied from the clock supply unit (23) are clock signals that repeat a low level and a high level at predetermined intervals, and are opposite to each other. Has characteristics.

  The switch control unit (24) receives input digital data (D1 to DN) and a clock signal (Φ1) output from the clock supply unit (23), and based on these, the switch control unit (24) in the first embodiment. Switch signals (φD1 to φDN) and switch signals (φD1B to φDNB) are generated in the same procedure as the switch control unit (14). Then, the switch signals (φD1 to φDN) are output to the input switches (SA1 to SAN) and the input switches (SC1 to SCN), and the switch signals (φD1B to φDNB) are output to the input switches (SB1 to SBN) and the input switches (SB1 to SBN). SD1 to SDN).

  Here, in the input segment unit (IU21 to IU2N), an input switch (SA1) that connects or disconnects the other end of the current source (IP1 to IPN), one end of which is connected to the reference voltage source (VREFP), and the terminal (Iout +). To SAN) are turned on when the polarity of the switch signals (φD1 to φDN) generated based on the input digital data (D1 to DN) is “+1”, and the other ends of the current sources (IP1 to IPN) and the terminals ( Iout +) is connected, and when the polarity of the switch signal (φD1 to φDN) is “−1”, it is turned off and the other end of the current source (IP1 to IPN) and the terminal (Iout +) are disconnected.

  On the other hand, the input switches (SB1 to SBN) for connecting or disconnecting the other end of the current sources (IP1 to IPN) whose one end is connected to the reference voltage source (VREFP) and the terminal (Iout−) are inverted in the input digital data. When the polarity of the switch signal (φD1B to φDNB) generated based on the signal (D1B to DNB) is “+1”, the switch is turned on and the other end of the current source (IP1 to IPN) is connected to the terminal (Iout−). When the polarity of the switch signals (φD1B to φDNB) is “−1”, the switch is turned off and the other end of the current source (IP1 to IPN) and the terminal (Iout−) are disconnected.

  Further, in the input segment unit (IU21 to IU2N), an input switch (SC1) for connecting or disconnecting the other end of the current source (IN1 to INN) and one terminal (Iout−), one end of which is connected to the reference voltage source (VREFN). To SCN) are turned on when the polarity of the switch signals (φD1 to φDN) generated based on the input digital data (D1 to DN) is “+1”, and the other ends of the current sources (IN1 to INN) and the terminals ( Iout−) is connected, and when the polarity of the switch signal (φD1 to φDN) is “−1”, the switch is turned off and the other end of the current source (IN1 to INN) and the terminal (Iout−) are disconnected.

  On the other hand, the input switches (SD1 to SDN) for connecting or disconnecting the other end of the current source (IN1 to INN) and the terminal (Iout +) having one end connected to the reference voltage source (VREFN) are inverted signals of the input digital data. When the polarity of the switch signal (φD1B to φDNB) generated based on (D1B to DNB) is “+1”, the switch is turned on to connect the other end of the current source (IN1 to INN) and the terminal (Iout +), and switch When the polarity of the signal (φD1B to φDNB) is “−1”, the signal is turned off and the other end of the current source (IN1 to INN) and the terminal (Iout +) are disconnected.

That is, these input switches (SA1 to SAN, SB1 to SBN, SC1 to SCN, SD1 to SDN) operate in the RTZ system based on the switch signal (φD1 to φDN) and the switch signal (φD1B to φDNB).
The output switch (SO1) and the output switch (SO2) are turned on when the clock signal (Φ1) is at a high level, and are turned off at other times.
The input switch (SE1 to SEN) and the output switch (SO3) for connecting or disconnecting the other end of the current source (IP1 to IPN) and the other end of the current source (IN1 to INN) have a clock signal (Φ2). It is on when it is high and off when it is not.

Next, the operation of the D / A converter (20) in the second embodiment shown in FIG. 3 will be described.
As shown in FIG. 2, when the clock signal (Φ1) is at a high level, the clock signal (Φ2) is at a low level.
Therefore, in the output stage (22), the output switch (SO1) is turned on, and the terminal (Iout +) and the inverting input terminal of the differential operational amplifier (200) are connected. Similarly, the output switch (SO2) is turned on, and the terminal (Iout−) is connected to the non-inverting input terminal of the differential operational amplifier (200). On the other hand, the output switch (SO3) that operates according to the clock signal (Φ2) is turned off, and the terminal (Iout +) and the terminal (Iout−) are disconnected.

  In the input stage (21), in the plurality of input segment units (IU21 to IU2N), in accordance with input digital data (D1 to DN) given to each unit and inverted signals (D1B to DNB) of the input digital data, Either the pair of the input switch (SA1 to SAN) and the input switch (SC1 to SCN) or the pair of the input switch (SB1 to SBN) and the input switch (SD1 to SDN) is turned on, The other pair is turned off.

At this time, the input switches (SE1 to SEN) that operate according to the clock signal (Φ2) are turned off, and the other ends of the current sources (IP1 to IPN) and the other ends of the current sources (IN1 to INN) are disconnected. .
Each of the plurality of input segment units (IU21 to IU2N) outputs a current to the terminal (Iout +) and the terminal (Iout−), and the sum of the currents output from the input segment units (IU21 to IU2N) Output from each of (Iout +) and terminal (Iout−). In the output stage (22), the current signals output from the terminals (Iout +) and (Iout−) are input to the inverting input terminal and the non-inverting input terminal of the differential operational amplifier (200), and the differential operational amplifier ( 200) outputs a differential analog signal.

  When the clock signal (Φ1) becomes low level and the clock signal (Φ2) switches to high level from the state where the clock signal (Φ1) is high level, the input digital data (D1 to DN) and its inverted signal (D1B to Regardless of the DNB), the switch signals (φD1 to φDN) and (φD1B to φDNB) are switched to “−1”. Therefore, the input switch (SA1 to SAN), the input switch (SB1 to SBN), the input switch (SC1 to SCN), and the input switch (SD1 to SDN) are turned off, and the other end of the current source (IP1 to IPN) and the current The other ends of the sources (IN1 to INN) are disconnected from the terminal (Iout +) and the terminal (Iout−).

At this time, the input switches (SE1 to SEN) are turned on, and the other ends of the current sources (IP1 to IPN) are connected to the other ends of the current sources (IN1 to INN).
Further, the output switch (SO1) is turned off and the terminal (Iout +) is disconnected from the inverting input terminal of the differential operational amplifier (200). Similarly, the output switch (SO2) is turned off and the terminal (Iout−) is differentially connected. The non-inverting input terminal of the operational amplifier (200) is disconnected. The output switch (SO3) is turned on to connect the terminal (Iout +) and the terminal (Iout−).

  Also in the second embodiment, as shown in FIG. 2, in the period T11 in which the clock signal (Φ1) is at the low level and the clock signal (Φ2) is at the high level, the differential analog output from the differential operational amplifier (200). The signal is a signal output immediately before the clock signal (Φ1) is switched from the high level to the low level by the differential operational amplifier (200), the capacitive element (Cfb1), and the capacitive element (Cfb2). 2 holds the same voltage value as the signal output in the period T10 shown in FIG.

  When the clock signal (Φ1) is switched to the high level again from the state where the clock signal (Φ1) is at the low level and the clock signal (Φ2) is at the high level, the output switch (SO1) is turned on and the terminal (Iout +) is connected to the inverting input terminal of the differential operational amplifier (200). Similarly, the output switch (SO2) is turned on and the terminal (Iout−) and the differential operational amplifier (200) are connected. To the non-inverting input terminal. On the other hand, the output switch (SO3) is turned off, and the terminal (Iout +) and the terminal (Iout−) are disconnected.

  Further, in the plurality of input segment units (IU21 to IU2N), new input digital data (D1-NEXT to DN-NEXT) given for each unit and inverted signal (D1B-NEXT to DNB-) of the new input digital data are given. NEXT), either a pair of input switches (SA1 to SAN) and input switches (SC1 to SCN) or a pair of input switches (SB1 to SBN) and input switches (SD1 to SDN) One pair is on and the other pair is off.

Further, the input switches (SE1 to SEN) are turned off, and the other end of the current sources (IP1 to IPN) and the other end of the current sources (IN1 to INN) are disconnected.
Each of the plurality of input segment units (IU21 to IU2N) outputs a current to the terminal (Iout +) and the terminal (Iout−). In the output stage (22), the differential operational amplifier (200) Output analog signals.

Thus, in the D / A converter (20), during the period when the clock signal (Φ2) is at the high level, the input segment units (IU21 to IU2N) are supplied with currents to the terminals (Iout +) and (Iout−). The differential analog signal output by the differential operational amplifier (200) is output immediately before the clock signal (Φ1) goes to the low level last time, even though the above-described RTZ method is adopted. It is possible to hold the same voltage value as that of the signal.
That is, this D / A converter (20) can avoid distortion to the output signal due to the influence of inter-symbol interference by adopting the RTZ method, and is a problem when the RTZ method is adopted. The S / N ratio does not deteriorate due to the voltage level drop of the dynamic analog signal.

  Also, during the period when the clock signal (Φ2) is at the high level, the input switches (SE1 to SEN) are turned on in the plurality of input segment units (IU21 to IU2N), and the other ends of the current sources (IP1 to IPN) The other ends of the sources (IN1 to INN) are connected. Therefore, when the clock signal (Φ2) becomes low level and the clock signal (Φ1) becomes high level, the influence that occurs in the input segment units (IU21 to IU2N) depending on the input digital data is Iout +) and the terminal (Iout−) can be avoided. That is, the conversion accuracy of the D / A converter (20) can be improved.

(Third embodiment)
Next, a third embodiment of the present invention will be described.
The D / A converter (30) according to the third embodiment is a D / A converter that converts an N-bit digital signal into an analog signal. Here, each bit data of the N-bit digital signal is set as input digital data (D1 to DN).
The D / A converter (10) in the first embodiment applies a fully differential operational amplifier as the differential operational amplifier (100) of the output stage (12), whereas the D / A conversion in the third embodiment. As shown in FIG. 4, the device (30) is a differential operational amplifier (300) in which a single-ended operational amplifier is applied.

The D / A converter (30) includes an input stage (31), an output stage (32), a clock supply unit (33), and a switch control unit (34).
The input stage (31) includes a plurality of input segment units (IU31 to IU3N).
The input segment units (IU31 to IU3N) are provided corresponding to each bit of the digital signal to be converted. That is, in the case of an N-bit digital signal, N input segment units are provided.

Since the input segment units (IU31 to IU3N) have the same configuration, the input segment unit (IU3m (m = 1 to N)) will be described here.
In the input segment unit (IU3m), one end of the current source (IPm) connected to the reference voltage source (VREFP) and the other end of the reference voltage source (VREFN) (D / A converter (30) shown in FIG. 4) The input switch (SAm) that connects or disconnects the current source (INm) connected to the ground potential, the other end of the current source (IPm), and the terminal (Iout) that is the output terminal of the input segment unit (IU3m). ) And an input switch (SBm) for connecting or disconnecting the other end of the current source (INm) and the terminal (Iout), and the terminal (Iout) of the input switch (SAm) and the input switch (SBm) One end of the connected side is commonly connected to a terminal (Iout).

The current source (IPm) and the current source (INm) supply currents having different polarities and equal current values.
The input switch (SAm) responds to switch signals (φD1 to φDN) based on the input digital data (D1 to DN) and the clock signal (Φ1) given to the input segment units (IU31 to IU3N). Operate. The input switch (SBm) operates in response to a switch signal (φD1B to φDNB) based on the inverted signals (D1B to DNB) of the given input digital data (D1 to DN) and the clock signal (Φ1).

The terminals (Iout) of the plurality of input segment units (IU31 to IU3N) are connected in common.
The output stage (32) has a non-inverting input terminal, an inverting input terminal, and an output terminal (Vout), and includes a differential operational amplifier (300) composed of a single-ended operational amplifier that outputs a single-ended signal. Further, the output stage (32) includes a capacitive element (Cfb) connected between the inverting input terminal and the output terminal (Vout) of the differential operational amplifier (300), a terminal (Iout), and an output terminal (Vout). And a resistance element (Rfb) connected in parallel with the capacitor element (Cfb). The non-inverting input terminal of the differential operational amplifier (300) is connected to a common voltage source (VCM).

Further, the output stage (32) includes an output switch (SO1) for connecting or disconnecting the terminal (Iout) and the inverting input terminal of the differential operational amplifier (300), a terminal (Iout), and a common voltage source (VCM). And an output switch (SO2) to be connected or disconnected.
The output switch (SO1) includes a connection point between one end of the resistance element (Rfb) and the inverting input terminal of the differential operational amplifier (300), one end of the capacitive element (Cfb), and an inverting input terminal of the differential operational amplifier (300). It is connected between the connection points. One end of the output switch (SO2) is connected to a connection point between one end of the resistance element (Rfb) and the inverting input terminal of the differential operational amplifier (300), and the other end is connected to a common voltage source (VCM).

These output switches (SO1) operate according to the clock signal (Φ1). The output switch (SO2) operates according to the clock signal (Φ2).
The clock supply unit (33) supplies the same two types of clock signals (Φ1, Φ2) as in the first embodiment shown in FIG.
The switch control unit (34) receives input digital data (D1 to DN) and a clock signal (Φ1) output from the clock supply unit (33), and based on these, the switch control unit (34) in the first embodiment. The switch signals (φD1 to φDN) and switch signals (φD1B to φDNB) shown in FIG. 2 are generated in the same procedure as the switch control unit (34). Then, the switch signals (φD1 to φDN) are output to the input switches (SA1 to SAN), and the switch signals (φD1B to φDNB) are output to the input switches (SB1 to SBN).

  In the input segment units (IU31 to IU3N), input switches (SA1 to SAN) for connecting or disconnecting the other end of the current source (IP1 to IPN) and one terminal (Iout), one end of which is connected to the reference voltage source (VREFP) Is turned on when the polarity of the switch signals (φD1 to φDN) generated based on the input digital data (D1 to DN) is “+1”, and the other end of the current sources (IP1 to IPN) and the terminal (Iout) When the polarity of the switch signal (φD1 to φDN) is “−1”, the switch is turned off and the other end of the current source (IP1 to IPN) and the terminal (Iout) are disconnected.

  On the other hand, the input switches (SB1 to SBN) for connecting or disconnecting the other end of the current source (IN1 to INN) and the terminal (Iout) whose one end is connected to the reference voltage source (VREFN) are inverted signals of the input digital data. When the polarity of the switch signal (φD1B to φDNB) generated based on (D1B to DNB) is “+1”, the switch is turned on to connect the other end of the current source (IN1 to INN) and the terminal (Iout), and switch When the polarity of the signal (φD1B to φDNB) is “−1”, the signal is turned off and the other end of the current source (IN1 to INN) and the terminal (Iout) are disconnected.

That is, these input switches (SA1 to SAN, SB1 to SBN) operate in the RTZ system based on the switch signals (φD1 to φDN) and the switch signals (φD1B to φDNB).
The output switch (SO1) is turned on when the clock signal (Φ1) is at a high level, and is turned off at other times.
The output switch (SO2) is turned on when the clock signal (Φ2) is at a high level, and is turned off at other times.

Next, the operation of the D / A converter (30) shown in FIG. 4 will be described.
As shown in FIG. 2, when the clock signal (Φ1) is at the high level and the clock signal (Φ2) is at the low level, the output switch (SO1) that operates according to the clock signal (Φ1) is turned on and the terminal (Iout) And the inverting input terminal of the differential operational amplifier (300). On the other hand, the output switch (SO2) that operates according to the clock signal (Φ2) is turned off, and the terminal (Iout) and the common voltage source (VCM) are disconnected.

In a plurality of input segment units (IU31 to IU3N), input switches (SA1 to SAN) are selected according to input digital data (D1 to DN) and inverted signals (D1B to DNB) of the input digital data given to each unit. And one of the input switches (SB1 to SBN) is turned on, and the other is turned off.
Each of the plurality of input segment units (IU31 to IU3N) outputs a current to the terminal (Iout), and in the output stage (32), the differential operational amplifier (300) uses the potential of the common voltage source (VCM) as a reference. A single-ended signal is output.

  When the clock signal (Φ1) becomes low level and the clock signal (Φ2) switches to high level from the state where the clock signal (Φ1) is high level, the input digital data (D1 to DN) and its inverted signal (D1B to DNB) ), The switch signals (φD1 to φDN) and (φD1B to φDNB) are switched to “−1”. Therefore, the input switches (SA1 to SAN) and the input switches (SB1 to SBN) are turned off, and the other end of the current source (IP1 to IPN) and the other end of the current source (IN1 to INN) are connected to the terminal (Iout). ).

The output switch (SO1) that operates in response to the clock signal (Φ1) is turned off, and the terminal (Iout) and the inverting input terminal of the differential operational amplifier (300) are disconnected. On the other hand, the output switch (SO2) that operates in response to the clock signal (Φ2) is turned on to connect the terminal (Iout) and the common voltage source (VCM).
Also in the third embodiment, as shown in FIG. 2, during the period T11 when the clock signal (Φ2) is at a high level, the single-ended signal output by the differential operational amplifier (300) is the same as the differential operational amplifier (300). The capacitor element (Cfb) holds the same voltage value as the signal output immediately before the clock signal (Φ1) changes from the high level to the low level, that is, the signal output in the period T10.

  When the clock signal (Φ2) becomes low level again and the clock signal (Φ1) switches to high level from the state where the clock signal (Φ2) is high level, the output switch (SO1) is turned on and the terminal ( Iout) and the inverting input terminal of the differential operational amplifier (300) are connected, the output switch (SO2) is turned off, and the terminal (Iout) and the common voltage source (VCM) are disconnected.

Further, in the plurality of input segment units (IU21 to IU2N), new input digital data (D1-NEXT to DN-NEXT) given for each unit and inverted signal (D1B-NEXT to DNB-) of the new input digital data are given. In response to NEXT), one of the input switches (SA1 to SAN) and the input switches (SB1 to SBN) is turned on, and the other is turned off.
Each of the plurality of input segment units (IU21 to IU2N) outputs a current to the terminal (Iout), and in the output stage (32), the differential operational amplifier (300) outputs a new single-ended signal.

Thus, in the D / A converter (30), the input segment units (IU31 to IU3N) do not output current to the terminal (Iout) during the period when the clock signal (Φ2) is at the high level. The single-ended signal output from the differential operational amplifier (300) is the same voltage value as the signal output immediately before the clock signal (Φ1) goes to the low level last time. Can be held.
Therefore, the D / A converter (30) in the third embodiment can avoid distortion to the output signal due to the influence of intersymbol interference, and in addition to the differential analog signal, which is a problem in the RTZ system. It is possible to avoid the deterioration of the S / N ratio due to the voltage level drop.

(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described.
In the D / A converter (40) according to the fourth embodiment, the D / A converter (20) in the second embodiment is a fully differential type as a differential operational amplifier (200) of the output stage (22). Whereas the operational amplifier is applied, the D / A converter (40) in the fourth embodiment is a single operational amplifier as the differential operational amplifier (400) as shown in FIG.
The D / A converter (40) includes an input stage (41), an output stage (42), a clock supply unit (43), and a switch control unit (44).

The input stage (41) includes a plurality of input segment units (IU41 to IU4N).
The input segment units (IU41 to IU4N) are provided corresponding to each bit of the digital signal to be converted. That is, in the case of an N-bit digital signal, N input segment units are provided.
Since the input segment units (IU41 to IU4N) have the same configuration, the input segment unit (IU4m (m = 1 to N)) will be described here.

  The input segment unit (IU4m) further includes an input switch (SEm) in the input segment unit (IU3m) in the third embodiment. The input switch (SEm) has one end connected to the reference voltage source (VREFP) and the other end of the current source (INm) connected to the reference voltage source (VREFN). Connect or disconnect. The input switch (SEm) operates according to the clock signal (Φ2). That is, when the clock signal (Φ2) is at a high level, it is turned on, and at other times it is turned off.

The output stage (42) has the same functional configuration as the output stage (32) in the third embodiment. In the output stage (42), the differential operational amplifier (400) corresponds to the differential operational amplifier (300) of the output stage (32) in the third embodiment, and the other elements are given the same reference numerals.
The clock supply unit (43) supplies the same two types of clock signals (Φ1, Φ2) as the clock supply unit (33) in the third embodiment shown in FIG.
The switch control unit (44) has the same functional configuration as the switch control unit (34) in the third embodiment. That is, the input switches (SA1 to SAN, SB1 to SBN) operate in the RTZ system based on the switch signal (φD1 to φDN) and the switch signal (φD1B to φDNB).

Next, the operation of the D / A converter (40) in the fourth embodiment shown in FIG. 5 will be described.
As shown in FIG. 2, when the clock signal (Φ1) is at the high level and the clock signal (Φ2) is at the low level, the output switch (SO1) is turned on in the output stage (42) and is differential from the terminal (Iout). The inverting input terminal of the operational amplifier (400) is connected. Further, the output switch (SO2) that operates according to the clock signal (Φ2) is turned off, and the terminal (Iout) and the common voltage source (VCM) are disconnected.

In the input stage (41), in the plurality of input segment units (IU41 to IU4N), in accordance with input digital data (D1 to DN) given to each unit and inverted signals (D1B to DNB) of the input digital data, One of the input switches (SA1 to SAN) and the input switches (SB1 to SBN) is turned on, and the other is turned off.
At this time, the input switches (SE1 to SEN) that operate according to the clock signal (Φ2) are turned off, and the other ends of the current sources (IP1 to IPN) and the other ends of the current sources (IN1 to INN) are disconnected. .

  Each of the plurality of input segment units (IU41 to IU4N) outputs a current to the terminal (Iout), and the sum of the currents output from the input segment units (IU41 to IU4N) is output from the terminal (Iout). The In the output stage (42), the current signal output from this terminal (Iout) is input to the inverting input terminal of the differential operational amplifier (400), and the differential operational amplifier (400) outputs a single-ended signal.

  When the clock signal (Φ1) is switched to the low level and the clock signal (Φ2) is switched to the high level from the state where the clock signal (Φ1) is at the high level, the input digital data (D1 to DN) and the inverted signals (D1B to DNB) ), The switch signals (φD1 to φDN) and (φD1B to φDNB) are switched to “−1”. Therefore, the input switches (SA1 to SAN) and the input switches (SB1 to SBN) are turned off, and the other end of the current source (IP1 to IPN) and the other end of the current source (IN1 to INN) are connected to the terminal (Iout). Disconnected from.

At this time, the input switches (SE1 to SEN) are turned on, and the other ends of the current sources (IP1 to IPN) are connected to the other ends of the current sources (IN1 to INN).
Further, the output switch (SO1) is turned off and the terminal (Iout) and the inverting input terminal of the differential operational amplifier (400) are disconnected, and the output switch (SO2) is turned on and the terminal (Iout) and the common voltage source (VCM). ).

  Also in the fourth embodiment, as shown in FIG. 2, in the period T11 in which the clock signal (Φ1) is at the low level and the clock signal (Φ2) is at the high level, the single-ended signal output by the differential operational amplifier (400). Is a signal output immediately before the clock signal (Φ1) is switched from the high level to the low level by the differential operational amplifier (400) and the capacitive element (Cfb), that is, output in the period T10 shown in FIG. Holds the same voltage value as that of the signal.

  When the clock signal (Φ1) is switched to the high level again from the state where the clock signal (Φ1) is at the low level and the clock signal (Φ2) is at the high level, the output switch (SO1) is turned on and the terminal (Iout) and the inverting input terminal of the differential operational amplifier (400) are connected, and the output switch (SO2) is turned off and the terminal (Iout) and the common voltage source (VCM) are disconnected. Is done.

  Also, in the plurality of input segment units (IU41 to IU4N), new input digital data (D1-NEXT to DN-NEXT) given for each unit and new input digital data inverted signal (D1B-NEXT to DNB-) In response to NEXT), one of the input switches (SA1 to SAN) and the input switches (SB1 to SBN) is turned on, and the other is turned off.

Further, the input switches (SE1 to SEN) are turned off, and the other end of the current sources (IP1 to IPN) and the other end of the current sources (IN1 to INN) are disconnected.
Each of the plurality of input segment units (IU41 to IU4N) outputs a current to the terminal (Iout), and in the output stage (42), the differential operational amplifier (400) outputs a new single-ended signal.

Thus, in the D / A converter (40), the input segment units (IU41 to IU4N) do not output current to the terminal (Iout) during the period when the clock signal (Φ2) is at the high level. The single-ended signal output from the differential operational amplifier (400) is the same voltage value as the signal output immediately before the clock signal (Φ1) goes to the low level last time. Can be held.
In other words, the D / A converter (40) can avoid distortion to the output signal due to the influence of intersymbol interference by adopting the RTZ method, and is a problem when the RTZ method is adopted. The S / N ratio does not deteriorate due to the voltage level drop of the dynamic analog signal.

  Also, during the period when the clock signal (Φ2) is at the high level, the input switches (SE1 to SEN) are turned on in the plurality of input segment units (IU41 to IU4N), and the other ends of the current sources (IP1 to IPN) The other ends of the sources (IN1 to INN) are connected. Therefore, next, when the clock signal (Φ2) becomes low level and the clock signal (Φ1) becomes high level, the influence that occurs in the input segment units (IU41 to IU4N) depending on the input digital data is expressed by the terminal ( Iout) can be avoided. That is, the conversion accuracy of the D / A converter (40) can be improved.

In each of the above embodiments, the current source (IP1 to IPN) having one end connected to the reference voltage source (VREFP) and the current source having one end connected to the reference voltage source (VREFN) are provided in the input segment unit. Each of (IN1 to INN) may have the same current value between the input segment units, or may be set to a different value.
Since the current values of the current sources (IP1 to IPN) and the current sources (IN1 to INN) are set equal between the input segment units, noise due to size errors can be reduced.

Also, between the input segment units, the current values of the current sources (IP1 to IPN) and the current values of the current sources (IN1 to INN) are doubled in order from small to large. By setting, the occupation area can be reduced.
In the input segment unit, the current sources (IP1 to IPN) and the current sources (IN1 to INN) may be composed of a voltage source and a resistance element, and may be composed of a voltage source and a MOS transistor or a bipolar transistor. May be.
Moreover, in each D / A converter (10-40), the number of input segment units is not restricted to plural, and may be one.

In the first and second embodiments, as shown in FIGS. 1 and 3, in the input stage (11, 21), the current source (IPm, INm) and the terminals (Iout +, Iout−) The case where the current signal corresponding to the input digital data (Dm) is output by switching the connection / disconnection by the input switch (SAm to SDm) has been described. However, the present invention is not limited to this. The configuration of the input stage (11, 21) is not limited to this as long as a current signal corresponding to (Dm) can be output to the commonly connected terminals (Iout +, Iout−).
Similarly, in the third and fourth embodiments, if the current signal corresponding to the input digital data (Dm) can be output to the commonly connected terminal (Iout), the configuration of the input stage (31, 41) is The configuration is not limited to the above.

(Fifth embodiment)
Next, a fifth embodiment of the present invention will be described.
In the fifth embodiment, the D / A converter (10-40) of the present invention is applied as a D / A converter of an oversampling delta sigma D / A converter (70) for audio. FIG. 6 is a configuration diagram showing an example thereof.
As shown in FIG. 6, the oversampling delta-sigma D / A converter (70) includes a digital interpolation filter (710), a 15-level digital delta-sigma modulator (720), a DWA dynamic element A matching circuit (730) and a 15-level D / A converter (740) are provided.

  The digital interpolation filter (710) interpolates a digital signal sampled at a predetermined sampling frequency and converts it to a digital signal having a frequency higher than the sampling frequency. The 15-level digital delta-sigma modulator (720) performs noise shaping on the digital signal interpolated by the digital interpolation filter (710) and converts it into a 15-level digital signal having a lower bit number (low resolution). . The 15-level D / A converter (740) is a circuit that receives the 15-level digital signal output from the DWA dynamic element matching circuit (730) and converts it into an analog signal, as shown in FIG. D / A converter (10), D / A converter (20) shown in FIG. 3, D / A converter (30) shown in FIG. 4, D / A conversion shown in FIG. A vessel (40) can be applied.

  The oversampling delta sigma D / A converter (70) shown in FIG. 6 converts the input 16-bit digital signal Din into 64 times, 128 times, or 256 times using a digital interpolation filter (710). Converted to high-speed binary 16-bit digital data, noise-shaped with a 15-level digital delta-sigma modulator (720), converted to low-resolution (15-level) digital data, and DWA dynamic element matching The circuit (730) performs signal processing for reducing mismatch noise in the analog conversion segment.

The analog signal is converted by a 15-level D / A converter (740) composed of the D / A converters (10 to 40) of the present invention, and an analog signal OUT is output.
As described above, the D / A converters (10 to 40) of the present invention oversample the input digital signal into high-speed digital data, and convert the analog signal into an analog signal, for example, an audio D / A converter. Available with A converter.
That is, an oversampling delta-sigma D / A converter (70) using a D / A converter with a low distortion and a high S / N ratio can be realized.

The D / A converter of the present invention is required to output a low distortion D / A converted analog signal, for example, an audio D / A converter, a video D / A converter, Although it can be used in a D / A converter for industrial measurement or the like, it is not limited to these applications, and the effect can be exhibited when it is used in an application where an analog signal with less distortion is required.
In particular, the use of an input digital signal, for example, in an audio D / A converter that converts it into an analog signal after oversampling the input digital signal into high-speed digital data is an effective example.

10, 20, 30, 40, 50 D / A converters 11, 21, 31, 41, 51 Input stages 12, 22, 32, 42, 52 Output stages 13, 23, 33, 43 Clock supply units 14, 24, 34, 44 Switch control unit 70 Oversampling type delta sigma D / A converter 100, 200, 300, 400, 500 Differential operational amplifier 710 Digital interpolation filter 720 15 levels Digital delta sigma modulator 730 DWA system dynamic element Matching circuit 740 15 level D / A converter Iout + terminal Iout- terminal Iout terminal Vout + non-inverting output terminal Vout- inverting output terminal Vout output terminal VREFP reference voltage source VREFN reference voltage source VCM common voltage sources IU11 to IU1N, IU21 to IU2N input Segment units IU31-IU3N, IU41-IU4N Input segment units IU51-IU5N Input segment units IP1-IPN Current sources IN1-INN Current sources SA1-SAN Input switches SB1-SBN Input switches SC1-SCN Input switches SD1-SDN Input switches SE1- SEN input switches SO1, SO2, SO3 output switches Rfb, Rfb1, Rfb2 resistive elements Cfb, Cfb1, Cfb2 capacitive elements

Claims (10)

A D / A converter that converts a digital signal composed of one or more input digital data that is a 1-bit signal into an analog signal,
A first current source and a second current source;
A first input switch for connecting or disconnecting the first current source and the first output terminal according to the input digital data;
A second input switch for connecting or disconnecting the first current source and the second output terminal according to an inverted signal of the input digital data;
A third input switch for connecting or disconnecting the second current source and the second output terminal according to the input digital data;
An input segment unit comprising: a fourth input switch that connects or disconnects the second current source and the first output terminal according to an inverted signal of the input digital data, for each input digital data Have
An input stage in which the first output terminals and the second output terminals of the input segment unit are respectively connected in common;
A differential operational amplifier;
A first capacitive element connected between the inverting input terminal and the non-inverting output terminal of the differential operational amplifier;
A second capacitive element connected between a non-inverting input terminal and an inverting output terminal of the differential operational amplifier;
A first resistive element connected in parallel with the first capacitive element between the first output terminal and a non-inverting output terminal of the differential operational amplifier;
A second resistive element connected in parallel with the second capacitive element between the second output terminal and an inverting output terminal of the differential operational amplifier;
A first output switch for connecting or disconnecting the first output terminal and an inverting input terminal of the differential operational amplifier;
A second output switch for connecting or disconnecting the second output terminal and the non-inverting input terminal of the differential operational amplifier;
A third output switch for connecting or disconnecting the first output end and the second output end;
Have
The differential operational amplifier includes an output stage that outputs a differential analog signal corresponding to the digital signal,
In the first period, which is the front period of one cycle of the input digital data,
In each of the input segment units, either one of the first input switch and the third input switch, or the second input switch and the fourth input switch is turned on according to the input digital data. And the other pair is turned off, and the first output switch and the second output switch are turned on, and the third output switch is turned off,
In a second period that is a remaining period following the first period in one cycle of the input digital data,
In each of the input segment units, the first, second, third and fourth input switches are turned off, and the first output switch and the second output switch are turned off. Is a D / A converter characterized by being turned on. The input segment unit has a fifth input switch for connecting or disconnecting the output side of the first current source and the input side of the second current source;
In the first period, the fifth input switch is turned off,
2. The D / A converter according to claim 1, wherein the fifth input switch is turned on in the second period. A D / A converter that converts a digital signal composed of one or more input digital data that is a 1-bit signal into an analog signal,
A first current source and a second current source;
A first input switch for connecting or disconnecting the first current source and an output terminal according to the input digital data;
A second input switch that connects or disconnects the second current source and the output terminal in response to an inverted signal of the input digital data, and has an input segment unit for each input digital data,
An input stage in which the output ends of the input segment units are respectively connected in common;
An operational amplifier,
A capacitive element connected between the inverting input terminal and the output terminal of the operational amplifier;
A resistive element connected in parallel with the capacitive element between the output terminal and the output terminal of the operational amplifier;
A first output switch for connecting or disconnecting the output terminal and the inverting input terminal of the operational amplifier;
A second output switch for connecting or disconnecting the output terminal and a reference potential;
Have
The operational amplifier includes an output stage that outputs an analog signal corresponding to the digital signal,
In the first period, which is the front period of one cycle of the input digital data,
In each of the input segment units, either the first input switch or the second input switch is turned on and the other is turned off according to the input digital data, and the first output switch is turned on. And the second output switch is turned off,
In a second period that is a remaining period following the first period in one cycle of the input digital data,
In each of the input segment units, the first and second input switches are turned off, and the first output switch is turned off and the second output switch is turned on. converter. The input segment unit has a third input switch for connecting or disconnecting the output side of the first current source and the input side of the second current source,
In the first period, the third input switch is turned off,
4. The D / A converter according to claim 3, wherein the third input switch is turned on in the second period.   5. The D / according to claim 1, wherein the first current source and the second current source supply currents having different polarities and equal current values. 6. A converter. A plurality of the input segment units;
6. The D / of claim 1, wherein current values of the first current sources and the second current sources are equal between the input segment units, respectively. A converter. A plurality of the input segment units;
6. The first current source and the second current source are set so that the current value is doubled in order between the input segment units, respectively. The D / A converter of any one of Claims. A D / A converter according to any one of claims 1 to 7 and a digital delta-sigma modulator,
The D / A converter converts the digital signal processed through the digital delta sigma modulator into an analog signal, and is a delta sigma type D / A converter. A D / A converter according to any one of claims 1 to 7, a digital delta-sigma modulator, and a dynamic element matching circuit,
The D / A converter converts the digital signal processed through the digital delta sigma modulator and the dynamic element matching circuit into an analog signal, and is a delta sigma type D / A converter. A D / A converter that converts a digital signal composed of one or more input digital data that is a 1-bit signal into an analog signal,
An input segment unit which is provided for each input digital data and outputs a current signal corresponding to the given input digital data to a first output terminal and a second output terminal; An input stage in which the first output terminals and the second output terminals are connected in common;
A differential operational amplifier;
A first capacitive element connected between the inverting input terminal and the non-inverting output terminal of the differential operational amplifier;
A second capacitive element connected between a non-inverting input terminal and an inverting output terminal of the differential operational amplifier;
A first resistive element connected in parallel with the first capacitive element between the first output terminal and a non-inverting output terminal of the differential operational amplifier;
A second resistive element connected in parallel with the second capacitive element between the second output terminal and an inverting output terminal of the differential operational amplifier;
A first output switch for connecting or disconnecting the first output terminal and an inverting input terminal of the differential operational amplifier;
A second output switch for connecting or disconnecting the second output terminal and the non-inverting input terminal of the differential operational amplifier;
A third output switch for connecting or disconnecting the first output end and the second output end;
Have
An output stage for outputting a differential analog signal corresponding to the digital signal,
In the first period, which is the front period of one cycle of the input digital data,
Each input segment unit outputs a current signal according to the input digital data, and the first output switch and the second output switch are turned on, and the third output switch is turned off,
In a second period that is a remaining period following the first period in one cycle of the input digital data,
Each input segment unit stops outputting a current signal, and the first output switch and the second output switch are turned off and the third output switch is turned on. A converter.

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