JP2014159367A - Manufacturing method of silicon epitaxial wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a silicon epitaxial wafer that can reduce oxygen precipitation to prevent wafer deformation from occurring even when subjected to rapid temperature increase/decrease heat treatment and can prevent slip extension from occurring due to boat scratches and transfer scratches causing strength deterioration of a wafer.SOLUTION: A manufacturing method of a silicon epitaxial wafer includes an epitaxial step for growing an epitaxial layer on the surface of a substrate that is doped with boron so as to have an ohmic value of 0.02 Ωcm - 1 kΩcm and has an initial oxygen concentration Oi of 14.0×10- 22×10atoms/cm(Old-ASTM), and a deposition/dissolution/heat treatment step for subjecting the substrate to treatment under conditions of a treatment temperature of 1,150°C-1,300°C, a holding time of 5 sec - 1 min, and a temperature descending speed of 10°C/sec - 0.1°C/sec before and after the epitaxial step.

Description

  The present invention relates to a method for manufacturing a silicon epitaxial wafer, and particularly to a technique suitable for use in preventing deformation such as warpage of a silicon epitaxial wafer subjected to a heat treatment in which high internal stress is generated.

  As the thermal process in the device process, a large number of low-temperature processes and high-temperature processes are used. Therefore, even when an epitaxial wafer is used, oxygen precipitates are formed on the substrate wafer. Conventionally, this oxygen precipitate is effective in capturing metal impurities (gettering) that may occur during the process, and the formation of oxygen precipitate has been desired.

  However, in recent device manufacturing processes, many rapid heating / cooling steps have been used, and the stress load in heat treatment during the device process is increasing. In particular, due to the high integration of devices, such a rapid temperature raising / lowering process tends to be further shortened and the maximum temperature tends to be increased. An annealing process called FLA (flash lamp annealing), LSA (Laser Spike Anneal), LTP (laser thermal process), or Spike-RTA (Rapid Thermal Annealing) may be used from the 45 nm node (hp65).

Of these, in FLA heat treatment, the wafer is heated to an initial temperature of 400 ° C. to 600 ° C., and the entire surface of the wafer is irradiated with light having a short wavelength such as an Xe lamp, so that only the wafer surface layer is silicon at 1100 ° C. or more. Rapid heating and cooling to near the melting point. The heat treatment time is in units (order) from μ (micro) seconds to milliseconds.
Techniques relating to FLA processing are disclosed in the following documents.

Special table 2008-515200 JP 2008-98640 A

  In such a heat treatment, a temperature difference of several hundred degrees Celsius occurs between the front surface and the back surface of the wafer, and an extremely high stress may be applied as compared with RTA that has been performed previously. Specifically, there is a possibility that a thermal stress exceeding 20 MPa is partially generated.

  However, in such a rapid temperature increase / decrease process, when oxygen precipitates are formed, the formed precipitates vary in size, and dislocations (Slip) are generated from the large-sized precipitates, and the wafer is localized. The problem of warping may occur. When warping occurs, the device process causes a misalignment with the underlying pattern during exposure, which lowers the device yield. Further, it is impossible to restore the shape of the wafer that has locally warped in this way.

On the other hand, it is impossible to completely suppress boat damage and conveyance damage in the device process. Dislocations (Slip) that cause wafer deformation as described above also occur from this boat flaw and transport flaw. It is known that such slip extension is suppressed when the oxygen concentration / boron concentration of the wafer is higher.
However, an increase in oxygen concentration and an increase in boron concentration have the effect of promoting the formation of oxygen precipitates at the same time. Therefore, it has been difficult to suppress the generation of slip caused by the process while suppressing the occurrence of wafer deformation and warpage due to the formation of oxygen precipitates.

  Furthermore, as precipitation formation proceeds in the process, oxygen is consumed and interstitial oxygen is reduced. In this case, extension of the generated dislocations cannot be further suppressed, and it is considered that the wafer strength further decreases. In addition, as described in the 0042th stage of Patent Document 2, in the device manufacturing process, heat treatment at 700 ° C. or higher is not performed in the process after the FLA for reasons such as suppressing diffusion of impurities. Since there are many restrictions on conditions, there has been a demand for solving such a problem in a silicon wafer before device manufacture.

  The present invention has been made in view of the above circumstances, and in order to prevent local wafer deformation in the device process as described above, precipitation formation does not occur in the device process, and an epitaxial wafer excellent in slip resistance and An object of the present invention is to provide a manufacturing method thereof.

  The inventors have high processing temperature (peak temperature) in the rapid temperature rising / falling process such as FLA, Spike-RTA, etc., and the temperature rise / fall is performed in a very short time, so the stress applied to the wafer increases, Since a deformation such as a warp occurs in the wafer due to a slip that is extended during oxygen precipitation, a means for providing a wafer that can withstand this deformation was sought. First, during heat treatment that is not strict as in the conventional conditions, slip elongation prevention due to oxygen precipitates in the wafer that has been adopted as a means for preventing wafer deformation is conversely because the temperature conditions in the above heat treatment are too severe and strict. It was found that slip extension from oxygen precipitation is ineffective because it causes wafer deformation. Further, in FLA and Spike-RTA, since the state of stress generation in the wafer differs depending on the type of wafer subjected to heat treatment, it is necessary to take a deformation prevention measure corresponding to these wafer types. all right.

  Specifically, before being subjected to a device process that generates a large stress, in order to suppress oxygen precipitation inside the wafer, setting of the oxygen concentration at the time of pulling up the ingot, setting of the dopant concentration added at the time of pulling, and precipitation nuclei RTA treatment conditions for dissolving As a result, by appropriately setting these conditions as in the examples described later, the slip suppression state that causes deformation in the wafer by the rapid temperature raising and lowering process and simultaneously processing other than the rapid temperature raising and lowering process. It has been found that it is possible to realize a state in which slip extension caused by a boat flaw or a conveyance flaw which is a problem can be prevented.

The method for producing a silicon epitaxial wafer according to the present invention is such that the internal stress generated in the wafer during heat treatment exceeds 20 MPa under the conditions that the maximum temperature is 1050 ° C. or higher and the melting point of silicon is 150 ° C./sec or higher. A method for manufacturing a silicon epitaxial wafer to be used in a semiconductor device manufacturing process having a heat treatment step as a condition,
An epitaxial process for growing an epitaxial layer on the surface of a substrate doped with 1 × 10 ^{13 to} 5 × 10 ¹⁴ atoms / cm ^{3 of} nitrogen, and a processing temperature in the range of 1200 to 1300 ° C. after the epitaxial process is maintained. By having a precipitation melting heat treatment step in which the range of time is 5 sec to 1 min, and the temperature drop rate is 10 ° C./sec to 0.1 ° C./sec in which the pores are not frozen,
Acceptable standard for oxygen precipitate density inside wafer when heat treatment at 1000 ° C for 16 hours is performed, and maximum deviation due to wafer deformation caused by slip dislocation generated from precipitate in photolithography process in semiconductor device manufacturing process The value is 5 × 10 ⁴ pieces / cm ² or less which does not exceed the value of 10 nm.
The method for producing a silicon epitaxial wafer according to the present invention is such that the internal stress generated in the wafer during heat treatment exceeds 20 MPa under the conditions that the maximum temperature is 1050 ° C. or higher and the melting point of silicon is 150 ° C./sec or higher. A method for manufacturing a silicon epitaxial wafer to be used in a semiconductor device manufacturing process having a heat treatment step as a condition,
For a substrate doped with boron to have a resistance value of 0.02 Ωcm to 1 kΩcm and an initial oxygen concentration Oi of 14.0 × 10 ^{17 to} 22 × 10 ¹⁷ atoms / cm ³ (Old-ASTM) An epitaxial process for growing an epitaxial layer on the surface, and a treatment temperature range of 1150 ° C. to 1300 ° C., a holding time range of 5 sec to 1 min, and a temperature lowering rate before and after the epitaxial process are 10 ° C./sec. By having a precipitation dissolution heat treatment step in the range of ~ 0.1 ° C / sec,
Acceptable standard for oxygen precipitate density inside wafer when heat treatment at 1000 ° C for 16 hours is performed, and maximum deviation due to wafer deformation caused by slip dislocation generated from precipitate in photolithography process in semiconductor device manufacturing process The value is 5 × 10 ⁴ pieces / cm ² or less which does not exceed the value of 10 nm.
In the present invention, there is provided a method for producing a silicon epitaxial wafer used in a semiconductor device production process having a heat treatment step in which the maximum temperature is 1050 ° C. or more and below the melting point of silicon and the temperature rising / falling rate is 150 ° C./sec or more. And
An epitaxial process for growing an epitaxial layer on the surface of a substrate doped with 1 × 10 ^{13 to} 5 × 10 ¹⁴ atoms / cm ^{3 of} nitrogen, and a processing temperature in the range of 1200 to 1300 ° C. after the epitaxial process is maintained. The above problems have been solved by having a precipitation dissolution heat treatment step in which the time is in the range of 5 sec to 1 min and the temperature drop rate is in the range of 10 ° C./sec to 0.1 ° C./sec.
The present invention is a method for manufacturing a silicon epitaxial wafer to be used in a semiconductor device manufacturing process having a heat treatment step in which the maximum temperature is 1050 ° C. or higher and below the melting point of silicon and the heating / cooling rate is 150 ° C./sec or higher. And
Boron is doped so that the resistance value is 0.02 Ωcm to 0.001 Ωcm, and the initial oxygen concentration Oi is 11.0 × 10 ^{17 to} 3 × 10 ¹⁷ atoms / cm ³ (Old-ASTM). On the other hand, the above-mentioned problem was solved by having an epitaxial process for growing an epitaxial layer on the surface.
The method for producing a silicon epitaxial wafer according to the present invention provides a silicon device for use in a semiconductor device production process having a heat treatment step in which the maximum temperature is 1050 ° C. or more and below the melting point of silicon and the temperature rising / falling rate is 150 ° C./sec or more. An epitaxial wafer manufacturing method comprising:
Boron is doped so that the resistance value becomes 0.02 Ωcm to 0.001 Ωcm, and the initial oxygen concentration Oi is 11.0 × 10 ¹⁷ to 18 × 10 ¹⁷ atoms / cm ³ (Old-ASTM). On the other hand, an epitaxial process for growing an epitaxial layer on the surface, and before the epitaxial process, a processing temperature range of 1150 ° C. to 1300 ° C., a holding time range of 5 sec to 1 min, and a cooling rate of 10 ° C./sec to 0.1 ° C. The above-described problems have been solved by having a precipitation dissolution heat treatment step in the range of / sec.
In the present invention, in the precipitation dissolution heat treatment step, it is also possible to employ means for making the treatment atmosphere a non-oxidizing gas atmosphere that does not contain nitrogen.
In the present invention, in the precipitation-melting heat treatment step, it is also possible to employ means for setting a mixed atmosphere of non-oxidizing gas not containing nitrogen and 1% or more oxygen gas as the processing atmosphere.
In the present invention, in the precipitation dissolution heat treatment step, a mixed atmosphere of non-oxidizing gas not containing nitrogen and 3% or more oxygen gas is used as the processing atmosphere, and the temperature lowering rate is in the range of 50 ° C./sec to 20 ° C./sec. Means can also be employed.
The silicon epitaxial wafer of the present invention can be manufactured by any one of the above-described silicon epitaxial wafer manufacturing methods.

(High oxygen p-wafer with RTA treatment before and after Epi)
The method for producing a silicon epitaxial wafer according to the present invention provides a silicon device for use in a semiconductor device production process having a heat treatment step in which the maximum temperature is 1050 ° C. or more and below the melting point of silicon and the temperature rising / falling rate is 150 ° C./sec or more. An epitaxial wafer manufacturing method comprising:
For a substrate doped with boron to have a resistance value of 0.02 Ωcm to 1 kΩcm and an initial oxygen concentration Oi of 14.0 × 10 ^{17 to} 22 × 10 ¹⁷ atoms / cm ³ (Old-ASTM) An epitaxial process for growing an epitaxial layer on the surface, and before and after the epitaxial process, a processing temperature range of 1150 ° C. to 1300 ° C., a holding time range of 5 sec to 1 min, and a cooling rate of 10 ° C./sec to 0.1 ° C. / Precipitation dissolution heat treatment step having a range of sec, even in a p-wafer having a relatively low boron concentration having a high oxygen concentration at the time of pulling and having a slip elongation suppressing effect, Depending on the process, the oxygen precipitation nuclei that cause deformation can be dissolved. The conditions are severe, the maximum temperature is in the range of 1050 ° C. to the silicon melting point to 2000 ° C., the heating / cooling rate is 150 ° C./sec to 10,000 ° C./sec, 500 ° C./sec to 3000 ° C./sec, 1000 ° C. to 2000 ° C./sec. A boat that can prevent deformation and at the same time reduce the strength of the wafer even when it is subjected to the device manufacturing process rapid heating and cooling heat treatment, which is an extremely severe condition in which the maximum stress generated in the silicon wafer exceeds 20 MPa. It is possible to provide a silicon wafer that can prevent slip extension caused by a flaw or a conveyance flaw.

  As an example of the rapid temperature raising / lowering process, there is an annealing process of a MOS FET at a 45 nm node (hp65). Here, annealing is performed at a higher temperature and in a shorter time than conventional RTA. As shown in FIG. 3, this is an ultra-shallow junction which is a shallow impurity diffusion region having a depth (junction depth) Xi of about 20 nm adjacent to the source Ms and drain Md of the MOS FET indicated by the symbol Mos. This is because, in Mex, it is necessary to realize a box-shaped impurity profile as shown in FIG. 4, that is, a uniform impurity concentration in the ultra-shallow junction Mex region and a steep change state at the boundary. In this way, the impurities implanted by the high heating temperature are fully activated to lower the resistance, and at the same time, the unnecessary diffusion of the impurities is suppressed by the short heating time and the deactivation of the activated impurities is avoided. is there.

As described above, in order to realize the junction depth Xi lower than 20 nm required for the 45 nm node (hp65), the wafer is heated to an initial temperature of 400 ° C. to 600 ° C. or less, and a short such as Xe flash lamp is used. FLA that irradiates the entire surface of the wafer with light of a wavelength and heats and cools only the wafer surface layer to about 900 ° C. to 1350 ° C. with a heat treatment time in milliseconds, or 400 ° C. to 600 ° C. on the hot plate. LSA is heated to 1100 ° C. or higher and rapidly cooled to near the melting point of silicon so that the heat treatment time is from microseconds to millisecond by irradiating a continuous wave laser and spot scanning the wafer. Etc. are performed.
For FLA and LSA, processing conditions are selected that can maintain halo impurity concentration distribution characteristics, reduce junction leakage, suppress gate leakage, reduce source / drain parasitic resistance, and suppress gate depletion. .

  In FLA and the like under the above conditions, the internal stress generated in the wafer during heat treatment may reach a level of 50 to 150 MPa. The rapid temperature raising / lowering process in the present invention is not limited to this FLA, but covers all severe heat treatments under conditions where the generated internal stress exceeds 20 MPa.

In addition, in FLA and Spike-RTA as a rapid temperature raising / lowering process, the temperature conditions are high, and the rate of temperature rise and temperature drop is large. Therefore, slip dislocation is caused from large-sized oxygen precipitates due to a large thermal stress as described above. Occur.
As a result, an overlay error (Overlay Error), that is, a situation in which the pattern overlay is shifted in the photolithography process performed before and after the rapid heating / cooling process in the device manufacturing, occurs.

  As an example, when a pattern is exposed on a silicon wafer as seen in the manufacture of IC, LSI, etc., as shown in FIG. 5, the wafer 1 is held and fixed on the work stage 2 by vacuum suction, and the photomask 3 is attached. It is held and fixed to a mask holder 4 above the work stage 2, the work stage 2 is raised, the thin plate-like work 1 is brought into close contact with the photomask 3, and then post-exposure is performed. A photoresist film (not shown) is formed on the surface of the wafer 1 in advance. The photoresist film is exposed to light and a pattern of the photomask 3 is baked.

  In FIG. 6, the amount of change in the horizontal direction generated when a pattern to be formed in the subsequent process of the rapid heating / cooling process is superimposed on the pattern formed in the previous process of the rapid heating / cooling process on the wafer. The length of the arrow at each point on the wafer is shown. During exposure, the wafer is vacuum-sucked on the stage. If there is deformation such as warping, the wafer is fixed to the stage with the deformation such as warping corrected during suction. It is considered that the pattern formed on the wafer in the previous process is deformed (horizontal movement) by the corrected deformation and is shifted from the original position to cause an overlay error.

  It is considered that deformation such as warpage of the wafer is caused by slip dislocations generated from precipitates having a large size. If deformation above a certain level occurs due to deformation such as warping, the deformation cannot be corrected, and the wafer will be discarded, resulting in a significant decrease in device yield and overall device manufacturing. Cost will increase significantly.

As the inventors' knowledge, such an overlay error can be almost predicted by the density of the generated BMD (oxygen precipitate), and as shown in FIG. 7, the generated BMD density is 5 × 10 ⁴ pieces / cm ^2. Deformation occurs abruptly at a level exceeding 1, and the maximum deviation amount exceeds the allowable reference value of 10 nm. The increase in the maximum deviation amount shown in the figure is considered to be caused by the increase in the slip generation amount.

  Conventionally, a wafer has been provided with gettering ability by oxygen precipitates, but the frequency at which gettering is actually required, that is, the frequency of occurrence of heavy metal contamination, is extremely low in the current device manufacturing process. This is because the cleanliness of the production line that mainly used φ200mm wafers that required gettering and the environment in which this line was installed (the rate at which foreign matter does not exist) is that of the current φ300mm wafers. This is because that of a φ450 mm wafer is extremely improved. Therefore, compared with the provision of gettering capability, which is a measure against contamination with a low probability of occurrence, we chose to reduce BMD as a measure against overlay errors that directly affect the device yield.

  At the same time, in Spike-RTA as the FLA or rapid temperature raising / lowering process, heat treatment is performed in a state where the wafer is supported such that the ring-shaped susceptor is in contact only with the edge portion of the wafer. For this reason, when observed by X-ray topography by reflection ore in the <4, 0, 0> direction, slip dislocation occurs at the supported wafer edge portion as shown in FIG.

  This slip dislocation is considered to have no effect on the device portion itself if it is about 3 mm from the periphery of the support portion, that is, the edge portion of the wafer that does not cover the device portion. As a result, the strength of the wafer itself is reduced, which causes a decrease in device yield. Previously, it was possible to suppress slip extension with oxygen precipitates. However, if there is oxygen precipitates that have a slip extension suppressing effect, an overlay error will occur due to wafer deformation in the rapid heating and cooling process. This measure is preferable.

The inventors of the present application have found a countermeasure capable of simultaneously preventing the occurrence of wafer deformation and the occurrence of slip in a silicon wafer manufacturing process.
In the present invention, the processing temperature in the epitaxial process may be lower than the processing temperature in the precipitation-melting heat treatment process, and general conditions can be set. Further, the temperature decreasing rate means a cooling rate in a range from at least the highest temperature to 700 ° C. which greatly contributes to dissolving the precipitate. Further, the dopant concentration such as boron in the epitaxial layer is set according to the standard of the device to be formed. However, since any contribution to slip and deformation of the present application is small, any material can be applied.

(N-dope high temperature RTA)
In the present invention, there is provided a method for producing a silicon epitaxial wafer used in a semiconductor device production process having a heat treatment step in which the maximum temperature is 1050 ° C. or more and below the melting point of silicon and the temperature rising / falling rate is 150 ° C./sec or more. And
An epitaxial process for growing an epitaxial layer on the surface of a substrate doped with 1 × 10 ^{13 to} 5 × 10 ¹⁴ atoms / cm ^{3 of} nitrogen, and a processing temperature in the range of 1200 to 1300 ° C. after the epitaxial process is maintained. Nitrogen-doped p-wafer that is easy to form oxygen precipitates by having a precipitation dissolution heat treatment step with a time range of 5 sec to 1 min and a temperature drop rate of 10 ° C./sec to 0.1 ° C./sec In this case, it is possible to simultaneously prevent wafer deformation and slip.

(Low oxygen p / p +, p / p ++ wafer)
The present invention is a method for manufacturing a silicon epitaxial wafer to be used in a semiconductor device manufacturing process having a heat treatment step in which the maximum temperature is 1050 ° C. or higher and below the melting point of silicon and the heating / cooling rate is 150 ° C./sec or higher. And
Boron is doped so that the resistance value is 0.02 Ωcm to 0.001 Ωcm, and the initial oxygen concentration Oi is 11.0 × 10 ^{17 to} 3 × 10 ¹⁷ atoms / cm ³ (Old-ASTM). On the other hand, by having an epitaxial process for growing an epitaxial layer on the surface of the p + wafer or p ++ wafer, which has a low oxygen concentration at the time of pulling up and a relatively high boron concentration that has a slip extension suppressing effect. Further, it is possible to simultaneously prevent wafer deformation and slip.

When a silicon single crystal (silicon ingot) into which the silicon epitaxial wafer of the present invention is sliced is grown by the CZ (Czochralski) method, the magnetic field applied to the silicon melt is set in the above oxygen concentration range. Although it can be handled by application, crucible / crystal rotation number control, etc., it may be difficult to reduce the interstitial oxygen concentration to 4 × 10 ¹⁷ atoms / cm ³ or less in the normal CZ method. In this case, the interstitial oxygen concentration can be reduced to 4 × 10 ¹⁷ atoms / cm ³ or less by MCZ method in which a single crystal is grown by applying a magnetic field to the silicon melt. The interstitial oxygen concentration can also be reduced by reducing the rotation speed of the quartz crucible and the single crystal to be pulled up.

Substantially, when the rotation speed of the quartz crucible is R1 (rpm) and the rotation speed of the crystal is R2 (rpm), the range is R1: 0.1 or more and 2 or less, R2: 1 or more and 7 or less, When R1: 0.5 or more and 0.7 or less, R2 <7-5 (R1-0.5) is satisfied, and when R1: 0.7 or more and 1 or less, R2 <6 is satisfied, and R1: 1 In the case of 2 or less, it can be set in a range satisfying R2 <6-4 (R1-1). In this case, a silicon single crystal having a low oxygen concentration can be grown by setting the interstitial oxygen concentration in the single crystal to 4.0 × 10 ¹⁷ atoms / cm ³ or less.

Further, the quartz crucible rotation speed R1 (rpm) and the crystal rotation speed R2 (rpm) are in the range of R1: 0.1 or more and 2 or less, R2: 1 or more and 7 or less, provided that R1: 0.3 or more, When 0.5 or less, R2 <7-5 (R1-0.3) is satisfied, and when R1: 0.5 or more and 0.7 or less, R2 <6 is satisfied, and R1: 0.7 or more and 1 In the following cases, it may be set in a range satisfying R2 <6-3.4 (R1-0.7). In this case, a silicon single crystal having a low oxygen concentration can be provided by setting the interstitial oxygen concentration in the single crystal to 3.5 × 10 ¹⁷ atoms / cm ³ or less.

In the present invention, the magnetic field applied to the silicon melt can be a horizontal magnetic field, a cusp magnetic field, or the like. For example, the intensity of the horizontal magnetic field is 3000 to 5000 G (0.3 T to 0.5 T). it can. If the magnetic field strength is not more than the above range, the effect of suppressing convection of the silicon melt is not sufficient, and the shape of the solid-liquid interface cannot be made preferable, and the oxygen concentration cannot be lowered sufficiently, which is not preferable. Further, if the magnetic field strength is increased beyond the above range, convection is suppressed too much, and the high temperature silicon melt advances the deterioration of the inner surface of the quartz crucible, and the dislocation-free rate of the crystal is lowered.
In the present invention, the magnetic field center position and the melt surface position during crystal pulling are preferably −75 to +50 mm, more preferably 20 to 45 mm. Here, the magnetic field center position means a height position where the center of the magnetic field generating coil is located in a horizontal magnetic field, and −75 mm means 75 mm above the melt surface. ing.

Also, in the pulling by the CZ method or the MCZ method, the convection of the silicon melt is suppressed, the amount of dissolution of the quartz crucible is reduced, and the synthetic quartz crucible is used to reduce the impurity concentration in the quartz crucible so that the quality closer to that of the FZ crystal CZ crystals can be grown.
Here, the synthetic quartz crucible means that at least the inner surface in contact with the raw material melt is formed of the following synthetic quartz.

Synthetic quartz is a chemically synthesized and manufactured raw material, and synthetic quartz glass powder is amorphous. Since the raw material of synthetic quartz is gas or liquid, it can be easily purified, and synthetic quartz powder can have a higher purity than natural quartz powder. Synthetic quartz glass raw materials are derived from gaseous raw materials such as carbon tetrachloride and liquid raw materials such as silicon alkoxide. In synthetic quartz powder glass, all impurities can be made 0.1 ppm or less.
In the glass obtained by melting synthetic quartz glass powder, when the light transmittance is measured, the synthetic quartz glass is made of carbon tetrachloride, which is used for ultraviolet optical applications as a raw material, and transmits ultraviolet rays up to a wavelength of about 200 nm. It is considered that the characteristics are close to.
In a glass obtained by melting synthetic quartz glass powder, when a fluorescence spectrum obtained by excitation with ultraviolet rays having a wavelength of 245 nm is measured, a fluorescence peak like a melted product of natural quartz powder is not observed.

  Whether the glass material was natural quartz by measuring the concentration of impurities contained, measuring the amount of silanol, or measuring the light transmittance, or measuring the fluorescence spectrum obtained by excitation with ultraviolet light having a wavelength of 245 nm. It can be determined whether it was quartz.

In the present invention, the pressure in the furnace is 10 torr (1.3 kPa) or more, preferably 30 to 200 torr (4.0 to 27 kPa), more preferably, in order to control the gas flow state on the surface of the silicon melt. 30 to 70 torr (4.0 to 9.3 kPa) is desirable. The upper limit of the pressure in the furnace is that when the pressure in the furnace increases, the gas flow rate on the melt of inert gas such as Ar decreases, so that it is difficult to exhaust the reactant gas such as SiO evaporated from the melt. As a result, the oxygen concentration in the crystal increases, and SiO aggregates in the upper part of the melt in the furnace at about 1100 ° C. or at a lower temperature, thereby generating dust and dropping into the melt. In order to prevent dislocations, the upper limit of the pressure was specified to prevent them.
In the present invention, the atmospheric gas flow rate supplied to the CZ furnace is set to 100 to 200 liters / min or more, the pressure in the CZ furnace is set to 6700 pa or less, and SiO evaporated from the melt surface is effectively discharged out of the apparatus. At the same time, foreign matter drifting on the surface of the melt can be driven to the crucible wall, and the oxygen concentration in the crystal can be prevented from increasing.

(High oxygen p +, p ++ wafer before Epi, after RTA treatment)
The method for producing a silicon epitaxial wafer according to the present invention provides a silicon device for use in a semiconductor device production process having a heat treatment step in which the maximum temperature is 1050 ° C. or more and below the melting point of silicon and the temperature rising / falling rate is 150 ° C./sec or more. An epitaxial wafer manufacturing method comprising:
Boron is doped so that the resistance value becomes 0.02 Ωcm to 0.001 Ωcm, and the initial oxygen concentration Oi is 11.0 × 10 ¹⁷ to 18 × 10 ¹⁷ atoms / cm ³ (Old-ASTM). On the other hand, an epitaxial process for growing an epitaxial layer on the surface, and before the epitaxial process, a processing temperature range of 1150 ° C. to 1300 ° C., a holding time range of 5 sec to 1 min, and a cooling rate of 10 ° C./sec to 0.1 ° C. In the p + wafer or p ++ wafer having a high oxygen concentration at the time of pulling and having a relatively large boron concentration having an effect of increasing oxygen precipitation, It is possible to simultaneously prevent wafer deformation and slip.

  Further, in the present invention, in the precipitation dissolution heat treatment step, a non-oxidizing gas atmosphere containing no nitrogen as a processing atmosphere, or a mixture of a non-oxidizing gas containing no nitrogen and 1% or more oxygen gas as a processing atmosphere. Adopting a means for setting the atmosphere or a means for setting the temperature drop rate in the range of 50 ° C./sec to 20 ° C./sec with a mixed atmosphere of non-oxidizing gas not containing nitrogen and 3% or more oxygen gas as the processing atmosphere Thus, by performing the treatment in an atmosphere that does not contain nitrogen, which is a hole injection gas, it is possible to simultaneously prevent wafer deformation and slip. Further, in addition to this, when the oxygen concentration is relatively high among the above means, it is possible to simultaneously prevent the wafer from being deformed and to prevent the slip from occurring by increasing the temperature decreasing rate.

  The silicon epitaxial wafer of the present invention is produced by any one of the above-described methods for producing a silicon epitaxial wafer, thereby causing deformation such as wafer warpage causing an overlay error shown in FIG. As shown, a wafer capable of preventing the occurrence of slip dislocation at the supported wafer edge portion at the same time can be obtained.

  In the manufacturing process related to wafer or device production, the deformation such as the warp of the wafer and the slip dislocation of the edge portion can be determined by the slip length. Specifically, as will be described later, 0.5 to 2 mm is indicated as ◯, 2 to 5 mm as Δ, and 5 to 10 mm as ×, respectively.

  According to the present invention, the conditions are stricter than those of the conventional RTA treatment, and even when subjected to a device manufacturing process rapid heating / cooling heat treatment in which the maximum stress generated in the silicon wafer exceeds 20 MPa, the oxygen precipitation that causes the reduction is reduced. Thus, it is possible to provide a silicon epitaxial wafer that can prevent wafer deformation and, at the same time, prevent slip extension caused by boat damage and transport damage that causes a reduction in wafer strength.

It is a flowchart which shows 1st Embodiment of the manufacturing method of the silicon epitaxial wafer which concerns on this invention. It is a conceptual diagram which shows a part of RTA processing apparatus. It is a schematic cross section which shows MOS FET. It is a graph which shows a box-shaped impurity profile in the relationship between impurity concentration and junction depth. It is sectional drawing of the work stage in the conventional exposure machine. It is a top view which shows an overlay error. It is a graph which shows the relationship between BMD density and the maximum deviation | shift amount by slip generation | occurrence | production. It is a figure which shows the slip dislocation generation state of a wafer edge part by X-ray topography. It is an expanded sectional view showing the edge of the silicon wafer concerning the present invention.

Hereinafter, a first embodiment of a silicon epitaxial wafer and a method for manufacturing the same according to the present invention will be described with reference to the drawings.
FIG. 1 is a flowchart showing a silicon epitaxial wafer and a manufacturing method thereof in the present embodiment.

  As shown in FIG. 1, the method for manufacturing a silicon epitaxial wafer in the present embodiment includes a manufacturing condition setting step S0, a wafer preparation step S11, a setting step S12 for setting a precipitation dissolution heat treatment step, an epitaxial step S13, The manufactured silicon epitaxial wafer having the precipitation melting heat treatment step S2 is subjected to the device manufacturing step S5 having the rapid heating / cooling heat treatment step S52.

In the manufacturing condition setting step S0 shown in FIG. 1, conditions for pulling a silicon single crystal from a silicon melt by the CZ (Czochralski) method in the wafer preparation step S1 and the standard of the wafer used in the device manufacturing step S5 are set. It shall be set.
In this manufacturing condition setting step S0, the oxygen concentration Oi of the silicon wafer (substrate), the boron concentration as the dopant concentration, and the nitrogen concentration, which are parameters to be controlled during pulling, are set as operating conditions in the wafer preparation step S1.
In the wafer preparation step S1, a single crystal is pulled by the CZ method, and a silicon wafer for forming an epitaxial layer is formed from the pulled silicon ingot by surface processing such as slicing, chamfering, grinding, polishing, and washing. It is a process to prepare. Here, a silicon wafer having a diameter of φ300 mm to 450 mm can be applied.

  In the setting step S12 shown in FIG. 1, the silicon wafer prepared in the wafer preparation step S11 is passed through the epitaxial step S3 and then provided with this silicon epitaxial wafer, followed by rapid heating and cooling such as FLA in the semiconductor device manufacturing step S5. According to the heat treatment step S52, the stress generated in the wafer and the oxygen precipitation state required corresponding to this stress are set to a desired state. The treatment conditions in the precipitation dissolution heat treatment step S3 are set in the device step S5. The pre-litho process S51 is performed before and after the rapid heating / cooling heat treatment process S52 in which the heat treatment provided for the silicon wafer is performed under conditions where the maximum temperature is 1050 ° C. or more and the melting point of silicon and the heating / cooling rate is 150 ° C./sec or more And the pattern formed in the post photolithography step S53. As the deviation in the emission does not overlay error occurs in this rapid heating cooling heat treatment process S52, thereby setting the suppressible conditions deformation occurs and slip occurrence. At the same time, the processing order including the precipitation dissolution heat treatment step S3 and the epitaxial step S2 is set. At this time, it is possible to select not to perform the precipitation dissolution heat treatment step S3. In other words, in the setting step S12, the conditions for the precipitation dissolution heat treatment step S3 are determined in consideration of the conditions in the manufacturing condition setting step S0 and the conditions in the rapid heating / cooling heat treatment step S52.

  As the conditions in the manufacturing condition setting step S0 and the setting step S12, the following can be selected.

In the manufacturing condition setting step S0, boron is doped so that the resistance value is 0.02 Ωcm to 1 kΩcm, and the initial oxygen concentration Oi is 14.0 × 10 ^{17 to} 22 × 10 ¹⁷ atoms / cm ³ (Old-ASTM). In the setting step S12, the processing temperature is in the range of 1150 ° C. to 1300 ° C., the holding time is in the range of 5 sec to 1 min, and the cooling rate is in the range of 10 ° C./sec to 0.1 ° C./sec.

In the manufacturing condition setting step S0, nitrogen is doped by 1 × 10 ^{13 to} 5 × 10 ¹⁴ atoms / cm ^3, and in the setting step S12, the precipitation solution heat treatment step S3 is performed after the epitaxial step S2, and the processing temperature is 1200 ° C. to 1300. A range of ° C., a holding time of 5 sec to 1 min, and a temperature drop rate of 10 ° C./sec to 0.1 ° C./sec.

In the manufacturing condition setting step S0, boron is doped so that the resistance value is 0.02 Ωcm to 0.001 Ωcm, and the initial oxygen concentration Oi is 11.0 × 10 ^{17 to} 3 × 10 ¹⁷ atoms / cm ³ (Old− ASTM)) and the precipitation dissolution heat treatment step S3 is not performed in the setting step S12.

In the manufacturing condition setting step S0, boron is doped so that the resistance value is 0.02 Ωcm to 0.001 Ωcm, and the initial oxygen concentration Oi is 11.0 × 10 ¹⁷ to 18 × 10 ¹⁷ atoms / cm ³ (Old− In addition, in the setting step S12, the precipitation dissolution heat treatment step S3 is performed before the epitaxial step S2, the treatment temperature is in the range of 1150 ° C. to 1300 ° C., the holding time is in the range of 5 sec to 1 min, and the cooling rate is 10 ° C./sec. The range is set to ˜0.1 ° C./sec.

  In the setting step S12, the treatment atmosphere of the precipitation dissolution heat treatment step S3 is a non-oxidizing gas atmosphere containing no nitrogen, or a mixed atmosphere of a non-oxidizing gas containing no nitrogen and 1% or more oxygen gas, or nitrogen. A mixed atmosphere of a non-oxidizing gas containing no oxygen and 3% or more oxygen gas is used, and the temperature lowering rate is in the range of 50 ° C./sec to 20 ° C./sec.

  In the epitaxial step S2 shown in FIG. 1, an epitaxial layer is formed on the wafer surface and can be, for example, p / p-type. This means a wafer obtained by laminating a p-type epitaxial layer with a film thickness of 1 to 10 μm on a p-type wafer. Here, the boron (B) concentration is a concentration corresponding to a resistivity of 0.1 to 100 Ωcm, and the p type is a concentration corresponding to a resistivity of 0.1 to 100 Ωcm.

  The precipitation dissolution heat treatment step S3 shown in FIG. 1 is performed at a treatment temperature higher than the treatment temperature in the epitaxial step S2 in the RTA treatment apparatus 10 as the above-described conditions. As shown in FIG. 2, the RTA processing apparatus 10 is set as described above for the wafer W that is supported in a horizontal state by a ring-shaped edge ring 11 made of SiC provided in the furnace and whose peripheral portion is supported. In an atmosphere gas G atmosphere, heating is performed by a plurality of lamps 13 through the upper dome 12 made of transparent quartz or the like, so that the element that becomes the precipitation nucleus inside the wafer W is dissolved. The lamps 13 in the RTA processing apparatus 10 are each provided inside a reflector 14 that has been subjected to surface treatment such as gold plating, and the upper dome 12 and the lower dome are connected to each other by a wall portion 15 made of SUS. (Furnace) is formed.

  In the device manufacturing process S5 shown in FIG. 1, a necessary process for making a device with a 65 nm node or a 45 nm node into a silicon wafer is performed, and a rapid heating / cooling heat treatment process S52 such as Spike-RTA or FLA is included. Is done.

  In the pre-photolithography step S51 and the post-photolithography step S53 shown in FIG. 1, as shown in FIG. 5, the wafer 1 is held and fixed on the work stage 2 by vacuum suction, and the photomask 3 is a mask holder above the work stage 2. 4, the work stage 2 is raised, the thin plate-like work 1 is brought into close contact with the photomask 3, and post-exposure is performed. A photoresist film (not shown) is formed on the surface of the wafer 1 in advance. The photoresist film is exposed to light and a pattern of the photomask 3 is baked.

In the silicon epitaxial wafer in the present embodiment, in the setting step S12, the conditions in the manufacturing condition setting step S0 and the conditions in the rapid heating / cooling heat treatment step S52 are considered, and the conditions for the precipitation dissolution heat treatment step S3 are determined. Since the processing as a manufacturing process was performed according to these conditions, precipitates having a density and size exceeding 5 × 10 ⁴ pieces / cm ^{2 in} which slip dislocation occurs inside the wafer are not formed. Due to such precipitates, as shown in FIG. 5, even when the wafer 1 is held and fixed on the work stage 2 by vacuum suction, the maximum deviation amount shown in FIG. 7 exceeds the allowable reference value of 10 nm. Therefore, there is no warping or deformation that causes the overlay error shown in FIG.
At the same time, it is possible to prevent slip dislocation from occurring at the edge portion of the supported wafer W as shown in FIG. 8 and to prevent the strength of the wafer from being lowered.

  In addition, when performing Spike-RTA process as rapid temperature raising / lowering process S52, it is possible to set and perform conditions in the RTA apparatus 10 shown in FIG.

  Furthermore, as shown in FIG. 9, the front surface 22 of the wafer is provided with a main surface W23 that is a flat surface, and a surface chamfered portion W24 formed at the peripheral edge. The back surface Wr is provided with a main surface W27 that is a flat surface and a back surface side chamfered portion W28 formed at the peripheral edge. The front side chamfered portion W24 has a width A1 in the direction from the peripheral edge Wt inward in the wafer radial direction, and a width A2 in the direction from the peripheral edge Wt in the rear surface side chamfered portion W28 inward in the wafer radial direction. It is narrowed. The width A1 of the surface chamfered portion W24 is preferably in the range of 50 μm to 200 μm. Further, the width A2 of the back side chamfered portion W28 is preferably in the range of 200 μm to 300 μm.

The front side chamfered portion W24 has a first inclined surface W11 that is inclined with respect to the main surface W23 of the front surface Wu, and the back side chamfered portion W28 is a first inclined surface with respect to the main surface W27 of the back surface Wr. Two inclined surfaces W12 are provided. The inclination angle θ1 of the first inclined surface W11 is preferably in the range of 10 ° to 50 °, the inclination angle θ2 of the second inclined surface W12 is preferably in the range of 10 ° to 30 °, and θ1 ≦ θ2 is satisfied. preferable.
In addition, a first curved surface W13 that connects the first inclined surface W11 and the peripheral edge Wt is provided on the outermost surface Wut of the surface. Further, between the second inclined surface W12 and the peripheral edge Wt, a second curved surface W14 that connects them is provided on the back outermost peripheral portion Wrt. The range of the radius of curvature R1 of the first curved surface W13 is preferably from 80 μm to 250 μm, and the range of the radius of curvature R2 of the second curved surface W14 is preferably from 100 μm to 300 μm.

  By using the above-described end configuration, it is possible to reduce the occurrence of scratches during wafer handling. In the present embodiment, in addition to setting the processing conditions in the rapid temperature raising / lowering step S52, further cracks are generated in the rapid temperature raising / lowering step S52, which is a severe condition, by setting the conditions in such a wafer peripheral portion. It is possible to prevent.

  Examples according to the present invention will be described below.

<Experimental example>
A (100) wafer is prepared by slicing and double-side polishing (DSP) from a 300 mm diameter silicon single crystal ingot pulled up by setting the boron concentration (resistivity), initial oxygen concentration, nitrogen concentration, etc. as shown in the table. did.
On this silicon wafer, the conditions of the precipitation dissolution heat treatment step S3 were set as shown in the table, the RTA treatment was performed, and an epitaxial film having a thickness of 4 μm was formed at an epitaxial step of 1150 ° C.

Furthermore, the RTA heat treatment as a forced thermal stress test for deformation generation was performed by simulating the heat treatment in the device manufacturing process as the following conditions, and the presence or absence of slip generation due to oxygen precipitates (BMD) was confirmed by X-ray topography. .
・ Process simulation 1 step in the device manufacturing process; 850 ° C. 30 minutes 2 steps; 1000 ° C. 30 minutes 3 steps; 1000 ° C. 60 minutes 4 steps; 850 ° C. 30 minutes (both heating and cooling rate is 5 ° C./min)
-RTA furnace thermal stress load test conditions The temperature rising / lowering rate from 700 ° C was 150 ° C / sec, the maximum temperature was 1250 ° C, and the holding time was 1 sec.

The results are shown in the table as RTA furnace stress load test results (BMD-induced slip generation).
Here, the measurement of the BMD density was performed after light etching 2 μm after the above-mentioned device simulation and after the obvious heat treatment at 1000 ° C./16 hr.

Further, as a stress load test for the generation of scratches, heat treatment was performed in a batch furnace under the following conditions, and then the slip length was measured using X-ray topography. This result is shown in the table as a vertical furnace stress load test result (boat-derived slip).
-Vertical furnace thermal stress test conditions The temperature rising rate from 700 ° C to 1150 ° C was set at 8 ° C / min, held at 1150 ° C for 60 min, and cooled to 700 ° C at a temperature decreasing rate of 1.5 ° C / min.

Here, the notation of the result is the presence or absence of slip occurrence measured by X-ray topography or the slip length in the following range.
As for the RTA furnace thermal stress load test result, X is obtained when X-ray topography confirms the occurrence of minute slip in the wafer surface, and ○ is indicated when occurrence of minute slip cannot be confirmed. Since the RTA treatment is a short time, the slip length is fine and it is difficult to measure the Slip length.
On the other hand, in the vertical furnace thermal stress load test, the Slip length extended from the boat trace was measured and expressed as follows.
○: Slip length 0.5-2mm
Δ: Slip length 2-5mm
X: Slip length 5 to 10 mm

  Further, after epi growth, in the BMD density (/ cm @ 2), <1e4 means a value below the real detection limit.

  In Sample 1, even after Epi (epi) growth, there is no precipitate formation even with Epi growth + precipitation treatment in order to keep oxygen precipitation nucleation at a low level. Therefore, there is no slip caused by BMD. However, in the vertical furnace test, because the oxygen concentration is low, the slip caused by the boat grows, so it is NG.

  In Sample 2, the oxygen concentration was low, but the boron concentration was high, and precipitation nuclei were formed by the heat treatment after EPi. Slip generation due to boat is suppressed due to high boron concentration, but NG due to generation of Slip due to BMD.

  In sample 3, oxygen and boron concentrations are high, and BMD-derived slip is generated. Slip generation caused by boats is suppressed. Therefore NG.

  In sample 4, both oxygen and boron concentrations are high, and BMD-induced slip is generated. Slip generation caused by boats is extremely suppressed. Therefore NG.

  In Sample 5, precipitation after Epi was suppressed by reducing oxygen. The vertical furnace slip is suppressed by the effect of boron. So OK.

  In sample 6, precipitation after Epi was suppressed by reducing oxygen. Furthermore, the vertical furnace slip is suppressed by the effect of high-concentration boron. So OK.

  In sample 7, BMD formation was suppressed by RTA treatment. So OK.

  In sample 8, BMD formation was suppressed by RTA treatment. So OK.

  In sample 9, BTA formation was suppressed by RTA treatment. So OK.

  In sample 10, BTA formation was suppressed by RTA treatment. So OK.

  In sample 11, when the RTA temperature is 1150 ° C. or lower, BMD-induced slip occurs. Therefore NG.

  In sample 12, RTA freezes the vacancies by rapid cooling, and BMD formation causes SMD generation. Therefore NG.

  In sample 13, the oxygen concentration is high, and SMD generation due to BMD is easily caused by oxygen precipitation nucleation even after Epi growth. Slip caused by boats is suppressed due to high oxygen. Therefore NG.

  Sample 14 has no BMD and no boat slip because it is a high oxygen substrate. So OK.

  In sample 15, there is no BMD and no boat slip because it is a high oxygen substrate. So OK.

  Sample 16 has no BMD and no boat slip because it is a high oxygen substrate. So OK.

  In sample 17, since the oxygen concentration is high, the formation of BMD is promoted even after the RTA treatment, and slip caused by BMD is generated. Therefore NG.

  In sample 18, the cooling rate was too fast, and freezing of the holes caused slippage due to BMD. Therefore NG.

  In sample 19, BMD-derived slip was generated in the BMD nucleus due to insufficient RTA processing time. Therefore NG.

  In sample 20, there was vacancy injection by forming a nitride film with nitrogen, and BMD-derived slip was generated by oxygen precipitate formation. Therefore NG.

  In sample 21, there is no BMD and no boat slip because it is a high oxygen substrate. So OK.

  In sample 22, interstitial Si was injected by forming an oxide film during the RTA process, and vacancy was not frozen even when cooled at 10 ° C./sec or higher.

  In Sample 23, interstitial Si was injected by forming an oxide film during the RTA process, and vacancy was not frozen even when cooled at 10 ° C./sec or higher.

  In sample 24, although the oxide film was formed, the cooling rate was too fast, and the pores were frozen to generate slip caused by BMD. Therefore NG.

  In sample 25, BMD was formed by the effect of nitrogen doping. Therefore, NG.

  In sample 26, the BMD of the nitrogen-doped epi-wafer is stable at a high temperature and does not disappear at 1150 ° C. RTA. Therefore, NG.

  In Samples 27 to 30, BMD disappears even with nitrogen doping regardless of the concentration. There is no boat slip because it is a high oxygen substrate. Therefore, OK.

  From this result, it is understood that deformation and slip dislocation elongation can be prevented by setting the oxygen concentration, boron concentration, and RTA treatment conditions.

W ... Silicon wafer

Claims (4)

A semiconductor device having a heat treatment process in which an internal stress generated in a wafer during heat treatment exceeds 20 MPa under conditions where the maximum temperature is 1050 ° C. or more and below the melting point of silicon and the temperature rising / falling rate is 150 ° C./sec or more. A method for producing a silicon epitaxial wafer to be subjected to a production process,
An epitaxial process for growing an epitaxial layer on the surface of a substrate doped with 1 × 10 ^{13 to} 5 × 10 ¹⁴ atoms / cm ^{3 of} nitrogen, and a processing temperature in the range of 1200 to 1300 ° C. after the epitaxial process is maintained. By having a precipitation melting heat treatment step in which the range of time is 5 sec to 1 min, and the temperature drop rate is 10 ° C./sec to 0.1 ° C./sec in which the pores are not frozen,
Acceptable standard for oxygen precipitate density inside wafer when heat treatment at 1000 ° C for 16 hours is performed, and maximum deviation due to wafer deformation caused by slip dislocation generated from precipitate in photolithography process in semiconductor device manufacturing process A method for producing a silicon epitaxial wafer, wherein the value is 5 × 10 ⁴ pieces / cm ² or less which does not exceed a value of 10 nm. A semiconductor device having a heat treatment process in which an internal stress generated in a wafer during heat treatment exceeds 20 MPa under conditions where the maximum temperature is 1050 ° C. or more and below the melting point of silicon and the temperature rising / falling rate is 150 ° C./sec or more. A method for producing a silicon epitaxial wafer to be subjected to a production process,
For a substrate doped with boron to have a resistance value of 0.02 Ωcm to 1 kΩcm and an initial oxygen concentration Oi of 14.0 × 10 ^{17 to} 22 × 10 ¹⁷ atoms / cm ³ (Old-ASTM) An epitaxial process for growing an epitaxial layer on the surface, and a treatment temperature range of 1150 ° C. to 1300 ° C., a holding time range of 5 sec to 1 min, and a temperature lowering rate before and after the epitaxial process are 10 ° C./sec. By having a precipitation dissolution heat treatment step in the range of ~ 0.1 ° C / sec,
Acceptable standard for oxygen precipitate density inside wafer when heat treatment at 1000 ° C for 16 hours is performed, and maximum deviation due to wafer deformation caused by slip dislocation generated from precipitate in photolithography process in semiconductor device manufacturing process A method for producing a silicon epitaxial wafer, wherein the value is 5 × 10 ⁴ pieces / cm ² or less which does not exceed a value of 10 nm.   3. The method for producing a silicon epitaxial wafer according to claim 1, wherein in the precipitation solution heat treatment step, a non-oxidizing gas atmosphere containing no nitrogen is used as a processing atmosphere.   3. The method for producing a silicon epitaxial wafer according to claim 1, wherein in the precipitation dissolution heat treatment step, a mixed atmosphere of a non-oxidizing gas not containing nitrogen and 1% or more oxygen gas is used as a processing atmosphere.

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