JP2014158160A - Amplification circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To match input impedance to a signal source and enhance stability.SOLUTION: A resistor R3 is disposed between a gate of a transistor Q1 and an output terminal 4, and a resistor R4 is disposed between a gate of a transistor Q2 and the output terminal 4. The resistors R3, R4 provide new feedback paths from the output terminal 4 to the transistors Q1, Q2. In a low frequency range apart from a signal band of amplification, a forward gain from an input terminal 2 to the output terminal 4 and a reverse gain from the output terminal 4 to the input terminal 2 both reduce to improve stability.

Description

  The present invention relates to a complementary amplifier circuit.

  As an amplifier circuit having high linearity, there is a complementary amplifier circuit described in Patent Document 1. In this amplifier circuit, a P-channel MOS transistor and an N-channel MOS transistor operate complementarily to an input signal. For this reason, it is possible to design the input capacitance and transconductance of the entire circuit so as not to vary substantially with respect to the input amplitude, and high linearity can be obtained. The amplifier circuit includes a biasing resistor and an impedance matching inductor.

  In general, an amplifier circuit using a MOS transistor has a high input impedance and is difficult to match with a signal source such as an antenna or a filter having an impedance of 50Ω connected to the input terminal of the amplifier circuit. The inductor is provided to lower the input impedance of the amplifier circuit to achieve impedance matching with the signal source and to further improve linearity.

US Patent Application Publication No. 2009/0140812

  When this amplifier circuit is integrated on a semiconductor substrate to constitute an IC, the lower the frequency of the input signal, the larger the size of the inductor required for impedance matching, making it unsuitable for practical use. Further, since the LC resonance is used, the band becomes narrow. As an input impedance matching means that does not use an inductor, a configuration in which resistive feedback is applied between the input and output of the amplifier circuit to lower the input impedance is conceivable. When this feedback is combined with the above-mentioned amplifier circuit, not only the input impedance can be reduced, but also the output impedance can be reduced, so that it is useful not only as an input stage amplifier circuit but also as an output stage amplifier circuit.

  However, this amplifier circuit also has a problem that it may become unstable and oscillate in a low frequency region. The cause of instability is the frequency where the forward gain from input to output and the reverse gain from output to input are both large due to the high-pass characteristics of the capacitors provided between the input terminal and each gate of the MOS transistor. There is a belt.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an amplifier circuit in which input impedance is matched with a signal source and stability is improved.

  The amplifier circuit according to claim 1 includes a P-channel first transistor and an N-channel second transistor connected in series with an output terminal interposed between the first power line and the second power line. It is a complementary amplifier circuit. The first and second transistors are grounded to the power supply line.

  The amplifier circuit includes a first bias voltage source that outputs a first bias voltage and a second bias voltage source that outputs a second bias voltage. The first bias voltage source biases the gate of the first transistor via the first resistor. The second bias voltage source biases the gate of the second transistor through the second resistor.

  First and second capacitors for AC coupling of input signals are connected between the input terminal and the gates of the first and second transistors, respectively. Connected between the input terminal and the output terminal is a feedback resistor that lowers the input impedance and output impedance of the amplifier circuit by applying negative feedback between the input and output. Thereby, for example, the input impedance can be matched to a signal source having an impedance of 50Ω. In addition, the conventionally used inductor is not required, and the bandwidth and size can be reduced.

  Further, a third resistor is provided between the gate of the first transistor and the output terminal, and a fourth resistor is provided between the gate of the second transistor and the output terminal. These third and fourth resistors provide a new feedback path from the output terminal to the first and second transistors. Due to the low-pass characteristics, both the forward gain from the input terminal to the output terminal and the reverse gain from the output terminal to the input terminal are reduced in a low frequency region outside the signal band to be amplified. As a result, stability is improved.

  According to the means described in claim 2, the output impedance of the signal source connected to the input terminal is Rs, the resistance value of the feedback resistor is Rf, and the resistance values of the first, second, third, and fourth resistors are respectively When R1, R2, R3, and R4 are defined, and f = Rs / (Rf + Rs), K1 = R1 / (R1 + R3), K2 = R2 / (R2 + R4), and f, K1, and K2 are defined, K1, K2> f holds doing.

  The forward signal path from the input terminal to the gates of the first and second transistors has a high-pass characteristic, and the reverse signal path from the output terminal to the gates of the first and second transistors has a low-pass characteristic. They have approximately equal cut-off frequencies. By satisfying the above condition, the pole frequencies of the forward transfer function and the reverse transfer function can be shifted to a frequency region higher than the cutoff frequency. As a result, both the forward gain and the reverse gain are lowered in the low frequency region described above, and the stability is further improved.

  According to the means described in claim 3, the first constant voltage element is provided in series with the third resistor, and the second constant voltage element is provided in series with the fourth resistor. As a result, a bias voltage obtained by dividing the difference voltage between the first bias voltage and the output voltage by the first resistor, the third resistor, and the first constant voltage element is applied to the gate of the first transistor, and the output voltage and the second bias are applied. A bias voltage obtained by dividing a voltage difference from the voltage by the second constant voltage element, the fourth resistor, and the second resistor is applied to the gate of the second transistor.

  The first and second resistors are set to relatively high resistance values so that input signals do not flow into the first and second bias voltage sources. Therefore, in order to apply an appropriate bias voltage to the gates of the first and second transistors, it is necessary to increase the resistance values of the third and fourth resistors that determine the bias voltage together with the first and second resistors. However, increasing the resistance values of the third and fourth resistors makes it difficult to satisfy the condition (K1, K2> f) and increases the layout area. Therefore, by adding the first and second constant voltage elements in series by this means, the resistance values of the third and fourth resistors can be lowered by an amount corresponding to the constant voltage. As a result, the range of resistance values that simultaneously satisfy the condition (K1, K2> f) and the condition resulting from the bias setting is expanded, and the degree of freedom in design is increased. In addition, an increase in layout area due to the provision of the third and fourth resistors can be suppressed.

  According to the means described in claim 4, the first resistor is constituted by a series circuit of the divided first A resistor and the first B resistor, and the second resistor is a series of the divided second A resistor and the second B resistor. Consists of a circuit. The third resistor is connected between the connection node of the first A and first B resistors and the output terminal, and the fourth resistor is connected between the connection node of the second A and second B resistors and the output terminal.

  According to this configuration, the bias voltage obtained by dividing the difference voltage between the first bias voltage and the output voltage by the first A resistor and the third resistor is applied to the gate of the first transistor, and the second bias voltage and the output voltage are A bias voltage obtained by dividing the difference voltage by the fourth resistor and the second A resistor is applied to the gate of the second transistor.

  For example, if the series resistance value of the first A resistor and the first B resistor is set equal to the resistance value of the first resistor, the high-pass characteristic by the first capacitor and the first A and first B resistors is a configuration using a non-divided first resistor. Is kept equal to On the other hand, in order to apply an appropriate bias voltage to the gate of the first transistor, it is sufficient to set the resistance value of the third resistor smaller than in the configuration using the non-divided first resistor. The same effect is obtained with respect to the second capacitor, the second A, the second B resistor and the fourth resistor. As a result, the layout area of the third and fourth resistors can be further reduced. Further, the layout area of the third and fourth resistors can be reduced by providing the first constant voltage element in series with the third resistor and the second constant voltage element in series with the fourth resistor as described in claim 3. It can be made even smaller.

  According to the means described in claim 5, the first constant voltage element is composed of a diode whose cathode is the output terminal side, and the second constant voltage element is composed of a diode whose anode is the output terminal side. . As a result, the resistance values of the third and fourth resistors can be set smaller by the amount corresponding to the forward voltage of the diode. A diode can be formed with a smaller layout area than a resistor that produces the same voltage drop.

  According to a sixth aspect of the present invention, the first constant voltage element is composed of an N-channel type transistor whose gate and drain are connected and whose output terminal side is the source, and the second constant voltage element is the gate It is composed of a P-channel transistor whose drain is connected and whose output terminal is the source. As a result, the resistance values of the third and fourth resistors can be set smaller by the amount of the gate-source voltage of the transistor. Transistors can be formed with a smaller layout area than resistors that produce the same voltage drop.

  According to a seventh aspect of the present invention, the first and second bias voltage sources include a P-channel type transistor having a source connected to the first power supply line and a gate-drain connected, and the second power supply line. N-channel transistors having a source connected to each other and a gate and a drain connected to each other, and a circuit for generating an equal current to these P-channel and N-channel transistors. The gate-source voltages of the transistors are output as first and second bias voltages, respectively.

  According to this configuration, an equal current flows through the P-channel transistor and the N-channel transistor. The gate-source voltage of the P-channel transistor determines the bias voltage of the P-channel first transistor, and the gate-source voltage of the N-channel transistor determines the bias voltage of the N-channel second transistor. To do. With such a bias setting, the output voltage of the complementary amplifier circuit can be biased to the center level between the potential of the first power supply line and the potential of the second power supply line.

  Further, in the case where the means described in claim 6 is provided, a bias setting path from the first power supply line to the output terminal via the P-channel transistor, the first A resistor, the third resistor, and the N-channel transistor is One gate and one source of the P-channel transistor and the N-channel transistor are included. On the other hand, the gate and source of the P-channel transistor and the N-channel transistor are also connected to the bias setting path from the output terminal to the second power supply line through the P-channel transistor, the fourth resistor, the second A resistor, and the N-channel transistor. One interval is included. As a result, the influence of the variation in the threshold voltage of the transistors is canceled in the two bias setting paths, and the output voltage of the complementary amplifier circuit is set to the center level between the potential of the first power supply line and the potential of the second power supply line. Can be biased.

1 is a configuration diagram of an amplifier circuit showing a first embodiment of the present invention. Frequency characteristics diagram of forward gain and reverse gain Diagram showing signal flow, transfer function, and frequency characteristics in the forward and reverse directions of the conventional circuit FIG. 3 is an equivalent diagram of the amplifier circuit according to the first embodiment. FIG. 1 equivalent diagram showing a second embodiment of the present invention FIG. 1 equivalent view showing a third embodiment of the present invention FIG. 1 equivalent view showing a fourth embodiment of the present invention FIG. 1 equivalent view showing a fifth embodiment of the present invention

In each embodiment, substantially the same parts are denoted by the same reference numerals and description thereof is omitted.
(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. An amplifying circuit 1 shown in FIG. 1 amplifies a voltage Vi supplied from an external signal source 3 connected to an input terminal 2 and outputs a voltage Vo to an external load 5 connected to an output terminal 4. Type amplifier circuit. The amplifier circuit 1 is configured as a semiconductor integrated circuit manufactured by a CMOS process.

  The signal source 3 is an antenna, a filter, or the like, and has an output impedance of 50Ω. In FIG. 1, the signal source 3 is equivalently represented by a signal generator 3a and an output resistor 3b (resistance value Rs). The load 5 has an impedance of 500Ω, for example, and is represented by a resistor in FIG. These impedance values are merely examples, and the present invention is not limited to these values.

  The amplifier circuit 1 operates by receiving the supply of the power supply voltage VDD from the first power supply line 6 and the second power supply line 7. A P-channel first transistor Q1 whose source is grounded to the power line 6 and an N-channel second transistor Q2 whose source is grounded to the power line 7 are connected in series in a push-pull configuration with the output terminal 4 interposed therebetween. Has been. The first bias voltage source 8 outputs a first bias voltage VA for the transistor Q1, and the second bias voltage source 9 outputs a second bias voltage VB for the transistor Q2.

  A first capacitor C1 for AC coupling is connected between the input terminal 2 and the gate of the transistor Q1. A second capacitor C2 for AC coupling is connected between the input terminal 2 and the gate of the transistor Q2. A first resistor R1 is connected between the bias voltage source 8 and the gate of the transistor Q1. A second resistor R2 is connected between the bias voltage source 9 and the gate of the transistor Q2. The resistors R1 and R2 are set to relatively high resistance values (as an example, several tens of kΩ) so that the input signal does not flow into the bias voltage sources 8 and 9.

  A feedback resistor Rf is connected between the input terminal 2 and the output terminal 4. A third resistor R3 that constitutes a feedback path is connected between the gate of the transistor Q1 and the output terminal 4. A fourth resistor R4 that forms a feedback path is connected between the gate of the transistor Q2 and the output terminal 4.

  Next, the operation of this embodiment will be described with reference to FIGS. The complementary amplifier circuit 1 includes a circuit on the power supply line 6 side (transistor Q1, capacitor C1, resistors R1, R3, bias voltage source 8) and a circuit on the power supply line 7 side (transistor Q2, capacitor C2, resistors R2, R4, bias). The voltage source 9) is constructed symmetrically including constants. For this reason, the gate bias states of the transistors Q1 and Q2 become equal, and the same drain current flows through the transistors Q1 and Q2. As a result, the potential of the output terminal 4 is biased to the center level VDD / 2 between VDD and 0V. The amplifier circuit 1 inverts and amplifies the signal voltage Vi input from the signal source 3 and outputs a signal voltage Vo biased to VDD / 2.

  By providing the feedback resistor Rf, the input impedance of the amplifier circuit 1 can be reduced to match the impedance (50Ω) of the signal source 3. Moreover, since the output impedance of the amplifier circuit 1 is also reduced, it can be applied as an amplifier circuit in the output stage. An amplifier circuit that does not include the resistors R3 and R4 (hereinafter referred to as a conventional circuit) may become unstable in a low frequency region that is out of the signal band to be amplified.

  2A shows the forward gain (dB) from the input voltage Vi to the output voltage Vo of the amplifier circuit 1 and the conventional circuit, and FIG. 2B shows the output voltage Vo of the amplifier circuit 1 and the conventional circuit. It is a simulation result showing the reverse direction gain (dB) to the input voltage Vi. The amplifier circuit 1 and the conventional circuit are subjected to stable negative feedback in a frequency band of approximately 10 MHz to 200 MHz.

  However, in the conventional circuit, the reverse gain is increased in a frequency band lower than about 1 MHz, while the forward gain is kept high up to about 500 kHz. That is, in the low frequency region (˜1 MHz, particularly frequency region A shown in FIG. 2), there is a frequency band in which both the forward gain and the reverse gain are large. It becomes unstable.

  On the other hand, in the amplifier circuit 1 including the resistors R3 and R4, the reverse gain decreases in a frequency band lower than about 5 MHz, and the forward gain also decreases in a frequency band lower than about 5 MHz. That is, it can be understood that there is no frequency band in which both the forward gain and the reverse gain are large in the low frequency region (˜5 MHz), and the stability is improved.

Therefore, the frequency characteristics (gain) of the conventional circuit and the amplifier circuit 1 are analyzed in more detail.
(1) Conventional circuit without resistors R3 and R4 FIG. 3 shows a signal flow diagram, a transfer function, and a frequency characteristic in the forward direction and the reverse direction of the conventional circuit. a1 is a signal path from the input terminal 2 to the transistors Q1 and Q2, and has a high-pass characteristic composed of the resistor R1 and the capacitor C1 or a high-pass characteristic composed of the resistor R2 and the capacitor C2. This high-pass characteristic can be expressed by equations (1) and (2).
a1 = s / (s + ω1) (1)
ω1 = 1 / (C1 · R1) = 1 / (C2 · R2) (2)

a2 is an inverting amplification by the transistors Q1 and Q2, and has a negative value. f is a path through which the voltage generated at the output terminal 4 is transmitted to the input terminal 2 due to voltage division between the feedback resistor Rf and the output resistor 3b (resistance value Rs) of the signal source 3, and is expressed by equation (3). Can do.
f = Rs / (Rf + Rs) (3)

  In a frequency band of approximately 10 MHz or less, the frequency dependence of a2 and f is small and can be regarded as constant. The forward transfer function Vo / Vi and the reverse transfer function Vi / Vo can be expressed by equations (4) and (5), respectively.

  A pole exists at -ω1 / (1-a2 · f) for both the forward transfer function and the reverse transfer function, and the slope of the gain with respect to the frequency changes before and after the frequency ω1 / (1-a2 · f). . Hereinafter, the frequency (p) at which the gain slope due to the pole -p changes is called the pole frequency. Since a2 is a negative value and f is a positive value, the frequency of the pole of the transfer function is lower than the frequency ω1 of the pole of a1 alone. As can be seen from the frequency characteristics shown in FIG. 3, the forward gain is kept high between ω1 / (1-a2 · f) and ω1, and the reverse gain is also higher than the value at the frequency equal to or higher than ω1. growing. This coincides with the result shown in FIG. 2, and it has been analytically proved that the frequency band is unstable.

(2) Amplifier circuit 1 having resistors R3 and R4
In the amplifier circuit 1 of the present embodiment, both the forward gain and the reverse gain are reduced by shifting the pole frequency to a frequency region higher than ω1. FIG. 4 shows a signal flow diagram, a transfer function, and a frequency characteristic in the forward direction and the reverse direction of the amplifier circuit 1. By providing the resistors R3 and R4, a feedback path returning from the output terminal 4 to the gates of the transistors Q1 and Q2 is newly added to the feedback path returning to a1 through f.

a1 is a high-pass characteristic composed of the resistors R1, R3 and the capacitor C1, or a high-pass characteristic composed of the resistors R2, R4 and the capacitor C2. Since the resistance value of the load 5 is sufficiently smaller than R3 and R4, the high-pass characteristic can be expressed by the equations (6) and (7). Since the resistors R3 and R4 are added, the cut-off frequency ω1 expressed by the equation (7) is different from the cut-off frequency ω1 expressed by the equation (2).
a1 = s / (s + ω1) (6)
ω1 = (R1 + R3) / (C1 · R1 · R3) = (R2 + R4) / (C2 · R2 · R4) (7)

f2 is a low-pass characteristic composed of resistors R1, R3 and a capacitor C1, or a low-pass characteristic composed of resistors R2, R4 and a capacitor C2. Since the impedance of the signal source 3 is sufficiently smaller than the impedance of the capacitor C1 (C2), the low-pass characteristic can be expressed by the equations (8) and (9) assuming that the input terminal 2 is connected to the power supply line. . f2 and a1 have the same cutoff frequency ω1.
f2 = K1 · ω1 / (s + ω1) = K2 · ω1 / (s + ω1) (8)
K1 = K2 = R1 / (R1 + R3) = R2 / (R2 + R4) (9)

  The forward transfer function Vo / Vi and the reverse transfer function Vi / Vo can be expressed by equations (10) and (11), respectively.

For both the forward transfer function and the reverse transfer function, the pole frequency is (1−a2 · K2) / (1−a2 · f) · ω1. Since a2 is a negative value and f is a positive value, the frequency of the pole can be made higher than ω1 by satisfying the condition of equation (12).
K1, K2> f (12)

  As can be seen from the frequency characteristics shown in FIG. 4, the forward gain and the reverse gain decrease as the frequency decreases from (1-a2 · K2) / (1-a2 · f) · ω1. This coincides with the result shown in FIG. 2, and it has been proved that the frequency band in which both the forward gain and the reverse gain are large disappears. Here, the output of f2 is added before a2, but if the DC gain of f2 is large, the same effect can be obtained by adding after a2. However, the circuit configuration becomes complicated in order to increase the DC gain of f2.

  As described above, the amplifier circuit 1 according to the present embodiment includes the resistors R3 and R4, and a feedback path that returns from the output terminal 4 to the gates of the transistors Q1 and Q2 is added. As a result, in a low frequency region outside the signal band to be amplified, there is no frequency band in which both the forward gain and the reverse gain are large, and a stable amplification operation is possible. Since the amplifier circuit 1 includes the feedback resistor Rf, the input impedance can be matched with the signal source 3 having an impedance of 50Ω, for example. In addition, the bandwidth can be increased and the size can be reduced as compared with the configuration in which the inductor is provided and matched.

(Second Embodiment)
A second embodiment will be described with reference to FIG. Compared with the amplifier circuit 1 shown in FIG. 1, the amplifier circuit 11 includes a diode D1 (first constant voltage element) in series with the resistor R3, and a diode D2 (second constant voltage element) in series with the resistor R4. The configuration provided is different.

  At this time, the gate potential of the transistor Q1 is a voltage obtained by dividing (VA−VDD / 2) by the resistors R1 and R3, and the gate potential of the transistor Q2 is (VDD / 2−VB) by the resistors R4 and R2. The voltage is divided. As described above, the resistors R1 and R2 are set to relatively high resistance values so that the input signal does not flow into the bias voltage sources 8 and 9. Therefore, in order to appropriately bias the gates of the transistors Q1 and Q2, it is necessary to increase the resistance values of the resistors R3 and R4. However, when the resistance value is increased, K1 and K2 decrease from the equation (9), and it becomes difficult to satisfy the condition of the equation (12). In addition, the layout area is increased.

  On the other hand, when the diodes D1 and D2 are provided in series with the resistors R3 and R4, respectively, the diodes D1 and D2 bear the voltage Vf (forward voltage of the PN junction), so that the resistor R3 corresponds to the constant voltage. , R4 can be reduced in resistance value. The diodes D1 and D2 can be formed with a smaller layout area than a resistor that causes the same voltage drop. As a result, the range of resistance values that simultaneously satisfy the condition of equation (12) and the condition resulting from the bias setting is expanded, and the degree of freedom in design is increased. Further, an increase in layout area due to the provision of the third and fourth resistors R3 and R4 can be suppressed. In addition, the same effects as those of the first embodiment can be obtained.

(Third embodiment)
A third embodiment will be described with reference to FIG. The amplifier circuit 21 differs from the amplifier circuit 11 shown in FIG. 5 in the configuration of resistors R1 and R2. That is, the first resistor R1 is configured by a series circuit of a first A resistor R1A and a first B resistor R1B, and the second resistor R2 is configured by a series circuit of a second A resistor R2A and a second B resistor R2B. Yes. The series circuit of the resistor R3A and the diode D1 is connected between the connection node of the resistors R1A and R1B and the output terminal 4, and the series circuit of the resistor R4A and the diode D2 is connected to the connection node of the resistors R2A and R2B. It is connected between the output terminal 4.

  The DC bias current flows from the bias voltage source 8 through the resistors R1A and R3A, the diodes D1 and D2, and the resistors R4A and R2A. The gate potential of the transistor Q1 is a voltage obtained by dividing (VA−VDD / 2) by the resistors R1A, R3A, and the diode D1, and the gate potential of the transistor Q2 is (VDD / 2−VB) by the diode D2 and the resistor. The voltage is divided by R4A and resistor R2A.

  Here, by setting R1 = R1A + R1B and R2 = R2A + R2B, the high-pass characteristic by the capacitor C1 and the resistors R1A and R1B becomes equal to the high-pass characteristic by the capacitor C1 and the resistor R1 in the amplifier circuit 11. At this time, R1> R1A and R2> R2A. Further, by setting R3A / R1A and R4A / R2A equal to R3 / R1 and R4 / R2 in the amplifier circuit 11, respectively, the bias of the transistors Q1 and Q2 can be made equal to that of the amplifier circuit 11. At this time, R3A <R3.

  According to the amplifier circuit 21 of the present embodiment, the resistance values of the resistors R3A and R4A can be further lowered while having high pass characteristics and bias settings equivalent to those of the amplifier circuit 11, so that the layout area can be further reduced. . In addition, the same effects as those of the second embodiment can be obtained.

(Fourth embodiment)
A fourth embodiment will be described with reference to FIG. The amplifier circuit 31 includes diode-connected N-channel transistor Q3 and P-channel transistor Q4 instead of the diodes D1 and D2 of the amplifier circuit 21 shown in FIG. This is a concrete embodiment.

  The bias voltage source 32 includes a constant current source 33, N-channel transistors Q5 and Q6 constituting a current mirror circuit, and a diode-connected P-channel transistor Q7. Since the current flowing through the resistors R1A and R2A is very small, the current mirror circuit generates a current equal to the current from the constant current source 33 in the N-channel transistor Q5 and the P-channel transistor Q7. The gate potential of the transistor Q7 is the first bias voltage VA, and the gate potential of the transistor Q5 is the second bias voltage VB.

As described above, in the complementary amplifier circuit, it is desirable to bias the output terminal 4 to VDD / 2. For that purpose, it is necessary to satisfy the following two conditions.
(1) The drain currents of the transistors Q1 and Q2 are equal.
(2) A voltage drop in the bias setting path W1 from the power supply line 6 to the output terminal 4 via the transistor Q7, resistors R1A and R3A, and the transistor Q3, and via the transistor Q4, resistors R4A and R2A, and the transistor Q6 from the output terminal 4 Thus, the voltage drop of the bias setting path W2 reaching the power supply line 7 is equal.

  In order to satisfy the condition (1), it is sufficient to prepare a bias voltage source 32 that biases the gate so that the same drain current flows through the transistors Q1 and Q2. Actually, the current flowing through the bias setting paths W1 and W2 is very small, and the voltage drop of the resistors R1A and R2A is also very small. Therefore, the gates and the source voltages of the P-channel transistor Q7 and the N-channel transistor Q5 through which the output current of the constant current source 33 flows are respectively applied to the gates of the P-channel transistor Q1 and the N-channel transistor Q2. Good to give.

  In order to satisfy the condition (2), it is preferable that the first and second constant voltage elements are composed of a diode-connected N-channel transistor Q3 and a P-channel transistor Q4, respectively. Transistors Q3 and Q4 can be formed with a smaller layout area than resistors that cause the same voltage drop. Each of the bias setting paths W1 and W2 includes one between the gate and the source of one P-channel transistor and one N-channel transistor. Thereby, the influence of the variation in the threshold voltage of the MOS transistor is canceled.

  According to the present embodiment, the output voltage Vo can be biased to the middle level between the potential of the first power supply line 6 and the potential of the second power supply line 7, and the maximum amplitude of the output voltage Vo can be increased. In addition, since the diode-connected transistors Q3 and Q4 are provided in series with the resistors R3 and R4, the resistance values of the resistors R3 and R4 are set to an amount corresponding to the gate-source voltage borne by the transistors Q3 and Q4. Can be lowered. As a result, the condition of the expression (12) can be easily satisfied, and an increase in layout area can be suppressed. In addition, the same effects as those of the third embodiment can be obtained.

(Fifth embodiment)
An amplifier circuit 41 shown in FIG. 8 includes diode-connected N-channel transistor Q3 and P-channel transistor Q4 instead of the diodes D1 and D2 of the amplifier circuit 11 shown in FIG. 32. Also according to the present embodiment, an increase in layout area can be suppressed.

(Other embodiments)
As mentioned above, although preferred embodiment of this invention was described, this invention is not limited to embodiment mentioned above, A various deformation | transformation and expansion | extension can be performed within the range which does not deviate from the summary of invention.

In the third embodiment, the diodes D1 and D2 may be omitted.
The first constant voltage element and the second constant voltage element may be configured by a series circuit of a plurality of diodes, a series circuit of a plurality of diode-connected transistors, a Zener diode, a combination thereof, or the like. 7 and 8, the transistor Q3 may be configured by a P-channel transistor, and the transistor Q4 may be configured by an N-channel transistor.

  In the drawing, 1, 11, 21, 31, and 41 are amplifier circuits, 2 is an input terminal, 3 is a signal source, 4 is an output terminal, 6 and 7 are first and second power lines, and 8 and 9 are first, The second bias voltage source, 32 is a bias voltage source (first and second bias voltage sources), C1 and C2 are first and second capacitors, Q1 and Q2 are first and second transistors, and Q3 is a transistor (first transistor). Constant voltage element), Q4 is a transistor (second constant voltage element), D1 is a diode (first constant voltage element), D2 is a diode (second constant voltage element), R1 is a first resistor, and R1A and R1B are first A , 1B resistor, R2 is a second resistor, R2A and R2B are 2A and 2B resistors, R3 and R3A are 3rd resistors, R4 and R4A are 4th resistors, and Rf is a feedback resistor.

Claims (7)

A P-channel first transistor (Q1) grounded at the first power supply line (6) and the second power supply line (7), and connected in series with the output terminal (4) sandwiched between the power supply lines, An N-channel second transistor (Q2);
A feedback resistor (Rf) connected between the input terminal (2) and the output terminal;
A first capacitor (C1) connected between the input terminal and the gate of the first transistor;
A second capacitor (C2) connected between the input terminal and the gate of the second transistor;
A first bias voltage source (8, 32) for outputting a first bias voltage;
A second bias voltage source (9, 32) for outputting a second bias voltage;
A first resistor (R1) provided between the first bias voltage source and the gate of the first transistor;
A second resistor (R2) provided between the second bias voltage source and the gate of the second transistor;
A third resistor (R3, R3A) provided between the gate of the first transistor and the output terminal;
An amplifier circuit comprising a fourth resistor (R4, R4A) provided between the gate of the second transistor and the output terminal. The output impedance of the signal source (3) connected to the input terminal is Rs, the resistance value of the feedback resistor is Rf, and the resistance values of the first, second, third, and fourth resistors are R1, R2, and R3, respectively. , R4,
f = Rs / (Rf + Rs)
K1 = R1 / (R1 + R3)
K2 = R2 / (R2 + R4)
2. The amplifier circuit according to claim 1, wherein K1, K2> f is established when f, K1, and K2 are defined as follows. A first constant voltage element (D1, Q3) connected in series with the third resistor;
3. The amplifier circuit according to claim 1, further comprising a second constant voltage element (D2, Q4) connected in series with the fourth resistor. The first resistor includes a series circuit of a first A resistor (R1A) and a first B resistor (R1B),
The second resistor is configured by a series circuit of a second A resistor (R2A) and a second B resistor (R2B),
The third resistor (R3, R3A) is connected between a connection node of the first A and first B resistors and the output terminal,
The said 4th resistance (R4, R4A) is connected between the connection node of the said 2A, 2B resistance, and the said output terminal, The Claim 1 characterized by the above-mentioned. Amplifier circuit. The first constant voltage element is composed of a diode (D1) having the output terminal side as a cathode,
5. The amplifier circuit according to claim 3, wherein the second constant voltage element includes a diode having an anode on the output terminal side. The first constant voltage element is composed of an N-channel transistor (Q3) having a gate-drain connected and having the output terminal side as a source,
5. The amplifier circuit according to claim 3, wherein the second constant voltage element includes a P-channel transistor (Q 4) having a gate and a drain connected and having the output terminal side as a source. 6. . The first and second bias voltage sources (32) are:
A P-channel transistor (Q7) having a source connected to the first power supply line and a gate-drain connected;
An N-channel transistor (Q5) having a source connected to the second power supply line and a gate-drain connected;
A circuit for generating an equal current to these P-channel and N-channel transistors,
7. The amplifier circuit according to claim 1, wherein gate-source voltages of the P-channel and N-channel transistors are output as the first and second bias voltages, respectively.

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