JP2014157404A - Electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a peripheral device to be reset when a CPU is restarted even in an electronic apparatus using an SoC without a reset output function to the peripheral device.SOLUTION: An electronic apparatus provided with an integrated circuit having a CPU, and a storage device from which information is read in accordance with an address signal and a readout signal transmitted from the integrated circuit comprises a restart detection unit that transmits a reset signal to the storage device when the address signal specifying a specific address and the readout signal are input.

Description

  The present invention relates to an electronic device using an integrated circuit including a CPU (Central Processing Unit), and more particularly to an electronic device including a reset circuit that resets peripheral devices connected to the integrated circuit when the CPU is restarted.

  Many electronic devices use an integrated circuit called SoC (System on a chip). The SoC is an integrated circuit in which a CPU (Central Processing Unit), a memory controller, and various IF (InterFace) controllers are combined into one. In this SoC, there is a case where a device called WDT (Watch Dog Timer) is provided in the SoC as protection when a program runs away.

  FIG. 6 shows a connection diagram around the CPU and WDT in the related art. The WDT 12 in the SoC 14 includes a subtraction counter. The CPU 11 resets the subtraction counter of the WDT 12 by sending a timer reset signal before the counter of the WDT 12 expires at 0 during normal operation. When the device program runs away and the CPU 11 cannot send a timer reset signal to the WDT 12, the counter of the WDT 12 expires. Upon receiving the expiration of the timer, the reset unit 13 outputs a reset signal to the CPU 11 to reset the CPU 11.

  However, since the reset process of the CPU 11 by the WDT 12 is performed only in the SoC 14, there are cases where the peripheral device connected to the SoC 14 cannot directly receive the reset process information of the CPU 11 by the WDT 12. For this reason, the SoC 14 is in a restarted state after resetting, but the peripheral device is not reset, so that a state mismatch occurs between the SoC 14 and the peripheral device.

  In particular, the memory storing the system program cannot read correct data unless it is reset after the SoC 14 is restarted and before the system program is read.

  In order to solve this problem, Patent Document 1 discloses a technique for generating a reset signal by WDT at an arbitrary timing and outputting the signal to an external peripheral device.

JP 2006-079345 A

  In order to solve the above problem, it is necessary for the SoC to have a function of outputting a reset signal to an external peripheral device, and an increase in circuit design and control for that purpose causes an increase in cost.

  The objective of this invention is providing the electronic device which solves the subject mentioned above.

  In order to solve the above-described problems, the present invention provides an integrated circuit having a CPU, a storage device from which information is read by an address signal and a read signal sent from the integrated circuit, an address signal for specifying a specific address, and a read signal And a restart detection unit that sends a reset signal to the storage device when.

  Further, the present invention provides an integrated circuit having a CPU, a peripheral device that exchanges information with the integrated circuit, and a reset signal to the peripheral device when a signal that appears at a predetermined terminal that exchanges information with the integrated circuit falls. And a restart detection unit for transmitting a signal.

  According to the present invention, in an electronic device using a SoC with no reset output, it is possible to reset a peripheral device simply by installing a circuit with a simple configuration, and to obtain an effect of preventing malfunction. . Further, since the above circuit is independent of the SoC, the program change can be greatly reduced.

It is a block diagram which shows the basic composition of the electronic device in the 1st Embodiment of this invention. It is a block diagram which shows the detailed structure of the electronic device in the 1st Embodiment of this invention. It is a figure which shows the address of the memory in the 1st Embodiment of this invention. It is an operation | movement transition diagram when CPU in the 1st Embodiment of this invention runs away. It is a block diagram which shows the structure of the electronic device in the 2nd Embodiment of this invention. It is a block diagram which shows the structure in related technology.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(First embodiment)
FIG. 1 is a diagram illustrating a basic configuration example of an electronic device 1 according to a first embodiment of the present invention. The electronic device 1 includes an integrated circuit 2 including a CPU, a peripheral device 3, and a restart detection unit 4. In the present invention, the restart detection unit 4 is disposed between the integrated circuit 2 and the peripheral device 3. The peripheral device 3 is a storage device, for example.

  FIG. 2 shows a detailed configuration example of the first embodiment of the present invention.

  In FIG. 2, in the electronic device 201, the memory 203 in which the system program is stored, the SoC 202, and the restart detection unit 204 disposed therebetween are illustrated. The SoC 202 includes a CPU 211, a WDT 213, and a reset unit 214. Further, a memory controller 212 is connected to the CPU 211, and the memory controller 212 transmits and receives signals and data to and from the memory 203.

  The memory 203 is a parallel type nonvolatile memory, and is connected to the memory controller 212 of the SoC 202 through a plurality of address lines and a plurality of data lines.

  The restart detection unit 204 includes an address monitoring unit 205, a data control unit 210, and an OR circuit 216. The restart detection unit 204 detects the address signal 206 output to the address line by the address monitoring unit 205, and outputs a Low signal as the detection signal 208 when the address is a preset value. The data control unit 210 connects the data line A215 and the data line B207, and when the detection signal 208 becomes Low, the data control unit 210 disconnects the data line A215 and the data line B207 and can transmit predetermined data only to the SoC 202 side. I can do it. The OR circuit 216 takes the OR of the detection signal 208 and the read signal 209 and outputs a Low signal as a reset signal to the signal line connected to the reset terminal of the memory 203 when both are Low.

  Here, as a precondition, the SoC 202 sets the read signal 209 to a low level when reading data in the memory 203. Further, when Low is input to the reset terminal of the memory 203, the memory 203 is reset.

  FIG. 3 shows data stored in the memory 203. Dummy data is stored at address 0x2000 of the memory 203, and system programs are stored at addresses 0x2001 to 0x4000. When the CPU 211 is restarted, the SoC 202 reads data from the address 0x2000 of the memory 203 in order to read the system program.

  FIG. 4 shows an operation transition diagram when the CPU runs away, and the operation will be described.

  First, the CPU 211 runs away (S41). The runaway CPU 211 cannot perform a timer reset on the WDT 213 and the WDT 213 counter expires. The reset unit 214 receives information indicating that the counter has expired from the WDT 213 and resets the CPU 211. When the CPU 211 is reset and then restarted (S42), the SoC 202 (or the CPU 211) goes to read the data in the memory 203 to read the system program. At this time, the SoC 202 first reads the address 0x2000 of the memory 203 (S43). When the address monitoring unit 205 in the restart detection unit 204 detects that the address is 0x2000, it outputs a Low signal as the detection signal 208 (S44). The OR circuit 216 receives the Low signal and the read signal 209 (Low signal) output from the address monitoring unit 205, outputs the Low signal to the reset terminal of the memory 203, and resets the memory 203 (S45). While the detection signal 208 is Low, the data control unit 210 receives the detection signal 208, disconnects the connected data line A215 and data line B207, and sends a NOP (No-Operation) command to the data line A215 side. (S46). The SoC 202 that received the NOP (S47) does not perform any processing, and then reads the data at the address 0x2001 (S48). Since the operation of reading the address 0x2000 is completed, the detection signal 208 becomes a High signal, and the reset of the memory 203 is released. The data control unit 210 also returns the connection between the data line A 215 and the data line B 207. When the SoC 202 reads the data after the address 0x2001 in the memory 203 up to the address 0x4000, the restart of the SoC 202 is completed (S49).

  The SoC 202 does not read the data at the address 0x2000 in the memory 203 except at the time of activation or restart, and the restart detection unit 24 does not reset the memory 23. Even if data is written to the address 0x2000 of the memory 203, the restart detection unit 24 does not reset the memory 203 because the read signal 209 does not go low.

As described above, the present invention detects the restart of the CPU by detecting the address signal and the read signal by installing a simple circuit between the SoC and the memory storing the system program. In addition, the memory can be reset.
(Second Embodiment)
A second embodiment of the present invention will be described with reference to FIG.

  FIG. 5 is a block diagram illustrating a configuration example of the electronic device 51 according to the second embodiment of the present invention. The SoC 52 includes a restart detection unit 54 and a memory 53.

  In FIG. 5, GPIO (General Purpose Input / Output) of the SoC 52 is connected to the restart detection unit 54, and the restart detection unit 54 is further connected to the reset terminal of the memory 53 of the peripheral device. GPIO is also connected to GND through a resistor. Here, GPIO is a general-purpose terminal of SoC.

  As a precondition, the GPIO is in a High-Z state (a state in which neither the High signal nor the Low signal is driven on the SoC side) before the SoC 52 reads the system program from the memory 53. Further, after the SoC 52 reads the system program from the memory 53, the system can control High output / Low output.

  The restart detection unit 54 includes a falling edge detection unit 55 and a reset signal generation unit 56 that detect a change in GPIO from High to Low. The falling edge detection unit 55 transmits a signal to the reset signal generation unit 56 when detecting the fall of GPIO. The reset signal generator 56 that has obtained the signal sends a reset pulse to the reset terminal of the memory 53 for a certain period of time to perform a reset.

  Next, the operation of the second embodiment will be described below.

  First, the SoC 52 reads the system program and sets it in a normal operating state. At this time, the SoC 52 sets GPIO to High output. Thereafter, when a CPU (not shown) in the SoC 52 restarts, the GPIO of the SoC 52 enters a High-Z state. However, the GPIO terminal changes to Low because it is connected to GND via a resistor. At this time, the falling edge detection unit 55 of the restart detection unit 54 detects the falling edge. Thereafter, the reset signal generation unit 56 outputs a reset pulse for a predetermined time in response to the reset of the memory 53 to reset the memory 53. Before the SoC 52 goes to the memory 53 to read the system program, the restart detection unit 54 releases the reset of the memory 53. Thereafter, the SoC 52 reads the system program into the memory 53. If the GPIO of the SoC 52 is set to High output on the system after reading the system program, the above operation can be performed even when restarting by WDT occurs again.

  As described above, according to the present invention, it is possible to detect the restart of the CPU and reset the peripheral devices by using the GPIO terminal of the SoC.

  The present invention is not limited to the above-described embodiment, and can be implemented with various changes and modifications without departing from the gist of the present invention.

  The present invention can be used for an electronic device using an SoC that does not have a reset output function.

DESCRIPTION OF SYMBOLS 1 Electronic device 2 Integrated circuit 3 Peripheral device 4 Restart detection part 11 CPU
12 WDT
13 Reset section 14 SoC
31 Memory data 51 Electronic device 52 SoC
53 Memory 54 Restart Detection Unit 55 Falling Edge Detection Unit 56 Reset Signal Generation Unit 201 Electronic Device 202 SoC
203 Memory 204 Restart Detection Unit 205 Address Monitoring Unit 206 Address Signal 207 Data Line B
208 Detection signal 209 Read signal 210 Data control unit 211 CPU
212 Memory controller 213 WDT
214 Reset unit 215 Data line A
216 OR circuit

Claims (10)

An integrated circuit having a CPU;
A storage device from which information is read by an address signal and a read signal sent from the integrated circuit;
A restart detection unit that sends a reset signal to the storage device when the address signal designating a specific address and the read signal are input;
An electronic device comprising:   The electronic device according to claim 1, wherein dummy information is stored at the specific address in the storage device.   The electronic device according to claim 1, wherein the specific address is an initial address of an area in which program information to be accessed when the CPU is restarted.   The restart detection unit includes an address monitoring unit that outputs a predetermined signal when the address signal designating the specific address is detected, and a circuit unit that generates the reset signal from the predetermined signal and the read signal. The electronic device according to any one of claims 1 to 3, wherein the electronic device is an electronic device.   The restart detection unit includes a data control unit that receives the predetermined signal output from the address monitoring unit and stops transmission / reception of information between the storage device and the integrated circuit. The electronic device according to claim 4.   6. The electronic apparatus according to claim 5, wherein the data control unit receives the predetermined signal output from the address monitoring unit and sends a NOP (No Operation) command to the integrated circuit. An integrated circuit having a CPU;
A peripheral device for exchanging information with the integrated circuit;
A restart detection unit that sends a reset signal to the peripheral device when a signal that appears at a predetermined terminal that transmits and receives the information of the integrated circuit falls;
An electronic device comprising:   8. The electronic apparatus according to claim 7, wherein a predetermined terminal for transmitting and receiving the information of the integrated circuit is in a high impedance state when the CPU is restarted.   9. The electronic apparatus according to claim 8, wherein a predetermined terminal for inputting / outputting the integrated circuit is grounded via a resistor having a predetermined resistance value.   The electronic device according to claim 7, wherein the peripheral device is a storage device.

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