JP2014155184A - Integrated circuit for oscillation - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an integrated circuit for oscillation designed to shorten an oscillation startup time and reduce current consumption during a steady oscillation state.SOLUTION: The integrated circuit for oscillation comprises: an oscillation unit 1 having a CMOS inverter configured by connecting MOS transistors PM1, NM1 in series, a feedback resistor 11 connected in parallel to the CMOS inverter, and load capacitances 12, 13 connected to each of the input terminal and output terminal of the CMOS inverter, and used by connecting a crystal vibrator 2 thereto; an oscillation detection circuit 3 for detecting a change in the amplitude of an oscillation signal outputted from the oscillation unit 1; and a bias circuit 4 for adjusting a supply current to the CMOS inverter by a detection signal of the oscillation detection circuit 3. When, after oscillation startup, the amplitude of the oscillation signal is not detected by the oscillation detection circuit 3 to have reached a size greater than or equal to a prescribed size, a current satisfying oscillation condition is supplied to the MOS transistor PM1; when the amplitude of the oscillation signal is detected to have reached a size greater than or equal to a prescribed size, a current smaller than the above is supplied.

Description

  The present invention relates to an oscillation integrated circuit including an oscillation circuit.

  The oscillation circuit is required to have a short oscillation start-up time from the start to the steady oscillation state and to have a stable oscillation operation. In order to meet this demand, for example, a CMOS inverter circuit is conventionally connected in parallel with a feedback resistor of an oscillation circuit in a crystal oscillator, and the CMOS inverter circuit is a PMOS transistor connected in series between a power supply voltage and a constant voltage. A configuration is known in which an input signal of a CMOS inverter circuit is supplied to the gate of a MOS transistor having an NMOS transistor and a capacitor and having one end of a current path connected to the constant potential via the capacitor (patent) Reference 1). On the other hand, in order to reliably oscillate with the crystal oscillator, it is necessary to set the negative resistance to 3 to 10 times the equivalent series resistance CI value of the crystal at the time of startup. Satisfactory oscillator current is set.

JP 2007-159077 A

  According to the above-described conventional configuration, the oscillation characteristic does not fluctuate and stable oscillation from a low voltage is possible. However, even when the steady oscillation state is reached, the current of the oscillation circuit is the same as at startup. However, in the steady oscillation state, the oscillation can be continued if the negative resistance is at least one time the equivalent series resistance CI value. Therefore, in the steady oscillation state, the oscillation circuit consumes more current than necessary. There is an inconvenience. If the setting of the oscillation unit current is reduced in the conventional configuration with respect to this problem, another problem such as worsening of the oscillation start characteristic, an increase in the oscillation start time, and an oscillation failure occurs.

  The first object of the present invention is to provide an oscillation integrated circuit including an oscillation circuit that eliminates this inconvenience, shortens the oscillation start-up time, and reduces the current consumption in the steady oscillation state. To do. It is a second object of the present invention to provide an oscillation integrated circuit including an oscillation circuit that guarantees a stable output in a steady oscillation state with reduced current consumption.

  In order to achieve the first object, an oscillation integrated circuit according to claim 1 of the present invention comprises a CMOS inverter comprising a series connection of first and second MOS transistors, and a feedback resistor connected in parallel to the CMOS inverter. , An oscillation unit having a load capacitance connected to each of the input terminal and the output terminal of the CMOS inverter, connected to a piezoelectric vibrator, and detecting a change in amplitude of an oscillation signal output from the oscillation unit And an adjustment means for adjusting a current supplied to the CMOS inverter by a detection signal of the oscillation detection circuit, and after the oscillation starts, the oscillation detection circuit makes the amplitude of the oscillation signal larger than a predetermined value. When it is not detected that the current has reached, a current that satisfies an oscillation condition is supplied to the first MOS transistor, and the amplitude of the oscillation signal is larger than a predetermined value. When it detects that it has reached the difference, and supplies a current smaller than the current.

  Similarly, in order to achieve the first object, an oscillation integrated circuit according to claim 2 of the present invention is the oscillation integrated circuit according to claim 1 described above, wherein the adjusting means is controlled by the output of the oscillation detection circuit. The bias circuit is configured to generate a gate voltage of the first MOS transistor, and the bias circuit detects that the amplitude of the oscillation signal has reached a predetermined level after the oscillation is started. If not, the drive is started while the gate of the first MOS transistor is biased with a power supply through a resistor, and the oscillation detection circuit detects that the amplitude of the oscillation signal has reached a predetermined level or more. After that, the first MOS transistor is controlled to be driven with a smaller current than when the bias is driven by the power source.

  In order to achieve the second object, an oscillation integrated circuit according to claim 3 of the present invention has the signal output state and the signal output stop state in the oscillation integrated circuit according to claim 1 or 2 described above. An output circuit that generates a signal to be output to the outside based on an oscillation signal from the oscillation unit, and has a time constant for charging and discharging, and an output voltage level is set by an output signal of the oscillation detection circuit, A narrow signal elimination circuit, for example, a filter circuit, in which the output voltage level does not change with respect to fluctuations of the output signal of the oscillation detection circuit within a predetermined time, and the output circuit is controlled by the output voltage level of the narrow signal elimination circuit. The signal output state or the signal output stop state is controlled.

  According to the oscillation integrated circuit according to claim 1 or 2 of the present invention, the oscillation start time is shortened by switching the oscillation unit current between the oscillation start time and the steady oscillation state, and at the steady oscillation state. The consumption current can be reduced. Further, according to the oscillation integrated circuit according to claim 3 of the present invention, the output circuit does not stop the signal output when the amplitude of the oscillation signal is temporarily reduced. A stable output can be obtained without causing an intermittent signal output stop state.

The block diagram which shows the whole structure in the 1st Embodiment of this invention. Similarly, the block diagram of a bias circuit. FIG. 3 is an explanatory diagram showing the relationship between the detection signal of the oscillation detection circuit and the gate voltage and current of the first MOS transistor. Explanatory drawing which similarly shows operation | movement of the filter circuit which is a narrow signal removal circuit. The block diagram which shows the whole structure in the 2nd Embodiment of this invention. The block diagram which shows the whole structure in the 3rd Embodiment of this invention.

  First, a first embodiment of the present invention will be described. First, a configuration of an oscillation integrated circuit will be described based on FIG. 1 of the accompanying drawings. The oscillation integrated circuit includes a P-type MOS transistor (hereinafter referred to as a PMOS transistor) PM1 that is a first MOS transistor and an N-type MOS transistor (hereinafter referred to as an NMOS transistor) NM1 that is a second MOS transistor. And an oscillation detection circuit 3 that detects a change in the amplitude of an oscillation signal output from the oscillation unit 1. A bias circuit 4 that is controlled by the output of the circuit 3 and generates the gate voltage of the PMOS transistor PM1, an output circuit 5, and a filter circuit 6 that is a narrow signal removal circuit are provided.

  The oscillation unit 1 includes a CMOS inverter, a feedback resistor 11 connected in parallel to the CMOS inverter, a load capacitor 12 connected to the input terminal of the CMOS inverter, and a load capacitor 13 connected to the output terminal of the CMOS inverter. . The output terminal of the bias circuit 4 is connected to the gate of the PMOS transistor PM1 through the resistor 7, and a capacitor 8 is connected between the gates of the PMOS transistor PM1 and the NMOS transistor NM1. In the CMOS inverter, the source of the PMOS transistor PM1 is connected to a high potential (constant potential Vref), and the source of the NMOS transistor NM1 is connected to a low potential power supply (ground potential Vss).

  As shown in FIG. 2, the bias circuit 4 includes two PMOS transistors PM2 and PM3, the source of the PMOS transistor PM2 is connected to the constant potential Vref, the drain thereof is connected to the source of the PMOS transistor PM3, The detection signal B output from the oscillation detection circuit 3 is input to the gate. The drain and gate of the PMOS transistor PM3 are commonly connected to the ground potential Vss via the resistor 41. The gate of the PMOS transistor PM3 is further connected to a low-pass filter composed of a resistor 42 and a capacitor 43, and the output of the low-pass filter is input to the oscillation unit 1 via the resistor 7 (see FIG. 1). However, the low-pass filter (resistor 42 and capacitor 43) is not essential.

  The output circuit 5 includes an amplifier circuit, a frequency divider circuit, an output drive circuit, and the like. The output circuit 5 generates a signal C to be output to the outside based on the oscillation signal from the oscillation unit 1. The signal output state to be output and the signal output stop state to stop the output of the oscillation signal that does not reach the steady oscillation state. The filter circuit 6 has a time constant with respect to charging / discharging, and the output voltage level is set depending on whether the detection signal B of the oscillation detection circuit 3 is H level or L level. When the detection signal B is at the H level, the signal output stop instruction level is set, and when the detection signal B is at the L level, the signal output instruction level is set. If the change of the detection signal B of the oscillation detection circuit 3 is within a predetermined time determined by the time constant, the output voltage level does not change. As described above, the output circuit 5 is controlled to be in the signal output state or the signal output stop state according to the output voltage level of the filter circuit 6 according to the change of the detection signal B of the oscillation detection circuit 3.

  Next, the operation of this embodiment will be described. As shown in FIG. 3, when the power is turned on and the amplitude of the output signal A of the oscillation unit 1 is small and the oscillation detection circuit 3 is in an oscillation non-detection state, the detection signal B is at the H level. The PMOS transistor PM2 is in an off state. For this reason, the PMOS transistor PM1 is turned on with the gate voltage thereof set to the ground potential Vss, the current IVref flows, and the supply current to the oscillation unit 1 increases. As a result, when the amplitude of the output signal A becomes large and this amplitude becomes a steady oscillation state greater than or equal to a predetermined value, the detection signal B of the oscillation detection circuit 3 that detects this becomes L level.

  When the detection signal B of the oscillation detection circuit 3 becomes L level, the PMOS transistor PM2 of the bias circuit 4 is turned on, the gate voltage of the PMOS transistor PM1 rises to Vss + α, and the current flowing through the PMOS transistor PM1 decreases from IVref. As a result, the supply current to the oscillation unit 1 decreases. Thus, when the oscillation unit 1 reaches the steady oscillation state, the current consumption is reduced and the oscillation state is maintained and the output signal A is output from the output circuit 5 as the output signal C. Note that the change in the gate voltage and current of the PMOS transistor PM1 shown in FIG. 3 does not accurately indicate the actual change amount, but indicates a general tendency.

  When the amplitude of the output signal A decreases with a decrease in the supply current to the oscillating unit 1 and becomes equal to or less than a predetermined value, the detection signal B of the oscillation detection circuit 3 that detects this becomes H level. When the detection signal B becomes H level, the PMOS transistor PM2 of the bias circuit 4 is turned off, the gate voltage of the PMOS transistor PM1 becomes Vss, the current IVref flows, and the supply current to the oscillation unit 1 increases. To go. When the amplitude of the output signal A is increased and a steady oscillation state exceeding a predetermined level is detected, the detection signal B of the oscillation detection circuit 3 that detects this becomes the L level again.

  By the way, even when the detection signal B of the oscillation detection circuit 3 returns from the H level to the L level, in other words, even when the duration of the H level is short, the output state of the output circuit 5 is directly controlled by the detection signal B. Then, as shown in FIG. 4, the output circuit 5 repeats the signal output stop state when the detection signal B is at the H level and the signal output state when the detection signal B is at the L level. This will interfere with the oscillation output operation.

  In the present embodiment, the change of the detection signal B of the oscillation detection circuit 3 from the H level to the L level, that is, the duration of the H level is determined by the time constant (the slope of the line segment B ′ shown in FIG. 4). If it is within the predetermined time, in other words, if the line segment B ′ does not reach the signal detection level shown in FIG. 4, the output voltage level of the filter circuit 6 is set so as not to change from the signal output instruction level to the signal output stop level. ing. Since the signal output state and signal output stop state of the output circuit 5 are controlled by the output voltage level of the filter circuit 6, the H level duration of the detection signal B is within a predetermined time determined by the time constant. If so, the output circuit 5 can maintain a signal output state and continue a stable oscillation output operation.

  On the other hand, when the continuation of the H level of the detection signal B of the oscillation detection circuit 3 exceeds a predetermined time determined by the time constant, the output voltage level of the filter circuit 6 changes from the signal output instruction level to the signal output stop level, The oscillation output from the output circuit 5 stops. When the oscillation detection circuit 3 detects that the output signal A of the oscillation unit 1 has reached a predetermined amplitude and the detection signal B becomes L level, the output voltage level of the filter circuit 6 changes to the signal output instruction level. Thus, the output signal C in the steady oscillation state is output from the output circuit 5. The above description of the operation is the same for the L level duration of the detection signal B.

  FIG. 5 shows a second embodiment of the present invention, in which a bias voltage is supplied from the bias circuit 4 to the gate of the NMOS transistor NM1 of the CMOS inverter. The CMOS inverter is a source of the PMOS transistor PM1. Are connected to a high potential power supply (power supply potential VDD), and the source of the NMOS transistor NM1 is connected to a low potential (constant potential Vref). For other configurations, the same reference numerals are assigned to the components corresponding to those of the first embodiment, and detailed description thereof is omitted.

  Although not shown, the bias circuit 4 according to this embodiment includes two NMOS transistors. One NMOS transistor has a source connected to the constant potential Vref and a drain connected to the source of the other NMOS transistor. And the detection signal B output from the oscillation detection circuit 3 is input to the gate thereof. The other NMOS transistor has its drain and gate commonly connected to the power supply potential VDD via a resistor, and its gate connected to the gate of the NMOS transistor NM1 via a resistor 7. In this embodiment, the same operation as in the first embodiment is performed.

  FIG. 6 shows a third embodiment of the present invention, which employs an oscillation amplitude control circuit instead of a bias circuit as an adjusting means. The configuration of this embodiment is the same as that of the first embodiment except for the oscillation amplitude control circuit. Although not shown, the oscillation circuit 21 as an oscillation unit is connected in parallel to a CMOS inverter formed by connecting a P-type first MOS transistor and an N-type second MOS transistor in series, and the CMOS inverter. The feedback resistor and the load capacitance connected to each of the input terminal and the output terminal of the CMOS inverter are used by connecting a crystal resonator 22 which is a piezoelectric resonator.

  The oscillation detection circuit 23 detects a change in the amplitude of the oscillation signal output from the oscillation circuit 21 and outputs a detection signal B. The oscillation amplitude control circuit 24 receives the detection signal B from the oscillation detection circuit 23 and outputs a control signal for controlling the oscillation amplitude to the oscillation unit. For example, the oscillation amplitude control circuit 24 adjusts the supply current to the CMOS inverter. The oscillation amplitude is controlled. Further, for example, a circuit that changes the inversion potential and mutual conductance of the CMOS inverter may be used.

  The output circuit 25 has a signal output state in which an oscillation signal in a steady oscillation state is output, and a signal output stop state in which an oscillation signal that does not reach the steady oscillation state stops outputting. Based on the oscillation signal A from the oscillation circuit 21 An output signal C to be output to the outside is generated. The filter circuit 26 has a time constant for charging and discharging, and the output voltage level is set depending on whether the detection signal B of the oscillation detection circuit 23 is H level or L level. At the level and L level, the signal output instruction level is obtained. If the change in the detection signal B of the oscillation detection circuit 23 is within a predetermined time determined by the time constant, the output voltage level does not change. Thus, the signal output state and the signal output stop state of the output circuit 25 are controlled by the output voltage level of the filter circuit 26 according to the change of the detection signal B of the oscillation detection circuit 23.

  Since the operation of this embodiment is the same as the operation shown in FIG. 4 described above, the description thereof is omitted. The filter circuit 26 only needs to remove a signal having a certain width or less from the signal for controlling the output circuit 25. For example, the filter circuit 26 is a low-pass that suppresses a frequency signal that can be calculated from the signal width to be removed. A filter or a filter that masks signal transitions in a certain interval can be used.

DESCRIPTION OF SYMBOLS 1 Oscillator 2, 22 Crystal oscillator 3, 23 Oscillation detection circuit 4 Bias circuit 5, 25 Output circuit 6, 26 Filter circuit 11 Feedback resistor 12, 13 Load capacity 21 Oscillation circuit 24 Oscillation amplitude control circuit PM1, PM2, PM3 PMOS Transistor NM1 NMOS transistor

Claims (3)

A CMOS inverter comprising a series connection of first and second MOS transistors, a feedback resistor connected in parallel to the CMOS inverter, and a load capacitance connected to each of the input terminal and output terminal of the CMOS inverter; An oscillating unit used by connecting a piezoelectric vibrator;
An oscillation detection circuit that detects a change in amplitude of an oscillation signal output from the oscillation unit; and an adjustment unit that adjusts a supply current to the CMOS inverter by a detection signal of the oscillation detection circuit,
After the oscillation is started, when the oscillation detection circuit does not detect that the amplitude of the oscillation signal has reached a predetermined level or more, a current that satisfies an oscillation condition is supplied to the first MOS transistor, and the oscillation signal An oscillation integrated circuit, wherein a current smaller than the current is supplied when it is detected that the amplitude of the current reaches a predetermined magnitude or more.   The adjusting means is configured by a bias circuit that is controlled by an output of the oscillation detection circuit and generates a gate voltage of the first MOS transistor. The bias circuit is configured such that after the oscillation starts, the oscillation detection circuit When it has not been detected that the amplitude has reached a predetermined level or more, driving is started while the gate of the first MOS transistor is biased with a power supply through a resistor, and the oscillation detection circuit The first MOS transistor is controlled to be driven with a smaller current than when the bias is driven by the power source after detecting that the amplitude has reached a predetermined level or more. The oscillation integrated circuit according to Item 1. An output circuit having a signal output state and a signal output stop state, and generating a signal to be output to the outside based on the oscillation signal from the oscillation unit;
It has a time constant for charging and discharging, and an output voltage level is set by the output signal of the oscillation detection circuit, and the output voltage level does not change for fluctuations within a predetermined time of the output signal of the oscillation detection circuit With a narrow signal removal circuit,
The oscillation integrated circuit according to claim 1 or 2, wherein the signal output state and the signal output stop state of the output circuit are controlled by the output voltage level of the narrow signal removal circuit.

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