JP2014143599A - Optical transmitter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To restore an optical signal quickly when an electric signal and a reference clock are restored from an abnormal state.SOLUTION: An optical transmitting/receiving module 1 comprises: phase locked loop circuits 3a and 3b for generating multiplication clocks CLon the basis of reference clocks CLand, when the reference clocks CLare not normal, outputs alarm signals ALM; a frame processing part 3d to which an electric input signal and the multiplication clocks CLare inputted, which reads data on the basis of the clocks after data is read from the electric input signal, and outputs an alarm signal ALMwhen the clock is desynchronized; an optical transmission part 5 for outputting an optical signal on the basis of the read data; and a control unit 7 for performing control so as to reset the phase locked loop circuit 3a and the frame processing part 3d in this order when the alarm signal ALMis restored after optical output is cut off in the case that the alarm signals ALMand ALMare received.

Description

  The present invention relates to an optical transmitter that generates an optical signal based on an electrical signal.

  IEEE 802.3ba and IEEE 802.3bg are defined as standards for optical transmission networks in order to eliminate bottlenecks in the transmission capacity of communication between servers. In response to these standards, optical communication modules are required to expand optical transmission capacity to 40 Gbps or 100 Gbps. In order to generate a high-quality optical signal with a communication speed of 40 Gbps, an EA (Electronic Absorption) optical modulator is used as an optical modulator in the optical transmission module, and an optical modulator driving circuit is used for driving the optical modulator. Is used. Further, the optical transmission module is provided with a control circuit. The control circuit receives setting information from the host and controls each part in the module, monitors each part and notifies the host of various information such as an alarm. .

  In the optical transmission module, the optical output is appropriately controlled according to the monitoring state of each unit. For example, in the wavelength division multiplex transmission apparatus described in Patent Document 1 below, control is performed to keep the optical output level in an appropriate state even when an input signal applied to a certain wavelength of the transmission apparatus is disconnected or out of synchronization. Yes. In the optical transmitter described in Patent Document 2 below, the optical output is controlled in accordance with the cause of occurrence of an abnormal state in automatic power control.

JP 2002-44035 A JP 2007-325189 A

  In a conventional optical transmission module, when an externally supplied electrical signal or reference clock is different from a preset frequency or does not have sufficient amplitude, abnormal random noise is transmitted to the optical transmission network side. In general, a control for shutting off the optical output is executed in order to prevent the optical output from being generated, and thereafter, when the electric signal or the reference clock is recovered, a control for restarting the optical output is executed. When such control is executed, an optical signal containing transiently erroneous data may be transmitted when the electric signal or the reference clock is recovered.

  In view of the above, an object of the present invention is to provide an optical transmitter capable of quickly returning an optical signal when an electrical signal or a reference clock is recovered from an abnormal state. It is to be.

  In order to solve the above problems, the optical transmitter according to the present invention receives a reference clock signal from the outside, generates and outputs a first clock signal based on the reference clock, and the reference clock is not normal A first phase-locked loop circuit that outputs a first alarm signal, an electric input signal from the outside, and a first clock signal from the first phase-locked circuit are input, and the second phase signal is synchronized with the electric input signal. After the data is read from the electrical input signal based on the second clock signal, the data is read based on the first clock signal, and the second clock signal and the first clock signal are synchronized. The first phase synchronization circuit that outputs the second alarm signal, the optical transmission circuit that outputs the optical signal based on the data read from the second phase synchronization circuit, and the first Alarm signal or When the second alarm signal is received, the optical signal is cut off, and after the first alarm signal or the second alarm signal is restored, the first phase synchronization circuit is reset. And a control circuit that controls to reset the second phase synchronization circuit.

  According to the optical transmitter of the present invention, the first clock signal is generated based on the reference clock from the outside by the first phase synchronization circuit, and is synchronized with the electric input signal from the outside by the second phase synchronization circuit. The second clock is generated, the data is read from the electrical input signal based on the second clock signal, the data is read based on the first clock signal, and the data is read by the optical transmission circuit. An optical signal is output to. At that time, if the reference clock is not normal, or if the first clock signal and the second clock signal are out of synchronization, the alarm signal is detected by the control circuit and the optical signal is cut off. When the signal is recovered, the first phase synchronization circuit and the second phase synchronization circuit are reset in order. Thereby, the reading process of data from the electric signal and the reading process of the data are normally initialized, and the optical signal can be quickly returned in a normal state.

  The optical transmission circuit includes a laser diode element that generates an optical signal and an optical modulator that modulates the optical signal, and the control circuit receives the first alarm signal or the second alarm signal and then receives the laser diode. It is preferable to control so that the drive current supplied to the element is cut off. By adopting such a configuration, it is possible to prevent the optical signal from being transmitted in an abnormal state such as excessive light emission.

  In addition, the control circuit controls the drive current to be cut off, and then sets the drive signal applied to the laser diode element or the optical modulator to a predetermined set value for preventing excessive light emission, and then sets the drive current. It is also preferable to control to turn on. In this case, the optical signal can be quickly returned when the alarm signal is recovered.

  According to the present invention, an optical signal can be quickly restored when an electrical signal or a reference clock is recovered from an abnormal state.

It is a block diagram which shows schematic structure of the optical transmitter which concerns on embodiment. FIG. 2 is a block diagram illustrating in detail a connection configuration of a control unit of the optical transmitter in FIG. 1. It is a flowchart which shows the procedure of the control action by the control part 7 of FIG.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. In the description of the drawings, if possible, the same elements are denoted by the same reference numerals, and redundant description is omitted. The optical transceiver module 1 according to the present embodiment is an apparatus including an optical transmitter that receives an electrical signal input from a host device that is an external device and outputs an optical signal in accordance with the electrical signal.

  The configuration of the optical transceiver module 1 will be described with reference to FIGS. As shown in these figures, the optical transmission / reception module 1 receives a reference clock signal from an external host device and four pairs of electrical signals having a transmission rate of 10 Gbps, for example. Multiplexes and outputs an optical signal based on the electrical signal received from the multiplexer 3 and outputs it to the optical transmission network (optical transmission circuit) 5 and a control unit (control circuit) 7.

The multiplexing unit 3 includes an integrated circuit (IC), phase synchronization circuits (first phase synchronization circuits) 3a and 3b, a frame processing unit (second phase synchronization circuit) 3d, and a multiplexing process. The part 3e is mainly provided. Specifically, the phase synchronization circuit 3a, the phase synchronization circuit (frequency multiplication circuit) 3b, the frame processing unit 3d, and the multiplexing processing unit 3e are configured on separate integrated circuits. Phase synchronization circuit 3a receives the reference clock CL ₁ of a predetermined frequency from the outside, the jitter components of the reference clock CL ₁ is removed to output the reference clock CL _2. The phase synchronization circuit 3a, the jitter component of the reference clock CL ₁ to be able to sufficiently removed, the bandwidth of the PLL (phase locked loop) is formed by a narrowed phase synchronizing circuit to 1KHz below. Further, the phase synchronization circuit 3a, when the frequency of the reference clock CL ₁ from the outside is abnormal out of a predetermined frequency, and outputs the reference clock CL ₂ of a predetermined frequency by performing a free-running oscillation. Phase locked loop (frequency multiplier) 3b are phase synchronized by receiving a reference clock CL ₂ output from circuit 3a, the reference clock CL ₂ from multiplied clock (first clock signal) CL ₃ generates and outputs phase the It is a synchronous circuit. In the phase synchronization circuit 3b, the bandwidth of the PLL is widened to about several MHz or more compared to the phase synchronization circuit 3a. Further, the phase synchronization circuit 3b, if the frequency of the reference clock CL ₂ input is out of a predetermined frequency range, or if the amplitude of the reference clock CL ₂ is smaller than the prescribed value, the reference clock CL ₂ An abnormality is detected, and an alarm signal (first alarm signal) ALM ₁ is output.

  The phase synchronization circuit 3b of the multiplexing unit 3 includes, for example, a multiplication clock corresponding to the transmission rate of the electrical signal from the host device, and a multiplication clock corresponding to the transmission rate of the electrical signal multiplexed by the multiplexing processing unit 3e. Are output to the frame processing unit 3d and the multiplexing processing unit 3e, respectively.

The frame processing unit 3d includes a clock data recovery circuit and a FIFO (Fast-In-Fast-Out) memory, and includes four pairs of electrical signals D ₁ , D ₂ , D ₃ , D ₄ from the host device, and a phase The multiplied clock (first clock signal) from the synchronization circuit 3b is input, and the clock signal (second clock signal) synchronized with all of the electric signals D ₁ , D ₂ , D ₃ , and D ₄ is converted into the electric signal. _{D 1, D 2, D 3} , is generated by extracting at least one or more or all _{D 4.} Further, the frame processing unit 3d reads data from each of the electrical signals D ₁ , D ₂ , D ₃ , and D ₄ in synchronization with the extracted clock, reads the data into the internal FIFO memory, and then reads each electrical signal D Data corresponding to ₁ , D ₂ , D ₃ , and D ₄ is read from the FIFO memory in synchronization with the multiplied clock generated by the phase synchronization circuit 3b. By such frame processing of the frame processing unit 3d, the time-series data included in the four pairs of electrical signals are synchronously and sequentially output to the multiplexing processing unit 3e, so that the four pairs of electrical signals are shaped and output. Is done. The extraction, frame processing unit 3d, from the electrical signal _{D 1, D 2, D 3} , when detecting a frequency or abnormal state of the amplitude of _{D 4,} and electrical signals _{D 1, D 2, D 3} , D 4 When the synchronized clock (second clock signal) is out of synchronization with the multiplied clock (first clock signal) from the phase synchronization circuit (frequency multiplication circuit) 3b, an alarm signal (second alarm signal) ALM ₂ is also generated and output. For example, the frame processing unit 3d monitors the pointer of the FIFO memory to monitor the data writing position and the reading position, and detects the loss of synchronization of the clock when the positions of both pointers greatly deviate.

The multiplexing processing unit 3e receives the output of four pairs of time series data from the frame processing unit 3d, and executes the multiplexing processing using the multiplied clock generated by the phase synchronization circuit 3b. By this multiplexing processing, an electric signal D ₀ in which four pairs of time-series data are multiplexed is generated and output to the optical transmitter 5.

The optical transmitter 5 includes a laser diode element 5a that generates an optical signal, an EA optical modulator 5b that modulates the optical signal, and an optical modulator drive circuit 5c that drives the EA optical modulator 5b. Yes. Optical modulator driving circuit 5c, by increasing or decreasing the drive voltage applied to the EA modulator 5b based on an electrical signal D ₀ output from the multiplexer 3, the light transmitted from the laser diode element 5a to the outside signal, to modulate the data contained in the electrical signal D ₀ based. In the optical transmitter 5 having such a configuration, a current source 9a for supplying a bias current to the laser diode element 5a is connected to the laser diode element 5a via a switch 9b, and the EA optical modulator 5b has an EA A bias voltage source 9c for applying a bias voltage to the optical modulator 5b is connected.

  The control unit 7 is a digital control circuit incorporating an analog circuit composed of a microprocessor, a DA converter, an AD converter, and the like, and receives various setting information from the host device and controls each unit of the optical transmission / reception module 1. The state of each part and the state of the signal from the outside are monitored, and various information such as an alarm signal is notified to the host device according to the monitoring result. Specifically, the control unit 7 is connected to the multiplexing unit 3, the current source 9a, the switch 9b, the bias voltage source 9c, and the optical modulator driving circuit 5c. The control unit 7 sets the light emission intensity of the laser diode element 5a by controlling the current source 9a, and controls on / off of the current flowing through the laser diode element 5a by controlling the switch 9b. Toggle on / off. The control unit 7 also adjusts the bias voltage applied to the EA optical modulator 5b by controlling the bias voltage source 9c. Further, the control unit 7 adjusts the cross point of the optical signal by controlling the optical modulator driving circuit 5c.

At this time, in the control unit 7, the microprocessor generates a control value for various controls with a digital value, converts the control value into an analog value with a DA converter, and outputs the analog value. For this reason, in the control processing in the control unit 7, a delay corresponding to the time of the periodic processing of the microprocessor occurs. Therefore, in the on / off control of the optical signal, a switch 9 b for shutting down the optical signal at high speed is provided. . The control unit 7 receives the alarm signal ALM ₁ or the alarm signal ALM ₂ from the multiplexing unit 3 and generates an abnormality in the reference clock CL ₂ or the electrical signals D ₁ , D ₂ , D ₃ , D ₄ , or When a loss of synchronization between the clock extracted from the signals D ₁ , D ₂ , D ₃ , and D ₄ and the multiplied clock from the phase synchronization circuit 3b is recognized by interrupt processing, the optical signal is turned off by controlling the switch 9b ( Cut off. In addition, when the alarm signal ALM ₁ or the alarm signal ALM ₂ from the multiplexing unit 3 is recovered, the control unit 7 resets the circuit unit including the phase synchronization circuit 3a, and then the phase synchronization circuit 3b and the frame processing unit. The integrated circuit unit including 3d and the multiplexing processing unit 3e is controlled to be reset.

  Next, an operation procedure of optical signal on / off control by the control unit 7 of the optical transceiver module 1 will be described with reference to FIG. FIG. 3 is a flowchart showing the procedure of the control operation by the control unit 7.

The monitoring process and the control process by the control unit 7 are executed by a periodic process by the microprocessor. First, when this periodic processing is activated, alarm signals ALM ₁ and ALM ₂ from the multiplexing unit 3 are accepted by the interrupt processing, and the reference clock CL ₂ or the electric signals D ₁ , D ₂ , D ₃ , and D ₄ are received. Presence or absence of occurrence of abnormality (hereinafter simply referred to as “signal abnormality occurrence”), or clock extracted from the electric signals D ₁ , D ₂ , D ₃ , D ₄ and clock from the phase synchronization circuit (frequency multiplication circuit) 3b Is detected (hereinafter simply referred to as “out of synchronization”) (step S01, abnormality confirmation processing). As a result, when the occurrence of signal abnormality or out-of-synchronization is not confirmed (step S02; NO), the abnormality confirmation process is repeated again in the next cycle. On the other hand, when the occurrence of signal abnormality or out-of-synchronization is confirmed (step S02; YES), the optical signal is shut down (blocked) by controlling the switch 9b by the control unit 7 (step S03).

  After that, the abnormality confirmation process is repeated again in the periodic process, and there is no signal abnormality occurrence or out-of-synchronization occurrence N times (N is a specified integer) (hereinafter, simply referred to as “normal state”). It is determined whether or not has been confirmed (step S04). If the normal state is confirmed N times consecutively as a result of the determination (step S04; YES), the counter stored in the control unit 7 is reset (step S05), and then the laser diode element 5a is driven. The current, the cross point in the drive voltage of the optical modulator drive circuit 5c, and the bias voltage of the EA optical modulator 5b are set to the normal state value (normal set value), and the optical output is returned to the normal state (step S06). . Then, the process is returned to step S01, and the abnormality confirmation process is repeated. As described above, when the recovery from the abnormality is determined several times in succession, the normal state is restored, and thus the phase synchronization circuit 3b erroneously returns the alarm signal due to the harmonics of the reference clock or the like. However, excessive light emission can be prevented.

  On the other hand, if the occurrence of signal abnormality or out-of-synchronization has continued, or if it has been recovered to a normal state but has not yet been confirmed to have recovered N times (step S04; NO), control is performed. The unit 7 sets the low light output state. That is, any one of the drive current applied to the laser diode element 5a by the control unit 7, the cross point in the drive voltage applied to the EA optical modulator 5b by the optical modulator drive circuit 5c, and the bias voltage applied to the EA optical modulator 5b. Alternatively, all are controlled so as to be set to a preset value (low light output setting value) that does not cause excessive light emission (step S07). Thereafter, the bias current of the laser diode element 5a shut down in step S03 is turned on by the control of the switch 9b (step S08).

Next, the control unit 7 determines whether or not the alarm signal ALM ₁ from the multiplexing unit 3 has been recovered (step S09). If the alarm signal ALM ₁ is determined to have recovered (Step S09; YES), the control unit 7, so that the reference clock CL ₂ of the correct frequency is output, the phase synchronization circuit 3a is reset (step S10). On the other hand, when it is not determined that the alarm signal ALM ₁ has been recovered (step S09; NO), the phase synchronization circuit 3a is not reset. Further, it is determined whether or not the counter inside the control unit 7 has reached a predetermined value (step S11). If the counter has not reached the predetermined value (step S11; NO), 1 is added to the counter (incremented), and the process returns to step S04 (step S12). On the other hand, when the counter reaches a predetermined value (step S11; YES), it is determined that the signal abnormality has continued for a long time, and the phase synchronization circuit 3b, the frame processing unit 3d, and the multiplexing processing unit The initialization process of the multiplexing unit 3 including 3e is executed. Specifically, after the counter of the control unit 7 is reset (step S13), the initialization process of the multiplexing unit 3 is executed (step S14). Thereafter, the process returns to step S01, and the abnormality confirmation process is repeated. This initialization process, the alarm signal ALM ₂ is released, the reference clock and input electrical signals, and the like can be executed smoothly automatic return after return successfully. Here, the predetermined value referred to in the determination in step S11 is set to a value that does not cause the operation to become unstable by repeating the initialization process due to noise or the like, for example, a value corresponding to a sufficiently long time of about 3 seconds Is done.

According to the optical transceiver module 1 described above, the reference clock CL ₂ based on the reference clock CL ₁ from the outside is generated by the phase synchronization circuit 3a, the frame processing unit 3d, electrical input signal D ₁ of the _external, D ₂ , D ₃ and D ₄ are generated, and after the data is read from the electric input signals D ₁ , D ₂ , D ₃ and D ₄ based on the clock, the data is generated based on the reference clock CL _2. The optical signal is read out and an optical signal is output by the optical transmitter 5 based on the data.

In order to avoid overflow or underflow in the FIFO memory of the frame processing unit 3d, the clocks of the electric input signals D ₁ , D ₂ , D ₃ , and D ₄ need to have the same frequency. In view of this, when the reference clock CL ₂ is not normal, or when the synchronized clock CL ₃ and the clock extracted from the electric input signals D ₁ , D ₂ , D ₃ , D ₄ are out of synchronization. The control unit 7 detects the alarm signals ALM ₁ and ALM _{2 and} blocks the optical signal. After that, when the electrical input signals D ₁ , D ₂ , D ₃ , D ₄ or the reference clock CL ₂ are suddenly restored and are in a transiently unstable state, the pointer is not simply reset by resetting the FIFO memory. In some cases, it would get stuck in the wrong state. As a result, the frame processing unit 3d may not correctly multiplex signals and may send out an incorrect optical signal. In the present embodiment, by being reset when the alarm signal ALM ₁ is restored in the order of the phase synchronizing circuit 3a and the frame processing section 3d, after the preparation of the reference clock CL ₂ is supplied to the correct phase synchronization circuit 3b is in place Since the frame processing unit 3d is reset, it is possible to reduce the risk of the FIFO memory pointer being stacked. Thereby, the process of reading and reading data from the electrical input signals D ₁ , D ₂ , D ₃ , D ₄ is normally initialized, and the optical signal can be quickly returned in a normal state.

Further, in this embodiment, when the alarm signals ALM ₁ and ALM ₂ are generated, the drive current supplied to the laser diode element 5a is controlled to be cut off, so that the optical signal is in an abnormal state such as excessive light emission. It can be prevented from being sent out. Thereafter, the control unit 7 sets the drive signal applied to the laser diode element 5a or the EA optical modulator 5b to a predetermined set value for preventing excessive light emission, and the drive current of the laser diode element 5a is turned on. Later, when the alarm signals ALM ₁ and ALM ₂ are restored, the set value is returned to the normal set value. When the alarm signal is restored, an overshoot of the optical output level due to a sudden change in the bias current is generated. It is possible to prevent an erroneous optical signal from being sent to the network side.

  While the principles of the invention have been illustrated and described in the preferred embodiments, it will be appreciated by those skilled in the art that the invention can be modified in arrangement and detail without departing from such principles. The present invention is not limited to the specific configuration disclosed in the present embodiment. We therefore claim all modifications and changes that come within the scope and spirit of the following claims.

  DESCRIPTION OF SYMBOLS 1 ... Optical transmission / reception module (optical transmitter), 3a, 3b ... Phase synchronous circuit (1st phase synchronous circuit), 3d ... Frame processing part (2nd phase synchronous circuit), 3e ... Multiplexing processing part, 5 ... Optical transmitter (optical transmitter circuit), 5a... Laser diode element, 5b... EA optical modulator, 7.

Claims (3)

A first phase synchronization circuit which receives a reference clock signal from the outside, generates and outputs a first clock signal based on the reference clock, and outputs a first alarm signal when the reference clock is not normal When,
An electrical input signal from the outside and the first clock signal from the first phase synchronization circuit are input, a second clock signal synchronized with the electrical input signal is generated, and the second clock signal is generated from the electrical input signal. After the data is read based on the second clock signal, the data is read based on the first clock signal, and when the second clock signal and the first clock signal are out of synchronization, A second phase-locked loop that outputs two alarm signals;
An optical transmission circuit that outputs an optical signal based on the data read from the second phase synchronization circuit;
When the first alarm signal or the second alarm signal is received and the first alarm signal or the second alarm signal is recovered after the control to cut off the optical signal when the first alarm signal or the second alarm signal is received. A control circuit for controlling to reset the second phase synchronization circuit after resetting the first phase synchronization circuit;
An optical transmitter comprising: The optical transmission circuit includes a laser diode element that generates an optical signal, and an optical modulator that modulates the optical signal,
The control circuit controls to cut off a drive current supplied to the laser diode element when the first alarm signal or the second alarm signal is received.
The optical transmitter according to claim 1. The control circuit, after controlling to cut off the drive current, after setting the drive signal to be applied to the laser diode element or the optical modulator to a predetermined set value for preventing over light emission, Control to turn on the drive current,
The optical transmitter according to claim 2.

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