JP2014143234A - Semiconductor device, and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a method of manufacturing the same, capable of suppressing impact ionization in an I/O transistor and reduction in ON breakdown voltage caused by the impact ionization.SOLUTION: A semiconductor device comprises: an n-type channel first transistor ITR configuring an input/output circuit; and an n-type channel second transistor CTR formed on a main surface and configuring a logic circuit. With respect to a source region or a drain region of the first transistor ITR, the maximum impurity concentration of a first n-type impurity region NR21 is higher than that of a second n-type impurity region NR22. With respect to a source region or a drain region of the second transistor CTR, the maximum impurity concentration of a third n-type impurity region NR1O is higher than that of a fourth n-type impurity region NR1X. The maximum impurity concentration of the first n-type impurity region NR21 is lower than that of the third n-type impurity region NR1O.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and can be suitably used particularly for a semiconductor device including a semiconductor element constituting an input / output circuit.

  As a semiconductor device incorporating a flash memory or a CPU (Central Processing Unit), for example, a microcomputer can be considered. This microcomputer generally has a configuration in which a number of MOS (Metal Oxide Semiconductor) transistors are formed on a semiconductor substrate.

  As MOS transistors formed on a semiconductor substrate of a microcomputer, for example, a core transistor used in a logic circuit such as a CPU or a memory, and an I / O transistor used in an input / output circuit electrically connected to another semiconductor device And are formed. A semiconductor device in which a plurality of types of transistors are formed on the same semiconductor substrate, such as the core transistor and the I / O transistor, is disclosed in, for example, Japanese Patent Application Laid-Open No. 11-163156 (Patent Document 1) and Japanese Patent Application Laid-Open No. 2006-186180. (Patent Document 2).

JP-A-11-163156 JP 2006-186180 A

  Due to the miniaturization of the MOS transistor, the electric field strength at the end of the drain region of the MOS transistor becomes excessively high, and a so-called short channel effect may occur. In order to suppress this, a so-called LDD (Lightly Doped Drain) region having an impurity concentration lower than that of the normal drain region may be formed not only in the core transistor but also in the I / O transistor at the end of the drain region.

  However, the inventors have found that there are the following problems when an LDD region is formed in an I / O transistor. Since a drain voltage higher than that of the core transistor is applied to the I / O transistor, when the gate length is shortened, a high electric field region is formed between the drain region having a high impurity concentration and the LDD region having a low impurity concentration. There arises a problem that the ON breakdown voltage is lowered. For example, when the n-type I / O transistor having a power supply voltage of 5 V is miniaturized and the gate length becomes 1 μm or less, the electric field strength at the end of the drain region of the n-type I / O transistor increases, and the normal drain The electric field strength at the boundary between the region (S / D region) and the surrounding LDD region is increased. Then, the on-breakdown voltage of the n-type I / O transistor decreases due to so-called impact ionization.

  In the semiconductor device disclosed in Japanese Patent Application Laid-Open No. 2006-186180, an n-type I / O transistor having an LDD region is disclosed, but the above problem and solution are not disclosed at all. In the semiconductor device disclosed in JP-A-11-163156, an LDD region is not formed in an electrostatic protection element corresponding to an I / O transistor.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, the semiconductor device includes an n-type channel first transistor constituting an input / output circuit and an n-type channel second transistor constituting a logic circuit. The source region or the drain region of the first transistor has a first n-type impurity region and a second n-type impurity region formed so as to surround the first n-type impurity region. The source region or the drain region of the second transistor has a third n-type impurity region. The maximum impurity concentration of the first n-type impurity region is higher than the maximum impurity concentration of the second n-type impurity region, and the maximum impurity concentration of the first n-type impurity region is the maximum impurity concentration of the third n-type impurity region. Lower than.

  According to another embodiment, a semiconductor device manufacturing method includes forming an n-type channel first transistor constituting an input / output circuit and an n-type channel second transistor constituting a logic circuit. . In the step of forming the first transistor, a first n-type impurity region and a second n-type impurity region formed so as to surround the first n-type impurity region are formed in the source region or the drain region. Process. The step of forming the second transistor includes a step of forming a third n-type impurity region in the source region or the drain region. The maximum impurity concentration of the first n-type impurity region is higher than the maximum impurity concentration of the second n-type impurity region, and the maximum impurity concentration of the first n-type impurity region is the maximum impurity concentration of the third n-type impurity region. Lower than.

  According to one embodiment, the on-breakdown voltage in the I / O transistor can be improved.

1 is a schematic plan view showing a state of a wafer, which is a semiconductor device according to a first embodiment. FIG. 2 is a schematic cross-sectional view showing a configuration of an n-type core transistor and an n-type I / O transistor that constitute the semiconductor device of the first embodiment. A graph (A) showing an impurity concentration distribution in the dotted line portion A applied to the drain region D of the core transistor CTR in FIG. 2, and an impurity in the dotted line portion B applied to the drain region D of the I / O transistor ITR in FIG. It is the graph (B) which shows density distribution. FIG. 6 is a schematic cross sectional view showing a first step of the method for manufacturing the semiconductor device in the first embodiment. FIG. 6 is a schematic cross sectional view showing a second step of the method for manufacturing the semiconductor device in the first embodiment. FIG. 7 is a schematic cross sectional view showing a third step of the method for manufacturing the semiconductor device in the first embodiment. FIG. 10 is a schematic cross sectional view showing a fourth step of the method for manufacturing the semiconductor device in the first embodiment. FIG. 10 is a schematic cross sectional view showing a fifth step of the method for manufacturing the semiconductor device in the first embodiment. It is a schematic sectional drawing which shows the 6th process of the manufacturing method of the semiconductor device in this Embodiment 1. It is a schematic sectional drawing which shows the 7th process of the manufacturing method of the semiconductor device in this Embodiment 1. It is a schematic sectional drawing which shows the 8th process of the manufacturing method of the semiconductor device in this Embodiment 1. It is a schematic sectional drawing which shows the 9th process of the manufacturing method of the semiconductor device in this Embodiment 1. It is a schematic sectional drawing which shows the 10th process of the manufacturing method of the semiconductor device in this Embodiment 1. It is a schematic sectional drawing which shows the 11th process of the manufacturing method of the semiconductor device in this Embodiment 1. It is a schematic sectional drawing which shows the 12th process of the manufacturing method of the semiconductor device in this Embodiment 1. It is a schematic sectional drawing which shows the structure of the n-type core transistor and n-type I / O transistor which comprise the semiconductor device of this Embodiment 2. FIG. 17 is a schematic sectional view collectively showing impurity regions including both arsenic and phosphorus in the n-type core transistor of FIG. 16. As a first example of the second embodiment, a graph (A) showing an impurity concentration distribution in a dotted line portion A applied to the drain region D of the core transistor CTR in FIG. 16, and a drain of the I / O transistor ITR in FIG. 17 is a graph (B) showing the impurity concentration distribution in the dotted line portion B applied to the region D (same as FIG. 3B) and a graph (C) showing the impurity concentration distribution in the dotted line portion C of FIG. . As a second example of the second embodiment, a graph (A) showing the impurity concentration distribution in the dotted line portion A applied to the drain region D of the core transistor CTR in FIG. The graph (B) is the same as 18 (B), and the graph (C) shows the impurity concentration distribution in the dotted line portion C of FIG. 16 and the total concentration of arsenic. FIG. 13 is a schematic cross-sectional view showing a step that follows the step shown in FIG. 12 in the method for manufacturing a semiconductor device in the second embodiment. FIG. 21 is a schematic cross-sectional view showing a step that follows the step shown in FIG. 20 in the method for manufacturing a semiconductor device in the second embodiment. FIG. 22 is a schematic cross-sectional view showing a step that follows the step shown in FIG. 21 in the method for manufacturing a semiconductor device according to the second embodiment. FIG. 23 is a schematic cross sectional view showing a step that follows the step shown in FIG. 22 in the method for manufacturing a semiconductor device according to the second embodiment. As a first example of the third embodiment, a graph (A) obtained by adding a scale with an impurity concentration of 1 × 10 ²⁰ cm ⁻³ to FIG. 19A and an impurity concentration of 1 × 10 ²⁰ cm in FIG. It is the graph (B) which added the scale of ^-3 . As a second example of the third embodiment, FIG. 3A is a graph (A) obtained by adding a scale of an impurity concentration of 1 × 10 ²⁰ cm ⁻³ , and FIG. 3B is an impurity concentration of 1 × 10 ²⁰ cm. It is the graph (B) which added the scale of ^-3 . The relationship between the gate length of an I / O transistor ITR having a maximum impurity concentration higher than 1 × 10 ²⁰ cm ⁻³ and the ON breakdown voltage, and the gate length of an I / O transistor ITR having a maximum impurity concentration of 1 × 10 ²⁰ cm ⁻³ or less. It is a graph which shows the relationship between ON pressure | voltage resistance. It is a schematic sectional drawing which shows the structure of the n-type core transistor and n-type I / O transistor which comprise the semiconductor device of this Embodiment 4. FIG. 28 is a schematic sectional view collectively showing impurity regions including both arsenic and phosphorus in the n-type core transistor of FIG. 27. As the fourth embodiment, a graph (A) showing the impurity concentration distribution in the dotted line portion A applied to the drain region D of the core transistor CTR in FIG. 27 and the drain region D of the I / O transistor ITR in FIG. 28 is a graph (B) showing the impurity concentration distribution in the dotted line portion B, and a graph (C) showing the impurity concentration distribution in the dotted line portion C of FIG. FIG. 22 is a schematic cross sectional view showing a step corresponding to the step shown in FIG. 13 and FIG. 21 of the method for manufacturing a semiconductor device in the fourth embodiment. As a first example of the fifth embodiment, a graph (A) showing an impurity concentration distribution in a dotted line portion A in FIG. 3A as a sum of concentrations of arsenic and phosphorus, and an I / O in FIG. 6 is a graph (B) showing an impurity concentration distribution of an O-transistor ITR as a sum of concentrations of arsenic and phosphorus. As a second example of the fifth embodiment, a graph (A) showing the impurity concentration distribution of FIG. 24A as a sum of concentrations of arsenic and phosphorus, and an impurity concentration distribution of FIG. A graph (B) showing the sum of the concentrations of arsenic and phosphorus, and a graph (C) showing the sum of the concentrations of arsenic and phosphorus by adding a scale as in FIG. . As a third example of the fifth embodiment, a graph (A) showing the impurity concentration distribution of FIG. 29A as a sum of concentrations of arsenic and phosphorus, and an impurity concentration distribution of FIG. A graph (B) showing the total concentration of arsenic and phosphorus, and a graph (C) showing the impurity concentration distribution of FIG. 29C by the total concentration of arsenic and phosphorus.

Hereinafter, the present embodiment will be described with reference to the drawings.
(Embodiment 1)
First, a semiconductor device in a wafer state will be described as this embodiment.

  Referring to FIG. 1, semiconductor device DEV of the present embodiment has a plurality of types of circuits formed on the main surface of semiconductor substrate SUB such as a semiconductor wafer. As an example, a circuit constituting the semiconductor device DEV includes a signal input / output circuit, a DA-AD converter, a power supply circuit, a CPU, a flash memory, and an SRAM (Static Random Access Memory).

  The role of each circuit constituting the semiconductor device DEV is as follows. First, in the signal input / output circuit, an electrical signal is input / output to / from a circuit arranged outside the semiconductor device DEV. In the DA-AD converter, an analog signal and a digital signal are converted. The power supply circuit supplies power necessary for driving the semiconductor device DEV and controls the power. In the CPU, a logical operation is performed by a logic circuit. Data is stored in the flash memory or the SRAM. A DRAM (Dynamic Random Access Memory) may be used instead of the SRAM.

  Each of these circuits is mainly composed of switching elements such as MOS transistors. The CPU, SRAM, etc. are composed of core transistors used for logic circuits. The signal input / output circuit, DA-AD converter, power supply circuit, flash memory, and the like are configured by I / O transistors used for the input / output circuit.

  The logic circuit operates with a power supply voltage of 0.5V to less than 2V, and the input / output circuit operates with a power supply voltage higher than the logic circuit, for example, 3V to 5V or less. Therefore, the maximum applied voltage between the source and drain of the I / O transistor is higher than the maximum applied voltage between the source and drain of the core transistor. Therefore, the withstand voltage between the source and the drain of the I / O transistor is higher than the withstand voltage between the source and the drain of the core transistor. In order to operate at high speed, the gate length of the core transistor is shorter than the gate length of the I / O transistor. For example, the gate length of the core transistor is 0.05 μm or more and 0.5 μm or less, and the gate length of the I / O transistor is greater than 0.5 μm and 2 μm or less.

FIG. 2 is a schematic cross-sectional view taken along the line II-II in FIG. This straddles the I / O transistor constituting the signal input / output circuit and the core transistor constituting the CPU. Therefore, in FIG. 2, the I / O transistor and the core transistor are in parallel. For example, the core transistor and the I / O transistor formed on the surface layer of the main surface on the semiconductor substrate SUB are partitioned by the element isolation film II. That is, it is preferable that the region where the core transistor is formed and the region where the I / O transistor is formed in the surface layer on the semiconductor substrate SUB are partitioned by the element isolation film II. The element isolation film II is preferably made of, for example, a silicon oxide film (SiO ₂ ).

  The semiconductor substrate SUB is preferably made of a single crystal of silicon, for example. The semiconductor substrate SS may be either n-type or p-type. However, in FIG. 2, the semiconductor substrate SS is an n-type semiconductor.

  Note that both an n-type transistor and a p-type transistor are actually arranged for both the core transistor and the I / O transistor. However, in this embodiment, the illustration of the p-type transistor is omitted, and only the n-type transistor is shown. That is, referring to FIG. 2, the semiconductor device DEV has an n-type core transistor region and an n-type I / O transistor region, and the core transistor CTR (first transistor of the n-type channel) is included in the n-type core transistor region. However, an I / O transistor ITR (n-type channel second transistor) is arranged in the n-type I / O transistor region. Here, the n-type channel indicates that carriers are electrons when an inversion layer is formed under the gate by applying a gate voltage.

  The n-type channel core transistor CTR and the I / O transistor ITR are formed in the p-type well region PWR formed in the surface layer of the semiconductor substrate SUB. The p-type well region PWR is formed by ion implantation of boron (B), for example.

  The core transistor CTR includes a source region S composed of an n-type impurity region NR11 (third n-type impurity region), a drain region D composed of an n-type impurity region NR11 (third n-type impurity region), and a gate insulating film. GI and a gate structure G composed of a gate conductive film GE and a sidewall insulating film SW. N-type impurity region NR11 is formed by ion implantation of arsenic, for example. The gate structure G includes a gate (gate conductive film GE) for applying a voltage used for on / off control of the transistor. The source region S and the drain region D are arranged on the surface layer of the semiconductor substrate SUB at a distance from each other. A gate conductive film GE is formed on the surface of the semiconductor substrate SUB sandwiched between the pair of source region S and drain region D via a gate insulating film GI.

  The source region S and the drain region D of the I / O transistor ITR are an n-type impurity region NR21 (first n-type impurity region) and a low-concentration n-type impurity region NR22 (second n-type) formed so as to surround it. Type impurity region). First, phosphorus (P) is ion-implanted into the low-concentration n-type impurity region NR22 and the n-type impurity region NR21, and then arsenic (As) is ion-implanted only into the n-type impurity region NR21. A drain region D is formed. Therefore, the n-type impurity region NR21 is doped with arsenic and phosphorus.

  It is preferable that the maximum impurity concentration of phosphorus in the low-concentration n-type impurity region NR22 is lower than the maximum impurity concentration of arsenic in the n-type impurity region NR21. Here, the low-concentration n-type impurity region NR22 forms a so-called LDD region.

  In each of the core transistor CTR and the I / O transistor ITR, the gate structure G includes a gate conductive film GE formed so as to cover the gate insulating film GI, and sidewall insulating covering the gate insulating film GI and the side walls of the gate conductive film GE. It consists of a film SW. The gate insulating film GI is made of, for example, a silicon oxide film, and the gate conductive film GE is made of, for example, polycrystalline silicon. Sidewall insulating film SW is made of, for example, a silicon oxide film, but may be composed of a combination of a silicon oxide film and a silicon nitride film.

  The film thickness of the gate insulating film GI of the I / O transistor ITR may be the same as the gate insulating film GI of the core transistor CTR, but from the viewpoint of gate breakdown voltage, the film of the gate insulating film GI of the I / O transistor ITR The thickness is preferably larger than the thickness of the gate insulating film GI of the core transistor CTR.

  During driving, for example, a voltage in the range of 1.0 V to 1.8 V is applied to the gate (gate conductive film GE) of the core transistor, and a maximum of 5 V is applied to the gate (gate conductive film GE) of the I / O transistor. A voltage is applied. During the burn-in operation, a voltage of 7 V may be applied to the I / O transistor.

  Further, in both the core transistor CTR and the I / O transistor ITR, a silicide SC is formed on the n-type impurity regions NR11 and NR21 and the gate conductive film GE. The silicide SC is a metal-containing layer formed by reacting silicon or polycrystalline silicon with cobalt (Co) or nickel (Ni), such as the n-type impurity regions NR11 and 21 and the surface of the gate conductive film GE.

  In the present embodiment, the maximum impurity concentration in n-type impurity region NR21 of I / O transistor ITR is lower than the maximum impurity concentration in n-type impurity region NR11 of core transistor CTR. This will be described below.

  Referring to FIGS. 3A and 3B, the horizontal axis of FIG. 3A is a dotted line portion that passes through the portion where the concentration of arsenic is maximum, applied to the drain region D of the core transistor CTR of FIG. A position on A is shown, and a horizontal position on the horizontal axis corresponds to a horizontal position (expressed as X position in the figure) on the dotted line A in FIG. The vertical axis in FIG. 3A indicates the type of impurity and its concentration (not considering the silicide SC) at each position on a logarithmic scale. Similarly to the above, the horizontal axis of FIG. 3B is the position (X on the dotted line B passing through the portion where the concentration of arsenic or phosphorus is maximum, which is applied to the drain region D of the I / O transistor ITR of FIG. The vertical axis of FIG. 3B indicates the type and concentration of impurities at each of the above positions on a logarithmic scale.

3A and 3B, the maximum impurity concentration b of arsenic (As) in the n-type impurity region NR21 constituting the drain region D of the I / O transistor ITR is the drain region D of the core transistor CTR. Is lower than the maximum impurity concentration a of arsenic in the n-type impurity region NR11 constituting n. For example, the concentration b is 1 × 10 ²⁰ cm ⁻³ or less, and the concentration a is preferably higher than 1 × 10 ²⁰ cm ⁻³ . Thus, since the maximum impurity concentration of the n-type impurity region NR21 of the I / O transistor ITR is lower than the maximum impurity concentration of the n-type impurity region NR11 of the n-type core transistor CTR, the I / O transistor ITR The electric field strength in the vicinity of n-type impurity region NR21 can be suppressed.

  Here, in the present embodiment, the maximum impurity concentration (maximum concentration) of the n-type impurity region NR21 refers to the maximum impurity concentration of arsenic in the n-type impurity region NR21.

Further, as described above, the maximum impurity concentration b of arsenic in the n-type impurity region NR21 constituting the drain region D of the I / O transistor ITR is the low concentration n-type impurity region constituting the drain region D of the I / O transistor ITR. It is higher than the maximum impurity concentration c1 of phosphorus (indicated by P) in NR22. For example, the concentration b can be larger than 1 × 10 ¹⁹ cm ^{−3 and} smaller than 1 × 10 ²⁰ cm ⁻³ , and the concentration c1 can be 1 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ¹⁹ cm ⁻³ or less. be able to. As described above, since the low-concentration n-type impurity region NR22 having a lower maximum impurity concentration than the n-type impurity region NR21 is provided, the electric field strength at the end of the drain region D is relaxed, and the impact ionization of the I / O transistor ITR is performed. In addition, it is possible to suppress a decrease in ON breakdown voltage.

  In particular, in the present embodiment, the maximum impurity concentration of the n-type impurity region NR21 of the I / O transistor ITR is made lower than the maximum impurity concentration of the n-type impurity region NR11 of the core transistor CTR, and the I / O transistor ITR The maximum impurity concentration of the n-type impurity region NR22 is set lower than the maximum impurity concentration of the n-type impurity region NR21. Therefore, the difference between the impurity concentration of the n-type impurity region NR21 and the impurity concentration of the n-type impurity region NR22 can be reduced while forming the low-concentration n-type impurity region NR22. As a result, the electric field strength at the interface between the n-type impurity region NR21 and the n-type impurity region NR22 can be reduced while the electric field at the end of the drain region is suppressed by the low-concentration n-type impurity region NR22. The breakdown voltage can be improved.

  In this embodiment, the n-type impurity regions NR11, NR21, and NR22 are formed as described above for the n-type channel I / O transistor ITR and the n-type channel core transistor CTR. Since the hole mobility is low in the p-type channel transistor, the above-described on-breakdown voltage problem seen in the n-type channel transistor does not occur.

  The maximum impurity concentration c in the n-type impurity region NR21 of phosphorus constituting the low-concentration n-type impurity region NR22 is higher than the maximum impurity concentration c1 in the low-concentration n-type impurity region NR22. Is low.

  Further, at the boundary between the two regions of the n-type impurity region NR21 and the low-concentration n-type impurity region NR22, the concentration indicated by the curve 21 is 0 from FIG. 3B, and arsenic is present in the n-type impurity region NR21. It can be seen that the lightly doped n-type impurity region NR22 is not doped with arsenic. Thus, since the gradient of the impurity concentration is discontinuous at the boundary between the two regions, it can be determined that the region has two regions. Here, the inclination is the inclination of the change in the vertical axis (concentration) with respect to the change in the horizontal axis (position) in the impurity concentration graph shown in FIG. The slope of the impurity concentration is discontinuous. Specifically, the amount of change (rate of change) of the impurity concentration in the direction intersecting the boundary in the vicinity of the boundary between NR21 and NR22 is compared with other regions. Means that it changes suddenly.

  Next, a method for manufacturing the semiconductor device DEV of the present embodiment will be described with reference to FIGS. 4 to 15, the manufacturing method in which one transistor is arranged in each of the n-type core transistor region and the n-type I / O transistor region is described. However, a plurality of transistors are arranged in each case. Also good.

  Referring to FIG. 4, first, a semiconductor substrate SUB is prepared. The semiconductor substrate SUB is preferably an n-type silicon single crystal substrate, for example. A pad oxide film PI and a silicon nitride film SN are sequentially formed on one (upper) main surface of the semiconductor substrate SUB by using, for example, a CVD (Chemical Vapor Deposition) method.

  Pad oxide film PI is made of, for example, a silicon oxide film. Moreover, the thickness shall be 5 to 20 nm. Silicon nitride film SN is made of, for example, silicon nitride (SiN). Moreover, the thickness is about 100 nm, for example, it is preferable to set it as 70 nm or more and 150 nm or less.

  Next, after the photoresist PHR is formed, the photoresist PHR is patterned using photolithography. The pad oxide film PI and the silicon nitride film SN are etched using the patterned photoresist PHR as a mask. Here, the pad oxide film PI and the silicon nitride film SN immediately above a region where two different adjacent regions such as a boundary portion between the n-type core transistor region and the n-type I / O transistor region are desired to be separated are removed. Then, the pad oxide film PI and the silicon nitride film SN are etched.

  As shown in FIG. 5, a trench TR is further formed in the semiconductor substrate SUB. The depth of the trench TR is, for example, not less than 200 nm and not more than 300 nm. Next, the photoresist PHR is removed, the trench TR is buried, and a silicon oxide film II covering the silicon nitride film SN is formed by a CVD method or the like. The thickness of the silicon oxide film II is about 500 nm, and preferably 400 nm or more and 600 nm or less.

  Referring to FIG. 6, next, silicon oxide film II is ground by CMP (Chemical Mechanical Polishing) using silicon nitride film SN as a stopper. In this way, an element isolation film II that electrically isolates adjacent transistor regions is formed.

  Referring to FIG. 7, first, silicon nitride film SN is removed, for example, by wet etching. Next, patterning is performed using a normal photolithography technique. Specifically, first, a pattern of photoresist PHR having an opening in a region where the p-type well region PWR is to be formed in the n-type core transistor region and the n-type I / O transistor region is formed. Next, using the pattern of the photoresist PHR as a photomask, p-type impurities such as boron are ion-implanted from the direction (vertical direction in the figure) substantially right above the surface of the semiconductor substrate SUB from above the pad oxide film PI. Is done. Thereby, a p-type well region PWR made of boron is formed.

In the above ion implantation technique, it is preferable that the energy of the implanted boron is as follows. As a first stage, boron is ion-implanted while applying energy of several hundred keV, for example, 100 keV or more and 500 keV or less. At this time, for example, boron is preferably ion-implanted with a dose (surface density) of 1 × 10 ¹² cm ⁻² or more and 5 × 10 ¹³ cm ⁻² or less in plan view. Next, as a second stage, boron is ion-implanted while applying energy of several tens keV, for example, 10 keV or more and 50 keV or less. At this time, for example, boron is preferably implanted at a dose of 1 × 10 ¹¹ cm ⁻² or more and 5 × 10 ¹² cm ⁻² or less in plan view.

Although not shown, for regions where p-type core transistors and I / O transistors are to be formed, a photoresist PHR having an opening in the region is formed in the same manner as described above, and then phosphorus and arsenic are formed directly above the region. Are similarly implanted. Specifically, as the first stage, phosphorus is ion-implanted while applying energy of several hundred keV, for example, 100 keV or more and 500 keV or less. At this time, for example, phosphorus is preferably ion-implanted at a dose of 1 × 10 ¹² cm ⁻² or more and 5 × 10 ¹³ cm ⁻² or less in plan view. Next, as a second stage, arsenic is ion-implanted while applying energy of several tens keV, for example, 10 keV to 50 keV. At this time, it is preferable that arsenic is ion-implanted, for example, at a dose of 1 × 10 ¹¹ cm ⁻² or more and 5 × 10 ¹² cm ⁻² or less in plan view.

Referring to FIG. 8, only the n-type core transistor region is additionally ion-implanted. Specifically, using the photoresist PHR with the p-type well region PWR in the n-type core transistor region as an opening, p-type impurities such as boron are converted into the p-type in the n-type core transistor region as in the step of FIG. Implanted into the well region PWR (channel implantation). At this time, the energy of boron to be ion-implanted is preferably several tens keV, for example, 10 keV or more and 20 keV or less. Boron has a dose of 1 × 10 ¹² cm ⁻² or more and 5 × 10 ¹³ cm ⁻² or less, for example, in plan view. It is preferred that the ions be implanted in a quantity.

Although not shown, additional ion implantation is similarly performed on the p-type core transistor region. Specifically, n-type impurities such as arsenic are channel-implanted as in the step of FIG. The energy of arsenic implanted at this time is preferably several tens keV, for example, 10 keV or more and 50 keV or less, and arsenic has a dose amount of 1 × 10 ¹² cm ⁻² or more and 5 × 10 ¹³ cm ⁻² or less in plan view, for example. Is preferably injected.

  Referring to FIG. 9, first, pad oxide film PI is removed by, eg, wet etching. After removing pad oxide film PI, gate insulating film GI is formed on the entire surface of semiconductor substrate SUB using, for example, a thermal oxidation method. The gate insulating film GI is preferably formed to have a thickness of several tens nm, for example, 5 nm to 20 nm. The gate insulating film GI is preferably made of, for example, a silicon oxide film. After the formation of the gate insulating film GI, only the gate insulating film GI in the n-type core transistor region is removed by wet etching, and a gate insulating film GI thinner than the gate insulating film GI in the n-type I / O transistor region is formed. The gate insulating film GI in the n-type core transistor region is preferably formed to have a thickness of several nm, for example, 1 nm to 3 nm. Similar processing is performed for the p-type transistor region.

Referring to FIG. 10, a polycrystalline silicon thin film is formed by, for example, a CVD method so as to cover the entire surface of gate insulating film GI. Next, ions are implanted into the polycrystalline silicon thin film. Specifically, in the n-type core transistor region and the n-type I / O transistor region, an n-type impurity such as phosphorus has an energy of several keV to several tens keV (for example, 1 keV to 50 keV), and 1 × in plan view Ions are implanted at a dose of 10 ¹⁵ cm ⁻² or more and 5 × 10 ¹⁵ cm ⁻² or less. In a p-type transistor region not shown, a p-type impurity such as boron has an energy of several keV (1 keV or more and 5 keV or less) and a dose of 1 × 10 ¹⁵ cm ⁻² or more and 5 × 10 ¹⁵ cm ⁻² or less in plan view. Ion implanted in quantity. Thereafter, the pattern of the gate conductive film GE is formed by performing a normal photolithography technique and etching on the polycrystalline silicon thin film.

Referring to FIG. 11, impurities for forming n-type impurity region NR11 to be the source region and drain region of the n-type core transistor region are ion-implanted. Here, for example, arsenic is preferably ion-implanted with an energy of 1 keV to 20 keV and a dose of 5 × 10 ¹³ cm ^{−2 to} 1 × 10 ¹⁵ cm ⁻² in plan view.

Although not shown, ion implantation is performed to form p-type impurity regions (S / D or LDD) to be the source region and drain region of the p-type core transistor region. Specifically, boron fluoride (BF ₂ ) or the like is ion-implanted with an energy of, for example, 1 keV or more and 20 keV or less with a dose amount of 5 × 10 ¹³ cm ⁻² or more and 1 × 10 ¹⁵ cm ⁻² or less in plan view. The Further, ion implantation for forming a p-type impurity region (S / D or LDD) in the p-type I / O transistor region is performed. Specifically, boron or the like is ion-implanted with an energy of, for example, 1 keV or more and 20 keV or less at a dose of 5 × 10 ¹² cm ⁻² or more and 1 × 10 ¹⁴ cm ⁻² or less in plan view.

  Referring to FIG. 12, gate insulating film GI is patterned to remain only under gate conductive film GE, for example, using gate conductive film GE as a photomask. Note that immediately after the gate conductive film GE is patterned after the step of FIG. 10, the gate insulating film GI may be patterned using the gate conductive film GE as a photomask.

  Next, in each of the n-type core transistor region, the n-type I / O transistor region, and the p-type transistor region, a sidewall insulating film SW is formed so as to cover the upper side surface of the gate conductive film GE and the side surface of the gate insulating film GI. G is formed.

Next, impurities for forming a p-type impurity region (S / D region) to be a source region and a drain region of a p-type I / O transistor region (not shown) are ion-implanted. Specifically, boron fluoride (BF ₂ ) or the like is ion-implanted, for example, with an energy of 1 keV or more and 50 keV or less and a dose of 5 × 10 ¹³ cm ⁻² or more and 1 × 10 ¹⁵ cm ⁻² or less in plan view. Thereafter, boron or the like is ion-implanted with an energy of, for example, 1 keV or more and 50 keV or less with a dose amount of 1 × 10 ¹³ cm ⁻² or more and 1 × 10 ¹⁴ cm ⁻² or less in plan view.

Referring to FIG. 13, ion implantation is performed to form n-type impurity regions (LDD region and S / D region) to be the source region and drain region of the n-type I / O transistor region. Specifically, first, in order to form the S / D region (n-type impurity region NR21), arsenic or the like has an energy of 10 keV or more and 50 keV or less, for example, 5 × 10 ¹³ cm ⁻² or more and 1 × 10 5 in plan view. Ions are implanted with a dose of ¹⁵ cm ^-2 or less. The ion implantation at this time is preferably performed by irradiating from 0 ° to 7 ° with respect to a direction perpendicular to the surface of the semiconductor substrate SUB (vertical direction in FIG. 13). Next, in order to form an LDD region (low-concentration n-type impurity region NR22), phosphorus or the like has an energy of, for example, 10 keV or more and 50 keV or less, and is 1 × 10 ¹³ cm ⁻² or more and 1 × 10 ¹⁴ cm ^{−2 in} plan view. Ions are implanted with the following dose. The ion implantation at this time is preferably performed by irradiation from a direction of 30 degrees or more and 60 degrees or less with respect to a direction perpendicular to the surface of the semiconductor substrate SUB. In this way, as shown in FIG. 13, the low-concentration n-type impurity is reached so as to reach a region (inner side) closer to the gate structure G than the n-type impurity region NR21, such as a region immediately below the sidewall insulating film SW. Region NR22 can be formed.

  13, the maximum impurity concentration of the n-type impurity region NR21 is higher than the maximum impurity concentration of the low-concentration n-type impurity region NR22, and the maximum impurity concentration of the n-type impurity region NR21 is n-type impurity region NR11. The n-type impurity regions NR21 and NR22 can be formed so as to be lower than the maximum impurity concentration.

  Referring to FIG. 14, the entire semiconductor substrate SUB formed in each of the above steps is heat-treated at about 1000 ° C., thereby activating the formed n-type impurity regions NR11, NR21, NR22 to have a desired shape. A stable region having

  Referring to FIG. 15, a metal thin film MLL is formed by, for example, a normal sputtering method so as to cover the upper surfaces of the impurity regions NR11, NR21, NR22 and the upper surface of the gate structure G (gate conductive film GE). The Here, for example, it is formed by depositing cobalt (Co) at a thickness of several nm to several tens of nm. Further, for example, nickel (Ni) may be formed instead of cobalt.

  Thereafter, the entire semiconductor substrate SUB formed in each of the above steps is heat-treated at several hundred degrees Celsius. By this treatment, the silicon atoms constituting the impurity regions NR11, NR21, NR22 and the gate conductive film GE react with the cobalt or nickel atoms of the metal thin film MLL thereon to form the silicide SC. The metal thin film MLL formed in regions other than the source region S, drain region D, and gate conductive film GE is removed by normal wet etching. Through the above steps, the semiconductor device DEV having the core transistor CTR and the I / O transistor ITR shown in FIG. 2 is formed.

Next, the function and effect of this embodiment will be described.
For example, if the maximum impurity concentration of the impurity region is known, the distribution of the impurity concentration of the entire impurity region is generally generalized. Specifically, for example, when comparing the impurity region A having a maximum impurity concentration with the impurity region B having a maximum impurity concentration smaller than the impurity region A, generally the impurity region A is generally larger than the impurity region B. It can be said that the impurity concentration increases. For this reason, if the size of the maximum impurity concentration of each impurity region is compared as described above, the size of the impurity concentration of each impurity region can be compared. In the following, based on this premise, the operational effects of the present embodiment will be described.

  Therefore, if the concentration b in FIG. 3 is lower than the concentration a and higher than the concentrations c and c1 as in the present embodiment, for example, the concentrations a, c and c1 are the same as in FIG. 3, but the concentration b is equal to the concentration a. Compared with the case, the electric field strength at the boundary part (curve 21 part of FIG. 2) between the n-type impurity regions NR21 and NR22 can be lowered. This is because by reducing the maximum impurity concentration b of the n-type impurity region NR21, the impurity concentration of the entire n-type impurity region NR21 is lowered, and the overall impurity concentration of the n-type impurity region NR21 and the low-concentration n-type impurity region NR22 is reduced. This is because the difference is reduced.

The core transistor CTR is a transistor having a central role in the semiconductor device. Therefore, when the impurity concentration of the n-type impurity region NR11 of the core transistor CTR is lowered, the current at the time of driving the core transistor CTR is lowered, and the performance of the transistor may be lowered. Specifically, the maximum impurity concentration a (see FIG. 3A) of the n-type impurity region NR11 is preferably higher than 1 × 10 ²⁰ cm ⁻³ . However, since the I / O transistor ITR is an input / output circuit transistor, even if the impurity concentration of the n-type impurity region NR21, which is the S / D region, is slightly reduced, the performance of the semiconductor device DEV is not greatly affected. For this reason, the I / O transistor ITR can reduce the n-type impurity concentration to such an extent that its performance is not deteriorated.

  Therefore, as described above, the impurity concentration of the n-type impurity region NR21 is changed (lower than the impurity concentration of the n-type impurity region NR11). Then, even if a particularly high electric field strength is generated at the end of the drain region D of the I / O transistor having a higher power supply voltage than the core transistor as described above, due to the miniaturization of the transistor, the electric field strength at the boundary portion 21 is increased. Can be reduced. Therefore, impact ionization in which electrons as carriers generate electrons or holes can be suppressed. As a result, it is possible to suppress a decrease in ON breakdown voltage and to improve a hot carrier life. Therefore, miniaturization of the transistor can be promoted without any problem, and the circuit area of the n-type I / O transistor region can be reduced.

  The above-described problem of lowering the on-breakdown voltage occurs in an n-type MOS transistor using electrons as carriers and hardly occurs in a p-type MOS transistor using holes as carriers. This is because the mobility of holes is considerably smaller than that of electrons. Therefore, it is necessary to take the above-mentioned measures for the n-type I / O transistor ITR.

(Embodiment 2)
This embodiment differs from the first embodiment in the configuration of the core transistor CTR. Hereinafter, the configuration of the semiconductor device of the present embodiment will be described with reference to FIG.

  FIG. 16 corresponds to the schematic cross-sectional view of the second embodiment shown in FIG. 2 of the first embodiment. Referring to FIGS. 16 and 2, in the present embodiment, source region S and drain region D of core transistor CTR are n-type impurity regions NR12, NR13, NR14 (third n-type impurity region) and low Consist of n-type impurity regions NR11 and NR15 (fourth n-type impurity region).

  Referring to FIG. 16, low-concentration n-type impurity region NR11 is formed by ion implantation of, for example, arsenic using curve 11 as a boundary portion, and n-type impurity region NR12 is formed of, for example, phosphorus by ion implantation using curve 12 as a boundary portion. Is formed. N-type impurity region NR13 is formed by ion implantation of arsenic, for example, with curve 13 as the boundary. The n-type impurity region NR14 is a region generally sandwiched between the curves 11 and 13, and the low-concentration n-type impurity region NR15 is a region generally sandwiched between the curves 12 and 13. Therefore, in this case, the low-concentration n-type impurity region NR11 is doped only with arsenic, the n-type impurity regions NR12, 13, and 14 are doped with both arsenic and phosphorus, and the low-concentration n-type impurity region NR15 is doped with only phosphorus. Will be.

  Referring to FIGS. 16 and 17, since n-type impurity regions NR12, NR13, and NR14 are all doped with both arsenic and phosphorous, they are collectively bounded by curve 13 (1O) in FIG. It can be considered as an n-type impurity region NR1O (third n-type impurity region) serving as a part. On the other hand, the n-type impurity region NR11 is a region where the n-type impurity region NR13 is excluded from the region having the curve 11 as a boundary here, and only the arsenic is doped, and the low-concentration n-type impurity region NR15 is doped only with phosphorus. . For this reason, the regions NR11 and NR15 are combined, and only one of arsenic and phosphorus is doped, and the low concentration n-type impurity region NR1X (fourth n-type impurity region) having a lower impurity concentration than the n-type impurity region NR1O. ). The low concentration n-type impurity region NR1X has a curve 12 (1X) in FIG.

  The low-concentration n-type impurity region NR22 is formed deeper than the low-concentration n-type impurity region NR1X (low-concentration n-type impurity region NR15).

  The low-concentration n-type impurity region NR1X is formed so as to substantially surround the n-type impurity region NR1O from below. The maximum impurity concentration of, for example, arsenic in n-type impurity region NR1O is preferably higher than the maximum impurity concentration of, for example, arsenic (phosphorus) in low-concentration n-type impurity region NR1X. The n-type impurity region NR1O is formed as a so-called S / D region, and the low-concentration n-type impurity region NR15 is formed as a so-called LDD region.

  In the present embodiment, the maximum impurity concentration in n-type impurity region NR21 of I / O transistor ITR is lower than the maximum impurity concentration in n-type impurity region NR1O of core transistor CTR. This will be described below.

  18A, 18B, 19A, and 19B, the horizontal axis and the vertical axis are the same coordinates as in FIGS. 3A and 3B, and the horizontal axis in FIGS. The positions on the dotted lines A and B (X position) are shown. On the other hand, in FIGS. 18C and 19C, the vertical axis is the same coordinate as in FIGS. 3A and 3B, but the horizontal axis is on the dotted line portion C in FIGS. A position (expressed as Y position in the figure) corresponding to the position in the vertical direction is shown. Here, the dotted lines A, B, and C in FIGS. 16 and 17 pass through the point where the concentration of arsenic or phosphorus is maximum.

  18A to 18C, the maximum impurity concentration b of arsenic in n-type impurity region NR21 constituting drain region D of I / O transistor ITR constitutes drain region D of core transistor CTR. It is lower than the maximum impurity concentration e, a of arsenic in the n-type impurity region NR13 (n-type impurity region NR1O).

The concentration e is the maximum impurity concentration for forming an impurity region of arsenic with the curve 13 in FIG. 16 (curve 13 (1O) in FIG. 17) as the boundary, and the concentration a has the curve 11 in FIG. 16 as the boundary. This is the maximum impurity concentration for forming an arsenic impurity region. As shown in FIG. 18A, the maximum impurity concentration e doped to form the n-type impurity region having the curve 13 (curve 10) as the boundary is n-type having the curve 11 as the boundary. It is higher than the maximum impurity concentration a that is doped to form the impurity region. FIGS. 18A and 18B show that the maximum impurity concentration b doped for forming the n-type impurity region having the curve 21 as a boundary is lower than both e and a. For example, the concentration b can be 1 × 10 ²⁰ cm ⁻³ or less, and the concentrations e and a can be higher than 1 × 10 ²⁰ cm ⁻³ .

  In this embodiment, the maximum impurity concentration of phosphorus in both the low concentration n-type impurity region NR15 (NR1X) of the core transistor CTR and the low concentration n-type impurity region NR22 of the I / O transistor ITR is c1 (FIG. 18). , 19) (c1 is lower than the maximum impurity concentration in the region NR1O, 21 (both are substantially equal to c)). The maximum impurity concentration of arsenic in the low-concentration n-type impurity region NR11 (NR1X) of the core transistor CTR is a1, which is lower than the maximum impurity concentration a of arsenic in the n-type impurity region NR13 (NR1O).

  Referring to FIGS. 19A to 19C, the maximum impurity concentration b of arsenic in n-type impurity region NR21 constituting drain region D of I / O transistor ITR constitutes drain region D of core transistor CTR. It is lower than the maximum impurity concentration f of arsenic in the n-type impurity region NR13 (n-type impurity region NR1O). The above f (indicated by As-T) forms the maximum impurity concentration e doped to form the n-type impurity region with the curve 13 as the boundary and the n-type impurity region with the curve 11 as the boundary. Therefore, it is the sum of the maximum impurity concentration a to be doped. That is, the curve As-T in FIG. 19A represents the sum of the curve 13As (the arsenic concentration distribution with the curve 13 as a boundary) and the curve 11As (the arsenic concentration distribution with the curve 13 as a boundary). For this reason, for example, the region where only arsenic of the curve 13 exists such as the region NR14 overlaps with the curve 13As, and for example, the region where the arsenic of the curve 13 and the arsenic of the curve 11 exist such as the region NR15. The sum of the values indicated by.

When the finished product is verified, the total amount f of impurities shown in FIG. 19 can be analyzed, and this value is preferably higher than b. For example, the concentration b can be 1 × 10 ²⁰ cm ⁻³ or less, and the concentration f can be higher than 1 × 10 ²⁰ cm ⁻³ .

  In FIGS. 19A and 19B, each of the concentrations e and a is higher than the concentration b, and as a result, the concentration f is higher than the concentration b. However, each of the concentrations e and a (or one of them) may be lower than the concentration b, and the total concentration f may be higher than the concentration b.

  As described above, in the present embodiment, the maximum impurity concentration (maximum concentration) of the n-type impurity regions NR1O and NR21 refers to the maximum impurity concentration of arsenic in the n-type impurity regions NR1O and NR21. The maximum impurity concentration (maximum concentration) of the low-concentration n-type impurity region NR1X is the maximum impurity concentration a1 of arsenic in the low-concentration n-type impurity region NR11 constituting the low-concentration n-type impurity region NR1X or the low-concentration n-type impurity region. It represents the maximum impurity concentration c1 of phosphorus of NR15.

  At the boundary between the two regions of the n-type impurity region 1O and the low-concentration n-type impurity region 1X, the concentration indicated by the curve 12 from FIG. 19A and the concentration indicated by the curve 13 from FIG. , 0 respectively. In FIG. 19A, n-type impurity region 1O is doped with phosphorus, and low-concentration n-type impurity region 1X is not doped with phosphorus. In FIG. 19B, arsenic is doped in the n-type impurity region NR21, and arsenic is not doped in the low-concentration n-type impurity region NR22. In FIG. 19C, arsenic is doped in the n-type impurity region 1O, and arsenic is not doped in the low-concentration n-type impurity region 1X. As described above, since the gradient of the impurity concentration is discontinuous in at least one of the boundaries between the two regions shown in FIGS. 19A, 19B, and 19C, the region has two regions. Can be determined.

  Next, a method for manufacturing the semiconductor device DEV of the present embodiment will be described with reference to FIGS.

Referring to FIG. 20, after processing similar to that in FIGS. 4 to 12 of the first embodiment is performed, ion implantation for forming n-type impurity regions NR12 to NR15 in the n-type core transistor region is performed. Specifically, an n-type impurity such as arsenic first has an energy of several keV to several tens keV (for example, 1 keV to 50 keV), and is 3 × 10 ¹⁴ cm ^{−2 to} 3 × 10 ¹⁵ cm ^{−2 in} plan view. Ion implantation is preferably performed with the following dose. Thereby, an impurity region (S / D region) having the curve 13 as a boundary is formed. Next, an n-type impurity such as phosphorus has an energy of several keV to several tens keV (for example, 1 keV to 50 keV), and a dose amount of 5 × 10 ¹² cm ^{−2 to} 1 × 10 ¹⁴ cm ⁻² in plan view. It is preferable that ion implantation is performed. As a result, a phosphorus LDD region (such as the low-concentration impurity region NR15) having the curve 12 as a boundary is formed.

  Since the sidewall insulating film SW is formed in the step of FIG. 12, the n-type impurity region NR12 and the like are less likely to enter the inner side (side closer to the gate structure G in the drawing) than the n-type impurity region NR11.

Next, ion implantation for forming a p-type impurity region (S / D or LDD) of a p-type core transistor region and an I / O transistor region (not shown) is simultaneously performed. Specifically, first, a p-type impurity such as boron fluoride is ion-implanted with an energy of, for example, 1 keV or more and 50 keV or less and a dose amount of 3 × 10 ¹⁴ cm ⁻² or more and 3 × 10 ¹⁵ cm ⁻² or less in plan view. Thereafter, a p-type impurity such as boron is ion-implanted with an energy of 1 keV to 50 keV, for example, at a dose of 5 × 10 ¹² cm ^{−2 to} 1 × 10 ¹⁴ cm ⁻² in plan view.

  Referring to FIGS. 21 to 23, after the step of FIG. 20, the same processing as in FIGS. 13 to 15 is performed. The low-concentration n-type impurity region NR22 is formed so as to be deeper than the low-concentration n-type impurity region NR15 (NR1X).

  20 to 23, the maximum impurity concentration of arsenic in n-type impurity region NR1O is lower than the maximum impurity concentration of arsenic in n-type impurity region NR1O, and the maximum impurity concentration of n-type impurity region NR1O is increased. The n-type impurity regions NR1O and NR1X are formed so as to be higher than the maximum impurity concentration of the low-concentration n-type impurity region 1X. Further, both the low concentration n-type impurity region NR22 and the low concentration n-type impurity region NR15 (NR1X) are formed so that the maximum impurity concentration of phosphorus is substantially equal.

Next, the function and effect of this embodiment will be described.
If the concentration b is set lower than the concentrations e and a as in the present embodiment, for example, the concentrations a, e, and c are the same as in the present embodiment, but the concentration b is not lower than the concentrations e and a (the concentration b is Compared with the case where the concentrations are equal to e and a), the electric field strength at the boundary between the n-type impurity regions NR21 and NR22 can be reduced, and the same effect as in the first embodiment can be obtained.

  In particular, when the maximum impurity concentration c1 of phosphorus in the LDD region is equal in both the transistors CTR and ITR, the difference in overall impurity concentration between the n-type impurity region NR21 and the low-concentration n-type impurity region NR22 is n-type impurity. The difference is smaller than the overall impurity concentration difference between the region NR1O and the low-concentration n-type impurity region NR15. In this way, there is an effect that the electric field strength at the boundary between the n-type impurity regions NR21 and NR22 is more reliably reduced.

However, in the present embodiment, the concentration c1 (maximum phosphorus concentration in the low-concentration n-type impurity regions NR22 and NR15: about 1 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ¹⁹ cm ⁻³ or less) Compared to the concentration of arsenic in the impurity regions NR1O and NR21 (a level slightly lower than 1 × 10 ²⁰ cm ⁻³ ), it is sufficiently small to be ignored. Therefore, even if the impurity concentration of phosphorus in the low-concentration n-type impurity region NR22 and the low-concentration n-type impurity region NR15 is not equal, if the arsenic concentration is as described above, the above effect is usually obtained. Play.

  Further, as described above, the low-concentration n-type impurity region NR22 is formed deeper than the low-concentration n-type impurity region NR1X (low-concentration n-type impurity region NR15). Therefore, even if a high source / drain voltage is applied to the I / O transistor ITR, it is formed under the silicide SC formed on the surface of the low-concentration n-type impurity region NR22 and, for example, under the low-concentration n-type impurity region NR22. The distance to the depletion layer becomes longer. Therefore, the contact between the silicide SC and the depletion layer is suppressed. That is, the occurrence of leakage current is suppressed and the reliability of each circuit constituting the semiconductor device is improved.

  The present embodiment is different from the first embodiment only in each point described above. In other words, all the configurations, conditions, procedures, effects, and the like that have not been described above in the present embodiment are the same as those in the first embodiment.

(Embodiment 3)
Referring to FIGS. 24A and 24B, as described above, for example, in the graphs of FIGS. 19A and 19B, the maximum impurity concentration b should be 1 × 10 ²⁰ cm ⁻³ or less. The maximum impurity concentration f can exceed 1 × 10 ²⁰ cm ⁻³ . Here, the maximum concentrations e and a of the arsenic impurity regions ion-implanted a plurality of times for the S / D region of the core transistor CTR may be higher than 1 × 10 ²⁰ cm ⁻³ .

In FIG. 24A, each of the concentrations e and a is 1 × 10 ²⁰ cm ⁻³ or less, and the total concentration f is higher than 1 × 10 ²⁰ cm ⁻³ . However, each of the concentrations e and a (or either one) may be higher than 1 × 10 ²⁰ cm ⁻³ and the total concentration f may be higher than 1 × 10 ²⁰ cm ⁻³ .

Referring to FIGS. 25A and 25B, for example, in the graphs of FIGS. 3A and 3B, the same as in FIGS. 24A and 24B, the maximum impurity concentration b is 1. × is the 10 ²⁰ cm ^-3 or less, the maximum impurity concentration a is preferably higher than 1 × 10 ²⁰ cm ^-3.

  As described above, in the present embodiment, the maximum impurity region (maximum concentration) of each of the n-type impurity regions NR13 and NR21 shown in FIGS. 24 and 25 is the maximum impurity of arsenic in the n-type impurity regions NR13 and NR21. It shall refer to the concentration.

  Next, the effect of this Embodiment is demonstrated, referring the actual measurement data of FIG.

The horizontal axis of the graph of FIG. 26 indicates the gate length of the n-type I / O transistor ITR in the semiconductor device of FIG. 17 as a relative value, and the vertical axis indicates the on-breakdown voltage of the n-type I / O transistor ITR as a relative value. In FIG. 26, a triangle mark indicates that the maximum impurity concentration of arsenic in the n-type impurity region NR21 (see FIG. 17) of the I / O transistor ITR is 1 × 10 ²⁰ cm ⁻³ or less, and the n-type of the core transistor CTR Data of a sample in which the maximum impurity concentration of arsenic in the impurity region NR1O (see FIG. 17) exceeds 1 × 10 ²⁰ cm ⁻³ is shown. Similarly, marks shown by squares in FIG. 26 indicate that both the maximum impurity concentration of arsenic in the n-type impurity region NR21 of the I / O transistor ITR and the n-type impurity region NR21 of the core transistor CTR is higher than 1 × 10 ²⁰ cm ^−3. The data of the comparative example of this Embodiment which were made are shown.

As shown in FIG. 26, by setting the maximum impurity concentration of the n-type impurity region NR21 of the I / O transistor ITR to 1 × 10 ²⁰ cm ⁻³ or less, the on-breakdown voltage can be greatly improved (about 1. Can be improved 5 times). Further, by making the maximum impurity concentration of the n-type impurity region NR1O of the core transistor CTR higher than 1 × 10 ²⁰ cm ⁻³ , a decrease in the amount of current flowing when driving the core transistor CTR is suppressed, and the output of the core transistor CTR It is possible to suppress a decrease in power.

(Embodiment 4)
This embodiment is different from the second embodiment in the configuration of the n-type I / O transistor ITR. Hereinafter, the configuration of the semiconductor device of the present embodiment will be described with reference to FIGS.

  27 corresponds to the schematic cross-sectional view of the fourth embodiment shown in FIG. 2 of the first embodiment (FIG. 16 of the second embodiment), and FIG. 28 shows the second embodiment of the fourth embodiment. This corresponds to the schematic cross-sectional view shown in FIG. Referring to FIGS. 27 and 16, in the present embodiment, source region S and drain region D of I / O transistor ITR have n-type impurity region NR31 (first n-type impurity region) and low concentration n. It consists of a type impurity region NR22 (second n-type impurity region). The n-type impurity region NR31 is formed by ion implantation of, for example, phosphorus using the curve 31 as a boundary. Similarly to the above, the low-concentration n-type impurity region NR22 is formed by ion implantation of, for example, phosphorus with the curve 22 as a boundary. Therefore, in this case, only n is doped in the n-type impurity regions NR31 (S / D region) and NR22 (LDD region) of the I / O transistor ITR.

  As described above, the present embodiment differs from the second embodiment in that an n-type impurity region NR31 (including only phosphorus) is used instead of the n-type impurity region NR21 (including arsenic and phosphorus) of the I / O transistor ITR. It differs in that it is formed.

  In the present embodiment, the maximum impurity concentration in n-type impurity region NR31 of I / O transistor ITR is lower than the maximum impurity concentration in n-type impurity region NR1O of core transistor CTR. This will be described below.

  29 (A) and 29 (B), the maximum impurity concentration d of phosphorus in n-type impurity region NR31 constituting drain region D of I / O transistor ITR constitutes drain region D of core transistor CTR. It is lower than the maximum impurity concentration f of arsenic in the n-type impurity region NR13 (n-type impurity region NR1O). The above d (indicated by PT) is the maximum impurity concentration b of phosphorus doped to form the n-type impurity region with the curve 31 as the boundary, and the n-type impurity region with the curve 22 as the boundary. It is the sum of the maximum impurity concentration c1 of phosphorus doped to form.

Both the concentrations b and c1 can be made 1 × 10 ²⁰ cm ⁻³ or less (less than), and as a result, the total concentration d can be made 1 × 10 ²⁰ cm ⁻³ or less. In this way, the same effect as in the third embodiment can be obtained.

The core transistor CTR is the same as the graph shown in FIG. That is, in FIG. 29A, as in FIG. 24A, each of the concentrations e and a can be 1 × 10 ²⁰ cm ⁻³ or less, and the total concentration f is 1 × 10 ^20. It can be higher than cm ⁻³ . However, each of the concentrations e and a (or either one) can be made higher than 1 × 10 ²⁰ cm ⁻³ and the total concentration f can be made higher than 1 × 10 ²⁰ cm ⁻³ .

  As described above, in the present embodiment, the maximum impurity concentration (maximum concentration) of n-type impurity regions NR1O and 31 is the maximum impurity concentration of arsenic in n-type impurity region NR1O and the phosphorus concentration of n-type impurity region NR31. It shall refer to the maximum impurity concentration.

  Next, a method for manufacturing the semiconductor device DEV of the present embodiment will be described with reference to FIG.

Referring to FIG. 30, the manufacturing method of the present embodiment is basically the same as the manufacturing method of the second embodiment. However, in the process shown in FIG. 21 (FIG. 13) of the second embodiment, an n-type impurity is used. This is different from the manufacturing method of the second embodiment in that phosphorus for forming the n-type impurity region NR31 is implanted instead of arsenic for forming the region NR21. Specifically, phosphorus or the like is ion-implanted with an energy of, for example, 10 keV or more and 50 keV or less at a dose of 5 × 10 ¹³ cm ⁻² or more and 1 × 10 ¹⁵ cm ⁻² or less in plan view. Other conditions such as the injection direction are the same as those in the process of FIG.

  30, the n-type impurity regions NR1O and NR31 can be formed so that the maximum impurity concentration of phosphorus in the n-type impurity region NR31 is lower than the maximum impurity concentration of arsenic in the n-type impurity region NR1O.

Next, the function and effect of this embodiment will be described.
Also in this embodiment, basically, as in the other embodiments, the maximum impurity concentration of phosphorus in the n-type impurity region NR31 of the I / O transistor ITR is made lower than the maximum impurity concentration of arsenic in the core transistor CTR. . As a result, for example, the maximum impurity concentration of phosphorus in the n-type impurity region NR31 of the I / O transistor ITR is lower than that of the maximum impurity concentration of arsenic in the core transistor CTR (substantially the same). It is possible to reduce the electric field strength in the drain region of the O transistor ITR and suppress problems.

  In addition, in the present embodiment, since the n-type impurity regions NR31 and NR22 of the I / O transistor ITR are formed of only phosphorus, a gentle impurity concentration profile can be created as compared with the case where they are formed of arsenic. it can. This can be understood, for example, by comparing the shape of the graph 31P in FIG. 29B with the shape of the graph 21As in FIG. For this reason, in the present embodiment, the electric field strength caused by the drain voltages of the n-type impurity regions NR31 and NR22 can be further relaxed. As a result, the on-breakdown voltage and the off-breakdown voltage are improved, impact ionization is suppressed, and the element Can be miniaturized.

  The present embodiment is different from the second embodiment only in each point described above. In other words, all the configurations, conditions, procedures, effects, and the like that have not been described above in the present embodiment are the same as those in the second embodiment.

(Embodiment 5)
In each of the above embodiments, the concentration of phosphorus contained in the LDD region is considered to be negligibly small compared to the concentration of arsenic, and without considering this, the core transistor CTR and the I / O transistor ITR are basically considered. The arsenic concentrations in the S / D regions (such as the n-type impurity region NR21 in FIG. 16) are compared. However, when the semiconductor device DEV is formed, phosphorus in the LDD region of the core transistor CTR may be formed to have a relatively high concentration. In this way, it is possible to suppress the depletion layer from spreading immediately below the gate structure G of the core transistor CTR, and to reduce the resistance in the source region S and the drain region D.

  In this case, for example, the influence of the concentration of phosphorus contained in the S / D region on the electric field strength of the drain region D cannot be ignored. Therefore, in such a case, in comparing the impurity concentration of the S / D region between the core transistor CTR and the I / O transistor ITR, the S / D region was doped to form the LDD region of the S / D region. It is preferable to consider the concentration of impurities (considering the total concentration of arsenic and phosphorus in the S / D region and the LDD region). However, even if the concentration of phosphorus in the LDD region is small enough to be ignored, this may be considered as in the present embodiment.

FIG. 31 is a graph showing the impurity concentration distribution in the configuration of FIG. 2 of the first embodiment as the sum of the concentrations of arsenic and phosphorus contained in each impurity region. Referring to FIGS. 31A and 31B, in the present embodiment, the maximum impurity concentration d obtained by adding arsenic and phosphorus in n-type impurity region NR21 constituting drain region D of I / O transistor ITR. Is lower than the maximum impurity concentration a of arsenic in the n-type impurity region NR11 constituting the drain region D of the core transistor CTR. The above d (indicated by TTL) is a maximum impurity concentration b doped to form an arsenic n-type impurity region having the curve 21 as a boundary, and a phosphorus n-type impurity region having the curve 22 as a boundary. It is the sum of the maximum impurity concentration c1 doped to form. The concentration a can be higher than 1 × 10 ²⁰ cm ⁻³ , and the concentration d can be 1 × 10 ²⁰ cm ⁻³ or less.

FIG. 32 is a graph showing the impurity concentration distribution in the configuration of FIG. 16 of the second embodiment as the sum of the concentrations of arsenic and phosphorus contained in each impurity region. Referring to FIGS. 32A to 32C, in the present embodiment, the maximum impurity concentration d obtained by adding together arsenic and phosphorus in n-type impurity region NR21 constituting drain region D of I / O transistor ITR. Is lower than the maximum impurity concentration g obtained by adding arsenic and phosphorus in the n-type impurity region NR13 (n-type impurity region NR1O) constituting the drain region D of the core transistor CTR. The above g (indicated by TTL) is the maximum impurity concentration e doped for forming an n-type impurity region of arsenic with the curve 13 as a boundary, and the n-type impurity region of arsenic with the curve 11 as a boundary. This is the sum of the maximum impurity concentration a doped to form and the maximum impurity concentration c doped to form the n-type impurity region of phosphorus with the curve 12 as a boundary. The concentration g is preferably higher than 1 × 10 ²⁰ cm ⁻³ and the concentration d is preferably 1 × 10 ²⁰ cm ⁻³ or less. In FIG. 32A, as in the other embodiments, each of the concentrations e and a is 1 × 10 ²⁰ cm ⁻³ or less, and the total concentration f is 1 × 10 ²⁰ cm ^−. While higher than ^3, the concentration e, each of a (or either one) is higher than 1 × 10 ²⁰ cm ^-3, these total concentration f is not higher than 1 × 10 ²⁰ cm ^-3 Also good.

FIG. 33 is a graph showing the impurity concentration distribution in the configuration of FIG. 27 of the third embodiment as the sum of the concentrations of arsenic and phosphorus contained in each impurity region. Referring to FIGS. 33A and 33B, in the present embodiment, the maximum impurity concentration d (expressed as TTL) of phosphorus in n-type impurity region NR31 constituting drain region D of I / O transistor ITR. The sum of the concentration b and the concentration c1) is lower than the maximum impurity concentration g obtained by adding arsenic and phosphorus in the n-type impurity region NR13 (n-type impurity region NR1O) constituting the drain region D of the core transistor CTR. FIG. 33 (A) is the same graph as FIG. 32 (A), and the above g (indicated by TTL) is the same as the concentration g in FIG. 32 (A). FIG. 33B is obtained by replacing the curve 21 (concentration b arsenic) in FIG. 32B with a curve 31 (concentration b phosphorus). The concentration g is preferably higher than 1 × 10 ²⁰ cm ⁻³ and the concentration d is preferably 1 × 10 ²⁰ cm ⁻³ or less.

  As described above, in the present embodiment, the maximum impurity concentration (maximum concentration) of n-type impurity regions NR1O, 21, and 31 is the maximum impurity that is the sum of arsenic and phosphorus in n-type impurity regions NR1O, 21, and 31. The concentration (the sum of the maximum impurity concentration of arsenic and the maximum impurity concentration of phosphorus) shall be indicated.

  As described above, particularly when the maximum impurity concentration c1 of phosphorus in the LDD region of the core transistor CTR is high and cannot be ignored, arsenic (phosphorus) in the S / D region of the core transistor CTR and the I / O transistor ITR. It is preferable to compare the sum of the concentration of the phosphorous and the concentration of phosphorus doped to form the LDD region in the S / D region. Specifically, the maximum impurity concentration (d) of the I / O transistor ITR is preferably lower than the maximum impurity concentration (g) of the core transistor CTR. In this way, the electric field strength caused by the drain voltage of the I / O transistor ITR can be relaxed as in the other embodiments described above, and as a result, the on-breakdown voltage and off-breakdown voltage can be improved, and impact ionization can be achieved. Can be suppressed and the device can be miniaturized.

  Further, if the ion implantation amount of arsenic and / or phosphorus in the steps shown in FIGS. 13, 20 to 23, and 30 is adjusted as appropriate, the relationship of the impurity concentrations shown in the above examples of the present embodiment is obtained. A semiconductor device can be formed.

  The present embodiment is different from the first to fourth embodiments only in the points described above. In other words, all the configurations, conditions, procedures, effects, and the like that have not been described above in the present embodiment are the same as those in the first to fourth embodiments.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  CTR core transistor, D drain region, DEV semiconductor device, G gate structure, GE gate conductive film, GI gate insulating film, II element isolation film, ITR I / O transistor, MLL metal thin film, NR1O, NR12, NR13, NR14, NR21 , NR31 n-type impurity region, NR22, NR11, NR15, NR1X low-concentration n-type impurity region, PHR photoresist, PI pad oxide film, PWR p-type well region, S source region, SC silicide, SN silicon nitride film, SS, SUB Semiconductor substrate, TR trench.

Claims (20)

A semiconductor substrate having a main surface;
An n-channel first transistor forming an input / output circuit formed on the main surface;
A semiconductor device comprising: an n-type channel second transistor forming a logic circuit formed on the main surface;
The source region or drain region of the first transistor has a first n-type impurity region and a second n-type impurity region formed so as to surround the first n-type impurity region,
A source region or a drain region of the second transistor has a third n-type impurity region;
A maximum impurity concentration of the first n-type impurity region is higher than a maximum impurity concentration of the second n-type impurity region;
The semiconductor device, wherein a maximum impurity concentration of the first n-type impurity region is lower than a maximum impurity concentration of the third n-type impurity region.   2. The semiconductor device according to claim 1, wherein an impurity concentration gradient is discontinuous at a boundary portion between the first n-type impurity region and the second n-type impurity region. The source region or the drain region of the second transistor further includes a fourth n-type impurity region formed so as to surround the third n-type impurity region,
The semiconductor device according to claim 1, wherein a maximum impurity concentration of the third n-type impurity region is higher than a maximum impurity concentration of the fourth n-type impurity region.   The semiconductor device according to claim 3, wherein the second n-type impurity region is deeper than the fourth n-type impurity region.   The semiconductor device according to claim 3, wherein a maximum impurity concentration of phosphorus contained in the second n-type impurity region is equal to a maximum impurity concentration of phosphorus contained in the fourth n-type impurity region.   Impurities in at least one of the boundary between the first n-type impurity region and the second n-type impurity region and the boundary between the third n-type impurity region and the fourth n-type impurity region The semiconductor device according to claim 3, wherein the concentration gradient is discontinuous. The first and third n-type impurity regions include arsenic and phosphorus impurities,
4. The semiconductor device according to claim 3, wherein the maximum impurity concentration of arsenic in the first n-type impurity region is lower than the maximum impurity concentration of arsenic in the third n-type impurity region. The maximum impurity concentration of arsenic in the third n-type impurity region is higher than 1 × 10 ²⁰ cm ⁻³ , and the maximum impurity concentration of arsenic in the first n-type impurity region is 1 × 10 ²⁰ cm ⁻³ or less. The semiconductor device according to claim 6. The third n-type impurity region includes arsenic and phosphorus impurities,
The first n-type impurity region includes only phosphorus impurities;
4. The semiconductor device according to claim 3, wherein the maximum impurity concentration of phosphorus in the first n-type impurity region is lower than the maximum impurity concentration of arsenic in the third n-type impurity region. The maximum impurity concentration of arsenic in the third n-type impurity region is higher than 1 × 10 ²⁰ cm ⁻³ , and the maximum impurity concentration of phosphorus in the first n-type impurity region is 1 × 10 ²⁰ cm ⁻³ or less. The semiconductor device according to claim 9. The first and third n-type impurity regions include arsenic and phosphorus impurities;
6. The semiconductor according to claim 5, wherein the maximum impurity concentration of arsenic and phosphorus in the first n-type impurity region is lower than the maximum impurity concentration of arsenic and phosphorus in the third n-type impurity region. apparatus. The maximum impurity concentration of arsenic and phosphorus in the third n-type impurity region is higher than 1 × 10 ²⁰ cm ⁻³ , and the maximum impurity concentration of arsenic and phosphorus in the first n-type impurity region is The semiconductor device according to claim 11, which is 1 × 10 ²⁰ cm ⁻³ or less. The third n-type impurity region includes arsenic and phosphorus impurities,
The first n-type impurity region includes only phosphorus impurities;
6. The semiconductor device according to claim 5, wherein the maximum impurity concentration of phosphorus in the first n-type impurity region is lower than the maximum impurity concentration of arsenic and phosphorus in the third n-type impurity region. The maximum impurity concentration of arsenic and phosphorus in the third n-type impurity region is higher than 1 × 10 ²⁰ cm ⁻³ , and the maximum impurity concentration of phosphorus in the first n-type impurity region is 1 × 10 ²⁰ cm 3. The semiconductor device according to claim 13, which is ⁻³ or less. Preparing a semiconductor substrate having a main surface;
Forming an n-channel first transistor constituting an input / output circuit on the main surface;
Forming a second transistor of an n-type channel constituting a logic circuit on the main surface, comprising the steps of:
In the step of forming the first transistor, a first n-type impurity region and a second n-type impurity region formed so as to surround the first n-type impurity region are formed in a source region or a drain region. Including the step of forming,
The step of forming the second transistor includes a step of forming a third n-type impurity region in the source region or the drain region,
A maximum impurity concentration of the first n-type impurity region is higher than a maximum impurity concentration of the second n-type impurity region;
The semiconductor device manufacturing method, wherein the maximum impurity concentration of the first n-type impurity region is lower than the maximum impurity concentration of the third n-type impurity region.   The method of manufacturing a semiconductor device according to claim 15, wherein an inclination of an impurity concentration is discontinuous at a boundary portion between the first n-type impurity region and the second n-type impurity region. The source region or the drain region of the second transistor further includes a fourth n-type impurity region formed so as to surround the third n-type impurity region,
The method for manufacturing a semiconductor device according to claim 15, wherein a maximum impurity concentration of the third n-type impurity region is higher than a maximum impurity concentration of the fourth n-type impurity region.   The method of manufacturing a semiconductor device according to claim 17, wherein the second n-type impurity region is deeper than the fourth n-type impurity region.   18. The method for manufacturing a semiconductor device according to claim 17, wherein the maximum impurity concentration of phosphorus contained in the second n-type impurity region is equal to the maximum impurity concentration of phosphorus contained in the fourth n-type impurity region.   Impurities in at least one of the boundary between the first n-type impurity region and the second n-type impurity region and the boundary between the third n-type impurity region and the fourth n-type impurity region The method of manufacturing a semiconductor device according to claim 17, wherein the concentration gradient becomes discontinuous.

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