JP2014135970A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine capable of executing a complicated and highly advanced performance operation without increasing a processing load of a CPU.SOLUTION: A performance control part 22' including a CPU for controlling lamps in a prescribed mode comprises a serial port S0 that is disposed with a plurality of drivers DRij, a transmission data register DR for temporarily storing parallel data, and a transmission shift register SR for serially outputting the data received from the transmission data register by synchronizing the data with a level change in the clock signal CK. The serial port further comprises: first means (ST51) for outputting a start command representing to start transmission of a series of serial signals to the transmission data register; second means (ST53) for outputting a driver address for identifying any of the drivers DRij to the transmission data register; third means (ST57) for outputting the register address for identifying any of lamps that the driver DRij can drive, to the transmission data register; and fourth means for outputting lighting data for prescribing a lighting state of the lamp identified by the register address, to the transmission data register.

Description

  The present invention relates to a gaming machine that generates a big hit state by a lottery process caused by a gaming operation, and more particularly to a gaming machine that can stably execute an advanced lamp effect or the like.

  A ball game machine such as a pachinko machine has a symbol start opening provided on the game board, a symbol display section for displaying a series of symbol variation patterns by a plurality of display symbols, and a big winning opening for opening and closing the opening and closing plate. Configured. When the detection switch provided at the symbol start port detects the passage of the game ball, the winning state is entered, and after the game ball is paid out as a prize ball, the display symbol is changed for a predetermined time in the symbol display section. Thereafter, when the symbol is stopped in a predetermined manner such as 7, 7, 7, etc., a big hit state is established, and the big winning opening is repeatedly opened to generate a gaming state advantageous to the player.

  Whether or not to generate such a game state is determined by a jackpot lottery executed on the condition that a game ball has won at the symbol start opening, and the above symbol variation operation is based on this lottery result. It has become a thing. For example, when the lottery result is in a winning state, an effect operation called reach action or the like is executed for about 20 seconds, and then the special symbols are aligned. On the other hand, a similar reach action may be executed even in the case of a lost state. In this case, the player pays close attention to the big hit state and pays close attention to the transition of the performance operation. When the predetermined symbols are aligned on the stop line at the end of the symbol variation operation, the player is guaranteed to be in the big hit state.

JP 2009-11368 A

  The above-mentioned performance operation is centered on the image production on the liquid crystal display device. In conjunction with this image production, a lamp production that blinks various lamps, an audio production that outputs a sound that excites the player, Movable effects such as moving animals are executed. And as these game effects are enriched, it takes time for each control operation, so it is desirable to optimize the circuit configuration and control operation.

  Considering the lamp production from this point of view, if the configuration to transmit the lighting data that defines the lighting / extinguishing state of each lamp as a series of serial data, there is an advantage that the number of wires can be suppressed, but it corresponds to the number of lamps Since the processing load on the CPU increases, there is a problem that the control time available for other control operations decreases (for example, FIG. 108 of Patent Document 1). In particular, in the case of controlling the gradation of the light emission luminance of each lamp or performing advanced luminance control such as fade-in and fade-out, the problem of control time for that becomes obvious. This problem is the same when the motor is driven in addition to the lamp.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a gaming machine capable of performing a complex and advanced performance operation without increasing the processing load on the CPU.

  In order to achieve the above object, the present invention is a gaming machine provided with an effect control means having a CPU for controlling the light emission of a lamp in a predetermined manner based on a control command received from another control means. The control means includes a plurality of drivers having substantially the same configuration capable of driving the lamp, and a serial port that outputs a serial signal to be transmitted to the driver together with a clock signal. A transmission data register that temporarily stores parallel data; and a transmission shift register that serially outputs data received from the transmission data register in synchronization with a level change of the clock signal. A first means for outputting a start command indicating start of transmission to the transmission data register, and the first means Then, after the second means for outputting a driver address for specifying one of the drivers to the transmission data register and the second means function, the register address for specifying any of the lamps that can be driven by the driver is set as the transmission data register. And fourth means for outputting lighting data defining the lighting state of the lamp specified by the register address to the transmission data register after the third means has functioned. Yes.

  The present invention outputs a serial signal and a clock signal to be transmitted to the driver from the serial port, so that the control burden on the CPU is small and control time for other control operations is secured, and a complicated and advanced lamp effect is produced. Operation etc. can be realized. Further, even if the serial transmission rate is increased, the processing load on the CPU does not increase at all.

  The operations of the third means and the fourth means are preferably repeated by the number of lamps whose lighting state is updated among all the lamps that can be driven by the driver specified by the second means.

  In this case, after the operations of the third means and the fourth means are repeated as many times as necessary, it is advantageous to further include fifth means for outputting an end command indicating that transmission of a series of serial signals is ended to the transmission data register. Is. In this case, the driver who has received the end command preferably updates the lighting state of the lamp based on the lighting data received so far at a predetermined timing thereafter. More preferably, it is defined by a counter.

  The transmission of lighting data to the driver and the update of the lamp lighting state by the driver that has received the lighting data are defined by a 1-bit clock signal and a 1-bit serial signal transmitted from the serial port. It is preferable that transmission of other signals is unnecessary, and the serial port further includes a baud rate generator that outputs a clock signal and a control register configured to allow the CPU to grasp the contents of the operation being executed. It is preferable to be configured.

  As described above, according to the gaming machine of the present invention, it is possible to realize a gaming machine capable of performing a complicated and sophisticated production operation.

It is a perspective view of the pachinko machine shown in an example. It is the front view which illustrated the game board of the pachinko machine of FIG. It is a block diagram which shows the whole structure of the pachinko machine of FIG. It is a block diagram illustrating a circuit configuration of an effect control unit. It is a block diagram which illustrates the internal structure of a digital amplifier. It is drawing explaining the principal part and operation | movement content of the internal structure of the one-chip microcomputer of an effect control part. It is a block diagram which shows the internal structure of three lamp drive boards. It is a time chart which shows the serial signal transmitted to a lamp drive board | substrate. It is a flowchart explaining operation | movement of an effect control part. 10 is a flowchart showing a part of FIG. 9 in detail. It is a circuit block diagram which shows the structure of a lamp drive board | substrate and a peripheral board | substrate. It is a circuit diagram which shows the internal circuit of a collective buffer circuit, each buffer, and the input part of an LED driver. It is a circuit block diagram which shows the modification of FIG. It is a flowchart explaining the output process corresponding to the circuit of FIG. It is a figure explaining the usage example of a FIFO buffer.

  Hereinafter, the present invention will be described in detail based on examples. FIG. 1 is a perspective view showing a pachinko machine GM of the present embodiment. This pachinko machine GM includes a rectangular frame-shaped wooden outer frame 1 that is detachably mounted on an island structure, and a front frame 3 that is pivotably mounted via a hinge 2 fixed to the outer frame 1. It is configured. A game board 5 is detachably attached to the front frame 3 from the front side, not from the back side, and a glass door 6 and a front plate 7 are pivotally attached to the front side so as to be openable and closable.

  On the outer periphery of the glass door 6, an electric lamp such as an LED lamp is arranged in a substantially C shape. On the other hand, at the upper left and right positions and the lower side of the glass door 6, all three speakers are arranged. The two speakers arranged in the upper part are each configured to output sound of the left and right channels R and L, and the lower speaker is configured to output heavy bass.

  The front plate 7 is provided with an upper plate 8 for storing game balls for launching, and a lower plate 9 for storing game balls overflowing or extracted from the upper plate 8 and a launch handle at the lower part of the front frame 3. 10 are provided. The launch handle 10 is interlocked with the launch motor, and a game ball is launched by a striking rod that operates according to the rotation angle of the launch handle 10.

  A chance button 11 is provided on the outer peripheral surface of the upper plate 8. The chance button 11 is provided at a position where it can be operated with the left hand of the player, and the player can operate the chance button 11 without releasing the right hand from the firing handle 10. The chance button 11 does not function normally, but when the game state becomes the button chance state, the built-in lamp is turned on and can be operated. The button chance state is a game state provided as necessary.

  On the right side of the upper plate 8, an operation panel 12 for ball lending operation with respect to the card-type ball lending machine is provided, a frequency display unit for displaying the remaining amount of the card with a three-digit number, and a ball of game balls for a predetermined amount A ball lending switch for instructing lending and a return switch for instructing to return the card at the end of the game are provided.

  As shown in FIG. 2, a guide rail 13 made of a metal outer rail and an inner rail is provided on the surface of the game board 5 in an annular shape, and a central opening HO is provided at the approximate center thereof. A display device DS composed of a large liquid crystal color display (LCD) is disposed in the central opening HO.

  The display device DS is a device that variably displays a specific symbol related to the big hit state and displays a background image and various characters in an animated manner. This display device DS has special symbol display portions Da to Dc in the center portion and a normal symbol display portion 19 in the upper right portion. In the special symbol display portions Da to Dc, there is a case where a reach effect that expects a big hit state is invited, and in the special symbol display portions Da to Dc and the surroundings, an appropriate notice effect is executed.

  In the game area where the game ball falls and moves, a symbol start port 15, a big winning port 16, a normal winning port 17, and a gate 18 are arranged. Each of these winning openings 15 to 18 has a detection switch inside, and can detect the passage of a game ball.

  The symbol start port 15 is configured to be opened and closed by an electric tulip having a pair of left and right opening and closing claws 15a, and when the stop symbol after fluctuation of the normal symbol display unit 17 displays a winning symbol, a predetermined time is displayed. The opening / closing claw 15a is opened only until a predetermined number of game balls are detected.

  The normal symbol display unit 19 displays a normal symbol. When a game ball that has passed through the gate 18 is detected, the normal symbol fluctuates for a predetermined time and is extracted when the game ball passes through the gate 18. The stop symbol determined by the selected lottery random value is displayed and stopped.

  The special winning opening 16 includes an opening / closing plate 16a that advances and retreats in the front-rear direction. The operation of the special winning opening 16 is not particularly limited, but in a typical big hit state, a predetermined time elapses after the opening / closing plate 16a of the special winning opening 16 is opened, or a predetermined number (for example, ten) of games. When the ball wins, the opening / closing plate 16a is closed. Such an operation is continued up to 15 times, for example, and is controlled in a state advantageous to the player. In addition, when the stop symbol after the change of the special symbol display parts Da to Dc is a specific symbol among the special symbols, there is a privilege that the game after the end of the special game becomes a high probability state (probability variation state). Is granted.

  FIG. 3 is a block diagram showing an overall circuit configuration of the pachinko machine GM that realizes the above-described operations. As shown in the figure, this pachinko machine GM mainly receives a 24V AC and outputs various DC voltages, power supply abnormality signals ABN1, ABN2, a system reset signal (power reset signal) SYS, and the like, and a game control operation. Based on the main control board 21 that performs overall control, the effect control board 22 that executes the lamp effect and the sound effect based on the control command CMD received from the main control board 21, and the control command CMD ′ received from the effect control board 22 The image control board 23 for driving the display device DS, the payout control board 24 for controlling the payout motor M based on the control command CMD "received from the main control board 21, and paying out the game balls. It is mainly composed of a launch control board 25 that responds and launches a game ball.

  However, in this embodiment, the control command CMD output from the main control board 21 is transmitted to the effect control board 22 via the command relay board 26 and the effect interface board 27. The control command CMD ′ output from the effect control board 22 is transmitted to the image control board 23 via the effect interface board 27 and the image interface board 28, and is output from the main control board 21. Is transmitted to the payout control board 24 via the main board relay board 32. Although the control commands CMD, CMD ′, and CMD ″ are all 16 bits long, the main control board 21 and the payout control board 24 are used. The control commands related to are transmitted in parallel every two 8 bit lengths. On the other hand, the control command CMD 'transmitted from the effect control board 22 to the image control board 23 is 16 bits in length and transmitted in parallel. Therefore, even when the notification effects including the movable notification effect are diversified and a large number of control commands are continuously transmitted and received, the processing can be completed quickly, and other control operations are not hindered.

  By the way, in the present embodiment, the production interface board 27 and the production control board 22 are directly connected to each other by a male connector and a female connector without passing through a wiring cable, and two circuit boards are laminated. . Similarly, with respect to the image interface board 28 and the image control board 23, two circuit boards are laminated by directly connecting a male connector and a female connector without going through a wiring cable. Therefore, even if the circuit configuration of each electronic circuit is complicated and sophisticated, the storage space of the entire board can be minimized, and noise resistance can be improved by minimizing the connection lines.

  The main control board 21, the effect control board 22, the image control board 23, and the payout control board 24 are each equipped with a computer circuit including a one-chip microcomputer. Therefore, in this specification, the control board 21 to 24, the circuits mounted on the interface boards 27 to 28, and the operations realized by the circuits are generically named. May be referred to as a section 22 ′, an image control section 23 ′, and a payout control section 24. That is, in this embodiment, the effect control board 22 and the effect interface board 27 constitute an effect control part 22 ′, and the image control board 23 and the image interface board 28 constitute an image control part 23 ′. . Note that all or part of the effect control unit 22 ′, the image control unit 23 ′, and the payout control unit 24 are sub-control units.

  The pachinko machine GM is roughly divided into a frame side member GM1 surrounded by a broken line in FIG. 3 and a board side member GM2 fixed to the back of the game board 5. The frame side member GM1 includes a front frame 3 on which a glass door 6 and a front plate 7 are pivotally attached, and a wooden outer frame 1 on the outside thereof. Is fixedly installed. On the other hand, the board side member GM2 is replaced in response to the model change, and a new board side member GM2 is attached to the frame side member GM1 instead of the original board side member. All except the frame side member 1 is the panel side member GM2.

  As shown in the broken line frame in FIG. 3, the frame side member GM1 includes a power supply board 20, a payout control board 24, a launch control board 25, a frame relay board 35, and a lamp drive board 36. These circuit boards are respectively fixed at appropriate positions of the front frame 3.

  A plurality of LEDs are connected to the lamp drive board 36, and the drive data SDATA for driving these LED groups is a serial signal, the production control board 22 → the production interface board 27 → the frame relay board 34 → the frame relay. The signal is transmitted to a plurality of drivers DRij mounted on the lamp driving substrate 36 via the substrate 35.

  Each of the drivers DRij (driver ICs) of the embodiment can drive up to 24 LED groups such as LEDs and electric lamps, but in the following description, five drivers mounted on the lamp driving board 36 are used. Assume that a total of 5 × 24 LEDs are driven by DRij (see FIG. 7). In this specification, these LEDs are referred to as a 0th channel (CH0) LED group for convenience.

  On the back surface of the game board 5, a main control board 21, an effect control board 22, and an image control board 23 are fixed together with the display device DS and other circuit boards. And the frame side member GM1 and the board | substrate side member GM2 are electrically connected by the connection connectors C1-C4 concentratedly arranged in one place.

  The power supply board 20 is connected to the main board relay board 32 through the connection connector C2, and is connected to the power supply relay board 33 through the connection connector C3. The power supply board 20 is provided with a power supply monitoring unit MNT that monitors whether AC power is turned on or off. When power supply monitoring unit MNT detects that AC power is turned on, it maintains system reset signal SYS at L level for a predetermined time, and then transitions it to H level.

  Further, when power supply monitoring unit MNT detects the interruption of the AC power supply, power supply abnormality signals ABN1 and ABN2 are immediately shifted to the L level. The power supply abnormality signals ABN1 and ABN2 quickly become H level after the power is turned on.

  Incidentally, the system reset signal of this embodiment is generated by a DC power supply based on an AC power supply. For this reason, after detecting the turning-on of the AC power supply (usually turning on the power switch) and increasing it to the H level, the H level is maintained unless the DC power supply voltage drops to an abnormal level. Therefore, even if the AC power supply is in an instantaneous power interruption state while the DC power supply voltage is maintained, the system reset signal SYS does not reset the CPU. The power supply abnormality signals ABN1 and ABN2 are also output even when the AC power supply is instantaneously stopped.

  The main board relay board 32 outputs the power abnormality signal ABN1, the backup power supply BAK, and DC5V, DC12V, and DC32V output from the power board 20 to the main control unit 21 as they are. On the other hand, the power relay board 33 outputs the system reset signal SYS received from the power board 20 and the AC and DC power supply voltages to the effect interface board 27 as they are. The effect interface board 27 outputs the received system reset signal SYS to the effect control unit 22 'and the image control unit 23' as it is.

  On the other hand, the payout control board 24 is directly connected to the power supply board 20 without going through the relay board, and directly receives the same power abnormality signal ABN2 and backup power supply BAK as the main control unit 21 receives together with other power supply voltages. Is receiving.

  The system reset signal SYS output from the power supply board 20 is a power supply reset signal indicating that the AC power supply 24V has been applied to the power supply board 20, and one of the effect control unit 22 ′ and the image control unit 23 ′ is generated by the power supply reset signal. The chip microcomputer is reset together with other IC elements.

  However, the system reset signal SYS is not supplied to the main control unit 21 and the payout control unit 24, and a power reset signal (CPU reset signal) is generated in the reset circuit RST of each of the circuit boards 21 and 24. ing. Therefore, for example, even if the connection connector C2 is rattled or noise is superimposed on the wiring cable, there is no possibility that the CPU of the main control unit 21 or the payout control unit 24 is abnormally reset. The production control unit 22 ′ and the image control unit 23 ′ perform production operations dependently on the basis of the control command from the main control unit 21, so that the power supply board 20 is avoided in order to avoid complication of the circuit configuration. The system reset signal SYS output from is used.

  By the way, the reset circuits RST provided in the main control unit 21 and the payout control unit 24 each have a built-in watchdog timer, and unless a regular clear pulse is received from the CPUs of the control units 21 and 24, Each CPU is forcibly reset.

  In this embodiment, the RAM clear signal CLR is generated by the main control unit 21 and transmitted to the one-chip microcomputer of the main control unit 21 and the payout control unit 24. Here, the RAM clear signal CLR is a signal for deciding whether or not to initialize all the areas of the built-in RAM of the one-chip microcomputer of each control unit 21 and 24. The initialization switch SW operated by the attendant is turned on. It has a value corresponding to the / OFF state.

  The main control unit 21 and the payout control unit 24 receive the power supply abnormality signals ABN1 and ABN2 from the power supply board 20 to start necessary end processing prior to a power failure or business end. The backup power supply BAK is a DC5V DC power source that retains data in the RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 24 even after the AC power supply 24V is shut off due to business termination or power failure. Therefore, the main control unit 21 and the payout control unit 24 can resume the game operation before power-off after power-on (power backup function). This pachinko machine is designed to retain the stored contents of the RAM of each one-chip microcomputer for at least several days.

  As shown in FIG. 3, the main control unit 21 transmits a control command CMD ″ to the payout control unit 24 via the main board relay board 32, while the payout control unit 24 indicates a game ball payout operation. A prize ball counting signal, a status signal CON relating to an abnormality in the payout operation, and an operation start signal BGN are received, and the status signal CON includes, for example, a replenishment signal, a payout shortage error signal, and a lower plate full signal. The operation start signal BGN is a signal for notifying the main control unit 21 that the initial operation of the payout control unit 24 has been completed after the power is turned on.

  The main control unit 21 is connected to each game component of the game board 5 via the game board relay board 31. And while receiving the switch signal of the detection switch built in each winning opening 16-18 on a game board, solenoids, such as an electric tulip, are driven. The solenoids and the detection switch are configured to operate with the power supply voltage VB (12 V) distributed from the main control unit 21. Each switch signal indicating a winning state to the symbol start opening 15 is converted to a TTL level or CMOS level switch signal by an interface IC that operates with the power supply voltage VB (12 V) and the power supply voltage Vcc (5 V). And then transmitted to the main control unit 21.

  As described above, the effect control board 22 and the effect interface board 27 are integrated by connector connection, and the effect control unit 22 ′ is connected to each level from the power supply board 20 via the power relay board 33. A DC voltage (5V, 12V, 32V) and a system reset signal SYS are received (see FIGS. 3 and 4). The effect control unit 22 'receives the control command CMD and the strobe signal STB from the main control unit 21 via the command relay board 26 (see FIGS. 3 and 4).

  The effect control unit 22 ′ supplies lamp drive data SDATA (serial signal) to the driver DRij mounted on the lamp drive board 29 and the lamp drive board 30 via the effect interface board 27. Although not particularly limited, the driver DRij mounted on the lamp driving boards 29 and 30 has the same configuration as the driver DRij mounted on the lamp driving board 36, and each of the lamp driving boards 29 and 30 includes Five drivers DRij are arranged.

  As described above, each of these drivers DRij can drive a maximum of 24 lamps. In the following description, a total of 24 × 5 lamps connected to the lamp driving board 29 are connected to the first lamps. A total of 24 × 5 lamps connected to the lamp driving substrate 30 are referred to as a lamp group of the channel CH1, and are referred to as a lamp group of the second channel CH2 (see FIG. 7).

  As described above, in this embodiment, a large number (3 × 24 × 5) of lamps are divided into three groups of lamps of channel CH0 to channel CH2, respectively, and the lamp driving board 36, the lamp driving board 29, and the lamp driving, respectively. It is connected to the substrate 30. As will be described later with reference to FIG. 4, all drivers DRij receive a corresponding signal from serial signals SDATA output collectively by the one-chip microcomputer 40 of the effect control unit 22 ′, and are in charge of the lamp group. Is driven (see FIG. 4).

  By the way, it is possible to drive the stepping motor using the same driver DRij. For example, it is also preferable to drive the effect motor groups M1 to Mn via the lamp driving board 30 as indicated by a broken line. In this case, the motor drive data is a serial signal similar to the lamp drive data, and even if the number of production motors is increased in order to enrich production contents, the number of wiring cables does not increase, and the device configuration is simplified. .

  As shown in FIGS. 3 and 4, the effect control unit 22 ′ has two types of control commands CMD ′ and strobe signal STB ′, and a system reset signal SYS received from the power supply board 20, with respect to the image control unit 23 ′. DC voltage (12V, 5V).

  Then, the image controller 23 'drives the display device DS based on the control command CMD' to execute various image effects. The display device DS emits light by an LED backlight, and is driven by receiving five pairs of LVDS (Low voltage differential signaling) signals and a backlight power supply voltage (12 V) from the image interface board 28. (See FIG. 4).

  Next, the configurations of the effect control unit 22 'and the image control unit 23' will be described in more detail. As shown in FIG. 4, the production interface board 27 receives three types of DC voltages (5V, 12V, and 32V) from the power supply board 20 via the power supply relay board 33. Here, the DC voltage 5V is distributed as power supply voltage of the digital logic circuit to the rendering interface board 27, the lamp driving board 29, the lamp driving board 30, the image interface board 28, and the image control board 23, and is supplied to each digital circuit. Is operating.

  However, the direct current voltage 5V is not distributed on the effect control board 22, and the direct current voltage 3.3V stepped down from 12V by the DC / DC converter and the direct current stepped down from 3.3V by the DC / DC converter. Only the voltage 1.8V is distributed from the production interface board 27 to the production control board 22.

  In this way, the production control board 22 of the present embodiment is driven by the power supply voltage of 3.3V or lower because all the circuits are driven. Therefore, even if the production interface board 27 is arranged and laminated immediately above the production control board 22, there is no problem in heat dissipation.

  However, the DC voltage 12V received from the power supply board 20 is used as it is as the power supply voltage of the digital amplifier 46 and is distributed to the lamp drive board 30 and the lamp drive board 29 to become the power supply voltage of each lamp group. The direct current voltage 32V is stepped down to the direct current voltage 13V in the DC / DC converter of the production interface board and used as a drive power source for the production motors M1 to Mn as necessary.

  As shown in FIG. 4, the effect control unit 22 ′ includes a one-chip microcomputer 40 that executes processing such as a sound effect, a lamp effect, a notice effect by the effect movable body, and data transfer, and a control program for the one-chip microcomputer 40. A flash memory 41 to be stored, a voice synthesis circuit 42 that reproduces and outputs a voice signal based on an instruction from the one-chip microcomputer 40, and compressed voice data that is original data of the reproduced voice signal are stored. And an audio memory 43 that is configured.

  Here, the one-chip microcomputer 40, the flash memory 41, and the voice memory 43 operate at a power supply voltage of 3.3V, and the voice synthesis circuit 42 operates at a power supply voltage of 3.3V and a power supply voltage of 1.8V. It operates and significant power saving is realized. Here, 1.8V is the power supply voltage of the computer core part of the speech synthesis circuit, and 3.3V is the power supply voltage of the I / O part.

  The one-chip microcomputer 40 includes a plurality of parallel input / output ports PIO (Pi + Po + Po ′) and a plurality of serial output ports SI. Here, more specifically, the serial output port SI includes three-channel serial ports (S0 to S2) (see FIG. 6), and is mounted on the lamp driving boards 36, 29, and 30. Lamp drive data SDATA0 to SDATA2 are output to the five drivers DRij in synchronization with the clock signals CK0 to CK2, respectively. That is, the serial port S0 to serial port S2 transmit the lamp drive data SDATA0 to SDATA2 to the corresponding lamp drive boards 36, 29, and 30 based on the clock synchronization method. Note that the lamp driving data SDATA0 to SDATA2 are luminance data for adjusting the luminance of light emitted from each LED by PWM control (pulse width modulation).

  The lamp driving boards 36, 29, 30 are also connected to the parallel output port Po ′ of the parallel input / output port PIO. The driver DRij mounted on each of the lamp driving boards 36, 29, 30 is a parallel output port. The operation is started based on any of the 3-bit operation enable signals ENABLE0 to ENABLE2 output by Po ′.

  On the other hand, the control command CMD and the strobe signal STB from the main control unit 21 are input to the input port Pi of the parallel input / output port PIO, and the control command CMD ′ and the strobe signal STB ′ are output from the command output port Po. It is comprised so that.

  Specifically, a control command CMD and a strobe signal (interrupt signal) STB output from the main control board 21 correspond to the power supply voltage 3.3 V in the buffer 44 of the effect interface board 27 at the input port Pi. Converted to a logic level to be supplied in units of 8 bits. The interrupt signal STB is supplied to the interrupt terminal of the one-chip microcomputer, and the effect control unit 22 'is configured to acquire the control command CMD by the reception interrupt process.

  The control command CMD acquired by the effect control unit 22 ′ includes (1) an abnormality notification and other notification control commands, and (2) control for specifying an outline of various effect operations resulting from winning at the symbol start opening. A command (variation pattern command) and a control command (symbol designation command) for designating a symbol type are included. Here, the outline of the production operation specified by the variation pattern command includes the production total time from the production start to the production end and the result of winning or failing in the jackpot lottery.

  In addition, the symbol designating command includes information for identifying information on the jackpot type (15R probability variation, 2R probability variation, 15R normal, 2R normal, etc.) in the case of a jackpot according to the result of the jackpot lottery. In some cases, information for identifying a loss is included. The outline of the production operation specified by the variation pattern command includes the production total time from the production start to the production end, and the result of success or failure in the big hit lottery. In addition to these, the change pattern command including the presence or absence of the reach effect or the notice effect may be specified, but even in this case, the specific content of the effect content is not specified.

  Therefore, when the change pattern command is acquired, the effect control unit 22 ′ performs an effect lottery subsequently to further specify the effect outline specified by the acquired change pattern command. For example, the specific contents of the reach effect and the notice effect are determined. Then, in accordance with the determined specific game content, a lamp effect by blinking LEDs and a sound effect preparation operation by a speaker are performed, and an effect operation by a lamp or speaker is performed on the image control unit 23 ′. A control command CMD ′ relating to the synchronized image effect is output.

  In order to realize such an image effect synchronized with the effect operation, the effect control unit 22 ′, along with the strobe signal (interrupt signal) STB ′ for the image control unit 23 ′, is sent to the image control unit 23 ′ through the command output port Po. CMD ′ is output toward the production interface board 27. When the production control unit 22 ′ receives a design designation command, a notification control command related to the display device DS, and other control commands, the control command is summarized in a 16-bit length. It is output toward the production interface board 27 together with the interrupt signal STB ′.

  Corresponding to the configuration of the production control board 22 described above, the production interface board 27 is provided with an output buffer 45, and a 16-bit control command CMD ′ and a 1-bit interrupt signal STB ′ are sent to the image interface. It is output to the substrate 28. These data CMD ′ and STB ′ are transmitted to the image control board 23 via the image interface board 28.

  The effect interface board 27 is provided with a digital amplifier 46 that receives the audio signal output from the audio synthesis circuit 42. As described above, the speech synthesis circuit 42 operates with power supply voltages of 3.3 V and 1.8 V, and the digital amplifier 46 performs class D amplification operation with a power supply voltage of 12 V, reducing power consumption. It is possible to produce a loud sound while suppressing it.

  The left and right speakers at the upper part of the gaming machine and the speakers at the lower part of the gaming machine are driven by the output of the digital amplifier 46. Therefore, the voice synthesis circuit 42 needs to generate a three-channel voice signal, and if this is transmitted in parallel, the wiring between the voice synthesis circuit 42 and the digital amplifier 46 becomes complicated.

  Therefore, in this embodiment, the voice synthesis circuit 42 and the digital amplifier 46 are connected by four signal lines in order to prevent deterioration of sound quality and avoid complicated wiring. In this case, the transfer clock signal SCLK, the channel control signal LRCLK, and the 2-bit serial signals SD1 and SD2 are suppressed to a total of 4 bit signal lines. Note that the amplitude level of any signal is 3.3V.

  Here, SD1 is a serial signal for PCM data specifying the stereo signals R and L of the left and right speakers arranged at the upper part of the gaming machine, and SD2 is a monaural signal of the heavy bass speaker arranged at the lower part of the gaming machine. This is a serial signal for the PCM data to be specified. The voice synthesis circuit 342 transmits the left channel audio signal L while maintaining the channel control signal LRCLK at the L level, and maintains the channel control signal LRCLK at H level while maintaining the channel control signal LRCLK at the L level. Is transmitted. Note that since there is only one heavy bass speaker in this embodiment, a monaural audio signal is transmitted, but it is of course possible to transmit it as a stereo audio signal.

  In any case, in this embodiment, four types of audio signals can be transmitted with four cables, and therefore, signal transmission without audio deterioration due to noise can be performed with the minimum number of cables. That is, since it is serial transmission, the number of cables is far smaller than that of parallel transmission. Note that when analog transmission is employed, the number of cables is the same, but noise is superimposed on an analog signal having an amplitude of 3.3 V, and the sound quality is greatly deteriorated. On the other hand, when the amplitude level is increased, the power supply wiring becomes complicated and the power consumption increases.

  Such serial signals SD1 and SD2 are acquired by the digital amplifier 46 in synchronization with the rising edge of the clock signal SCLK. In the digital amplifier 46, parallel conversion is performed for each predetermined bit length, and after D / A conversion, D-class amplification is performed and supplied to each speaker.

  Although the internal configuration of the digital amplifier 46 is appropriate, FIG. 5 shows an internal configuration diagram when YDA171 (YAMAHA) is used as the digital amplifier. Although it is not limited to such an internal configuration, in any case, in this embodiment, since the voice synthesis circuit 42 and the digital amplifier 46 are connected by a serial line, the bit length of the PCM data (voice data) is increased. Even if the sound quality is improved, it is not necessary to change the wiring cable and the like, and the circuit configuration can be simplified.

  The effect interface board 27 is provided with parallel output port Po 'of the one-chip microcomputer 40, serial buffer SI, and output buffer circuits 47, 48, and 49 for transmitting various signals to be output. Here, the output buffer 47 is related to the LED group of the 0th channel, and outputs the lamp driving data SDATA0, the clock signal CK0, and the operation permission signal ENABLE0 output from the one-chip microcomputer 40 to the frame relay board 34. doing. The output 3-bit signal is transmitted to the driver DRij of the lamp driving board 36 via the frame relay board 34 and the frame relay board 35 (see FIG. 7).

  Similarly, the output buffer 48 transmits the lamp drive data SDATA1, the clock signal CK1, and the operation permission signal ENABLE1 output from the one-chip microcomputer 40 to the driver DRij of the lamp drive board 29, and the output buffer 49 The drive data SDATA2, the clock signal CK2, and the operation permission signal ENABLE2 are transmitted to the driver DRij of the lamp drive board 30 (see FIG. 7). The driver DRij of the lamp driving board 29 drives the LED group of the first channel, and the driver DRij of the lamp driving board 30 drives the LED group of the second channel.

  FIG. 6A illustrates the internal configuration of the serial port SI built in the one-chip microcomputer 40. As shown in the figure, the serial port S0 to serial port S2 all have the same configuration. The transmission data register DR that receives 1-byte data from the CPU core and the transfer of 1-byte data from the transmission data register DR receive the lamp driving data. A transmission shift register SR that outputs serially as SDATAi, a number of control registers RG that manage the internal operation state of the serial port, and a clock signal CKi of a frequency division ratio that is specified by the control register RG in response to the output pulse Φ of the counter circuit CT Baud rate generator BG.

  Here, the control register RG includes a READable control register including the empty bit EMP, and indicates whether or not the transmission data register DR can accept new data. That is, when transmission of 1-byte data in transmission shift register SR is completed, empty bit EMP changes to H level (empty level), indicating that new data can be written into transmission data register DR. Therefore, the CPU core (hereinafter referred to as CPU) writes new data into the transmission data register DR after confirming that the empty bit EMP is at the H level.

  The control register RG includes a WRITE control register including a transmission permission bit TXE. When the CPU sets the transmission permission bit TXE to the ON (H) level, the serial port transmission operation is permitted. When set to the OFF level, the transmission operation is prohibited. Therefore, in this embodiment, the CPU sets the transmission permission bit TXE to the ON state at the start of the transmission process, and resets the transmission permission bit TXE to the OFF level at the end of the transmission process.

  FIG. 6B is a time chart showing the operation at the start of transmission for the serial ports S0 to S2. As shown in the figure, when the serial ports S0 to S2 are in the transmission prohibited state (TXE = L), or after the data of the transmission data register DR is serially output, the clock signal CK is at the fixed H level. The transmission data register DR is empty, and the empty bit EMP is also at the H level (empty level).

  Then, after the CPU sets the transmission permission bit TXE to the ON state (transmission permission state) and then writes the first byte of transmission data to the transmission data register DR, the empty bit EMP transitions to the L level, and then After a predetermined time (τ) elapses, the first byte of transmission data is transferred to the transmission shift register SR, and the serial transmission operation is started.

  Further, since the transmission data is transferred to the transmission shift register SR, the empty bit EMP transitions to the H level (empty level) thereafter in response to the start of serial transmission of the first bit. Therefore, after confirming the H level empty bit EMP, the CPU writes the second byte of transmission data into the transmission data register DR.

  Then, in response to the data write operation to the transmission data register DR, the empty bit EMP transitions to the L level (full level). After that, when all the transmission data of the first byte is transmitted, the second byte of data is transferred from the transmission data register DR to the transmission shift register SR, and the data transmission of the second byte is started, and the empty bit EMP Transitions to the H level.

  The empty bit EMP changes to the L level in response to the data write operation of the third byte to the transmission data register DR. However, as shown in the figure, the empty bit EMP maintains the H level when no new data is written. . Further, after all the data is transmitted, the clock signal CK maintains the H level and does not change.

  Although not particularly limited, in this embodiment, in response to the internal operation of the driver DRij, transmission operation is performed in synchronization with the clock signal CK from the MSB (Most Significant Bit) of 1-byte data to the LSB (Least Significant Bit). Is set to be executed (MSB first). Specifically, an appropriate set value is set in the corresponding control register RG. Further, as shown in the figure, the transmission operation proceeds in synchronization with the falling edge of the clock signal CK.

  As will be described later, in this embodiment, the CPU writes the first byte of data in the transmission data register DRi in the order of serial port S0 → serial port S1 → serial port S2, and then the H of each empty bit EMPi. After determining the level, the second byte of data is written in each transmission data register DRi in the same order (see FIG. 10).

  However, in the data writing process executed in series in the order of serial port S0 → serial port S1 → serial port S2, the write time difference of 1-byte data is practically zero (see FIG. 6). Data transmission processing to the driver DRij is started almost simultaneously. Therefore, the end of the data transmission process to the driver DRij of the channels CH0 to CH2 is almost the same timing as long as the transmission data amount is the same, and the serial transmission process can be completed quickly (see FIG. 8).

FIG. 7 shows the circuit configuration of the lamp driving substrates 36, 29, and 30 in a confirmed manner. As shown in the figure, the lamp driver board 36 is equipped with five drivers DR ₀₀ , DR ₀₁ ... DR ₀₄ to drive and turn on the LED group of the 0th channel (5 × 24 LEDs in total). Yes. Similarly, five drivers DR ₁₀ , DR ₁₁ ... DR ₁₄ are mounted on the lamp drive board 29, and five drivers DR ₁₈ , DR _{19. 1C} is mounted, and each LED group of the first channel and the second channel (5 × 24 LEDs in total) is driven to light.

Each driver DRij is provided with a 5-bit numbering terminal. By adopting a circuit configuration in which fixed digital data is supplied to this numbering terminal, each slave address (port address) is assigned in series. It is numbered. That is, in the illustrated example, the slave address of each driver (DR ₀₀ , DR ₀₁ ... DR ₀₄ , DR ₁₀ , DR ₁₁ ... DR ₁₄ , DR ₁₈ , DR ₁₉ ... DR _1C ) is In hexadecimal notation, 00H, 01H... 04H, 10H, 11H... 14H, 18H, 19H.

  By assigning a series of slave addresses to the drivers DRij of the lamp control boards 36, 29, and 30, it is possible to speed up the setting process of luminance data and the like for each driver DRij. Although this point will be described later, a series of slave addresses do not necessarily have to be arranged in a +1 relationship, and may have a relationship of + N or -N.

  Each driver DRij has built-in gradation registers GR0 to GR23 that can define analog levels of lighting drive signals for driving 24 LEDs. In addition to the gradation register GRn, a number of setting registers are prepared in the driver DRij, but in this embodiment, only the gradation register GRn is used for convenience of explanation.

  Each of the gradation registers GRn can store 8-bit long luminance data, and the luminance level of the LED can be set in 256 steps from 00H to FFH. In other words, according to the driver DRij used in the embodiment, the brightness level of each LED is controlled to 256 gradations (PWM = Duty ratio = 0 to 255/256 = 0 to 99.6%). However, in this embodiment, the luminance level is suppressed to 16 gradations in consideration of human visual sensitivity, and the luminance data (00H to 0FH) of 4 bits length 16 gradations is multiplied by 16 to obtain 00H to F0H. Brightness data. The luminance data 00H means extinguishing (Duty ratio = 0%), and F0H means lighting with maximum luminance.

  FIG. 8 is a flowchart for explaining the operation of each driver DRij and the operation of the CPU. First, luminance data setting processing for the gradation registers GR0 to GR23 of each driver DRij will be described based on the lamp driving data SDATA0 to SDATA2 output from the one-chip microcomputer 40.

  In order to set the luminance data in the gradation registers GR0 to GR23, prior to this, the slave address transmission process for specifying each driver DRij and the register number N of the gradation registers GR0 to GR23 (for example, N = 15H to 1CH) need to be executed. However, when the register numbers N (= 15H to 1CH) are continuous as in the present embodiment, after the first register number N (= 15H) is transmitted, the register numbers 15H and subsequent grayscale registers GRn are transmitted. It is sufficient that the luminance data Dn to be set is output for each byte.

The slave address is a 5-bit length port address that identifies the driver DRij, but is an 8-bit length with an appropriate addition of 3 bits. This 8-bit slave address is transmitted from the MSB to the LSB. As is clear from FIG. 7, the 8-bit slave address is commonly transmitted to the five drivers DRij (for example, DR _{00 to} DR ₀₄ ), but the specific address corresponding to the transmitted slave address. Only the driver DRij will receive subsequent transmission data.

Specifically, in all the drivers DRij (for example, DR _{00 to} DR ₀₄ ), the first byte of data (slave address) is acquired at the rising edge of the 24th (= 8 × 3) clock signal CKi. Only the driver DRij that matches the slave address of the slave continues the subsequent reception process.

  As described above, the register number N of the gradation register GRn is then transmitted to the driver DRij of this embodiment, and subsequently, the setting data Dn to the gradation register GRn is transmitted. It has become. Then, in the driver DRij corresponding to the designated slave address, the register number N is automatically incremented, and the setting data Dn + 1, Dn + 2,... Received thereafter are the gradation registers GRn + 1, GRn + 2, respectively. ... is set.

  As described above, in this embodiment, only the gradation register GRi is used. Therefore, the number of serial data transmitted from the one-chip microcomputer 40 to the driver DRij of each channel (0 to 2) is the slave address. (1 byte), the register number of the gradation register GR0 (1 byte of 15H), and the luminance data (24 bytes) to be set in the 24 gradation registers GR0 to GR23, total 26 bytes.

  As described with reference to FIG. 8B, the serial port S0 to S2 of the one-chip microcomputer 40 maintains the empty bit EMP of the control register RG at the H level after outputting the luminance data of the 23rd byte. The 24th byte of luminance data written in the transmission data register DR is output from the transmission shift register SR toward the LSB for each bit from the transmission shift register SR in a state where the empty bit EMP = H level is maintained. Then, after the serial ports S0 to S2 of the one-chip microcomputer 40 output the LSB of the luminance data of the 24th byte, the clock signal CK maintains the H level.

  Therefore, the CPU of the one-chip microcomputer 40 returns the operation permission signals ENABLE0 to ENABLE2 to the L level at the timing when the 24th byte luminance data is assumed to have been acquired by the corresponding driver DRij, and permits transmission of the control register RG. The bit TXE is returned to the transmission inhibition level (see FIG. 8). Then, in response to the operation enable signals ENABLE0 to 2 = L, each driver DRij then drives the LED based on the brightness data newly set or set in the gradation registers GR0 to GR23. Become.

  In this embodiment, every time serial data for one driver is transmitted, the transmission permission bit TXE is returned to the prohibited level. However, the transmission permission bit TXE is not limited at all, and is prohibited after the transmission processing for all the drivers is completed. You may return to the level. In particular, there is no need to return to the prohibited level.

  FIG. 9 is a flowchart for explaining the operation content of the effect control unit 22 ′, which is executed by the CPU of the one-chip microcomputer 40. The operation of the effect control unit 22 ′ includes a main process (FIG. 9 (a)) executed in an infinite loop after the CPU reset, a timer interrupt process (FIG. 9 (b)) started every 1 mS, and the main control. And reception interrupt processing (not shown) for receiving a control command transmitted by the unit.

  First, the timer interrupt process will be described. In FIG. 9B, the process in the case where the production motors M1 to Mn are provided is indicated by broken lines. In the embodiment in which the effect motors M1 to Mn are provided, the drive data is updated when necessary to advance the stepping motor by one step at every predetermined timing (ST20). And this drive data is output to each effect motor M1-Mn, and when there exists control command CMD 'which should be transmitted to image control part 23', this is output toward image control part 23 '. (ST22).

  Finally, the interrupt counter is incremented to finish the interrupt process (ST23).

  Next, the main process will be described. The CPU repeatedly checks the interrupt counter and waits until the value of the interrupt counter becomes 16 (ST10). As described above, since the interrupt counter is updated every 1 mS (ST23), in step ST10, an elapsed time until 16 mS elapses from the process of the previous step ST11 is waited. That is, in this embodiment, steps ST11 to ST17 are repeated every 16 ms.

  Therefore, when the standby time of 16 mS has elapsed, the interrupt counter is cleared to zero (ST11), the control command CMD transmitted from the main control unit 21 is analyzed, and the operation corresponding to the control command CMD is executed. Therefore, necessary start processing is executed. For example, when a variation pattern command CMD is received, start processing such as a lamp effect and a sound effect is executed based on the control command CMD.

  Next, a switch signal such as the chance button 11 is determined (ST13), and an effect scenario for the effect to be newly executed is constructed or an effect scenario for the effect being executed is updated (ST14). Then, the audio reproduction operation is advanced in response to the production scenario (ST15).

  Subsequently, for the LEDs connected to each of the lamp drive substrates 36, 29, and 30, the brightness data defining the brightness is updated and stored in the output buffer table TBL (ST16). In this embodiment, a total of 3 × 5 × 24 LEDs are arranged on the three lamp driving substrates 36, 29, and 30, and each LED is based on 16-gradation 4-bit long luminance data. Lighting control. Therefore, the output buffer table TBL is 3 × 5 × 24/2 bytes long.

  Next, the brightness data of the output buffer table TBL updated in the process of step ST16 is transmitted to each of the lamp drive boards 36, 29, 30 via the serial ports S0 to S2 (ST17). However, the CPU is not in charge of the transmission process itself, but the CPU only writes necessary data to the transmission data register DR of the serial ports S0 to S2 at an appropriate timing, and the control burden on the CPU is extremely small. It is. Also, as shown in FIG. 8, serial data is transmitted all at once to the three lamp driving substrates 36, 29, and 30, so the processing time of step ST17 is not long regardless of the amount of transmission data.

  As shown in FIG. 8, the number of clock signals CK required to set the luminance data for the three drivers DR mounted on the three lamp driving boards 36, 29, and 30 is 8 × (2 + 24), and transmission starts. The timing and the transmission end timing are substantially the same for all three drivers DR.

  Therefore, the time required to update the lighting states of the three drivers DR mounted on the three lamp driving substrates 36, 29, and 30 is approximately 8 × (2 + 24) × T, and 8 × 26 × 5 × T. It is possible to update the lighting states of all 15 drivers in a certain processing time. The processing time for all the 15 drivers is substantially the same as the time required to update the lighting states of the five drivers.

  Here, T is the pulse period of the clock signal, and in this embodiment, T = 0.25 to 0... Corresponding to the clock signal having a frequency of about 4 to 5 MHz based on the set value to the baud rate generator BG. 2 μS. Therefore, the entire processing time is about 0.2 mS, and processing time for other processing is not consumed.

  However, even if the operation is performed at a low speed of the pulse period T = 1 μS, the entire processing time is about 1 mS, and the ratio of the total processing time (16 mS) in the main processing is not high. There is no adverse effect on the processing.

  FIG. 10 is a flowchart for explaining the LED output process (ST17) in more detail. In the LED output process, first, initialization data is transmitted to all 15 drivers DRij, and the LED is set to be turned on in accordance with the luminance data (PWM value) written in the gradation register. .

  Note that the processing in step ST17 is the same as the procedure shown in FIG. 8, and the processing procedures in steps ST31 to ST45 shown below are adopted. That is, the slave address transmission → register number transmission → initialization data transmission processing is collectively executed for predetermined drivers (three) of the channels CH0 to CH2, and this processing is repeated five times to obtain 15 The initialization process for each driver DRij is completed. Therefore, the total processing time is about 8 × 3 × 5 × T [= data bit length 8 × data number 3 × repetition processing count 5 × clock cycle T].

  It is not always necessary to repeat such initialization processing every 16 ms, but in this embodiment, initialization data of all drivers DRij is transmitted every time the blinking state is updated. Even if the part is garbled, the abnormal operation due to garbled setting data is automatically resolved after 16 mS.

  When the initialization process is completed as described above (ST30), the process proceeds to the brightness data setting process (ST31 to ST45). At this start timing, as shown in FIG. 6B, the transmission permission bit TXE of each control register RG is at the OFF (L) level, the empty bit EMP is at the H level (empty level), and the clock The signal CK maintains the H level. Further, the operation enable signals ENABLE0 to ENABLE2 are at the L level.

  Continuing the description based on the above, in the brightness data setting process, first, the start slave address is specified for each of the five drivers DRij of the channels CH0 to CH2 (ST31). As shown in FIG. 7, in this embodiment, a series of slave addresses in an increment relationship are assigned to the five drivers DRij mounted on each lamp driving board, and the head address is 00H, 10H and 18H.

  Next, ON (H) level operation enable signals ENABLE0 to ENABLE2 are respectively output from the parallel output port Po '(ST32). As a result, all drivers DRij of all channels CH0 to CH2 can receive serial data.

  Therefore, for the serial ports S0 to S2, the transmission permission bit TXE of each control register RG is set to the ON level, and the transmission processing of the serial ports S0 to S2 is set to the permitted state (ST33). In addition, the three types of slave addresses that are initialized in the process of step ST31 or are updated in the process of step ST44 are respectively written in the transmission data registers DR of the serial ports S0 to S2 (ST33).

  As shown in FIG. 8, the empty bit EMP of the control register RG of each of the serial ports S0 to S2 transitions to the L level by the process of step ST33, and after a predetermined time (τ), the empty bit EMP returns to the H level. At the same time, the slave address transmission operation is started.

  Therefore, when the empty bit EMP returns to the H level (ST34), for the gradation registers GR0 to GR23 of each driver DRij, the head address of the register number is written to the transmission data register DR of the serial ports S0 to S2. (ST35). In this embodiment, since the register numbers of the gradation registers GR0 to GR4 are N = 15H to 1CH, 15H is written in the transmission data registers DR of the serial ports S0 to S2 in the process of step ST35, respectively. . In addition, the empty bit EMP changes from the H level to the L level (full level) by the process of step ST35.

  Thereafter, when the transmission of the first slave address is completed, the empty bit EMP returns to the H level (empty level) (ST36), and thereafter, the process proceeds to a transmission process of 24 luminance data.

  Specifically, first, the variable n is initialized to zero (ST37). Here, the variable n specifies the gradation registers GR0 to GR23, and the variable n = 1 to 24 corresponds to the gradation registers GR0 to GR23.

  Therefore, next, after incrementing the variable n (ST38), the luminance data (PWM value) for the gradation register GRn-1 of each channel CH0 to CH2 is read from the output buffer table TBL, and the serial ports S0 to S2 are read. Each is written in the transmission data register DR (ST39). In step ST36, after the empty bit EMP transits to the H level, the empty bit EMP returns to the L level, and the register number transmission operation is repeated. When this transmission operation ends, the empty bit EMP Transitions to the H level.

  Therefore, next, the process waits for the empty bit EMP to transition to the H level (ST40). If the transition to the H level occurs, the process proceeds to step ST38 unless the variable n reaches 24 (ST41). Therefore, the luminance data to the gradation registers GR0 to GR23 are sequentially written in the transmission data register DR of the serial ports S0 to S2 by the processing of steps ST38 to ST41.

  Note that the timing at which the variable n reaches 24 is only that the 24th byte of luminance data is written in the transmission data register DR of the serial ports S0 to S2, and this is acquired by the driver DRij. After about eight clock signals CK are output.

  Therefore, after consuming about eight clock signals CK (ST42), the operation permission signal ENABLE is returned to the prohibited level, and the transmission permission bit TXE of the control register RG is returned to the prohibited level (ST43). As a result, the lighting state of the LED driven by the driver DRij whose luminance data has been updated is updated.

  With the above processing, the luminance data setting processing and lighting update for the three drivers DRij for each channel 0 to 2 are completed. Next, the slave address is updated (ST44), and the next three drivers DRij are updated. The setting process is repeated (ST45).

  As described above, in the present embodiment, the setting process for each of the 24 gradation registers of the three drivers DRij is completed at once by the processes of steps ST32 to ST43, and this process is repeated five times. Processing can be completed.

  Then, the setting process for the three drivers starts almost simultaneously and ends almost simultaneously. Therefore, the total processing time is about 8 × 26 × NUM × T corresponding to the pulse period T of the clock signal and the total number TOTAL = NUM × 3 of the drivers DRij, and 24 × NUM × 3 LEDs. The setting process of luminance data can be finished very quickly.

  Although the embodiments of the present invention have been described in detail above, the specific contents do not particularly limit the present invention.

  For example, in the embodiment, for convenience of explanation, the numbers of drivers DRij and LEDs in the three-channel lamp driving boards 36, 29, and 30 are the same. However, in practice, it is natural that they are appropriately different. In such a case, when the setting process for the necessary driver DRij (ST32 to ST45 in FIG. 10) is completed, the subsequent setting process (ST32 to ST45) is skipped for that channel.

  Similarly, for the driver DRij in which the number of LEDs to be driven is less than 24, unnecessary setting processing (ST38 to ST41) is skipped by changing the processing in step ST41 in FIG.

  In the embodiment, for convenience of explanation, the setting process for all the drivers is executed every 16 mS. However, it is also preferable to divide this appropriately. FIG. 9C illustrates such an operation. Instead of the LED output process in step ST17 of FIG. 9A, an LED output process (ST24) corresponding to the value CNT of the interrupt counter is executed. doing.

  Specifically, when CT = 10, initialization data is transmitted to all drivers, and when CT = 11, setting data is transmitted to three drivers in the first stage. Similarly, since the setting data is transmitted to the three drivers corresponding to the interrupt counter value CNT, no problem occurs even if the setting data is increased.

  As setting data, it is conceivable to transmit data defining the operation mode of fade-in and fade-out in addition to the luminance data defining the duty ratio (PWM). On the other hand, it is also conceivable to transmit switch data defining the ON / OFF state instead of the luminance data, and additionally transmitting data defining the operation mode of fade-in and fade-out.

  In the embodiment, the three-channel CH0 to CH2 lamp driving board has been described. However, the number of serial ports to be used may be increased in accordance with the number of lamp driving boards.

  Further, it is preferable to drive the stepping motor using the same driver DRij. In this case, a mode in which a motor drive board is separately provided and serial drive data (switch data) is transmitted every 1 mS, for example, is considered. (Refer to ST21 in FIG. 9B). On the other hand, a stepping motor may be connected to the lamp driving board. In this case, it is preferable that the driver DRij for driving the stepping motor repeats the serial driving data transmission process in a short cycle.

  Further, in the embodiment shown in FIG. 6, every time 1-byte serial data is transmitted, the CPU writes the next 1-byte parallel data in the transmission data register DR. . That is, a FIFO (First In First Out) buffer capable of temporarily storing parallel data of a predetermined unit length (multiple bytes) is secured, and each time 1-byte serial data is transmitted, the next data is automatically stored in the transmission data register DR. In this case, the CPU replenishes the FIFO buffer with the next 1-byte data when, for example, a 1-byte space (empty area) is generated in the FIFO buffer. It was enough.

  In each of the above embodiments, the CPU exclusively reads the control register repeatedly and checks the empty bit EMP of the control register. However, the timing when the transmission data register DR becomes empty is used. It is also preferable to adopt a configuration in which the CPU is interrupted at the timing when the FIFO buffer is empty (empty area). In this case, in response to the interrupt request, the CPU may write 1-byte data into the transmission data register DR or write data of a predetermined unit length into the FIFO buffer.

  Furthermore, in order to minimize the processing time, the driver of the embodiment is slave address → register address → 1 byte drive data → 1 byte drive data → 1 byte drive data →... → 1 byte drive. Although the procedure of data ... was taken, it is not limited at all. That is, it is possible to add 2 bytes to the number of data to be transmitted, first transmit a start command (start command), and finally transmit an end command (period command). However, in this case as well, the start bit and stop bit are not used, and each command has a unit length (1 byte length).

  Further, for example, drive data that defines the lighting state of each lamp may be transmitted to a driver capable of driving 24 lamps in a state where the lamps to be driven are individually specified. In this case, for example, a start command → a slave address that defines the driver → a subaddress that specifies a lamp → a driving data for the lamp → a subaddress that specifies a lamp → a driving data for the lamp → a period command Serial data is sent in the procedure. In this case, the total number of bytes of data to be transmitted is 24 × 2 + 3 bytes for one driver.

  6 to 10, the timing for updating the lighting state is defined by the operation permission signals ENABLE0 to ENABLE2, but this point is not limited at all. That is, if a configuration in which an end command (period command) is transmitted at the end of a series of serial data, the lighting state can be updated based on the internal processing of the driver DRij that recognizes that the period command has been received.

  In this case, for example, an internal counter that circulates in the range of 0 to 127 is provided in each driver DRij, and after receiving a period command, the lighting state is updated when the internal counter reaches a predetermined value (for example, 127). Is preferred. When such a configuration is adopted, after the lighting state is updated (that is, after the internal counter reaches a predetermined value), the same serial data transmission process can be started. In this sense, the operation permission signals ENABLE0 to ENABLE2 and other control signals are not necessary.

  In the embodiment shown in FIGS. 6 to 10, five drivers DRi0 to DRi04 are connected to the three-channel serial ports (S0 to S2) (a total of 15 drivers). The number of DRij may be further increased. In the following description, the driver and the buffer are explicitly referred to as an LED driver DRij for convenience.

  When a large number of LED drivers DRij are connected to one serial port Si, the maximum input current capacity of the serial port Si and the buffer is taken into consideration, and the input portion of the LED driver DRij is not a bipolar current drive system. A unipolar voltage drive system is preferable. 12C and 12D illustrate two unipolar input circuits, and an LED driver DRij having such an input circuit is preferably used.

  Also, it is not always necessary to use a plurality of channel serial ports (S0 to S2), and a large number of LED drivers DRij may be connected to a single serial port. However, in this case, it is necessary to repeat the serial data transmission process (see ST32 to ST43 in FIG. 10) as many as the number of LED drivers, so it is preferable to speed up the clock signal CK to the limit.

  In this case, even if the input part of the LED driver DRij is of a unipolar type (voltage drive system), the waveform summary due to the input capacitance Cin is unavoidable, and there is a risk of malfunction if high-speed transmission is performed. Therefore, when a large number of LED drivers DRij are connected to a single serial port, a circuit configuration as shown in FIG. 11 is used.

  As shown in the figure, in the embodiment of FIG. 11, a total of 16 LED drivers DR01 to DR16 are connected to the serial port S0, and the serial data transmission process is repeatedly executed a total of 16 times. Here, when 16 LED drivers DRij are directly connected to the serial data SDATA line and the clock signal CK line, the total input capacity is 16 × Cin, and the stray capacity Cc of each line is added to this ( 16 × Cin + Cc), the waveform summary of the transmission signal is inevitable.

  Therefore, in the embodiment of FIG. 11, the collective buffer circuit BUF is arranged between the serial port S0 and the LED driver DRij, thereby eliminating waveform numeration and realizing high-speed serial transmission. Each of the collective buffer circuits BUF1 and BUF2 has the circuit configuration shown in FIG. 12A, and each of the collective buffer circuits BUF1 and BUF2 includes eight buffers. The input terminals A1 to A8 of each buffer are internally connected to an inverter circuit INV having a CMOS (Complementary Metal Oxide Semiconductor) configuration (see FIG. 12B).

  Thus, in the embodiment of FIG. 11, since the input circuit of the buffer has a CMOS configuration, the input current Cin is substantially zero, but the input capacitance Cin can cause the waveform noise. However, since the SDATA signal and the clock signal CK output from the serial port S0 are only connected to a limited (for example, four) inverter circuit INV, the entire input capacity is 4 × Cin, and the serial Even if the transmission distance from the port S0 to the inverter circuit INV is long, the waveform summary is not a problem, and there is no risk of malfunction even during high-speed transmission.

  Further, only a limited number (for example, four) of LED drivers DRij are connected to one buffer on the output side of the collective buffer circuit BUF, and the input circuit of each LED driver DRij is shown in FIG. 12 (c) and the unipolar type shown in FIG. 12 (d). Therefore, if the input capacity of the input circuit of the LED driver DRij is Cin, the combined capacity for each buffer output of the collective buffer circuits BUF1 and BUF2 is 4 × Cin, and even if the transmission distance from the buffer to the LED driver DRij is long, the waveform is There is no risk of malfunction, and there is no risk of malfunction during high-speed transmission.

  By the way, in the circuit configuration of FIG. 11, the operation enable signal ENABLE0 is used. However, it can be omitted and the circuit configuration of FIG. 13 can be obtained. In this case, there is an advantage that the wiring can be simplified. . However, a start command (start command) and a period command (end command) are added in response to the omission of the operation permission signal ENABLE0.

  That is, when updating the luminance data of 24 lamps, [start command] → [slave address that defines the LED driver] → [sub-address specifying the register corresponding to the first lamp] → [the register [Gradation data for] → [Subaddress specifying register corresponding to second lamp] → [Gradation data for that register] →... → [Subaddress specifying register corresponding to 24th lamp] → 24 × 2 + 3 bytes of serial data are transmitted to one driver in the procedure of [gradation data for the lamp] → [period command]. When the number of lamps whose luminance data is updated is N (<24), serial data of N × 2 + 3 bytes is transmitted.

  FIG. 14 is a flowchart showing a process of updating the luminance data (serial data transmission process) in the embodiment of FIG. Although not particularly limited, in this transmission process as well, as in the case of FIG. 10, first, the initial setting process is executed for all LED drivers (ST50). Specifically, for example, in accordance with the PWM value written in the gradation register (24 each) of each LED driver, initial setting is performed for each LED driver so that 24 LEDs are turned on.

  Next, a 1-byte start command (for example, FFH) is written in the transmission data register DR of the serial port S0 (ST51). Then, the start bit serial transmission of the start command is awaited by determining the empty bit EMP of the control register RG (ST52). When the empty bit EMP of the control register RG becomes EMP = 1, the slave address of the LED driver is written in the transmission data register DR (ST53). The slave address is nothing but the port number assigned to the LED driver.

  Next, it waits for the empty bit EMP to become EMP = 1 (ST54), and when serial transmission of the slave address (port number) is started, the variable n is initialized to zero (ST55). The variable n specifies the gradation registers GR0 to GR23, and the value (1 to 24) of the variable n corresponds to the gradation registers GR0 to GR23.

  Next, after incrementing the variable n (ST56), the subaddress is written to the transmission data register DR of the serial port S0 (ST57). Here, the sub-address is a register number that specifies the gradation registers GR0 to GR23, and is simply a value corresponding to the variable n. Next, it waits for the empty bit EMP to become EMP = 1 (ST58), and if EMP = 1, the luminance data to be transmitted to the gradation register specified by the previous subaddress (register number) is transmitted to the transmission data register. Write to DR (ST59). The luminance data (PWM value) is read from an appropriately configured output buffer table TBL (see FIG. 9).

  The same applies to the following, and when serial transmission of luminance data is started (ST60), unless it is the 24th luminance data (ST61 is No), the next subaddress (register number) is used as the transmission data register of the serial port S0. Writing to DR (ST56 to ST57), the same serial data transmission processing is repeated.

  On the other hand, when serial transmission of the 24th luminance data is started (Yes in ST61), a period command indicating that serial transmission to the LED driver is completed is subsequently written in the transmission data register DR ( ST62). When serial transmission of a period command is started (ST63), the transmission time is secured (ST64), the slave address (port number) is updated, and the same serial data transmission processing (ST51 to ST65) is performed. repeat. In this embodiment, serial data transmission processing (ST51 to ST65) is repeated a total of 16 times corresponding to the number of LED drivers. However, transmission processing (luminance data) is performed by using a high-speed clock signal CK. Update processing) can be completed quickly.

  Incidentally, in the case where a total of N LED drivers DRij are used and each LED driver DRij drives M LEDs, and all luminance data is updated, the total number of data is (M × 2 + 3) × If N = 16 and M = 24, 816 bytes = 6528 bits, which is a considerable value. However, for example, when a clock signal of about 10 Mz is used, the entire processing can be completed in a processing time of about 0.653 mS, and the processing time of other control processing is not short.

  Moreover, even if the clock signal CK is increased in speed, in this embodiment, the input part of the element directly connected to the CK line or the SDATA line is a unipolar type, and the number of such elements is limited. There is no risk of malfunction due to waveform numeration. Here, for convenience of explanation, it is assumed that each LED driver DRij drives 24 LEDs, and all luminance data is updated every time. However, a gradation register that is updated by one update process. By thinning out to 1 / X, the update processing time for each time can be reduced to about 1 / X. In this case, each update processing time is (M × 2 / X + 3) × N × τ corresponding to the cycle τ of the clock signal CK.

  Further, when a serial port provided with a FIFO buffer is used, the serial data transmission process shown in FIG. 14 can be simplified. As shown in FIG. 15B, the FIFO buffer is configured to be accessible from the CPU core, and is automatically transferred to the transmission data register DR for each byte sequentially from the data stored in the FIFO buffer first (First In First Out), the data is output as serial data SDATA via the transmission shift register SR.

  The processing in this case is, for example, as shown in FIG. 15A. Using the FIFO buffer and setting the byte length to be used in the control register RG of the serial port S0, steps ST50 to ST66 are performed. Processing is executed.

  Specifically, after the initialization data is output to the LED driver (ST50), a group of data is written to the FIFO buffer (ST53), and a wait is made for an empty area to be generated in the FIFO buffer (ST54). As described above, the data having a plurality of bytes written in the FIFO buffer is automatically transferred to the transmission data register DR for each byte, and is output as serial data SDATA via the transmission shift register SR. When the output of 1-byte serial data is completed, the fact is indicated in the corresponding flag of the control register RG. Therefore, the variable n is appropriately updated (ST55 to ST56), and the next 1-byte data is stored in the FIFO buffer. (ST57).

  The subsequent process is the same, and whenever a 1-byte length free area is generated in the FIFO buffer (ST58), the process of replenishing the next 1-byte data to the FIFO buffer (ST59) is repeated. When serial transmission of all data is completed, a period command may be written into the FIFO buffer (ST62).

  In the example of FIG. 15, the group of data (M × 2 + 3) to be transmitted is larger than the storage capacity of the FIFO buffer. However, a FIFO buffer having a storage capacity of M × 2 + 3 bytes is illustrated. If secured, the processing of steps ST53 to ST63 can be integrated, and the processing load on the CPU is reduced to a limit. For example, if M = 24, a 51-byte FIFO buffer is required. For example, the gradation data is divided into four gradation registers by dividing the 24 gradation registers into four equal parts and time-divided four times of LED output processing. If the configuration is used, the storage capacity of the FIFO buffer is 15 bytes long, which is very reasonable.

  Further, in the configuration of FIG. 7 in which the start command and the period command are not used, the serial data required for updating the M gradation registers is M + 2 bytes. Therefore, even when M = 24, the gradation register is divided into two. Thus, only by dividing the LED output processing into two, the storage capacity of the 14-byte FIFO buffer is sufficient.

  Furthermore, when N effect motors are driven by one driver, the PWM setting value (= drive data: corresponding to the brightness data defining the brightness of the LED) to the gradation register supplied to the N effect motors. ) Becomes N bytes as a whole.

  Therefore, in the configuration of FIG. 7 that does not use the start command and the period command, it is sufficient to transmit N + 2 byte data to update the operation state of the N production motors, and if a 16 byte FIFO buffer is used. The set values for the 14 effect motors can be rewritten by a single write process to the FIFO buffer. For example, when the production motor is stepped at an interrupt interval of 1 mS, the CPU only has to write 16 bytes of drive data to the FIFO buffer at a time in each interrupt process, so the processing burden on the CPU is extremely reduced. The

  As described above, various embodiments have been described by taking the bullet feeding game machine as an example. However, the application of the present invention is not limited to the bullet ball gaming machine.

GM gaming machine 22 'presentation control unit DRij driver CK clock signal SDATA serial signal S0 serial port DR transmission data register SR transmission shift register ST51 first means ST53 second means ST57 third means

Claims (7)

Based on a control command received from another control means, a gaming machine provided with an effect control means having a CPU for controlling the light emission of the lamp in a predetermined manner,
The production control means is provided with a serial port for outputting a serial signal to be transmitted to the driver together with a clock signal, while a plurality of drivers having substantially the same configuration capable of driving the lamp are disposed.
The serial port is
A transmission data register that temporarily stores parallel data; and a transmission shift register that serially outputs data received from the transmission data register in synchronization with a level change of the clock signal.
First means for outputting to the transmission data register a start command indicating that transmission of a series of serial signals is started;
After the first means functions, the second means for outputting a driver address specifying one of the drivers to the transmission data register; and after the second means functions, specify any of the lamps that can be driven by the driver A third means for outputting a register address to the transmission data register;
And a fourth means for outputting lighting data defining the lighting state of the lamp specified by the register address to the transmission data register after the third means has functioned. .   The game machine according to claim 1, wherein the operations of the third means and the fourth means are repeated by the number of lamps whose lighting state is updated among all the lamps that can be driven by the driver specified by the second means.   3. The fifth means according to claim 2, further comprising a fifth means for outputting an end command indicating that transmission of a series of serial signals is completed to the transmission data register after the operations of the third means and the fourth means are repeated as many times as necessary. Gaming machine.   4. The gaming machine according to claim 3, wherein the driver that has received the end command updates the lighting state of the lamp based on the lighting data received so far at a predetermined timing thereafter.   The gaming machine according to claim 4, wherein the predetermined timing is defined by a counter inside the driver.   The transmission of the lighting data to the driver and the update of the lamp lighting state by the driver receiving the lighting data are defined by a 1-bit clock signal and a 1-bit serial signal transmitted from the serial port. The gaming machine according to any one of claims 1 to 5, wherein transmission of signals other than the above is unnecessary.   7. The serial port according to claim 1, further comprising: a baud rate generator that outputs a clock signal; and a control register configured so that the CPU can grasp the operation content being executed. Game machines.

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