JP2014132381A - Reception circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress malfunction in training operation.SOLUTION: An interface circuit 23 terminates transmission paths L1, L2 with a terminal circuit 36 in training operation, and adjusts the resistance value of the terminal circuit 36 to offset data strobe signals DQS, xDQS, i.e. potentials of the transmission path L1 and the transmission path L2. An input buffer 37 outputs an internal strobe signal DQSi of level L according to a potential difference between the data strobe signals DQS, xDQS, i.e. a difference between the potential of the transmission path L1 and the potential of the transmission path L2.

Description

  The present invention relates to a receiving circuit.

  Conventionally, a semiconductor memory device, for example, a dynamic random access memory (DRAM) is used for storing data of a system device. A double data rate semiconductor memory device that inputs and outputs data both at the rising edge and the falling edge of the clock corresponds to an increase in the operating speed of the system apparatus. Such a semiconductor memory device is called DDR-SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), DDR2-SDRAM, or DDR3-SDRAM.

  The system device outputs a command (for example, a read command) to the memory. The memory outputs a data strobe signal in response to the read command, and outputs read data in synchronization with the data strobe signal. A receiving circuit in the system apparatus adjusts the timing of the data strobe signal and takes in the read data based on the adjusted data strobe signal (see, for example, Patent Document 1).

  The transmission path (signal line) for transmitting the data strobe signal is also used when data is transmitted from the system LSI to the memory. That is, the above transmission path is used for bidirectional communication. For this reason, the system apparatus and the memory place the transmission path in a high impedance (Hi-Z) state when communication is not performed. Then, after the transmission path is set to the preamble state, a signal is transmitted. The receiving circuit has a function of detecting a preamble state, and takes in data according to the detection result.

  The level of the transmission line in the high impedance state varies due to, for example, external noise. This level fluctuation in the transmission path may cause a malfunction of the receiving circuit. For this reason, the receiving circuit uses a mask signal for the data strobe signal and does not use the level in the transmission line in the high impedance state. For example, the receiving circuit of the system apparatus inputs the received data strobe signal and mask signal to the AND circuit, and uses the output signal of the AND circuit as the internal strobe signal. Then, the receiving circuit of the system apparatus prevents the malfunction due to the transmission line in the high impedance state by setting the mask signal to a predetermined level (for example, L level) at a predetermined timing from the transmission of the read command.

JP 2007-109203 A

  Incidentally, the timing of the data strobe signal output from the memory varies depending on the connection state between the system apparatus and the memory, the operating environment (temperature), and the like. For this reason, the receiving circuit of the system apparatus performs a training operation and sets the timing at which the mask signal is set to a predetermined level (L level) according to the data strobe signal output from the memory. In setting the timing of the mask signal, it is necessary to change the mask signal over a wide range. In this case, if the timing for changing the level of the mask signal is in a period of high impedance, an error occurs in the timing setting of the mask signal. That is, the high impedance state in the transmission path causes a malfunction in the training operation.

  According to one aspect of the present invention, a receiving circuit that receives data according to a strobe signal that specifies a preamble by a first potential, and generates a mask signal that masks the strobe signal at a timing according to setting information A mask signal generation circuit that performs activation, deactivation according to a termination control signal, a termination circuit that terminates a transmission path through which the strobe signal is transmitted when activated, and an adjustment unit that adjusts a resistance value of the termination circuit A detection unit that detects whether the potential of the transmission line is the first potential or a second potential different from the first potential, and outputs a detection signal according to a detection result, and according to the mask signal And a gate circuit that generates an internal strobe signal based on the detection signal, and the adjustment unit has a resistance value of the termination circuit and a potential of the transmission line within a power supply voltage range during a reception operation. The termination is performed by adjusting the first resistance value to be a center voltage and adjusting the setting information according to the internal strobe signal so that the potential of the transmission line is adjusted by a predetermined voltage offset from the center voltage. The resistance value of the circuit is adjusted to the second resistance value.

  According to one aspect of the present invention, malfunctions in training operations can be suppressed.

1 is a schematic block diagram of a system. It is a block diagram of the memory interface circuit of the first embodiment. It is a circuit diagram of a termination circuit. (A), (b) is a circuit diagram of a termination resistance control circuit. (A)-(c) is an equivalent circuit schematic of a termination circuit. It is a wave form diagram for demonstrating read operation | movement. It is a wave form diagram for demonstrating operation | movement of the termination circuit at the time of read-operation. It is a wave form chart for explaining operation of a termination circuit at the time of training operation. (A) is a waveform diagram showing a data strobe signal during a read operation, and (b) is a waveform diagram showing a data strobe signal and an internal strobe signal during a training operation. It is a wave form diagram for demonstrating training operation | movement. 1 is a schematic block diagram of a system. It is a wave form diagram of a clock signal and a data strobe signal in a system. It is a block diagram of a memory interface circuit of a second embodiment. It is a wave form diagram for demonstrating read operation | movement. It is a wave form diagram which shows a data strobe signal and an internal strobe signal.

(First embodiment)
As shown in FIG. 1, the system includes a control device 11 and a memory device 12 accessed by the control device 11. The control device 11 is, for example, one chip (semiconductor integrated circuit device: LSI, for example, SoC (System on Chip)). The memory device 12 is a synchronous semiconductor memory device, for example, a DDR3-SDRAM (Double Data Rate 3 Synchronous Dynamic Random Access Memory).

The control device 11 includes a core circuit 21, a memory controller 22, and an interface circuit 23.
The core circuit 21 outputs a request or the like corresponding to the process to be executed to the memory controller 22. For example, the core circuit 21 outputs a write request for writing data to the memory device 12 and an address for storing the data to the memory controller 22. Further, the core circuit 21 outputs a read request for reading data in the memory device 12 and an address at which the data is stored to the memory controller 22 in accordance with processing to be executed. The core circuit 21 is, for example, a central processing unit (CPU).

  The memory controller 22 outputs the internal clock signal CLK of the memory controller 22 to the interface circuit 23. The interface circuit 23 operates based on the internal clock signal CLK. The interface circuit 23 supplies complementary clock signals CK and XCK generated based on the internal clock signal CLK to the memory device 12.

The memory controller 22 accesses the memory device 12 via the interface circuit 23 in response to a request from the core circuit 21.
For example, when the request from the core circuit 21 is a write request, the memory controller 22 outputs a write command, an address, and data IDQ. The interface circuit 23 outputs a command CMD, an address, a data strobe signal DQS, and data DQ. The memory device 12 receives the data DQ based on the clock signals CK and XCK and the data strobe signal DQS, and stores the data DQ in an area corresponding to the address based on the command CMD.

  When the request from the core circuit 21 is a read request, the memory controller 22 supplies a command CMD (here, a read command) and an address to the memory device 12 via the interface circuit 23. In response to the read command, the memory device 12 reads data from the area corresponding to the address. The memory device 12 outputs a data strobe signal DQS (preamble) at a predetermined level for a predetermined period (for example, one cycle of the clock signal CK), and then outputs a pulsed data strobe signal DQS corresponding to the cycle of the clock signal CK. To do. Then, the memory device 12 outputs the read data DQ in synchronization with the transition timing of the data strobe signal DQS. Then, after sending the data DQ, the memory device 12 outputs a data strobe signal DQS (postamble) of a predetermined level for a predetermined period. The interface circuit 23 receives the data DQ based on the data strobe signal DQS and outputs an internal strobe signal IDQS and data IDQ corresponding to the period. The memory controller 22 receives the data IDQ based on the internal strobe signal IDQS.

  Further, the memory controller 22 outputs a training enable signal (hereinafter simply referred to as an enable signal) TEN to the interface circuit 23 at a predetermined timing. The predetermined timing is a timing at which the core circuit 21 does not access the memory device 12 when the control device 11 is activated or during the operation of the control device 11, for example. In response to the enable signal TEN, the interface circuit 23 executes training for calibrating (adjusting) the timing for taking in the data string DQ.

The interface circuit 23 includes a mask signal generation circuit 31 and a training circuit 32.
The mask signal generation circuit 31 generates the DQS mask signal DQSM so as not to output the unnecessary internal strobe signal IDQS. The memory controller 22 receives the data IDQ based on the internal strobe signal IDQS. Therefore, the unnecessary internal strobe signal IDQS becomes a factor for receiving erroneous data IDQ. The period necessary for receiving the data IDQ is a period from the preamble to the postamble in the data strobe signal DQS. The mask signal generation circuit 31 generates a DQS mask signal corresponding to this period.

  The timing of the DQS mask signal DQSM is set according to the arrival of the data strobe signal DQS and the inverted data strobe signal xDQS output from the memory device 12. The memory device 12 operates based on the clock signals CK and XCK output from the control device 11, and outputs the data strobe signals DQS and xDQS in a predetermined period from the arrival of the clock signal CK. The mask signal generation circuit 31 generates the DQS mask signal DQSM at a timing according to the arrival of the data strobe signals DQS and xDQS output from the memory device 12. The data strobe signal DQS is an example of a first strobe signal, and the inverted data strobe signal xDQS is an example of a second strobe signal.

  The interface circuit 23 outputs an internal strobe signal IDQS corresponding to the data strobe signal DQS based on the DQS mask signal. Specifically, when the DQS mask signal is at L level (inactive), the internal strobe signal IDQS at L level can be output to the memory controller 22. When the DQS mask signal DQSM is at the H level (active), the internal strobe signal IDQS having a level equal to the level of the data strobe signal DQS is output to the memory controller 22.

  The training circuit 32 executes training in response to the enable signal TEN from the memory controller 22. The training circuit 32 receives the DQS mask signal DQSM according to the transition timing of the data strobe signal DQS input from the memory device 12 from the first potential (low potential) to the second potential (high potential) higher than the first potential. Adjust the activation timing. Specifically, the training circuit 32 sweeps the DQS mask signal DQSM and detects the transition of the data strobe signal DQS (the rising edge after the preamble) based on the DQS mask signal DQSM and the data strobe signal DQS. Then, the training circuit 32 sets the mask signal generation circuit 31 so as to activate the DQS mask signal DQSM during the preamble period of the data strobe signal DQS. Such a DQS mask signal DQSM suppresses the output of the internal strobe signal IDQS based on the data strobe signal DQS in the high impedance state (Hi-Z state) to the memory controller 22.

  As shown in FIG. 2, the interface circuit 23 includes a mask signal generation circuit 31, a training circuit 32, buffer circuits 33 and 34, a termination resistance control circuit 35, a termination circuit 36, an input buffer 37, and an AND circuit 38. .

The buffer circuit 33 outputs a clock signal CKI corresponding to the internal clock signal CLK output from the memory controller 22.
The buffer circuit 34 is a differential output buffer and outputs complementary clock signals CK and XCK based on the clock signal CKI.

The mask signal generation circuit 31 includes a latency adjustment circuit 41, a timing adjustment circuit 42, and a register 43.
The latency adjustment circuit 41 outputs a delayed clock signal CKD obtained by delaying the clock signal CKI for a time corresponding to the delay between the buffer circuit 34 and the input buffer 37.

  The timing adjustment circuit 42 operates based on the delayed clock signal CKD, and outputs a DQS mask signal DQSM with timing according to the adjustment information set in the register 43. The adjustment information corresponds to the preamble period of the internal strobe signal DQSi and is set according to the training result by the training circuit 32. For example, the adjustment information includes a transmission delay of the clock signals CK and XCK, a transmission delay of the data strobe signals DQS and xDQS, and an internal delay of the memory device 12.

  The timing adjustment circuit 42 outputs an H level DQS mask signal DQSM at a timing according to the adjustment information. The timing adjustment circuit 42 outputs an L-level DQS mask signal DQSM at a timing corresponding to the postamble period of the internal strobe signal DQSi. The memory device 12 outputs read data based on the clock signals CK and XCK, and then outputs a postamble, that is, a data strobe signal DQS having an L level for a predetermined period (an inverted data strobe signal xDQS having an H level). For example, the timing adjustment circuit 42 outputs the DQS mask signal DQSM of L level at a timing corresponding to the count value obtained by counting the delayed clock signal CKD output from the latency adjustment circuit 41 and the number of bursts of read data.

  Termination resistance control circuit 35 includes registers 35a and 35b. A first setting code is stored in the register 35a. The register 35b stores a second setting code. The first control code and the second control code are multi-bit codes corresponding to the termination circuit 36. The termination resistance control circuit 35 outputs a control code corresponding to the setting code stored in the registers 35a and 35b in response to the enable signal TEN. For example, the termination resistance control circuit 35 outputs a control code based on the first setting code stored in the register 35a in response to a first level (for example, L level) enable signal TEN. Further, the termination resistance control circuit 35 outputs a control code based on the second setting code stored in the register 35b in response to the enable signal TEN of the second level (for example, H level). The termination resistance control circuit 35 is an example of an adjustment unit.

  The termination circuit 36 includes a termination resistor RT1a connected between the transmission line L1 and a wiring for supplying the high potential voltage VDD (hereinafter referred to as power supply wiring VDD), and a wiring for supplying the transmission line L1 and the low potential voltage VSS (hereinafter referred to as power supply wiring VDD). Terminal resistor RT1b connected to the power supply wiring VSS). The termination circuit 36 includes a termination resistor RT2a connected between the transmission line L2 and the high-potential-side power supply wiring VDD, and a termination resistor connected between the transmission path L2 and the low-potential-side power supply wiring VSS. RT2b is included. The resistance values of the termination resistors RT1a and RT1b can be changed. Similarly, the resistance values of the termination resistors RT1a and RT2b can be changed. The termination circuit 36 is activated or deactivated based on the termination control signal SODT. The activated termination circuit 36 terminates the transmission lines L1 and L2 with a resistance value corresponding to the control code output from the termination resistance control circuit 35. The deactivated termination circuit 36 does not terminate the transmission lines L1 and L2. The transmission line L1 is an example of a first transmission line, and the transmission line L2 is an example of a second transmission line.

  The input buffer 37 outputs an internal strobe signal DQSi having a level corresponding to the levels of the data strobe signals DQS and xDQS in the transmission lines L1 and L2. The input buffer 37 is an example of a detection unit. Data strobe signals DQS and xDQS are examples of received signals. The non-inverting input terminal of the input buffer 37 is connected to the transmission line L1, and the inverting input terminal is connected to the transmission line L2. The input buffer 37 outputs the internal strobe signal DQSi based on the voltage difference between the data strobe signals DQS and xDQS supplied from the memory device 12 via the transmission lines L1 and L2. The input buffer 37 is an example of a detection unit.

  For example, a voltage for recognizing the data strobe signals DQS and xDQS as differential is set as a differential recognition voltage. In the input buffer 37, the data strobe signal DQS is lower than the inverted data strobe signal xDQS, and the difference voltage ΔV between the data strobe signals DQS and xDQS (= the voltage value VxDQS of the inverted data strobe signal xDQS−the voltage value VDQS of the data strobe signal DQS). When the voltage is equal to or higher than the differential recognition voltage, the internal strobe signal DQSi at the low potential voltage VSS level (L level) is output.

  The AND circuit 38 outputs an internal strobe signal IDQS corresponding to the result of logical product operation of both signals based on the DQS mask signal DQSM and the internal strobe signal DQSi. For example, the AND circuit 38 outputs the L-level internal strobe signal IDQS based on the L-level DQS mask signal DQSM. Then, the AND circuit 38 outputs the internal strobe signal IDQS having a level equal to the level of the internal strobe signal DQSi based on the DQS mask signal DQSM at the H level. That is, the AND circuit 38 passes or blocks the internal strobe signal DQSi according to the DQS mask signal DQSM. The AND circuit 38 is an example of a gate circuit.

  The training circuit 32 is activated in response to, for example, an H level enable signal TEN, and deactivated in response to an L level enable signal TEN. The activated training circuit 32 performs a training operation for the DQS mask signal DQSM. For example, the training circuit 32 controls the timing adjustment circuit 42 to sweep the DQS mask signal DQSM. Then, the training circuit 32 sets adjustment information for the DQS mask signal DQSM in the register 43 based on the DQS mask signal DQSM and the internal strobe signal DQSi.

  The register 43 outputs a control code corresponding to the set adjustment information. The timing adjustment circuit 42 outputs an H level DQS mask signal DQSM at a timing according to the control code output from the register 43.

  As shown in FIG. 3, the inverter circuit 51 of the termination circuit 36 outputs a termination control signal xSODT obtained by logically inverting the termination control signal SODT. Termination control signal SODT is supplied to termination resistors RT1b and RT2b, and termination control signal xSODT is supplied to termination resistors RT1a and RT2a.

  The termination resistor RT1a includes resistors R00 to R03, transistors T00 to T03, and OR circuits 61 to 64. The transistors T00 to T03 are, for example, P channel MOS transistors. Control signals SP0 to SP3 are supplied to the first terminals of the OR circuits 61 to 64, respectively, and the termination control signal xSODT is supplied to the second terminals in common. The output terminals of the OR circuits 61 to 64 are connected to the gate terminals of the transistors T00 to T03. The source terminals of the transistors T00 to T03 are connected to the power supply wiring VDD, and the drain terminals are connected to the first terminals of the resistors R00 to R03. The second terminals of the resistors R00 to R03 are connected to the transmission line L1.

  The OR circuits 61 to 64 output H level signals in response to the H level termination control signal xSODT. The transistors T00 to T03 are turned off in response to the H level signal output from the OR circuits 61 to 64. The OR circuit 61 outputs a signal having a level equal to the control signal SP0 in response to the L-level termination control signal xSODT. The transistor T00 is turned on / off according to the output signal level of the OR circuit 61. Similarly, the OR circuits 62 to 64 output signals having the same level as the control signals SP1 to SP3 in response to the L level termination control signal xSODT. The transistors T00 to T03 are turned on / off according to the output signal levels of the OR circuits 61 to 63.

  For example, the control signals SP0 to SP2 are set to L level and the control signal SP3 is set to H level. The OR circuits 61 to 62 output an L level signal, and the OR circuit 63 outputs an H level signal. Accordingly, the transistors T00 to T02 are turned on and the transistor T03 is turned off. The transmission line L1 is pulled up to the high potential voltage VDD by the turned on transistors T00 to T02 and the resistors R00 to R02. Therefore, the resistance value of the termination resistor RT1a is a value obtained by combining the resistance values of the transistors T00 to T02 and the resistors R00 to R02 that are turned on. That is, the termination resistor RT1a pulls up the transmission line L1 with a resistance value corresponding to the control signals SP0 to SP3.

  The termination resistor RT1b includes resistors R10 to R13, transistors T10 to T13, and AND circuits 71 to 74. The transistors T10 to T13 are, for example, N channel MOS transistors. Control signals SN0 to SN3 are supplied to the first terminals of the AND circuits 71 to 74, respectively, and the termination control signal SODT is supplied to the second terminals in common. The output terminals of the AND circuits 71 to 74 are connected to the gate terminals of the transistors T10 to T13. The source terminals of the transistors T10 to T13 are connected to the power supply wiring VDD, and the drain terminals are connected to the first terminals of the resistors R10 to R13. The second terminals of the resistors R10 to R13 are connected to the transmission line L1.

  The AND circuits 71 to 74 output L level signals in response to the L level termination control signal SODT. The transistors T10 to T13 are turned off in response to the L level signal output from the AND circuits 71 to 74. The AND circuits 71 to 74 output signals having a level equal to the control signals SN0 to SN3 in response to the termination control signal SODT having the H level. The transistors T10 to T13 are turned on / off according to the output signal levels of the AND circuits 71 to 74.

  For example, the control signals SN0 to SN2 are set to H level and the control signal SN3 is set to L level. The AND circuits 71 to 73 output an H level signal, and the AND circuit 74 outputs an L level signal. Accordingly, the transistors T10 to T12 are turned on and the transistor T13 is turned off. The transmission line L1 is pulled down to the low potential voltage VSS by the turned on transistors T10 to T12 and resistors R10 to R12. Therefore, the resistance value of the termination resistor RT1b is a value obtained by combining the resistance values of the transistors T10 to T12 and the resistors R10 to R12 that are turned on. That is, the termination resistor RT1b pulls down the transmission line L1 with a resistance value corresponding to the control signals SN0 to SN3.

  As described above, when the termination control signal SODT is at the H level (termination control signal xSODT is at the L level), the transmission line L1 is pulled up by the termination resistor RT1a and pulled down by the termination resistor RT1b. Therefore, the potential of the transmission line L1 becomes a value corresponding to the ratio between the resistance value of the termination resistor RT1a and the resistance value of the termination resistor RT1b.

  Similarly to the termination resistor RT1a, the termination resistor RT2a includes resistors R20 to R23, transistors T20 to T23, and OR circuits 65 to 68. The transistors T20 to T23 are, for example, P channel MOS transistors. The control signals xSP0 to xSP3 are supplied to the first terminals of the OR circuits 65 to 68, respectively, and the termination control signal xSODT is supplied to the second terminals in common. The output terminals of the OR circuits 65 to 68 are connected to the gate terminals of the transistors T20 to T23. The source terminals of the transistors T20 to T23 are connected to the power supply wiring VDD, and the drain terminals are connected to the first terminals of the resistors R20 to R23. The second terminals of the resistors R20 to R23 are connected to the transmission line L2.

  Similarly to the termination resistor RT1b, the termination resistor RT2b includes resistors R30 to R33, transistors T30 to T33, and AND circuits 75 to 78. The transistors T30 to T33 are, for example, N channel MOS transistors. Control signals xSN0 to xSN3 are supplied to first terminals of the AND circuits 75 to 78, respectively, and a termination control signal SODT is supplied to the second terminals in common. The output terminals of the AND circuits 75 to 78 are connected to the gate terminals of the transistors T30 to T33. The source terminals of the transistors T30 to T33 are connected to the power supply wiring VDD, and the drain terminals are connected to the first terminals of the resistors R30 to R33. The second terminals of the resistors R30 to R33 are connected to the transmission line L2.

  The termination resistor RT2a pulls up the transmission line L2 with a resistance value corresponding to the control signals xSP0 to xSP3 in response to an H level termination control signal SODT (L level termination control signal xSODT). The termination resistor RT2b pulls down the transmission line L2 with a resistance value corresponding to the control signals xSN0 to xSN3 in response to an H level termination control signal SODT (L level termination control signal xSODT). Therefore, the potential of the transmission line L2 becomes a value corresponding to the ratio of the resistance value of the termination resistor RT2a and the resistance value of the termination resistor RT2b.

  The combined resistance value of the turned-on transistor T00 and the resistor R00 and the combined resistance value of the turned-on transistor T10 and the resistor R10 are set to be equal to each other. The same applies to the other transistors T01 to T33 and resistors R01 to R33. For example, resistance values of the resistors R00 to R03, R10 to R13, R20 to R23, R30 to R33, resistance values when the transistors T00 to T03, T10 to T13, T20 to T23, and T30 to T33 are turned on (on resistance) Value) are set to the same value.

  As shown in FIG. 4A, the termination resistance control circuit 35 includes registers 35a and 35b and a selector 35c. The register 35a outputs control signals CPn, CNn, xCPn, XCNn (n = 0 to 3) corresponding to the first control code. The register 35b outputs control signals TPn, TNn, xTPn, xTNn (n = 0 to 3) corresponding to the second control code.

  The selector 35c selects the control signal output from the register 35a or the control signal output from the register 35b in response to the enable signal TEN, and the control signals SPn, SNn, xSPn, xSNn having the same level as the selected control signal. (N = 0 to 3) is output.

As shown in FIG. 4B, the selector 35c includes selectors 81-84.
The selector 81 selects the control signal CP0 or the control signal TP0 based on the enable signal TEN, and outputs a control signal SP0 having a level equal to the level of the selected control signal. For example, the selector 81 outputs a control signal SP0 having a level equal to the level of the control signal CP0 selected according to the L level enable signal TEN. The selector 81 outputs a control signal SP0 having a level equal to the level of the control signal TP0 selected according to the H level enable signal TEN.

  Similarly, the selector 82 selects the control signal xCP0 or the control signal xTP0 based on the enable signal TEN, and outputs a control signal xSP0 having a level equal to the level of the selected control signal. The selector 83 selects the control signal CN0 or the control signal TN0 based on the enable signal TEN, and outputs a control signal SN0 having a level equal to the level of the selected control signal. Similarly, the selector 84 selects the control signal xCN0 or the control signal xTN0 based on the enable signal TEN, and outputs a control signal xSN0 having a level equal to the level of the selected control signal.

  Control signals CP1-CP3, xCP1-xCP3, CN1-CN3, xCN1-xCN3, TP1-TP3, xTP1-xTP3, TN1-TN3, xTN1-xTN3, SP1-SP3, xSP1-xSP3, SN1-SN3, xSN1- Since xSN3 is the same as that in FIG. 4B, the drawing and description are omitted.

  5A to 5C show states of the termination circuit 36 (termination resistors RT1a to RT2b) based on the termination control signal SODT (xSODT) and the control signals SPn, SNn, xSPn, and xSNn (N = 0 to 3). Show.

  FIG. 5A shows the state of the termination circuit 36 based on the L-level termination control signal SODT (H-level termination control signal xSODT). The transistors T00 to T03 and T20 to T23 shown in FIG. 3 are turned off based on the L-level termination control signal SODT, and the transistors T10 to T13 and T30 to T33 are turned off based on the H-level termination control signal xSODT. Therefore, as shown in the upper part of FIG. 5A, the resistance values of the termination resistors RT1a and RT1b are infinite (∞ [Ω]) and do not terminate the transmission line L1. Similarly, as shown in the lower part of FIG. 5A, the resistance values of the termination resistors RT2a and RT2b are infinite (∞ [Ω]) and do not terminate the transmission line L2.

  FIG. 5B is based on an H-level termination control signal SODT (L-level termination control signal xSODT) and a first setting code (control signals SPn, SNn, xSPn, xSNn (N = 0 to 3)). The state of termination circuit 36 (termination resistors RT1a to RT2b) is shown.

  In the termination resistors RT1a to RT2b shown in FIG. 3, the same number (for example, three) of transistors are turned on based on the control signals SPn, SNn, xSPn, and xSNn (N = 0 to 3). Therefore, as shown in the upper part of FIG. 5B, the resistance values of the termination resistors RT1a and RT1b are equal to each other (R1), and the level of the transmission line L1 is set between the high potential voltage VDD and the low potential voltage VSS. Level. Similarly, as shown in the lower part of FIG. 5B, the resistance values of the termination resistors RT2a and RT2b are equal to each other (R1), and the level of the transmission line L2 is changed between the high potential voltage VDD and the low potential voltage VSS. Intermediate level. The resistance value R1 is an example of a first resistance value.

  The resistance values (R1) of the termination resistors RT1a to RT2b are based on the first setting code set in the register 35a shown in FIG. This first setting code is set according to the characteristic impedance of the transmission lines L1 and L2. For example, the first setting code is set so that the resistance values of the termination resistors RT1a to RT2b are equal to the characteristic impedances of the transmission lines L1 and L2. Thereby, in the read operation with respect to the memory device 12 shown in FIG. 1, reflection of signals is suppressed, signal quality is improved, and high-speed data transfer is enabled.

  FIG. 5C is based on the H-level termination control signal SODT (L-level termination control signal xSODT) and the second setting code (control signals SPn, SNn, xSPn, xSNn (N = 0 to 3)). The state of termination circuit 36 (termination resistors RT1a to RT2b) is shown. In the termination resistors RT1a and RT1b shown in FIG. 3, a number of transistors corresponding to the control signals SPn and SNn (N = 0 to 3) are turned on. Therefore, as shown in the upper part of FIG. 5C, the resistance values of the termination resistors RT1a and RT1b are R2a and R2b, respectively, and the level of the transmission line L1 is a level corresponding to the ratio of the respective resistance values R2a and R2b. And In the termination resistors RT2a and RT2b shown in FIG. 3, a number of transistors corresponding to the control signals xSPn and xSNn (N = 0 to 3) are turned on. Therefore, as shown in the lower part of FIG. 5C, the resistance values of the termination resistors RT2a and RT2b are R2b and R2a, respectively, and the level of the transmission line L2 is a level corresponding to the ratio of the respective resistance values R2b and R2a. And The resistance values R2a and R2b are examples of the second resistance value.

The resistance values (R2a, R2b) of the termination resistors RT1a to RT2b are based on the second setting code set in the register 35b shown in FIG.
The second setting code is terminated by termination resistors RT1a to RT2b having resistance values corresponding to the characteristic impedances of the transmission lines L1 and L1, and the potentials of the transmission lines L1 and L2 are offset in a predetermined direction from the median value of the power supply voltage range. Set to do. For example, the potential of the transmission line L1 to which the data strobe signal DQS is transmitted is offset to the low potential voltage VSS side, and the potential of the transmission line L2 to which the inverted data strobe signal xDQS is transmitted is offset to the high potential voltage VDD side. Is set.

  The difference (offset amount) between the offset potentials of the transmission lines L1 and L2 and the median value of the power supply voltage range is set according to the differential recognition voltage of the data strobe signals DQS and xDQS. The input buffer 37 outputs an internal strobe signal DQSi of H level or L level according to the level (potential) of the signals supplied to both input terminals, that is, the potential difference between the transmission lines L1 and L2.

  For example, the high potential voltage VDD is 1.5 [V], the low potential voltage VSS is 0 [V], and the intermediate voltage VREF is 0.75 [V]. The voltage for recognizing the data strobe signals DQS and xDQS as differential (differential recognition voltage) is 0.2 [V]. The input buffer 37 outputs the internal strobe signal DQSi at the low potential voltage VSS level (L level) when the potential of the transmission line L1 is lower than the potential of the transmission line L2 and the difference voltage between them is equal to or higher than the differential recognition voltage.

  For this reason, the second setting code offsets the potential of the transmission line L1 from the intermediate voltage VREF to a voltage that is ½ lower than the differential recognition voltage (VREF−0.1 [V]). Is set to be offset from the intermediate voltage VREF to a voltage (VREF + 0.1 [V]) that is 1/2 the differential recognition voltage.

Next, the operation of the above system will be described.
First, an outline of the read operation in the above system will be described.
As shown in FIG. 6, the clock signal CK is generated based on the clock signal CKI. For example, at time t0 shown in FIG. 6, a read command is issued from the memory controller 22 shown in FIG. The memory device 12 illustrated in FIG. 2 receives a read command at time t1 based on the clock signal CK.

  Next, the memory controller 22 shown in FIG. 2 outputs an H-level termination control signal SODT at a timing according to the read operation (for example, read latency) of the memory device 12. At this time, the enable signal TEN is at the L level. Therefore, the termination resistance control circuit 35 outputs a control signal corresponding to the first setting code. The termination circuit 36 terminates the transmission lines L1 and L2 with termination resistors RT1a to RT2b having resistance values corresponding to the first setting code. At this time, the level of the data strobe signal DQS becomes an intermediate potential depending on the resistance values of the termination resistors RT1a to RT2b (resistance value R1 shown in FIG. 5B).

  The memory device 12 shown in FIG. 2 operates in response to a read command, and outputs a data strobe signal DQS at an L level during the preamble period and then outputs a data strobe at a timing according to the clock signal CK as shown in FIG. The signal DQS is transited in a pulse shape. The input buffer 37 shown in FIG. 2 outputs an internal strobe signal DQSi based on the data strobe signal DQS. The L level (low potential voltage VSS level) is an example of a first potential, and the H level (high potential voltage VDD level) is an example of a second potential.

  The mask signal generation circuit 31 shown in FIG. 2 outputs an H level DQS mask signal DQSM at a predetermined timing based on the timing (time t0) at which the read command is issued. Thereby, while the DQS mask signal DQSM is at the L level, the L level internal strobe signal IDQS is generated. The internal strobe signal IDQS is at the same level as the internal strobe signal DQSi after the preamble period.

Next, the operation of the termination circuit during the read operation will be described.
FIG. 7 shows an example of control signals SPn, SNn, xSPn, and xSNn (n = 0 to 3) that are output according to the first setting code. In FIG. 7, the letters “H” and “L” in parentheses indicate examples of logic levels of the control signals SPn, SNn, xSPn, and xSNn (n = 0 to 3). The characters “on” and “off” written on the right side of the equal sign indicate the states of the transistors T00 to T33 controlled by the control signals SPn, SNn, xSPn, and xSNn (n = 0 to 3) shown in FIG. .

  For example, in the read operation, the L level control signals SP0 to SP2 and the H level control signal SP3 are output from the termination resistance control circuit 35 shown in FIG. 2 according to the first setting code. Also, the H level control signal SN0 to SN2, the L level control signal SN3, the L level control signal xSP0 to xSP2, the H level control signal xSP3, the H level control signal xSN0 to xSN2, and the L level control signal xSN3. It is output from the termination resistance control circuit 35 shown in FIG.

  In the memory device 12 shown in FIG. 2, the output terminal of the driver circuit (not shown) that outputs the data strobe signals DQS and xDQS is set to high impedance (Hi-Z) (the data strobe signals DQS and xDQS at the upper end in FIG. 7). .

  The memory controller 22 shown in FIG. 2 outputs an H-level termination control signal SODT at a timing (time t10) according to the operation of the memory device 12. By this termination control signal SODT, the termination control signal xSODT becomes L level.

  At this time, in the termination circuit 36 shown in FIG. 3, the transistors T00 to T02 are turned on based on the control signals SP0 to SP3. Therefore, the resistance value of the termination resistor RT1a is a value obtained by combining the resistance values of the transistors T00 to T02 and the resistors R00 to R02. Further, the transistors T10 to T12 are turned on based on the control signals SN0 to SN3. Therefore, the resistance value of the termination resistor RT1b is a value obtained by combining the resistance values of the transistors T10 to T12 and the resistors R10 to R12.

  Therefore, the termination circuit 36 shown in FIG. 2 terminates the transmission line L1 in response to the termination control signals SODT and xSODT. The data strobe signal DQS (shown at the lower end of FIG. 7) becomes an intermediate potential depending on the resistance values of the termination resistors RT1a and RT1b (resistance value R1 shown in FIG. 5B). Similarly, the termination circuit 36 shown in FIG. 2 terminates the transmission line L2 in response to the termination control signals SODT and xSODT. The inverted data strobe signal xDQS (shown at the lower end of FIG. 7) becomes an intermediate potential due to the resistance values of the termination resistors RT2a and RT2b (resistance value R1 shown in FIG. 5B).

  Next, when the memory device 12 shown in FIG. 2 outputs the L-level data strobe signal DQS and the H-level inverted data strobe signal xDQS at the time t11 as shown at the upper end of FIG. 7, according to those signals, The data strobe signals DQS and xDQS (shown at the lower end of FIG. 7) on the control device 11 side are L level and H level.

  Next, the memory device 12 shown in FIG. 2 outputs a pulsed data strobe signal DQS and an inverted data strobe signal xDQS as shown at the upper end of FIG. In response to these signals, the data strobe signals DQS and xDQS (shown at the lower end of FIG. 7) on the control device 11 side transition in a pulse shape. A period (a period from time t11 to time t12) until the timing when the data strobe signal DQS becomes H level is a preamble period tRPRE.

Next, the operation of the termination circuit during the training operation will be described.
FIG. 8 shows an example of the control signals SPn, SNn, xSPn, xSNn (n = 0 to 3) output in response to the second setting code. In FIG. 8, the letters “H” and “L” in parentheses indicate examples of logic levels of the control signals SPn, SNn, xSPn, and xSNn (n = 0 to 3). The characters “on” and “off” written on the right side of the equal sign indicate the states of the transistors T00 to T33 controlled by the control signals SPn, SNn, xSPn, and xSNn (n = 0 to 3) shown in FIG. .

  In the training operation, L level control signals SP0 and SP1 and H level control signals SP2 and SP3 are output from the termination resistance control circuit 35 shown in FIG. Further, H level control signals SN0 to SN3 are output from the termination resistance control circuit 35 shown in FIG. Further, the L level control signals xSP0 to xSP3, the H level control signals xSN0 and xSN1, and the L level control signals xSN2 and xSN3 are output from the termination resistance control circuit 35 shown in FIG.

  In the memory device 12 shown in FIG. 2, the output terminal of the driver circuit (not shown) that outputs the data strobe signals DQS and xDQS is set to high impedance (Hi-Z) (the data strobe signals DQS and xDQS at the upper end in FIG. 7). .

  The memory controller 22 shown in FIG. 2 outputs an H-level termination control signal SODT at a predetermined timing (time t20). By this termination control signal SODT, the termination control signal xSODT becomes L level. As shown in FIG. 8, the timing (time t20) at which the H-level termination control signal SODT is output is earlier than the timing (item t10) corresponding to the operation of the memory device 12.

  At this time, in the termination circuit 36 shown in FIG. 3, the transistors T00 and T01 are turned on and the transistors T02 and T03 are turned off based on the control signals SP0 to SP3. Therefore, the resistance value of the termination resistor RT1a is a value obtained by combining the resistance values of the transistors T00 and T01 and the resistors R00 and R01. Further, the transistors T10 to T13 are turned on based on the control signals SN0 to SN3. Therefore, the resistance value of the termination resistor RT1b is a value obtained by combining the resistance values of the transistors T00 and T01 and the resistors R00 and R01. Accordingly, the resistance value of the termination resistor RT1a is larger than the resistance value of the termination resistor RT1b. Thereby, the potential of the data strobe signal DQS on the control device 11 side is offset to the low potential voltage VSS side.

  Similarly, the resistance value of the termination resistor RT2a is a value obtained by combining the resistance values of the transistors T20 to T23 and the resistors R20 to R23. The resistance value of the termination resistor RT2b is a value obtained by combining the resistance values of the transistors T30 and T31 and the resistors R30 and R31. Accordingly, the resistance value of the termination resistor RT2a is smaller than the resistance value of the termination resistor RT2b. As a result, the potential of the inverted data strobe signal xDQS on the control device 11 side is offset to the high potential voltage VDD side.

  Next, when the memory device 12 shown in FIG. 2 outputs the L-level data strobe signal DQS and the H-level inverted data strobe signal xDQS at time t21, as shown at the upper end of FIG. 8, according to those signals, The data strobe signals DQS and xDQS (shown at the lower end of FIG. 8) on the control device 11 side are L level and H level. This time t21 is equal to the timing (time t11) at which the memory device 12 outputs the L level data strobe signal DQS in the read operation.

  Next, as shown in the upper end of FIG. 8, the memory device 12 shown in FIG. 2 outputs a pulsed data strobe signal DQS and an inverted data strobe signal xDQS from time t22. In response to these signals, the data strobe signals DQS and xDQS (shown at the lower end of FIG. 8) on the control device 11 transition in a pulse shape. The timing at which the output of the pulsed data strobe signal DQS is started (time t22) is equal to the timing at which the output of the pulsed data strobe signal is started in the read operation (time t12).

  FIG. 9A shows data strobe signals DQS and xDQS during the read operation. FIG. 9B shows the data strobe signals DQS and xDQS during the training operation and the internal strobe signal DQSi generated by the data strobe signals DQS and xDQS.

  The input buffer 37 shown in FIG. 2 outputs an internal strobe signal DQSi of H level or L level according to the voltage difference between the data strobe signal DQS and the inverted data strobe signal xDQS. The voltage difference between the two data strobe signals DQS and xDQS corresponds to the offset amount for each signal. As described above, the offset amounts of both data strobe signals DQS and xDQS are set according to the differential recognition voltage of the input buffer 37. The data strobe signal DQS is offset from the central voltage to the low potential voltage VSS side, and the inverted data strobe signal xDQS is offset from the central voltage to the high potential voltage VDD side. Therefore, the input buffer 37 outputs the internal strobe signal DQSi of L level according to the offset data strobe signals DQS and xDQS.

  2 makes the internal strobe signal DQSi transition at the cross point of the offset data strobe signals DQS and xDQS, that is, the timing at which the data strobe signal DQS and the inverted data strobe signal xDQS intersect each other. Therefore, the input buffer 37 outputs the L-level internal strobe signal DQSi after the termination circuit 36 shown in FIG. 2 offsets the data strobe signals DQS and xDQS to the cross point of the data strobe signals DQS and xDQS. . The internal strobe signal DQSi at L level is determined to be a preamble. Therefore, as shown in the lower end of FIG. 8, the period from the timing (time t20) at which the H-level termination control signal SODT is output to the timing (time t22) at which the pulsed data strobe signals DQS and xDQS are started. Is the preamble period tRPRE. Thus, in the training operation, the preamble period tRPRE is set based on the termination control signal SODT output from the memory controller 22.

Next, the training operation will be described.
As shown in FIG. 10, at time t30, the data strobe signals DQS and xDQS on the control device 11 side are offset voltage levels, and the internal strobe signal DQSi becomes L level accordingly. The hatched portion of the internal strobe signal DQSi is at an indefinite level.

  The DQS mask signal DQSM is swept from the timing indicated by the alternate long and short dash line to the timing indicated by the solid line, that is, in the range indicated by the arrow. The start timing of the range of the DQS mask signal DQSM is set before the start of the preamble period in the data strobe signals DQS and xDQS on the memory device 12 side shown in the upper part of FIG. When the output terminal of the memory device 12 is high impedance (indicated by an intermediate level in FIG. 10), the internal strobe signal DQSi is at L level. Accordingly, the internal strobe signal IDQS (see FIG. 2) generated in response to the DQS mask signal DQSM and the L-level internal strobe signal DQSi is output to the memory controller 22. For this reason, the internal strobe signal IDQS having an incorrect level is not output to the memory controller 22 by the data strobe signals DQS and xDQS in the high impedance state.

  The memory controller 22 shown in FIG. 2 determines the rising timing (time t32) of the internal strobe signal DQSi based on the internal strobe signal IDQS. Based on this rising timing (time t32), the preamble period (period from time t31 to time t32) in the read operation is determined, and the timing of the DQS mask signal DQSM (lowermost stage in FIG. 10) at the time of reading is set. .

The memory device 12 shown in FIG. 1 is used for a memory device (memory module).
For example, as illustrated in FIG. 11, the control device 100 is connected to the memory device 110 via the transmission path 120. The memory device 110 includes a plurality (four in FIG. 11) of memory devices 12a to 12d. The memory devices 12a to 12d are mounted on the module substrate 111. A transmission path (wiring) for supplying the clock signal CK output from the control device 100 to each of the memory devices 12a to 12d is formed on the module substrate 111. The wiring for supplying the clock signal CK to each of the memory devices 12a to 12d is daisy chain connected, for example.

  The clock signal CK receives a delay due to the wiring between the memory devices 12a to 12d and is supplied to the memory devices 12a to 12d at different timings. The clock signals for the memory devices 12a to 12d are CK0 to CK3. The memory device 12a operates based on the clock signal CK0. The memory device 12a outputs a data strobe signal DQS0 in response to the read command. Similarly, the memory devices 12b to 12d operate based on the clock signals CK1 to CK3. Each of the memory devices 12a to 12d outputs data strobe signals DQS1 to DQS3 in response to the read command. The data strobe signals DQS0 to DQS3 are transmitted to the control device 100 via different transmission paths.

FIG. 12 shows waveforms of the clock signal and the data strobe signal.
Based on the clock signal CK, the control device 100 outputs a read command, for example, at time t40.

  Then, control device 100 receives data output from memory device 12a based on data strobe signal DQS0 (time t50). Similarly, control device 100 receives data output from memory devices 12b to 12d based on data strobe signals DQS1 to DQS3 (time t51 to t53). The time from issuing a read command to receiving data is called flight time. For example, the flight time for the memory device 12a is the elapsed time from time t40 to time t50.

  Flight times for the memory devices 12a to 12d are different from each other. Accordingly, the preamble periods in the data strobe signals DQS0 to DQS3 are also different. In this way, the timing of the DQS mask signal is set for a plurality of preamble periods that occur at different timings. Therefore, it is necessary to sweep the DQS mask signal DQSM over a wide range.

  In the control device 11 described above, the interface circuit 23 terminates the transmission lines L1 and L2 by the termination circuit 36 and adjusts the resistance value of the termination circuit 36 in the training operation, thereby adjusting the data strobe signals DQS and xDQS, that is, the transmission line L1. And offset the potential of the transmission line L2. The input buffer 37 outputs an internal strobe signal DQSi of L level according to the potential difference between the data strobe signals DQS and xDQS, that is, the difference between the potential of the transmission line L1 and the potential of the transmission line L2. Therefore, the timing of the DQS mask signal DQSM can be set during the period in which the memory device 12 sets the output terminal in the high impedance state, and the range in which the DQS mask signal DQSM is swept can be widened compared to the conventional example. In other words, the internal strobe signal DQSi at the L level is generated by offsetting the data strobe signals DQS and xDQS by the termination circuit 36 during the period when the memory device 12 sets the output terminal in the high impedance state. Output of the strobe signal IDQS to the memory controller 22 can be suppressed.

As described above, according to the present embodiment, the following effects can be obtained.
(1-1) In the training operation, the interface circuit 23 terminates the transmission lines L1 and L2 by the termination circuit 36, adjusts the resistance value of the termination circuit 36, and transmits the data strobe signals DQS and xDQS, that is, the transmission line L1. The potential of the path L2 is offset. The input buffer 37 outputs an internal strobe signal DQSi of L level according to the potential difference between the data strobe signals DQS and xDQS, that is, the difference between the potential of the transmission line L1 and the potential of the transmission line L2. Therefore, the timing of the DQS mask signal DQSM can be set during the period in which the memory device 12 sets the output terminal in the high impedance state, and the range in which the DQS mask signal DQSM is swept can be widened compared to the conventional example. In other words, the internal strobe signal DQSi at the L level is generated by offsetting the data strobe signals DQS and xDQS by the termination circuit 36 during the period when the memory device 12 sets the output terminal in the high impedance state. Output of the strobe signal IDQS to the memory controller 22 can be suppressed.

  (1-2) In response to the enable signal TEN, the termination resistance control circuit 35 adjusts the resistance value of the termination circuit 36 so as to offset the data strobe signals DQS and xDQS, that is, the potentials of the transmission line L1 and the transmission line L2. To do. The input buffer 37 outputs an internal strobe signal DQSi of L level according to the potential difference between the data strobe signals DQS and xDQS, that is, the difference between the potential of the transmission line L1 and the potential of the transmission line L2. The internal strobe signal DQSi at L level is equal to the level of the internal strobe signal DQSi during the preamble period of the data strobe signals DQS and xDQS output from the memory device 12. That is, in the control device 11, the preamble period can be controlled by the enable signal TEN.

(Second embodiment)
In the present embodiment, the same members as those in the first embodiment are denoted by the same reference numerals, and a part or all of the description thereof is omitted.

  As shown in FIG. 13, the interface circuit 201 of the control device 200 includes a mask signal generation circuit 202, a training circuit 32, buffer circuits 33 and 34, a termination resistance control circuit 35, a termination circuit 36, an input buffer 37, and an AND circuit 38. Have.

The mask signal generation circuit 202 includes a latency adjustment circuit 41, a timing adjustment circuit 42, a register 43, and a correction circuit 203.
The correction circuit 203 corrects a timing shift caused by the offset data strobe signals DQS and xDQS in the training operation. More specifically, the register 43 stores adjustment information set by the training operation. The adjustment information indicates the timing of the DQS mask signal DQSM set based on the internal strobe signal DQSi output from the input buffer 37 during the training operation. The register 43 outputs a control code corresponding to the set adjustment information. In the correction circuit 203, a correction value corresponding to the timing shift is set. The correction circuit 203 generates a correction code obtained by correcting the control code output from the register 43 with a correction value, and outputs the correction code. The correction in the correction circuit 203 is, for example, an operation for subtracting the correction value from the control code, and the operation result value is output as a correction code. The timing adjustment circuit 42 outputs an H-level DQS mask signal DQSM at a timing according to the correction code output from the correction circuit 203.

  In FIG. 15, the upper waveform shows the data strobe signals DQS and xDQS during the read operation. During the read operation, the data strobe signal DQS transitions from the intermediate value set by the termination circuit 36 to the low potential voltage VSS level. Then, after the preamble period, the data strobe signal DQS transitions from the low potential voltage VSS level to the high potential voltage VDD level. Similarly, the inverted data strobe signal xDQS transits from the intermediate value set by the termination circuit 36 to the high potential voltage VDD level. Then, after the preamble period, the inverted data strobe signal xDQS transitions from the high potential voltage VDD level to the low potential voltage VSS level. Therefore, the cross point of the data strobe signal DQS and the inverted data strobe signal xDQS is a voltage ΔAV1 higher than the low potential voltage VSS level by a voltage ΔAV1 that is ½ of the difference between the high potential voltage VDD and the low potential voltage VSS.

  In FIG. 15, the middle waveform shows the data strobe signals DQS and xDQS during the training operation. For example, the data strobe signal DQS is offset to the low potential voltage VSS side, and the inverted data strobe signal xDQS is offset to the high potential voltage VDD side. Therefore, the data strobe signal DQS is stabilized at a voltage lower than the low potential voltage VSS by an offset voltage during the preamble period. The data strobe signal DQS rises from the voltage during the preamble period and crosses the inverted data strobe signal xDQS at an intermediate voltage between the high potential voltage VDD and the low potential voltage VSS. The voltage difference ΔAV2 between the voltage in the preamble period and the cross point (intermediate voltage) is larger than the voltage ΔAV1 at the time of reading. Therefore, the cross point of the data strobe signals DQS and xDQS in the training operation is delayed by a time ΔtD from the cross point in the read operation. That is, the rise of the internal strobe signal DQSi during the training operation is delayed by the time ΔtD from the rise of the internal strobe signal DQSi during the read operation.

  Then, the margin between the DQS mask signal DQSM at the timing set by the internal strobe signal DQSi during the training operation and the rising edge of the internal strobe signal DQSi during the read operation decreases according to the delay time ΔtD. This may lead to a shortage of margin in high-speed data transfer (clock signal CK having a short period, pulse-shaped data strobe signal DQS).

  In the correction circuit 203, a correction value corresponding to the delay time ΔtD is stored by the memory controller 22, for example. The delay time ΔtD corresponds to the offset amount of the data strobe signals DQS and xDQS.

  The correction circuit 203 outputs a correction code obtained by correcting the control code output from the register 43 according to the set correction value. The timing adjustment circuit 42 outputs an H-level DQS mask signal DQSM at a timing according to the correction code output from the correction circuit 203. Therefore, as shown in FIG. 14, the mask signal generation circuit 31 generates the DQS mask signal DQSM with the optimum timing at the time of reading.

As described above, according to this embodiment, in addition to the effects of the first embodiment, the following effects can be obtained.
(2-1) The correction circuit 203 stores a correction value corresponding to the time ΔtD of the difference between the cross points of the data strobe signals DQS and xDQS in the read operation and the cross points of the data strobe signals DQS and xDQS in the training operation. Then, the correction circuit 203 generates a correction code obtained by correcting the control code output from the register 43 with the correction value, and outputs the correction code. The timing adjustment circuit 42 outputs an H-level DQS mask signal DQSM at a timing according to the correction code output from the correction circuit 203. Thereby, it is possible to generate the DQS mask signal DQSM having the optimum timing at the time of reading.

In addition, you may implement each said embodiment in the following aspects.
・
The number of resistors R00 to R03, R10 to R13, R20 to R23, and R30 to R33 included in the termination circuit 36 may be changed as appropriate. Moreover, the resistance values of the resistors R00 to R03, R10 to R13, R20 to R23, and R30 to R33 may be appropriately changed, for example, as in weighting (x8, x4, x2, x1).

  The above embodiment is the interface circuits 23 and 201 for outputting the complementary data strobe signals DQS and xDQS, that is, the internal strobe signal IDQS according to the differential signal, but the internal strobe signal according to the single-ended data strobe signal. An interface circuit that outputs IDQS may be embodied.

11 control device 12 memory device 22 memory controller 23 interface circuit 31 mask signal generation circuit 35 termination resistance control circuit 36 termination circuit 37 input buffer 38 AND circuit DQS, xDQS data strobe signal DQ data DQSM DQS mask signal DQSi internal strobe signal IDQS internal strobe Signal L1, L2 Transmission line SODT Termination control signal

Claims (5)

A receiving circuit for receiving data in response to a strobe signal designating a preamble by a first potential;
A mask signal generation circuit for generating a mask signal for masking the strobe signal at a timing according to setting information;
A termination circuit that is activated or deactivated according to a termination control signal, and terminates a transmission path through which the strobe signal is transmitted when activated;
An adjustment unit for adjusting the resistance value of the termination circuit;
A detection unit that detects whether the potential of the transmission line is the first potential or a second potential different from the first potential, and outputs a detection signal according to a detection result;
A gate circuit that generates an internal strobe signal based on the detection signal in response to the mask signal;
Have
The adjustment unit is
During the reception operation, the resistance value of the termination circuit is adjusted to a first resistance value such that the potential of the transmission line becomes the center voltage of the power supply voltage range
Adjusting the resistance value of the termination circuit to a second resistance value so that the potential of the transmission line is adjusted by a predetermined voltage offset from the central voltage during a training operation for adjusting the setting information according to the internal strobe signal;
A receiving circuit. A correction circuit that stores a correction value corresponding to the offset amount of the transmission path by the second resistance value and outputs a correction code in which the setting information is corrected based on the correction value;
The mask signal generation circuit generates the mask signal at a timing according to the correction code;
The receiving circuit according to claim 1. The second resistance value is set to be equal to or higher than a differential recognition voltage that is a voltage for recognizing the offset amount of the transmission line as a differential signal of the detection unit;
The receiving circuit according to claim 2. The strobe signals are complementary first and second strobe signals;
The first strobe signal designates the preamble by the first potential, and the second strobe signal has a second potential different from the first potential during a period in which the first strobe signal designates the preamble. Yes,
The adjusting unit offset-adjusts the potential of the first transmission path for transmitting the first strobe signal from the central voltage to the first potential side during the training operation, and transmits the second strobe signal. Adjusting the second resistance value so as to offset the potential of the two transmission lines from the central voltage to the second potential side;
The receiving circuit according to claim 1 or 2. The detection unit outputs the detection signal according to a difference between the potential of the first transmission path and the potential of the second transmission path,
The second resistance value is a voltage for recognizing the difference between the offset-adjusted potential of the first transmission path and the potential of the second transmission path as a differential signal of the detection unit during the training operation. Be set to be higher than the differential recognition voltage,
The receiving circuit according to claim 4.