JP2014130513A - Electric current model creation method and cad device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently create an electric current model of a chip power supply reproducing frequency modulation.SOLUTION: An electric current model creation method includes computer execute procedures of: processing power supply electric current data in a chip by adjusting a timing of generation of a current wave form of a power supply noise model for each cycle using frequency modulation data stored in a storage part; and outputting the power supply electric current data in a chip including modulated power supply electric current data obtained by the processing as an electric current model to the storage part.

Description

  The present invention relates to creating a current model for a chip power supply.

  In recent years, simulation has been utilized as means for predicting the amount of power supply noise and defective radiation during LSI design in order to reduce the risk of occurrence of defects after trial manufacture of LSI. The model for simulating the power supply noise of the designed LSI includes a chip power supply model for an LSI internal circuit, a PKG power supply model for a package, and a PCB power supply model for a printed circuit board. In order to simulate the amount of power supply noise and the amount of electromagnetic radiation, a chip power supply model is required, and the power supply current generated by chip operation must be configured as a noise source.

  Focusing on the fact that the frequency of the output current of the circuit and the amount of shift of its waveform are the dominant factors that determine the electromagnetic radiation noise, a plurality of circuits having the same frequency and amount of shift of the output current are combined into one switching cell. There is an electromagnetic radiation noise analysis method that can scale down the modeled circuit by bundling and modeling, and can obtain a result close to the actual measurement result by simulation.

  Also, in designing electronic equipment, candidates for clock signal generators having a clock frequency modulation circuit are extracted, electromagnetic interference suppression effects are estimated from the specifications of the candidate clock signal generators, and the estimated electromagnetic interference suppression effects Has been proposed to select and use a clock signal generator that satisfies the target effect.

JP 2008-97392 A JP 2003-150660 A

  In the above-described method of bundling a plurality of circuits and modeling on a small scale, a current waveform that takes frequency modulation into consideration is not created. Further, as a technique for preventing unnecessary radiation, an SSCG (Spread Spectrum Clock Generator) circuit that modulates the clock frequency is used, and the effect of reducing the peak of unnecessary radiation can be obtained by shifting the clock period to a small amount. From such a viewpoint, it is conceivable to use a method of designing an electronic device by selecting a clock signal generator that satisfies the target effect of the electromagnetic interference suppression effect estimated from the above-mentioned specifications. In the simulation of electronic equipment after design, there was a problem that the electromagnetic interference suppression effect could not be confirmed.

  In one aspect, an object of the present invention is to create a current model of a chip power source that reproduces frequency modulation and can confirm the effect of reducing unnecessary radiation by frequency modulation by simulation.

  According to one aspect of the present embodiment, the current model creation method uses the frequency modulation data stored in the storage unit to adjust the timing at which the current waveform of the power supply noise model is generated for each cycle. The computer executes a procedure of processing the power supply current data and outputting the in-chip power supply current data including the modulated power supply current data obtained by the processing to the storage unit as a current model.

  Further, as means for solving the above-described problems, a CAD device that creates a current model, a current model creation program that causes a computer to execute the above procedure, and a recording medium that records the current model creation program may be used.

  According to one aspect of the present embodiment, the current waveform model of the chip power supply is processed by adjusting the timing at which the current waveform of the power supply noise model is generated for each cycle based on the frequency modulation data. Creation time can be shortened.

It is a conceptual diagram of the power supply model for simulating a power supply noise. It is a figure which shows the hardware constitutions of a CAD apparatus. It is a figure which shows the function structural example of a CAD apparatus. It is a figure which shows the example which compounded the modulation frequency by SSCG. It is FIG. (1) for demonstrating the process by (DELTA) tn calculation part. FIG. 6 is a diagram (part 2) for explaining processing by the Δtn calculation unit; It is a figure for demonstrating the process by a current waveform process part. It is a figure which shows the structural example of a LSI chip. It is a figure for demonstrating the example of SDC definition. It is a figure for demonstrating the example of SDC definition. It is a figure which shows the example of a result of grouping. It is a figure which shows the example of a definition of frequency modulation data and frequency modulation allocation data. It is a figure which shows the example of (DELTA) tn calculation result. It is a figure for demonstrating the example of a process by a power supply waveform process part.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In this embodiment, a chip power supply current model that reproduces frequency modulation and that can confirm the effect of reducing unnecessary radiation by frequency modulation by simulation is created.

  FIG. 1 is a conceptual diagram of a power supply model for simulating power supply noise. In FIG. 1, a power supply model 1 includes a chip power supply model 1a for an LSI internal circuit, a PKG power supply model 1b for a package, and a PCB power supply model 1c for a printed circuit board.

  The chip power supply model 1a is a model in which power supply noise is suppressed by frequency modulation by an SSCG (Spread Spectrum Clock Generator) or the like, and the chip power supply current 2 of the chip power supply model 1a shows a frequency-modulated current waveform.

  The frequency modulation is generally to change the period at a very low modulation frequency (for example, 24 KHz) with respect to the clock frequency to be modulated. By this frequency modulation, an increase in cycle-to-cycle jitter is suppressed.

  Therefore, in order to create a current waveform that reproduces frequency modulation, it is necessary to create a long-time current. For example, when the modulation frequency is 24 KHz, a current waveform of 41666 nsec is required. Creating a current waveform of 1000 nsec requires about one week of man-hours. Therefore, reproducing a frequency-modulated current waveform is usually not a realistic task.

  In addition, SSCG (Spread Spectrum Clock Generator) for frequency modulation has a function of combining modulation frequencies, and in order to reproduce it, a longer time of current is required to generate a current including a plurality of modulation periods. Become.

  The process according to the present embodiment, which will be described later, makes it possible to reproduce a frequency-modulated current waveform in a short time with respect to the chip power supply current 2 of the chip power supply model 1a. The processing according to the present embodiment is executed by a computer device for designing an electronic circuit such as an LSI (Large Scale Integration) functioning as a CAD (Computer-Aided Design) device.

  FIG. 2 is a diagram illustrating a hardware configuration of the CAD apparatus. In FIG. 2, a CAD device 100 is a terminal controlled by a computer, and includes a CPU (Central Processing Unit) 11, a main storage device 12, an auxiliary storage device 13, an input device 14, a display device 15, It has an output device 16 and a drive 18 and is connected to the bus B.

  The CPU 11 controls the CAD device 100 according to a program stored in the main storage device 12. The main storage device 12 uses a RAM (Random Access Memory) or the like, and stores a program executed by the CPU 11, data necessary for processing by the CPU 11, data obtained by processing by the CPU 11, and the like. A part of the main storage device 12 is allocated as a work area used for processing by the CPU 11.

  The auxiliary storage device 13 uses a hard disk drive and stores data such as programs for executing various processes. A part of the program stored in the auxiliary storage device 13 is loaded into the main storage device 12 and executed by the CPU 11, whereby various processes are realized. The storage unit 130 includes the main storage device 12 and / or the auxiliary storage device 13.

  The input device 14 includes a mouse, a keyboard, and the like, and is used for a user to input various information necessary for processing by the CAD device 100. The display device 15 displays various information required under the control of the CPU 11. The output device 16 has a printer or the like and is used for outputting various types of information in accordance with instructions from the user.

  A program that realizes processing performed by the CAD apparatus 100 is provided to the CAD apparatus 100 by a storage medium 19 such as a CD-ROM (Compact Disc Read-Only Memory). That is, when the storage medium 19 storing the program is set in the drive 18, the drive 18 reads the program from the storage medium 19, and the read program is installed in the auxiliary storage device 13 via the bus B. . When the program is activated, the CPU 11 starts its processing according to the program installed in the auxiliary storage device 13. The medium for storing the program is not limited to a CD-ROM, and any medium that can be read by a computer may be used. As a computer-readable storage medium, in addition to a CD-ROM, a portable recording medium such as a DVD disk or a USB memory, or a semiconductor memory such as a flash memory may be used.

  FIG. 3 is a diagram illustrating a functional configuration example of the CAD apparatus. In FIG. 3, the CAD apparatus 100 includes, as processing units, a current waveform extraction unit 41, a power supply capacitance extraction unit 42, a power supply wiring resistance extraction unit 43, a voltage drop analysis unit 44, a voltage convergence determination unit 45, A Δtn calculation unit 46, a current waveform processing unit 47, and a model output unit 48 are included. The CPU 11 functions as each of the processing units 41 to 48 by executing a corresponding program.

  Further, the storage unit 130 includes a net list 3e, a clock cycle 3d, an instance operation timing 3c, a cell current waveform table 3b, an in-chip arrangement wiring data 3a, a cell power source capacity library 3f, a wiring sheet resistor 3g, a PKG power source RL3h, a chip. Internal power supply wiring resistance 3i, intra-chip power supply capacitance 3j, drop voltage 3k, in-chip power supply current data 3m, frequency modulation data 3n, frequency modulation allocation data 3p, Δtn data 3q, in-chip power supply current data 3r, modulated current model 3t, chip power supply RC model 3s, etc. are stored.

  The current waveform extraction unit 41 is a processing unit that extracts a current waveform in an arbitrary chip region. When extracting a current waveform in an arbitrary chip area, a current waveform is generated for each clock system. The current waveform extraction unit 41 creates a short time current waveform such as several cycles of the clock frequency. In this embodiment, as will be described later, since a current waveform considering frequency modulation can be created with a current waveform for a predetermined cycle of the clock frequency, the processing time can be greatly shortened.

Specifically, the following steps are executed by the current waveform extraction unit 41.
1) The load capacity of each instance is acquired from the on-chip placement and routing data 3a.
2) The rising / falling current waveform of each instance is acquired from the cell power supply waveform table 3b. The cell power waveform table 3b stores current waveform data for each combination of cell, power supply voltage, external load, and uplink / downlink.
3) The rising / falling change time of each instance is obtained from the clock frequency and the instance operation timing 3c, and the current waveform of each instance reflecting the operation condition is generated.
4) Using the clock cycle 3d and the netlist 3e, the current waveform of each instance is synthesized with the current waveform of each region group obtained by dividing the chip into arbitrary units for each clock system. As will be described later, since the current waveform processing unit 47 performs processing on the current waveform for each clock system, the current waveforms are grouped for each clock system.

  The inter-power supply capacity extraction unit 42 is a processing unit that extracts the inter-power supply capacity in an arbitrary chip area with reference to the in-chip arrangement wiring data 3a and the cell power supply capacity library 3f. The extracted inter-chip power supply capacitance 3j is stored in the storage unit 130.

  The power supply wiring resistance extraction unit 43 is a processing unit that extracts power supply wiring resistance between arbitrary chip regions with reference to the in-chip arrangement wiring data 3a and the wiring sheet resistance 3g. The extracted in-chip power supply wiring resistance 3 i is stored in the storage unit 130.

  The voltage drop analysis unit 44 extracts the in-chip power source current data 3m extracted by the current waveform extraction unit 41, the intra-chip power source capacitance 3j extracted by the inter-power source capacitance extraction unit 42, and the power source wiring resistance extraction unit 43. The processing unit dynamically analyzes the power supply voltage in each chip region by referring to the in-chip power supply wiring resistance 3i and the PKG power supply RL3h.

  The voltage convergence determination unit 45 is a processing unit that determines whether the voltage has converged based on the analysis result of the voltage drop analysis unit 44. It is determined whether or not the previous value difference of the power supply voltage value of each instance is less than a specified value. When the voltage convergence determination unit 45 determines that the voltage has not converged, the current waveform extraction unit 41 extracts the current waveform again based on the drop voltage 3k. When the voltage convergence determination unit 45 determines that the voltage has converged, processing by the current waveform processing unit 47 is performed. That is, at the time of the first analysis or when the voltage value difference is greater than or equal to the specified value, the current waveform extraction and the power drop analysis are executed again. Reprocessing is performed by changing the voltage condition of the reference value in the cell power supply waveform table 3b.

  The Δtn calculation unit 46 calculates a period shift amount Δtn of each cycle for each clock system based on the frequency modulation data 3n, the frequency modulation allocation data 3p, and a clock period 3d such as SDC (Synopsys Design Constraints). It is a processing unit.

  The current waveform processing unit 47 is a processing unit that processes a current waveform for each clock system based on the frequency modulation data 3n. The current waveform processing unit 47 processes the current waveform in consideration of frequency modulation by shifting the period of the current waveform by a minute amount. The current waveform is processed repeatedly until the time necessary to express the frequency modulation.

Specifically, the following steps are executed by the current waveform processing unit 47.
1) Recognize whether the current waveform of the clock system in which frequency modulation by SSCG is performed.
2) For clock systems that perform frequency modulation:
2-1) Considering frequency modulation by correcting the cycle of each cycle by Δtn obtained by Δtn calculating unit 46 using the current waveform obtained by current waveform extracting unit 41 and not subjected to frequency modulation. Generated current waveform.
2-2) Correction is performed with Δtn corresponding to the number of cycles while repeatedly copying the current waveform up to the time necessary to express the frequency modulation. When multiple SSCGs are mounted on the chip, copying is repeated until the maximum required time.
3) For clock systems that do not perform frequency modulation:
3-1) The current waveform is repeated without performing period correction. Even for a clock system in which frequency modulation is not performed, the current waveform is repeatedly copied in order to match the time length of the current waveform as a whole.

  Through the processing by the current waveform processing unit 47 described above, the in-chip power supply current data 3r for each clock system is stored in the storage unit 130. The on-chip power supply current data 3r includes data indicating a current waveform that has been modulated with respect to a frequency-modulated clock system, and data indicating a current waveform without period correction for a clock system that is not frequency-modulated.

  The model output unit 48 is a processing unit that outputs the final current waveform, the inter-power source capacitance, and the power source wiring resistance to the storage unit 130 in a data format that can be used by software that simulates the analog operation of the electronic circuit. The software is, for example, SPICE (Simulation Program with Integrated Circuit Emphasis).

  The model output unit 48 stores the modulated current model 3t and the chip power supply RC model 3s in the storage unit 130. The modulated current model 3t is a model based on the in-chip power supply current data 3r for each clock system, and the chip power supply RC model 3s is based on the intra-chip power supply capacitance 3j and the in-chip power supply wiring resistance 3i. It is a model.

  The netlist 3e is a data file that defines connections between cells constituting an LSI and connections between functional unit blocks. The clock period 3d is a data file such as an SDC that defines a clock period for each clock. The instance operation timing 3c is a data file that defines the timing for each cell.

  The cell current waveform table 3b is a data file that defines a current waveform for each cell. The on-chip placement and routing data 3a is a data file that stores data relating to placement and routing in the chip after placement and routing processing in LSI design.

  The cell power capacity library 3f is a library data file in which the power capacity is defined for each cell. The wiring sheet resistance 3g is a data file that defines the sheet resistance for each wiring layer. The PKG power supply RL3h is a data file that defines the resistance RL of the package power supply.

  The in-chip power supply wiring resistance 3 i is a data file indicating the power supply wiring resistance between arbitrary chip regions extracted by the power supply wiring resistance extraction unit 43. The inter-chip power supply capacity 3j is a data file indicating the inter-power supply capacity in any chip area extracted by the inter-power supply capacity extraction unit 42.

  The drop voltage 3k is a data file indicating the drop voltage in each chip region analyzed by the voltage drop analysis unit 44. The in-chip power supply current data 3m is a data file for a power supply noise model indicating the power supply current for each clock system.

  The frequency modulation data 3n includes a table indicating a clock frequency (or period or period variation ratio) according to time (or clock cycle) as shown in FIG. FIG. 4 shows an example in which modulation frequencies are combined by SSCG and includes a plurality of modulation periods 4m-1, 4m-2, 4m-3,. A table representing a plurality of frequency modulations is managed by the frequency modulation data 3n.

  The frequency modulation allocation data 3p is a data file that stores the allocation of the frequency modulation table managed by the frequency modulation data 3n for each block grouped for each clock system.

  The Δtn data 3q is a data file indicating the period deviation amount Δtn of each cycle for each clock system calculated by the Δtn calculation unit 46. The on-chip power supply current data 3r is a data file that includes a current waveform that is processed by the current waveform processing unit 47 and that takes into account frequency modulation, and indicates a current waveform for each clock system.

  The modulated current model 3t is a data file indicating a current waveform synthesized for each group (block) based on the clock system, and is a model including a modulated current waveform. The chip power RC model 3s is a model representing the inter-power capacity and power wiring resistance in the chip.

  Among the various data stored in the storage unit 130 described above, the net list 3e, the clock cycle 3d, the instance operation timing 3c, the cell current waveform table 3b, the on-chip placement wiring data 3a, the cell power source capacity library 3f, the wiring sheet resistance 3g, PKG power supply RL3h, frequency modulation data 3n, and frequency modulation allocation data 3p are prepared in advance and stored in the storage unit 130.

  Hereinafter, processing by the Δtn calculation unit 46 and the current waveform processing unit 47 related to creation of a current waveform in consideration of frequency modulation will be described.

  5 and 6 are diagrams for explaining processing by the Δtn calculation unit. 5, the frequency modulation data 3n is a table in which frequency cycles are associated with each cycle. For example, the first cycle has a cycle of 100 ns, the second cycle has a cycle of 101 ns,..., The seventh cycle has a cycle of 98 ns. The eighth cycle is shown as a period 99 ns,.

  By such frequency modulation data 3n, a modulation waveform 5a represented by a graph 5 with a vertical axis representing a clock cycle and a horizontal axis representing time is represented. In the case of the clock cycle 5b having a period of 100 ns, the calculation result by the Δtn calculation unit 46 is shown as a Δtn calculation result 3n-2.

  In the Δtn calculation result 3n-2, the difference Δtn between the frequency modulation data 3n and the clock cycle 5b having a period of 100 ns is 0 ns in the first cycle, 1 ns in the second cycle,. In the cycle, it is shown as −1 ns,.

  FIG. 6 is a diagram illustrating an example of frequency modulation data. FIG. 6A shows an example of frequency modulation data 3n in the case where each clock system uses a different SSCG. In this example, regarding the modulation waveform 5a-1 of SSCG-1 and the modulation waveform 5a-2 of SSCG-2, frequency modulation data 3n in which clock cycles are associated with each cycle is stored in the storage unit 130 in advance. When the cell is an SSCG-1 clock system, the Δtn calculation unit 46 calculates the difference Δtn between the modulation frequency based on the assigned modulation waveform 5a-1 and the clock frequency input to the cell for each cycle. .

Δtn = modulation frequency−clock frequency FIG. 6B shows an example of frequency modulation data 3n in the case where each clock system uses the same SSCG but the frequency is different. This is the case when the clock signal from the same SSCG is divided or multiplied. In this example, the modulated waveform 5a-3 of SSCG-3 is indicated by a fluctuation ratio for each period (hereinafter referred to as a periodic fluctuation ratio) and is stored in the storage unit 130 in advance. The Δtn calculation unit 46 uses the reference clock period for each clock system for the cells in each clock system of the same SSCG-3 and uses the reference clock period for each clock system as a reference for the period variation ratio indicated by the modulation waveform 5a-3 of SSCG-3. By multiplying the clock period, Δtn is calculated.

Δtn = period variation ratio × reference clock period Next, processing by the current waveform processing unit 47 will be described. FIG. 7 is a diagram for explaining processing by the current waveform processing unit. FIG. 7A shows a current waveform before being processed by the current waveform processing unit 47, that is, a current waveform before frequency modulation. The current waveform processing unit 47 refers to the in-chip power supply current data 3m, acquires the cell power supply current 7b for each clock system, and creates a composite waveform 7c.

  For example, the current waveform processing unit 47 obtains the in-chip power supply current data 3m of the SSCG 7m clock system from the storage unit 130 and synthesizes the cell power supply current 7b. A composite waveform 7c of the power supply current synchronized with the reference clock 7a having a constant period T0 is created.

  Then, the current waveform processing unit 47 refers to the Δtn data 3q of the SSCG 7m using the synthesized waveform 7c, adds Δtn / 2 for each T0 / 2 period, and creates a current waveform 7p after frequency modulation. Since the in-chip power supply current data 3m shows only a current waveform for a predetermined period, when the current waveform 7p is created, the composite waveform 7c is repeated until the time length is sufficient to reproduce the frequency modulation. Then, Δtn / 2 is added every T0 / 2 period. By simply repeating a relatively simple process, a long-time current waveform can be created in a short time, so that the processing burden for creating the current waveform 7p after frequency modulation can be reduced.

  From the above, in the case of the related technology in which the processing by the Δtn calculation unit 46 and the current waveform processing unit 47 in the present embodiment is not performed, the clock frequency is constant in the current waveform extraction and the frequency modulation cannot be considered. In this embodiment, it is possible to generate a chip current waveform in consideration of frequency modulation.

  In addition, in the related technology, if a current waveform that takes frequency modulation into account is created in the current waveform extraction, the current waveform becomes a long time, and the calculation time for voltage drop analysis becomes enormous. Cannot create a model in On the other hand, in this embodiment, since the current waveform is processed after the power drop analysis process, a chip current waveform can be generated in consideration of frequency modulation without increasing the calculation time of the power drop analysis.

  Next, an example of chip power supply model creation processing by the CAD apparatus 100 according to the present embodiment will be described.

  FIG. 8 is a diagram illustrating a configuration example of an LSI chip. In the configuration example of the LSI chip 8 shown in FIG. 8, examples of cells / modules, instance names, cell terminal names, and external terminal names defined in the netlist 3e are associated. SSCG1A, CPU1A, MC1A, SSCG1B, and CODEC1A are cell / module names. Inbuf1, inbuf2, sscg1, sscg2, buf1, buf2, buf3, buf4, buf5, cpu1, memcon1, codec1, outbuf1, outbuf2, outbuf3 are instance names. CLK1, CLK2, DAT1, DAT2, and DAT3 are external terminal names. The cell terminal name is indicated by A on the input side and X on the output side.

  The frequency input to CLK1 is 20 MHz, the frequency output from SSCG1A is 200 MHz, the frequency output from the 1/2 divider circuit is 100 MHz, the frequency input to CLK2 is 10 MHz, and output from SSCG1B. The frequency is 50 MHz.

  In the LSI chip 8, a signal with a frequency of 20 MHz input from CLK1 is multiplied by 10 by sscg1 via inbuf1 and output at 200 MHz. The signal with a frequency of 200 MHz output from sscg1 branches via buf1. After branching, a signal having a frequency of 200 MHz is supplied to cpu1 via buf2, and then output from DAT1 to the outside via outbuf1.

  Further, a signal having a frequency of 200 MHz via buf3 after branching is frequency-divided to 100 MHz by df1 of the 1/2 frequency divider and supplied to memcon1. Thereafter, the data is output from DAT2 to the outside via outbuf2.

  On the other hand, a signal having a frequency of 10 MHz input from CLK2 is multiplied by 5 by sscg2 via inbuf2 and output at 50 MHz. A signal with a frequency of 50 MHz output from sscg2 is supplied to codec1 via buf4 and buf5. Thereafter, the data is output from DAT3 to the outside via outbuf3.

  Next, grouping for each clock system will be described with reference to FIGS. 9, 10, and 11 using an example of the LSI chip 8. FIG.

  9 and 10 are diagrams for explaining examples of SDC definitions. In FIG. 9, the correspondence with the clock system defined by the SDC in FIG. 10 is indicated by (C1), (C2), (C3), (C4), and (C5). A terminal that outputs a predetermined frequency first is specified by the clock system definition (C1) to (C5).

  From FIG. 10, in each of the clock system definitions (C1) to (C4), a clock system name, a clock cycle, a signal rise / fall time, a clock output instance / pin name, and the like are defined. The clock system definition (C5) defines the point at which the frequency is changed by the ½ frequency divider of fffl, and the new clock system name, the instance / pin name of the clock system of the frequency dividing source, and the clock of the frequency dividing source The designation of which edge is changed and the output instance / pin name of the divided clock are defined.

  When grouping is performed based on the clock system defined as described above, for example, a result as shown in FIG. 11 is obtained. FIG. 11 is a diagram illustrating an example of the result of grouping. In FIG. 11, inbuf1 and sscg1 are grouped by the clock system of (C1) clkin1, and inbuf2 and sscg2 are grouped by the clock system of (C2) clkin2. Further, buf1, buf2, buf3, cpu1, outbuf1, and dff1 are grouped by the clock system of (C3) sscgout1, and buf4, buf5, codec1, and outbuf3 are grouped by the clock system of (C4) sscgout2. Furthermore, memcon1 and outbuf2 are grouped by the clock system of (C5) memclk.

  FIG. 12 is a diagram illustrating a definition example of frequency modulation data and frequency modulation allocation data. In FIG. 12, for each SSCG macro (SSCG1A, SSCG1B), frequency modulation data 3n in which the cycle variation ratio is associated with the reference cycles A and B is prepared in advance and stored in the storage unit 130.

  In this example, for SSCG1A, in the reference cycle A, 0% in the first cycle, 0.1% in the second cycle, ..., -0.1% in the 9999th cycle, 0% in the 10,000th cycle. Frequency modulation data 3n indicating the period variation ratio is prepared.

  Also, for SSCG1B, in the reference cycle B, a frequency showing a cycle variation ratio of 0% in the first cycle, 1% in the second cycle, -1% in the 4999th cycle, and 0% in the 5000th cycle. Modulation data 3n is prepared.

  Based on the clock system, the frequency modulation data 3n of SSCG1A is assigned to (C3) sscgout1, the frequency modulation data 3n of SSCG1B is assigned to (C4) sscgout2, and SSCG1A is assigned to (C5) memclk. The frequency modulation allocation data 3p to which the frequency modulation data 3n is allocated is prepared.

  As described above, the frequency modulation data 3n and the frequency modulation allocation data 3p associate each clock system name defined in the SDC with the frequency modulation data.

  Next, an example of a Δtn calculation result by the Δtn calculation unit 46 will be described with reference to FIG. FIG. 13 is a diagram illustrating an example of a Δtn calculation result. In FIG. 13, the Δtn calculator 46 calculates a difference Δtn between the frequency after modulation and the frequency of the reference cycle for each cycle.

  (C3) In the calculation result of sscgout1, the difference Δtn in the first cycle is 0 ps, the difference Δtn in the second cycle is +5 ps,..., The difference Δtn in the 9999th cycle is −5 ps, and the difference Δtn in the 10000th cycle is 0 ps. It shows that there is. (C4) In the calculation result of sscgout2, the difference Δtn in the first cycle is 0 ps, the difference Δtn in the second cycle is +200 ps,..., The difference Δtn in the 4999th cycle is −200 ps, and the difference Δtn in the 5000th cycle is 0 ps. It shows that there is. (C5) In the calculation result of memclk, the difference Δtn in the first cycle is 0 ps, the difference Δtn in the second cycle is +10 ps,..., The difference Δtn in the 9999th cycle is −10 ps, and the difference Δtn in the 10000th cycle is 0 ps. It shows that there is.

  Next, processing by the power waveform processing unit 47 when the LSI chip 8 is taken as an example will be described. FIG. 14 is a diagram for explaining a processing example by the power waveform processing unit. In FIG. 14, the in-chip power supply current data 3m is data extracted by the current waveform extraction unit 41, and the in-chip power supply current data 3m can be classified for each clock system using the clock system name.

  For the in-chip power supply current data 3m of each clock system, the in-chip power supply current data 3r after frequency modulation is created by the method described with reference to FIG. 7 using the clock period 3d (SDC definition) and Δtn data. At this time, from the viewpoint of processing time, a power supply current corresponding to several tens of cycles of the main clock is generated. In this example, it is assumed that a current waveform for 200 ns corresponding to 10 cycles of codec 1 operating at 50 MHz is created.

  In the current waveform processing by the power waveform processing unit 47, the current waveform time after frequency modulation is calculated for each clock system with reference to the number of cycles of Δtn data and the reference clock cycle T0, and the maximum time is obtained.

  The current waveform time after frequency modulation and the maximum current waveform time are obtained as follows.

Current waveform time after frequency modulation = {initial_delay} + {number of cycles of Δtn data} × {T0}
Maximum current waveform time = maximum value of current waveform time after frequency modulation of each clock system Here, {initial_delay} is an arbitrary initial time from time 0 to the first clock transition. In this example, {initial_delay} = 0.

  In the example of FIG. 11, the current waveform time after frequency modulation is as follows.

Current waveform time after frequency modulation of sscgout1
= 0 + 10000 × 5000ps
= 50μsec
Current waveform time after frequency modulation of sscgout2
= 0 + 5000 × 2000ps
= 10μsec
Current waveform time after frequency modulation of memclk
= 0 + 10000 × 10000ps
= 100 μsec
Therefore, the maximum current waveform time is 100 μsec.

  For each clock system, the current waveform (200 ns) before frequency modulation is replicated by repeating the maximum current waveform time. The current waveform for 200 ns is repeated 500 times to create a modulated current waveform.

  At this time, the clock system in which Δtn data exists is subjected to frequency modulation processing by the method described in FIG.

  In order to create a current waveform having a length of 500 times when this embodiment is not applied, for example, when the processing time for creating a current waveform for 200 ns is 10 hours, the current waveform is 500 times that of 5000 hours. Processing time is required.

  On the other hand, as described above, in the processing of the current waveform in this embodiment, for example, the processing can be performed in a very single time of about 1 hour, so that the current waveform after frequency modulation is processed in a processing time of 10 hours + 1 hour = 11 hours. Can be created.

  According to the present embodiment, by adjusting the timing at which the current waveform of the power supply noise model is generated for each cycle based on the frequency modulation data and processing the current waveform model, the creation time of the current model of the chip power supply is reduced. It can be shortened.

  The present invention is not limited to the specifically disclosed embodiments, and various modifications and changes can be made without departing from the scope of the claims.

The following additional notes are further disclosed with respect to the embodiment including the above examples.
(Appendix 1)
Using the frequency modulation data stored in the storage unit, the timing of generating the current waveform of the power supply noise model is adjusted for each cycle, and the power supply current data in the chip is processed,
A current model creation method in which a computer executes a procedure of outputting a current model including a modulated current waveform obtained by processing the in-chip power supply current data to the storage unit.
(Appendix 2)
The current model creation method according to appendix 1, wherein a timing at which the current waveform is generated is adjusted using the frequency modulation data for each cycle based on a clock period of a reference clock supplied for each clock system.
(Appendix 3)
The current model creation method according to appendix 2, wherein the frequency modulation data represents frequency modulation for each clock system.
(Appendix 4)
The current model creation method according to claim 2, wherein the frequency modulation data represents a period variation ratio with respect to the reference clock for each clock system.
(Appendix 5)
The current model creation method according to appendix 3 or 4, wherein a difference in period from the reference clock is obtained from the frequency modulation data and the clock period, and the timing is adjusted based on the difference.
(Appendix 6)
The storage unit stores frequency modulation allocation data in which frequency modulation data for each clock system is associated with a clock system name based on the definition of the clock period,
6. The current model creation method according to appendix 5, wherein the difference is obtained from the clock period for each clock system and the frequency modulation data associated with the clock system name.
(Appendix 7)
Any one of appendices 1 to 6, wherein the timing for generating the current waveform of the power supply noise model is adjusted for each cycle while the current waveform for a predetermined period based on the power supply current data in the chip is repeatedly replicated The current model creation method according to one item.
(Appendix 8)
A storage unit for storing frequency modulation data for reducing power supply noise;
Using the frequency modulation data stored in the storage unit, a timing for generating a current waveform of a power supply noise model is adjusted for each cycle, and a current waveform processing unit that processes power current data in a chip;
A model output unit that outputs a current model including a modulated current waveform obtained by the current waveform processing unit to the storage unit;
A CAD apparatus comprising:
(Appendix 9)
The CAD apparatus according to appendix 8, wherein the timing at which the current waveform is generated is adjusted using the frequency modulation data for each cycle based on a clock period of a reference clock supplied for each clock system.
(Appendix 10)
Using the frequency modulation data stored in the storage unit, the timing of generating the current waveform of the power supply noise model is adjusted for each cycle, and the power supply current data in the chip is processed,
A current model creation program for causing a computer to execute a process of outputting a current model including a modulated current waveform obtained by the processing to the storage unit.
(Appendix 11)
11. The current model creation program according to appendix 10, wherein a timing at which the current waveform is generated is adjusted using the frequency modulation data for each cycle based on a clock period of a reference clock supplied for each clock system.

DESCRIPTION OF SYMBOLS 1 Power supply model 1a Chip power supply model 1b PKG power supply model 1c PCB power supply model 3a In-chip arrangement wiring data 3b Cell current waveform table 3c Instance operation timing 3d Clock period 3e Net list 3f Cell power supply capacity library 3g Wiring sheet resistance 3h PKG power supply RL
3i In-chip power supply wiring resistance 3j In-chip power supply capacitance 3m In-chip power supply current data 3n Frequency modulation data 3p Frequency modulation allocation data 3q Δtn data 3r In-chip power supply current data 3t Modulated current model 3s Chip power supply RC model 11 CPU
DESCRIPTION OF SYMBOLS 12 Main memory device 13 Auxiliary memory device 14 Input device 15 Display device 16 Output device B bus 18 Drive 19 Storage medium 41 Current waveform extraction part 42 Capacity extraction part between power supplies 43 Power supply wiring resistance extraction part 44 Voltage drop analysis part 45 Voltage convergence determination 45 Unit 46 Δtn calculation unit 47 current waveform processing unit 48 model output unit 100 CAD device

Claims (6)

Using the frequency modulation data stored in the storage unit, the timing of generating the current waveform of the power supply noise model is adjusted for each cycle, and the power supply current data in the chip is processed,
A current model creation method in which a computer executes a procedure of outputting a current model including a modulated current waveform obtained by processing the in-chip power supply current data to the storage unit.   2. The current model creation method according to claim 1, wherein timing for generating the current waveform is adjusted using the frequency modulation data for each cycle based on a clock period of a reference clock supplied for each clock system. .   The current model creation method according to claim 2, wherein the frequency modulation data represents frequency modulation for each clock system.   3. The current model creation method according to claim 2, wherein the frequency modulation data represents a period variation ratio with respect to the reference clock for each clock system.   5. The current model creation method according to claim 3, wherein a difference in period from the reference clock is obtained from the frequency modulation data and the clock period, and the timing is adjusted based on the difference. A storage unit for storing frequency modulation data for reducing power supply noise;
Using the frequency modulation data stored in the storage unit, a timing for generating a current waveform of a power supply noise model is adjusted for each cycle, and a current waveform processing unit that processes power current data in a chip;
A model output unit that outputs a current model including a modulated current waveform obtained by the current waveform processing unit to the storage unit;
A CAD apparatus comprising:

Images