JP2014123185A - Semiconductor integrated circuit and operation method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit that interrupts a read operation of a built-in nonvolatile memory by a central processing unit when a power source voltage of the built-in nonvolatile memory is reduced, and executes re-read operation of the built-in nonvolatile memory by the central processing unit when the power source voltage stops changing.SOLUTION: The semiconductor integrated circuit comprises: a built-in nonvolatile memory 12 storing a program executed by a central processing unit 11A; internal power source circuits 13A, B, and C generating an internal operation voltage V_ROM and supplying the internal operation voltage to the memory 12; and an internal power source voltage detection circuit 16 detecting reduced internal operation voltage to a level at which the read operation of the memory 12 is risky, and stopping the read operation of the memory by the central processing unit. The internal power source voltage detection circuit 16 detects increased internal operation voltage to a level at which the read operation of the memory is safe after the reduction in the internal operation voltage, and then resumes the read operation of the memory by the central processing unit.

Description

  The present invention relates to a semiconductor integrated circuit and an operation method thereof, and more particularly, when a power supply voltage of a built-in nonvolatile memory is lowered, the reading operation of the built-in nonvolatile memory by the central processing unit is interrupted and the fluctuation of the power supply voltage is finished. The present invention relates to a technique effective for executing a re-read operation of a built-in nonvolatile memory by a processing unit.

  Patent Document 1 below describes a technique for reducing a peak current during a program operation or a verify operation in a semiconductor storage system mounted with a plurality of NAND flash memory chips. A plurality of memory chips are commonly connected to a power supply wiring, and a power supply voltage is supplied to the plurality of memory chips through the power supply wiring. Each chip of the plurality of memory chips includes a voltage detection circuit that detects the power supply voltage of the power supply wiring. When a drop in the power supply voltage is detected by the voltage detection circuit, the operation of the flash memory chip until the power supply voltage is restored. Is controlled so as not to make a transition to, for example, a program operation. In other words, the memory chip is put into a waiting state without shifting to the program state, and it is possible to prevent a further decrease in the power supply voltage.

  Patent Document 2 below describes a flash memory using a split gate type MONOS memory having a memory gate and a selection gate.

JP 2012-138158 A JP 2011-210292 A

  Prior to the present invention, the present inventors mounted a central processing unit (CPU) and a built-in nonvolatile memory, and a single chip capable of storing a control program for the central processing unit (CPU) in the built-in nonvolatile memory. He was engaged in the development of semiconductor integrated circuits such as microcomputers.

  In this development, the present inventors have made the following studies on the high-speed read operation of the built-in nonvolatile memory mounted on the single-chip microcomputer and the high reliability of the memory retention performance.

  In previous single-chip microcomputers, the control program for the central processing unit (CPU) was stored in a mask ROM (Read Only Memory). If there was a bug in the control program stored in the mask ROM There is a problem that the manufacturing mask for manufacturing the mask ROM needs to be changed in the semiconductor manufacturing process, and the development period becomes long. In order to solve this problem, most of recent single-chip microcomputers are equipped with a built-in nonvolatile memory capable of storing a control program of a central processing unit (CPU).

  Non-volatile memory is a flash memory that starts with an EEPROM that can erase data by ultraviolet rays, and has developed an EEPROM that can be electrically written / erased in units of 1 byte. Has been developed. Flash memory is classified into NAND type and NOR type from the viewpoint of cell array. The NAND flash memory is suitable for data storage for large-capacity storage because a plurality of memory cells are connected in series to one bit line and the bit line contract area is reduced. In the NOR type flash memory, since a plurality of memory cells are connected in parallel to one bit line, the read speed is higher than that in the NAND type. However, in the NOR type flash memory, since two memory cells connected in parallel are connected to one bit line by one bit line control, the bit line control area increases, so that data storage for large capacity storage is possible. It is not suitable for. Therefore, the NOR flash memory is used as a relatively small-capacity built-in nonvolatile memory for storing a control program of the central processing unit (CPU) by utilizing the feature that the reading speed is high.

  A single-chip microcomputer equipped with a NOR-type flash memory as a relatively small-capacity built-in non-volatile memory usually reads a program directly from the built-in non-volatile memory without having a cache memory. Random access is required by a high-speed random access performance.

  Further, the NOR flash memory is classified into a single transistor type memory cell and a multi-transistor type memory cell based on the number of memory cell transistors.

  In the single transistor type, one nonvolatile memory cell includes a single transistor, and a charge storage layer is formed on the surface of the channel between the source and drain via a gate insulating film. A control gate is formed on the surface via an interlayer insulating film. When a positive voltage is applied to the control gate, negatively charged electrons are injected from the channel into the charge storage layer, the threshold voltage of the MOS transistor is increased, and writing is performed. On the other hand, when a negative voltage is applied to the control gate, negative charge electrons are emitted from the charge storage layer, the threshold voltage of the MOS transistor is lowered, and erasing is performed. When a single transistor is employed in the NOR type flash memory, both the low threshold voltage and the high threshold voltage are set to the enhancement mode. For example, when the low threshold voltage is in the depletion mode, a leak current always flows between the bit line and the ground potential in the NOR flash memory.

  In the multi-transistor type, one nonvolatile memory cell includes at least two transistors of a memory transistor and a selection transistor. A memory gate electrode as a charge storage layer of the memory transistor is formed on the surface of a portion between the source and the drain in the vicinity of the source via a gate insulating film, and the channel between the source and the drain is formed. A selection gate electrode as a gate electrode of the selection transistor is formed on the surface of the portion close to the drain via a gate insulating film. When a positive voltage is applied to the memory gate electrode and the selection gate electrode, negative charge electrons are injected into the memory gate electrode as a charge storage layer of the memory transistor from a portion close to the source, and the threshold voltage of the MOS transistor is increased. Writing is performed. This injection of negatively charged electrons into the memory gate electrode from a portion close to the source is called source side injection. When a negative voltage is applied to the memory gate electrode, negatively charged electrons are emitted from the memory gate electrode as a charge storage layer, and the threshold voltage of the MOS transistor is lowered to perform erasure. The read operation of the nonvolatile memory cell is performed during a period in which the selection transistor is controlled to be turned on by applying a positive voltage to the selection gate electrode. During the period in which the selection transistor is controlled to be in the ON state in this way, a read voltage having an intermediate level between the low threshold voltage and the high threshold voltage is applied to the memory gate electrode. When the memory transistor is in a high threshold voltage writing state, the memory transistor is turned off, so that the bit line is maintained at a high voltage precharge voltage level. When the memory transistor is in a low threshold voltage write state, the memory transistor is turned on, so that the bit line changes from the precharge voltage level, which is a high voltage, to the ground voltage. Therefore, it is possible to determine whether the nonvolatile memory cell is in the writing state or the erasing state by determining whether the bit line potential is a high voltage or a low voltage by the sense amplifier. In this multi-transistor type, the threshold voltage of the memory transistor can be in a wide range from a low threshold voltage depletion mode to a high threshold voltage enhancement mode. That is, when the non-volatile memory cell is not selected, the selection transistor is controlled to be turned off. Therefore, even when the depletion mode with the low threshold voltage is entered, the selection transistor controlled to be in the OFF state prevents the leakage current from always flowing between the bit line and the ground potential. Furthermore, since the read current of the nonvolatile memory cell can be increased by setting the threshold voltage of the memory transistor in a wide range, a high-speed read operation can be realized. Note that the multi-transistor type including the memory gate electrode and the selection gate electrode is called a split gate structure.

  Further, NOR type or NAND type flash memories are classified into floating gate type and MONOS type when classified from the device structure. The floating gate type is manufactured by a two-layer polysilicon manufacturing process, in which a floating gate as a charge storage layer is formed by lower polysilicon, and a control gate is formed by upper polysilicon. The MONOS type is an abbreviation for Metal Oxide Nitride Oxide, and uses a three-layer stacked gate insulating film of an oxide film (Oxide), a nitride film (Nitride), and an oxide film (Oxide) as a charge storage layer. More specifically, high threshold writing is achieved by injecting and holding negatively charged electrons and positively charged holes in the electron trap level and hole trap level existing in the nitride film, respectively. State and low threshold erase state. Furthermore, since the MONOS type holds stored charges at the trap level, it has a feature of high memory holding performance and high reliability as compared with the floating gate type. That is, in the floating gate type flash memory, electric charges are charged in the floating gate formed of polysilicon as a conductor. Therefore, if a charge discharge route due to a defect or the like is formed in the gate insulating film or the interlayer insulating film, the floating gate type flash memory is floating. There is a risk that all the accumulated charge of the gate flows out, and there is a problem in memory retention performance and reliability. On the other hand, in the MONOS flash memory, charges are trapped in the trap level in the nitride film, which is an insulating film. Therefore, even if a charge discharge route due to defects or the like is formed in the gate insulating film or the interlayer insulating film. In addition, the risk that all accumulated charges in the nitride film flow out is low, and the memory retention performance is high and the reliability is high.

  Prior to the present invention described above, the present inventors have reached the following conclusions by studying by the present inventors.

  That is, in order to realize high-speed read operation of the built-in nonvolatile memory by the central processing unit (CPU), a NOR flash memory in which a plurality of memory cells are connected in parallel to one bit line is suitable. Furthermore, in order to improve the high speed of the read operation, it is preferable to increase the read current of the memory cell by using a multi-transistor type memory cell (a split gate type memory cell) instead of a single transistor type memory cell. It is.

  Furthermore, since the control program for the central processing unit (CPU) is stored in the built-in nonvolatile memory of the single-chip microcomputer, if the data of the control program stored in the built-in nonvolatile memory is destroyed, the system equipped with the microcomputer There is a risk of serious failure in the operation. For example, if a microcomputer is executing brake control for an automobile, it may directly cause a serious traffic accident. Therefore, in order to improve the reliability of the memory retention performance of the built-in nonvolatile memory that stores the control program for the central processing unit (CPU), not the floating gate type but the MONOS type that has a low risk of stored charges flowing out. A flash memory is preferred.

  In the background described above, prior to the present invention, the present inventors have used a MONOS type multi-transistor type (split type) in a built-in nonvolatile memory for storing a control program for a central processing unit (CPU) of a single chip microcomputer. (Gate type) NOR type flash memory of the memory cell is decided to be adopted.

  However, prior to the present invention, the present inventors have encountered the following problems in the study of the single chip microcomputer equipped with the above-described built-in nonvolatile memory for storing the control program.

  That is, the high-speed read operation of the built-in non-volatile memory changes the power supply voltage of the CPU core of the single chip microcomputer, and the read operation of the built-in non-volatile memory by the central processing unit (CPU) becomes impossible. Accordingly, it has been clarified by the examination by the inventors prior to the present invention that the timing at which the fluctuation of the power supply voltage ends and the read operation can be performed again cannot be confirmed.

  The inventors examined the cause of this in advance prior to the present invention, and as a result, the mechanism described below was clarified. That is, an access operation of the built-in nonvolatile memory for storing the control program is started by an instruction fetch operation by the central processing unit (CPU), and all bit lines of the NOR type flash memory of the MONOS type multi-transistor type memory cell are started. Power supply voltage level precharge is started. Therefore, the power supply voltage level is lowered by precharging all the bit lines at the start of the access operation. Thereafter, all the sense amplifiers connected to all the bit lines are activated, and at least 32 bits of data output signals selected by the column gate circuit from all the sense output signals of all the sense amplifiers are activated. The data is output to the internal data bus via the output buffer circuit. Accordingly, all the sense amplifiers and at least 32 data output buffer circuits are activated, and the power supply voltage level of the built-in nonvolatile memory is greatly lowered by the data output operation to the internal data bus of the built-in nonvolatile memory. The power supply voltage of the built-in nonvolatile memory is determined by the power supply voltage of the CPU core of the single chip microcomputer.

  On the other hand, since the microcomputer executes the pipeline operation, the instruction execution operation of the microcomputer is executed in parallel with the instruction fetch operation by the central processing unit (CPU). On the other hand, in the instruction execution operation, not only the instruction execution operation of the central processing unit (CPU), but also the instruction execution operation of the floating point arithmetic unit (FPU) and the digital multiplier (MULT) and the direct memory access controller (DMAC). Instruction execution operations are included. The power supply voltage of the central processing unit (CPU), the floating point arithmetic unit (FPU), and the digital multiplier (MULT) is determined by the power supply voltage of the CPU core of the single chip microcomputer, and the direct memory access controller (DMAC) is also the CPU. Use the core supply voltage. Of the various instruction execution operations described above, the power supply voltage level of the CPU core is greatly reduced during heavy load instruction execution operations.

  As a result, a significant decrease in the CPU core power supply voltage level due to the data output operation to the internal data bus of the built-in nonvolatile memory is superimposed on a large decrease in the CPU core power supply voltage level due to the heavy load instruction execution operation. Therefore, the power supply voltage level of the CPU core is further greatly reduced. Therefore, the data output operation to the internal data bus of the built-in nonvolatile memory becomes impossible during the period in which the power supply voltage level of the CPU core is greatly reduced due to this superposition. As a result, the reading operation of the built-in nonvolatile memory by the central processing unit (CPU) becomes impossible, and it becomes impossible to confirm the timing when the fluctuation of the power supply voltage is finished and the reading operation becomes possible again.

  Means for solving such problems will be described below, but other problems and novel features will become apparent from the description of the present specification and the accompanying drawings.

  The outline of the typical embodiment disclosed in the present application will be briefly described as follows.

  That is, the semiconductor integrated circuit (1) according to the representative embodiment includes a central processing unit (11A), a built-in nonvolatile memory (12), internal power supply circuits (13A, B, C), and an internal power supply voltage detection circuit (16). ).

  The built-in nonvolatile memory (12) can store a program executed by the central processing unit (11A).

The internal power supply circuit (13A, B, C) is to generate an internal operating voltage _(V DD _ROM), is with the internal operating voltage _(V DD _ROM) can be supplied to the internal nonvolatile memory (12).

It said internal nonvolatile said internal operating voltage to a level that the read operation is a risk of the memory (12) (V _DD _ROM) said internal power supply voltage detecting circuit to decrease (16) is detectable, the detection result In response, the reading operation of the built-in nonvolatile memory (12) by the central processing unit (11A) is stopped.

The internal operating voltage (V _DD _ROM) said internal power supply voltage detecting circuit in that the said internal operating voltage to a level that the read operation is safe internal nonvolatile memory (12) (V _DD _ROM) rises after lowering of the ( 16) can be detected, and in response to the detection result, the reading operation of the built-in nonvolatile memory (12) by the central processing unit (11A) is resumed (see FIG. 1).

  The following is a brief description of an effect obtained by the typical embodiment of the embodiments disclosed in the present application.

  That is, according to this semiconductor integrated circuit, when the power supply voltage of the built-in nonvolatile memory is lowered, the reading operation of the built-in nonvolatile memory by the central processing unit is interrupted, and when the fluctuation of the power supply voltage is finished, the built-in by the central processing unit A re-read operation of the non-volatile memory can be executed.

FIG. 1 is a diagram showing a configuration of a CPU core 10 of the semiconductor integrated circuit 1 according to the first embodiment. FIG. 2 is a diagram for explaining an ideal pipeline operation including an instruction fetch operation executed by the CPU core 10 in the semiconductor integrated circuit 1 according to the first embodiment shown in FIG. 3, the first to detect a drop in operating voltage V _DD _ROM power supply voltage detection circuit 16 is the internal nonvolatile memory 12 of the CPU core 10 of the semiconductor integrated circuit 1 of the first embodiment shown in FIG. 1 It is a figure which shows a mode that the fetch interrupt controller 17 produces | generates the high level "H" fetch interrupt request signal F_IRQ in response to the detection result. 4 shows the fetch interrupt request signal F_IRQ, the internal bus clock Int_Bus_Clk, the internal address bus Int_Adr_Bus, the internal data bus Int_Dt_Bus, and other memory access signals in the period from the third cycle time T3 to the sixth cycle time T6 shown in FIG. It is a figure which shows the waveform change. FIG. 5 is a diagram for explaining an actual pipeline operation including an instruction fetch operation executed by the CPU core 10 in the semiconductor integrated circuit 1 according to the first embodiment shown in FIG. FIG. 6 is a diagram showing a structure of a built-in nonvolatile memory (Flash ROM) 12 included in the CPU core 10 of the semiconductor integrated circuit 1 according to the first embodiment shown in FIG. FIG. 7 shows a structure of a nonvolatile flash memory cell F_MC constituting a split gate type memory cell of the built-in nonvolatile memory 12 included in the CPU core 10 of the semiconductor integrated circuit 1 of the first embodiment shown in FIG. FIG. 8 shows the electrical characteristics of the nonvolatile flash memory cell F_MC constituting the split gate type memory cell of the built-in nonvolatile memory 12 included in the CPU core 10 of the semiconductor integrated circuit 1 of the first embodiment shown in FIG. FIG. FIG. 9 is a diagram showing a structure of a non-volatile flash memory cell F_MC constituting a single transistor type memory cell as a comparative reference example of the present invention. FIG. 10 is a diagram showing a configuration of the semiconductor integrated circuit 1 configured as a single-chip microcomputer including the CPU core 10 according to the first embodiment.

1. First, an outline of a typical embodiment disclosed in the present application will be described. The reference numerals of the drawings referred to in parentheses in the outline description of the representative embodiment merely exemplify what is included in the concept of the component to which the reference numeral is attached.

  [1] A semiconductor integrated circuit (1) according to a typical embodiment includes a central processing unit (11A), a built-in nonvolatile memory (12), internal power supply circuits (13A, B, C), and an internal power supply voltage detection circuit ( 16).

  The built-in nonvolatile memory (12) can store a program executed by the central processing unit (11A).

The internal power supply circuit (13A, B, C) is to generate an internal operating voltage _(V DD _ROM), is with the internal operating voltage _(V DD _ROM) can be supplied to the internal nonvolatile memory (12).

It said internal nonvolatile said internal operating voltage to a level that the read operation is a risk of the memory (12) (V _DD _ROM) said internal power supply voltage detecting circuit to decrease (16) is detectable, the detection result In response, the reading operation of the built-in nonvolatile memory (12) by the central processing unit (11A) is stopped.

The internal operating voltage (V _DD _ROM) said internal power supply voltage detecting circuit in that the said internal operating voltage to a level that the read operation is safe internal nonvolatile memory (12) (V _DD _ROM) rises after lowering of the ( 16) can be detected, and in response to the detection result, the reading operation of the built-in nonvolatile memory (12) by the central processing unit (11A) is resumed (see FIG. 1).

  According to the embodiment, when the power supply voltage of the built-in nonvolatile memory is lowered, the reading operation of the built-in nonvolatile memory by the central processing unit is interrupted, and when the fluctuation of the power supply voltage is further finished, the built-in nonvolatile data by the central processing unit A memory re-read operation can be performed.

In a preferred embodiment, the higher voltage level than the voltage level of the minimum operating voltage (V _DD _limit) of the internal operating voltage reading operation of the internal nonvolatile memory (12) becomes impossible (V _DD _ROM) The internal power supply voltage detection circuit (16) can detect that the internal operating voltage (V _DD _ROM) falls below the set first threshold value (Vth1).

The second threshold value first threshold (Vth1) the internal operating voltage below (V _DD _ROM) is set to a voltage level higher than the voltage level of the first threshold value (Vth1) after reduction (Vth2) said that the internal operating voltage (V _DD _ROM) rises above, the internal power supply voltage detecting circuit (16) is detectable.

Said that the internal operating voltage (V _DD _ROM) decreases the internal power supply voltage detection circuit (16) is detected below the first threshold value (Vth1), the internal power supply voltage detecting circuit (16) is first 1 detection result is generated.

In response to the internal operating voltage (V _DD _ROM) said internal power supply voltage detecting circuit (16) said first detection result generated from upon decreased below the first threshold value (Vth1), the central The reading operation of the built-in nonvolatile memory (12) by the processing unit (11A) is stopped.

Said that the internal operating voltage (V _DD _ROM) increases the internal power supply voltage detection circuit (16) detects the second threshold value (Vth2) or more, the internal power supply voltage detecting circuit (16) is first 2 Generate a detection result.

In response to the internal operating voltage (V _DD _ROM) said internal power supply voltage and the second detection result generated from the detection circuit (16) when rises to the second threshold value (Vth2) or more, the central The read operation of the built-in nonvolatile memory (12) by the processing unit (11A) is resumed (see FIG. 1).

  In another preferred embodiment, the central processing unit (11A) executes the read operation of the built-in nonvolatile memory (12) to execute the program stored in the built-in nonvolatile memory (12). An instruction fetch unit (11A) for executing an instruction fetch operation is included.

In response to the first detection result generated from the internal power supply voltage detection circuit (16) when the internal operating voltage (V _DD _ROM) drops below the first threshold (Vth1), the command The instruction fetch operation by the fetch unit (11A) is stopped.

In response to the internal operating voltage (V _DD _ROM) said internal power supply voltage and the second detection result generated from the detection circuit (16) when rises to the second threshold value (Vth2) or more, the instruction The instruction fetch operation by the fetch unit (11A) is resumed (see FIG. 1).

  In still another preferred embodiment, the semiconductor integrated circuit (1) further includes a fetch interrupt controller (17).

  The fetch interrupt controller (17) is supplied with the first detection result generated from the internal power supply voltage detection circuit (16) and the second detection result generated from the internal power supply voltage detection circuit (16). Is done.

In response to the internal operating voltage (V _DD _ROM) said internal power supply voltage detecting circuit (16) said first detection result generated from upon decreased below the first threshold value (Vth1), the fetch The interrupt controller (17) stops the instruction fetch operation by the instruction fetch unit (11A).

In response to the internal operating voltage (V _DD _ROM) said internal power supply voltage and the second detection result generated from the detection circuit (16) when rises to the second threshold value (Vth2) or more, the fetch The interrupt controller (17) restarts the instruction fetch operation by the instruction fetch unit (11A) by the central processing unit (11A) (see FIG. 1).

  In a more preferred embodiment, the semiconductor integrated circuit executes a pipeline operation including at least an instruction fetch stage (IF), an instruction decode stage (ID), an instruction execution stage (EX), and a memory access stage (MEM). To do.

  The instruction fetch stage (IF) is executed by the instruction fetch operation of the instruction fetch unit (11A).

  The instruction decode stage (ID) executes decoding of an instruction fetched by the instruction fetch operation of the instruction fetch stage (IF).

  The instruction execution stage (EX) executes the instruction decoded in the instruction decode stage (ID).

  The memory access stage (MEM) executes storage of the execution result of the instruction executed in the instruction execution stage (EX) in a memory (see FIG. 2).

  In another more preferred embodiment, it is to be fetched by the instruction fetch operation of the instruction fetch unit (11A) during a period (T4, T5) in which the internal operating voltage drops below the first threshold. Regarding an instruction, a no operation (Nop) is executed during the instruction execution stage (EX) of the instruction to be fetched (see FIG. 5).

  In still another more preferred embodiment, the semiconductor integrated circuit (1) further includes another functional block (11B).

The internal power supply circuit (13A, B, C) is further can be supplied to said internal operating voltage (V _DD _ROM) said central processing unit (11A) and the other functional blocks (11B).

Operating voltage of the central processing unit (11A) (V _DD _CPU) and the other functional blocks operating voltage of (11B) (V _DD _FPU) and said internal operating voltage supplied to said internal nonvolatile memory (12) It is superimposed on (V _DD _ROM), wherein the voltage level of the superimposed said internal operating voltage (V _DD _ROM) internal power supply voltage detecting circuit (16) is detectable.

Wherein the superimposed internal operating voltage (V _DD _ROM) is detected by the internal power supply voltage detecting circuit (16) to be lowered to the first threshold value (Vth1) below, the internal power supply voltage detecting circuit (16 ) Generates the first detection result.

Wherein the superimposed internal operating voltage (V _DD _ROM) is that the internal power supply voltage detecting circuit (16) detects rises to the second threshold value (Vth2) or more, the internal power supply voltage detecting circuit (16 ) Is characterized in that the second detection result is generated (see FIG. 1).

  In another more preferred embodiment, the other functional block is a floating point arithmetic unit (11B) (see FIG. 1).

  In still another more preferred embodiment, the built-in nonvolatile memory (12) is a NOR nonvolatile memory in which a plurality of nonvolatile memory cells (F_MC) are connected in parallel to each bit line of a plurality of bit lines. (See FIG. 6).

  In a specific embodiment, each memory cell (F_MC) of the plurality of nonvolatile memory cells includes a selection transistor (QnS) and a memory transistor (QnM) connected in series between each bit line and a ground potential. This is a split gate nonvolatile memory cell including the above (see FIG. 6).

  In another specific embodiment, the memory transistor (QnM) has a MONOS type structure using a three-layer gate insulating film of a first oxide film, a nitride film, and a second oxide film. (See FIG. 10).

  In a more specific embodiment, the built-in nonvolatile memory (12) is capable of storing an execution result of an instruction by the central processing unit (11A).

  In another more specific embodiment, the CPU core (10) including the central processing unit, the built-in nonvolatile memory, the internal power supply circuit, the internal power supply voltage detection circuit, and the fetch interrupt controller is directly connected to the CPU core (10). A peripheral core (20) including at least a memory access controller (21), a bus state controller (22), and an interrupt controller (23) is connected.

  The CPU core (10) is further connected to an analog core (30) including at least an analog / digital converter (31) and a digital / analog converter (32).

  In the most specific embodiment, the semiconductor integrated circuit (1) including the CPU core (10), the peripheral core (20), and the analog core (30) is a single chip microcomputer. It is a characteristic (see FIG. 10).

  [2] A typical embodiment of another viewpoint is that a central processing unit (11A), a built-in nonvolatile memory (12), an internal power supply circuit (13A, B, C), an internal power supply voltage detection circuit (16), The operation method of the semiconductor integrated circuit (1) comprising:

  The built-in nonvolatile memory (12) can store a program executed by the central processing unit (11A).

The internal power supply circuit (13A, B, C) is to generate an internal operating voltage _(V DD _ROM), is with the internal operating voltage _(V DD _ROM) can be supplied to the internal nonvolatile memory (12).

It said internal nonvolatile said internal operating voltage to a level that the read operation is a risk of the memory (12) (V _DD _ROM) said internal power supply voltage detecting circuit to decrease (16) is detectable, the detection result In response, the reading operation of the built-in nonvolatile memory (12) by the central processing unit (11A) is stopped.

The internal operating voltage (V _DD _ROM) said internal power supply voltage detecting circuit in that the said internal operating voltage to a level that the read operation is safe internal nonvolatile memory (12) (V _DD _ROM) rises after lowering of the ( 16) can be detected, and in response to the detection result, the reading operation of the built-in nonvolatile memory (12) by the central processing unit (11A) is resumed (see FIG. 1).

  According to the embodiment, when the power supply voltage of the built-in nonvolatile memory is lowered, the reading operation of the built-in nonvolatile memory by the central processing unit is interrupted, and when the fluctuation of the power supply voltage is further finished, the built-in nonvolatile data by the central processing unit A memory re-read operation can be performed.

2. Details of Embodiment Next, the embodiment will be described in more detail. In all the drawings for explaining the best mode for carrying out the invention, components having the same functions as those in the above-mentioned drawings are denoted by the same reference numerals, and repeated description thereof is omitted.

[Embodiment 1]
<Configuration of CPU core of semiconductor integrated circuit>
FIG. 1 is a diagram showing a configuration of a CPU core 10 of the semiconductor integrated circuit 1 according to the first embodiment.

  The CPU core 10 of the semiconductor integrated circuit 1 according to the first embodiment shown in FIG. 1 includes a central processing unit (CPU) 11A, a floating point arithmetic unit (FPU) 11B, a built-in nonvolatile memory (Flash ROM) 12, and an internal power supply circuit. 13A, 13B and 13C, internal power supply switches 14A and 14B, a reference voltage generation circuit 15, an internal power supply voltage detection circuit 16, and a fetch interrupt controller (Fetch_ICU) 17. Further, the CPU core 10 includes a ground wiring GND, an internal address bus Int_Adr_Bus, and an internal data bus Int_Dt_Bus.

≪Central processing unit and built-in nonvolatile memory≫
The central processing unit (CPU) 11A includes a fetch unit (Fetch_Unit) 11A1 that executes an instruction fetch operation for reading a control program stored in a built-in nonvolatile memory (Flash ROM) 12. The fetch unit (Fetch_Unit) 11A1 is connected to a built-in nonvolatile memory (Flash ROM) 12 via an internal address bus Int_Adr_Bus and an internal data bus Int_Dt_Bus. The built-in non-volatile memory (Flash ROM) 12 is composed of a NOR type flash memory that employs a multi-transistor type memory cell and a MONOS structure as discussed above prior to the present invention by the present inventors. is there.

<< Floating-point arithmetic unit >>
Although not shown in FIG. 1, the floating point arithmetic unit (FPU) 11B is roughly coupled to the central processing unit (CPU) 11A. Accordingly, when the instruction fetched by the fetch unit (Fetch_Unit) 11A1 of the central processing unit (CPU) 11A is a floating-point operation, the floating-point arithmetic instruction is floated from the central processing unit (CPU) 11A via the coarse coupling. It is supplied to the decimal point arithmetic unit (FPU) 11B. In accordance with this floating-point arithmetic instruction, the floating-point arithmetic unit (FPU) 11B reads an operand stored in a built-in volatile memory (RAM) (not shown), executes a floating-point arithmetic on this operand, and the operation result is also stored in the internal volatile memory. Stored in a random access memory (RAM).

≪Reference voltage generation circuit≫
The reference voltage generation circuit (RVG) 15 generates a reference voltage Vref that is a substantially constant voltage that does not substantially depend on changes in, for example, the semiconductor manufacturing process (P), the semiconductor chip temperature (T), and the power supply voltage (V). The reference voltage Vref is supplied to the internal power supply circuits 13A, B, and C. For example, the reference voltage generating circuit (RVG) 15 is a band gap reference voltage generating circuit, and generates a reference voltage Vref having a voltage level of approximately 1.2 volts, which is a silicon band gap voltage.

≪Internal power supply circuit≫
The internal power supply circuit 13A includes a differential amplifier 13A1 and an output transistor 13A2. A reference voltage Vref generated from a reference voltage generation circuit (RVG) 15 is supplied to an inverting input terminal − of the differential amplifier 13A1. For example, the output transistor 13A2 is composed of a P-channel MOS transistor, and an external power supply voltage Vcc supplied from the outside of the semiconductor integrated circuit 1 is supplied to the source of this transistor, and the gate and drain of this transistor are the differential amplifier 13A1. The output terminal is connected to the non-inverting input terminal +. From the output transistor 13A2 of the internal power supply circuit 13A by negative feedback controlled operating voltage _V DD _CPU is generated to match the voltage level of the reference voltage Vref, the operation power supply voltage _V DD _CPU a central processing unit (CPU ) Is supplied to 11A.

The internal power supply circuit 13B includes a differential amplifier 13B1 and an output transistor 13B2. A reference voltage Vref generated from a reference voltage generation circuit (RVG) 15 is supplied to an inverting input terminal − of the differential amplifier 13B1. For example, the output transistor 13B2 is composed of a P-channel MOS transistor, and an external power supply voltage Vcc supplied from the outside of the semiconductor integrated circuit 1 is supplied to the source of this transistor, and the gate and drain of this transistor are the differential amplifier 13B1. The output terminal is connected to the non-inverting input terminal +. The output transistor 13B2 of the internal power supply circuit 13B generates an operation power supply voltage V _DD _FPU that is subjected to negative feedback control so as to coincide with the voltage level of the reference voltage Vref. The operation power supply voltage V _DD _FPU is a floating point arithmetic unit ( FPU) 11B.

The internal power supply circuit 13C includes a differential amplifier 13C1 and an output transistor 13C2. The reference voltage Vref generated from the reference voltage generation circuit (RVG) 15 is supplied to the inverting input terminal − of the differential amplifier 13C1. For example, the output transistor 13C2 is composed of a P-channel MOS transistor, and the source of this transistor is supplied with an external power supply voltage Vcc supplied from the outside of the semiconductor integrated circuit 1. The gate and drain of this transistor are connected to the differential amplifier 13C1. The output terminal is connected to the non-inverting input terminal +. From the output transistor 13C2 of the internal power supply circuit 13C negative feedback controlled operating voltage _V DD _ROM is generated to match the voltage level of the reference voltage Vref, the operation power supply voltage _V DD _ROM internal nonvolatile memory ( Flash ROM) 12 is supplied.

≪Internal power switch≫
As shown in FIG. 1, an internal power switch 14A is connected between the power output terminal of the internal power circuit 13A and the power output terminal of the internal power circuit 13C, and the power output terminal of the internal power circuit 13A and the internal power circuit 13B. An internal power switch 14B is connected between the power output terminals of the two.

When the built-in nonvolatile memory (Flash ROM) 12 is controlled to be in a power cut-off state in order to realize low power consumption, the differential amplifier 13C1 and the output transistor 13C2 of the internal power supply circuit 13C are controlled to be in an off state. Further, the internal power switch 14A is controlled to be turned off. Accordingly, the supply of the plurality of operation power supply voltages V _{DD —} CPU, V _{DD —} FPU, and V _{DD —} ROM to the built-in nonvolatile memory (Flash ROM) 12 is stopped, so that the built-in nonvolatile memory (Flash ROM) 12 is in a power-off state. Controlled.

When the central processing unit (CPU) 11A is controlled to be in a power shut-off state in order to realize low power consumption, the differential amplifier 13A1 and the output transistor 13A2 of the internal power supply circuit 13A are controlled to be in an off state. The internal power switches 14A and 14B are controlled to be turned off. Accordingly, the supply of the plurality of operation power supply voltages V _{DD —} CPU, V _{DD —} FPU, and V _{DD —} ROM to the central processing unit (CPU) 11A is stopped, so that the central processing unit (CPU) 11A is controlled to be in a power-off state. .

In order to realize low power consumption, when the floating point arithmetic unit (FPU) 11B is controlled to be in the power cut-off state, the differential amplifier 13B1 and the output transistor 13B2 of the internal power supply circuit 13B are controlled to be in the off state. The internal power switch 14B is controlled to be turned off. Accordingly, the supply of the plurality of operation power supply voltages V _{DD —} CPU, V _{DD —} FPU, and V _{DD —} ROM to the central processing unit (CPU) 11A is stopped, so that the floating point arithmetic unit (FPU) 11B is controlled to be in a power-off state. The

≪Internal power supply voltage detection circuit and central processing unit fetch unit≫
Further, the CPU core 10 according to the first embodiment shown in FIG. 1 has a built-in nonvolatile memory (Flash ROM) that makes it impossible to read out the built-in nonvolatile memory (Flash ROM) 12 by the central processing unit (CPU) 11A. ) 12 includes an internal power supply voltage detection circuit 16 that detects fluctuations in the operating power supply voltage V _{DD —} ROM. The internal power supply voltage detection circuit 16 operates as a hysteresis voltage comparator using the first threshold value Vth1 and the second threshold value Vth2 as reference determination levels. When the operating power supply voltage V _{DD —} ROM of the built-in nonvolatile memory (Flash ROM) 12 falls to the voltage level of the operating lower limit voltage V _{DD —} limit of the built-in nonvolatile memory (Flash ROM) 12, as described at the beginning, the built-in nonvolatile memory It is impossible to read internal data to the internal data bus of the memory (Flash ROM) 12.

Therefore, that the operating power supply voltage _V DD _ROM the minimum operating voltage _V DD _limit first threshold Vth1 internal nonvolatile memory (Flash ROM) 12 below which is set slightly higher voltage level than the voltage level of the drops, The internal power supply voltage detection circuit 16 detects it. The detection result of the internal power supply voltage detection circuit 16 is supplied to the fetch interrupt controller (Fetch_ICU) 17, and in response to the first detection result, the fetch interrupt controller (Fetch_ICU) 17 fetches the fetch interrupt request signal F_IRQ at the high level “H”. Is supplied to the fetch unit (Fetch_Unit) 11A1 of the central processing unit (CPU) 11A. Therefore, the instruction fetch operation by the fetch unit (Fetch_Unit) 11A1 of the central processing unit (CPU) 11A is stopped, and invalid data in the built-in nonvolatile memory (Flash ROM) 12 is fetched by the central processing unit (CPU) 11A as a control program. It is possible to solve the problem.

After the operation power supply voltage V _DD _ROM of the built-in nonvolatile memory (Flash ROM) 12 falls below the first threshold value Vth1 and the instruction fetch operation by the fetch unit (Fetch_Unit) 11A1 is stopped, the built-in nonvolatile memory (Flash Flash) ROM) 12 operating supply voltage _V DD _ROM of it is assumed that rises in recovery. The internal power supply voltage detection circuit 16 has an operation power supply voltage V _DD of the built-in nonvolatile memory (Flash ROM) 12 equal to or higher than the second threshold value Vth2 set to a voltage level slightly higher than the voltage level of the first threshold value Vth1. It detects that the ROM has risen. As a result, a low level “L” fetch interrupt request signal F_IRQ as a second detection result of the internal power supply voltage detection circuit 16 is supplied to the fetch interrupt controller (Fetch_ICU) 17, and the fetch unit (CPU) 11 A of the central processing unit (CPU) 11 A The instruction fetch operation by Fetch_Unit) 11A1 is resumed. Therefore, the control program, which is valid data read from the built-in nonvolatile memory (Flash ROM) 12, is fetched by the central processing unit (CPU) 11A.

  The central processing unit (CPU) 11A is supplied with an interrupt request IRQ generated from an interrupt controller (ICU) included in a peripheral core described later.

≪Ideal pipeline operation including instruction fetch operation≫
FIG. 2 is a diagram for explaining an ideal pipeline operation including an instruction fetch operation executed by the CPU core 10 in the semiconductor integrated circuit 1 according to the first embodiment shown in FIG.

  The instruction fetch IF of FIG. 2 shows an instruction fetch operation executed by the fetch unit (Fetch_Unit) 11A1 of the central processing unit (CPU) 11A. The instruction decode ID of FIG. Fig. 4 illustrates a fetched instruction decoding operation executed by an instruction decoder. Further, the instruction execution EX in FIG. 2 is an instruction executed by an arithmetic unit such as an arithmetic logic unit (ALU) in the central processing unit (CPU) 11A or a floating point arithmetic unit (FPU) 11B. Indicates execution behavior. The memory access MEM in FIG. 2 shows an operation of storing the execution result of the instruction execution EX in a built-in volatile memory (RAM) (not shown). The write back WB in FIG. 2 shows the operation of storing the execution result of the instruction execution EX in the general-purpose register (register file) in the central processing unit (CPU) 11A.

  Times T1, T2,... T6 shown in FIG. 2 indicate cycle times determined by an operation clock CLK (not shown) of the central processing unit (CPU) 11A.

  In the first cycle time T1, the first instruction A is read from the built-in nonvolatile memory (Flash ROM) 12 and fetched by the fetch unit (Fetch_Unit) 11A1 of the central processing unit (CPU) 11A.

  In the second cycle time T2, the second instruction B is read from the built-in nonvolatile memory (Flash ROM) 12 and fetched by the fetch unit (Fetch_Unit) 11A1 of the central processing unit (CPU) 11A. At the same time, the first instruction A is decoded by an instruction decoder inside the central processing unit (CPU) 11A.

  In the third cycle time T3, the third instruction C is read from the built-in nonvolatile memory (Flash ROM) 12 and fetched by the fetch unit (Fetch_Unit) 11A1 of the central processing unit (CPU) 11A. At the same time, the second instruction B is decoded by an instruction decoder in the central processing unit (CPU) 11A, and the first instruction A is decoded by the central processing unit (CPU) 11 or the floating point arithmetic unit (FPU) 11B. Executed.

  In the fourth cycle time T4, the fourth instruction D is read from the built-in nonvolatile memory (Flash ROM) 12 and fetched by the fetch unit (Fetch_Unit) 11A1 of the central processing unit (CPU) 11A. At the same time, the third instruction C is decoded by an instruction decoder inside the central processing unit (CPU) 11A, and the second instruction B is decoded by the central processing unit (CPU) 11 or the floating point arithmetic unit (FPU) 11B. When executed, the execution result of the first instruction A is stored in a built-in volatile memory (RAM) (not shown).

  At the fifth cycle time T5, the fifth instruction E is read from the built-in nonvolatile memory (Flash ROM) 12 and fetched by the fetch unit (Fetch_Unit) 11A1 of the central processing unit (CPU) 11A. At the same time, the fourth instruction D is decoded by an instruction decoder inside the central processing unit (CPU) 11A, and the third instruction C is decoded by the central processing unit (CPU) 11 or the floating point arithmetic unit (FPU) 11B. As a result, the execution result of the second instruction B is stored in a built-in volatile memory (RAM) (not shown). At the same time, the execution result of the first instruction A is stored in a general-purpose register (register file) in the central processing unit (CPU) 11A.

  At the sixth cycle time T6, the sixth instruction F is read from the built-in nonvolatile memory (Flash ROM) 12 and fetched by the fetch unit (Fetch_Unit) 11A1 of the central processing unit (CPU) 11A. At the same time, the fifth instruction E is decoded by an instruction decoder inside the central processing unit (CPU) 11A, and the fourth instruction D is decoded by the central processing unit (CPU) 11 or the floating point arithmetic unit (FPU) 11B. As a result, the execution result of the third instruction C is stored in a built-in volatile memory (RAM) (not shown). At the same time, the execution result of the second instruction B is stored in a general-purpose register (register file) in the central processing unit (CPU) 11A.

<< Generation of Fetch Interrupt Request Signal F_IRQ >>
FIG. 3 shows a first example in which the power supply voltage detection circuit 16 of the CPU core 10 of the semiconductor integrated circuit 1 of the first embodiment shown in FIG. 1 detects a decrease in the operating power supply voltage V _DD _ROM of the built-in nonvolatile memory 12. It is a figure which shows a mode that the fetch interrupt controller 17 produces | generates the high level "H" fetch interrupt request signal F_IRQ in response to the detection result.

FIG. 3A shows that the operating power supply voltage V _DD _FPU of the floating point arithmetic unit (FPU) 11B is equal to the fourth cycle time T4 and the fifth cycle time by the heavy load instruction execution operation of the floating point arithmetic unit (FPU) 11B. It is shown that the cycle time T5 significantly decreases.

In FIG. 3B, the operating power supply voltage V _{DD —} ROM of the built-in nonvolatile memory (Flash ROM) 12 decreases in the second half of each cycle time of the first cycle time T1, the second cycle time T2, and the sixth cycle time T6. It is shown that The decrease in the operating power supply voltage V _{DD —} ROM of the built-in nonvolatile memory (Flash ROM) 12 in the latter half of each cycle time is the activation of all the sense amplifiers connected to all the bit lines of the built-in nonvolatile memory (Flash ROM) 12. This is due to the activation of at least 32 data output buffer circuits.

The FIG. 3 (C), the operating power supply voltage _{V DD} of the floating-point unit 11B operating voltage operating power supply voltage _V DD semiconductor integrated circuit 1 of the CPU core 10 _ROM is superimposed the _V DD _FPU the internal nonvolatile memory 12 of the However, it is shown that the values significantly decrease at the fourth cycle time T4 and the fifth cycle time T5.

  FIG. 3D also shows a waveform diagram of the fetch interrupt request signal F_IRQ generated by the internal power supply voltage detection circuit 16 and the fetch interrupt controller (Fetch_ICU) 17.

In the fourth cycle time T4, as described above, the voltage level is set slightly higher than the voltage level of the operation lower limit voltage V _DD _limit that makes it impossible to read internal data to the internal data bus of the built-in nonvolatile memory 12. The internal power supply voltage detection circuit 16 detects that the operating power supply voltage V _DD of the CPU core 10 falls below the first threshold value Vth1. The detection result of the internal power supply voltage detection circuit 16 is supplied to the fetch interrupt controller 17, and in response to this first detection result, the fetch interrupt controller 17 generates a high level “H” fetch interrupt request signal F_IRQ to generate a central processing unit. This is supplied to the fetch unit 11A1 of 11A. As a result, the instruction fetch operation by the fetch unit 11A1 of the central processing unit 11A is stopped, and the problem that invalid data in the built-in nonvolatile memory 12 is fetched by the central processing unit 11A as a control program can be solved. At the fifth cycle time T5, the operating power supply voltage V _DD of the CPU core 10 is maintained in a lowered state, so that the fetch interrupt controller 17 continues to generate the high level “H” fetch interrupt request signal F_IRQ in the middle. The supply of the processing unit 11A to the fetch unit 11A1 is continued.

In the sixth cycle time T6, the operating power supply voltage V _DD of the CPU core 10 recovers and starts to rise. As a result, in the internal power supply voltage detection circuit 16, the operating power supply voltage V _DD of the CPU core 10 has risen above the second threshold Vth2 set to a voltage level slightly higher than the voltage level of the first threshold Vth1. Detect that. Therefore, the low level “L” fetch interrupt request signal F_IRQ as the second detection result of the internal power supply voltage detection circuit 16 is supplied to the fetch interrupt controller 17, and the instruction fetch operation by the fetch unit 11A1 of the central processing unit 11A is resumed. Is done. Therefore, the control program that is valid data read from the built-in nonvolatile memory 12 is fetched by the central processing unit 11A.

<< Waveform change of internal bus clock, internal address bus, internal data bus, etc. >>
4 shows the fetch interrupt request signal F_IRQ, the internal bus clock Int_Bus_Clk, the internal address bus Int_Adr_Bus, the internal data bus Int_Dt_Bus, and other memory access signals in the period from the third cycle time T3 to the sixth cycle time T6 shown in FIG. It is a figure which shows the waveform change.

  As shown in FIG. 4, the fetch interrupt request signal F_IRQ is set to the high level “H” during the period from the middle of the fourth cycle time T4 to the beginning of the sixth cycle time T6, as in FIG. .

  As shown in FIG. 4, an internal address Address is supplied from a central processing unit (CPU) 11A to a built-in nonvolatile memory (Flash ROM) 12 in synchronization with an internal bus clock Int_Bus_Clk. This internal address Address is supplied from the central processing unit (CPU) 11A to the built-in nonvolatile memory (Flash ROM) 12 via the internal address bus Int_Adr_Bus.

  At the beginning of each period from the third cycle time T3 to the sixth cycle time T6, the inverted chip enable signal / CE supplied from the central processing unit 11A to the built-in nonvolatile memory 12 is set to the high level, and from the third cycle time T3. In the middle and the latter half of each period of the sixth cycle time T6, the inverted chip enable signal / CE is set to the low level.

  In the entire period from the third cycle time T3 to the sixth cycle time T6, the inverted write enable signal / WE supplied from the central processing unit 11A to the built-in nonvolatile memory 12 is set to the high level.

  At the beginning of each period from the third cycle time T3 to the sixth cycle time T6, the inverted output enable signal / OE supplied from the central processing unit 11A to the built-in nonvolatile memory 12 is set to the high level, and the third cycle time T3. From the middle to the latter half of each period of the sixth cycle time T6, the inverted output enable signal / OE is set to the low level.

  In the second half of the third cycle time T3 when the fetch interrupt request signal F_IRQ is set to the low level “L”, valid data Data is read from the built-in nonvolatile memory 12 and supplied to the internal data bus Int_Dt_Bus.

The second half of the fourth cycle time T4 and the fifth cycle time T5 in which the operating power supply voltage V _DD of the CPU core 10 falls below the first threshold value Vth1 and the fetch interrupt request signal F_IRQ is set to the high level “H”. Then, invalid data Invalid Data is read from the built-in nonvolatile memory 12 and supplied to the internal data bus Int_Dt_Bus.

The operation power supply voltage V _DD of the CPU core 10 recovers and rises to the second threshold value Vth2 or more and the fetch interrupt request signal F_IRQ is set to the low level “L” in the second half of the sixth cycle time T6. The valid data Data is read from the memory 12 and supplied to the internal data bus Int_Dt_Bus.

  Further, as shown in FIG. 4, in the latter half of the fourth cycle time T4 and the fifth cycle time T5 when the fetch interrupt request signal F_IRQ is set to the high level “H”, the central processing unit 11A invalidates the internal address bus Int_Adr_Bus. There is also a possibility of being supplied to the address Invalid Address.

≪Actual pipeline operation including instruction fetch operation≫
FIG. 5 is a diagram for explaining an actual pipeline operation including an instruction fetch operation executed by the CPU core 10 in the semiconductor integrated circuit 1 according to the first embodiment shown in FIG.

  The actual pipeline operation shown in FIG. 5 differs from the ideal pipeline operation shown in FIG. 2 in the following points.

  That is, invalid data of the fourth instruction D is read from the built-in nonvolatile memory 12 in the instruction fetch IF at the fourth cycle time T4 of the actual pipeline operation shown in FIG. On the other hand, at the fourth cycle time T4, the instruction fetch operation of invalid data of the fourth instruction D by the fetch unit 11A1 of the central processing unit 11A is stopped by the high level “H” fetch interrupt request signal F_IRQ. As described above, since the instruction fetch operation of the fourth instruction D at the fourth cycle time T4 is unsuccessful, the pipeline operation is performed in response to the high level “H” fetch interrupt request signal F_IRQ at the fourth cycle time T4. The fourth instruction D is read from the built-in nonvolatile memory 12 by the instruction fetch IF at the fifth cycle time T5. However, the fourth instruction D is invalid data even at the fifth cycle time T5, and the fourth instruction D by the fetch unit 11A1 of the central processing unit 11A by the fetch interrupt request signal F_IRQ at the high level “H” at the fifth cycle time T5. The instruction fetch operation of invalid data of the th instruction D is stopped. As described above, since the instruction fetch operation of the fourth instruction D at the fifth cycle time T5 is unsuccessful, the pipeline operation is performed in response to the high level “H” fetch interrupt request signal F_IRQ at the fifth cycle time T5. The fourth instruction D is read from the built-in nonvolatile memory 12 by the instruction fetch IF at the sixth cycle time T6. The fourth instruction D is valid data at the present sixth cycle time T6, and the fourth instruction D by the fetch unit 11A1 of the central processing unit 11A in response to the fetch interrupt request signal F_IRQ at the low level “L” at the sixth cycle time T6. The instruction fetch operation of valid data of the instruction D is executed.

  Further, in the instruction decode ID at the fifth cycle time T5 and the instruction decode ID at the sixth cycle time T6, the instruction decode result of No Operation (NoP) is high because the instruction of the fourth instruction D is not executed. In response to the “H” fetch interrupt request signal F_IRQ, it is generated by an instruction decoder inside the central processing unit 11A.

  Further, in the instruction execution EX at the sixth cycle time T6 of the actual pipeline operation shown in FIG. 5, the instruction execution of the no operation (NoP) is performed for the instruction non-execution of the fourth instruction D. At the same time, in the instruction fetch IF at the sixth cycle time T6 of the pipeline operation, valid data of the fourth instruction D is read from the built-in nonvolatile memory 12 and fetched by the fetch unit 11A1 of the central processing unit 11A. Is done.

  Since the program counter (PC: Program Counter) in the central processing unit 11A recognizes that the fourth instruction D is in the non-executed state at the timing of the sixth cycle time T6, the program counter In response to the information, the fetch unit 11A1 of the central processing unit 11A executes the refetch operation of the fourth instruction D at the timing of the sixth cycle time T6.

<< Structure of built-in nonvolatile memory including CPU core >>
FIG. 6 is a diagram showing a structure of a built-in nonvolatile memory (Flash ROM) 12 included in the CPU core 10 of the semiconductor integrated circuit 1 according to the first embodiment shown in FIG.

  As shown in FIG. 6, the built-in nonvolatile memory (Flash ROM) 12 includes y + 1 bit lines BL0, BL1, BL2,.

One end of the bit line BL0 is supplied with the operating power supply voltage V _DD _ROM of the built-in nonvolatile memory 2 via the drain / source current path of the P-channel MOS transistor Qp0, and one end of the bit line BL1 is connected to the drain / source of the P-channel MOS transistor Qp1. operating power supply voltage V _DD _ROM the internal nonvolatile memory 2 is supplied via a source current path. One end of the bit line BL2 is supplied with the operating power supply voltage V _DD _ROM of the built-in nonvolatile memory 2 via the drain / source current path of the P-channel MOS transistor Qp2, and one end of the bit line BLy is connected to the drain / source of the P-channel MOS transistor Qpy. operating power supply voltage V _DD _ROM the internal nonvolatile memory 2 is supplied via a source current path.

  Each of y + 1 bit lines BL0, BL1, BL2,... BLy is connected to a plurality of nonvolatile flash memory cells F_MC, and each of the plurality of nonvolatile flash memory cells F_MC is selected to constitute a split gate type memory cell. A transistor QnS and a memory transistor QnM are included. The select transistor QnS and the memory transistor QnM of the nonvolatile flash memory cell F_MC are connected in series between the bit line and the ground potential. The gates of the plurality of selection transistors QnS of the first row of nonvolatile flash memory cells F_MC are connected to the selection gate line SG0 of the first row, and the gates of the plurality of memory transistors QnM of the first row of nonvolatile flash memory cells F_MC are It is connected to the memory gate line MG0 in the first row. The gates of the plurality of selection transistors QnS of the second row of nonvolatile flash memory cells F_MC are connected to the selection gate line SG1 of the second row of the plurality of memory transistors QnM of the second row of nonvolatile flash memory cells F_MC. The gate is connected to the memory gate line MG1 in the second row. Similarly, the gates of the plurality of selection transistors QnS of the third row of nonvolatile flash memory cells F_MC are connected to the selection gate line SG2 of the third row, and the plurality of memory transistors QnM of the third row of nonvolatile flash memory cells F_MC of the third row. The gate is connected to the memory gate line MG2 in the third row. The gates of the plurality of select transistors QnS of the X-th row non-volatile flash memory cell F_MC are connected to the X-th row select gate line SGX, and the X-th row non-volatile flash memory cell F_MC of the plurality of memory transistors QnM The gate is connected to the Xth memory gate line MGX.

  The other end of the bit line BL0 is connected to the input terminal of the sense amplifier SA0, the other end of the bit line BL1 is connected to the input terminal of the sense amplifier SA1, and the other end of the bit line BL2 is connected to the input terminal of the sense amplifier SA2. Further, the other end of the bit line BLy is connected to the input terminal of the sense amplifier SAy. A plurality of output terminals of the sense amplifiers SA0, SA1, SA2,... SAy are connected to a plurality of input terminals of the column selection gate circuit YG, and 32 output terminals of the column selection gate circuit YG are 32 data output buffer circuits OB0, It is connected to 32 input terminals OB1, OB2,. 32 output terminals of the 32 data output buffer circuits OB0, OB1, OB2,... OB31 are connected to 32 data output terminals O0, O1, O2,... O31, and 32 data output terminals O0, O1, O2,. O31 is connected to a central processing unit (CPU) 11A of the CPU core 10 via an internal data bus Int_Dt_Bus.

<< Structure of split-gate nonvolatile flash memory cell >>
FIG. 7 shows a structure of a nonvolatile flash memory cell F_MC constituting a split gate type memory cell of the built-in nonvolatile memory 12 included in the CPU core 10 of the semiconductor integrated circuit 1 of the first embodiment shown in FIG. FIG.

  As shown in FIG. 7A, the nonvolatile flash memory cell F_MC includes a select transistor QnS and a memory transistor QnM connected in series between the bit line BL0 and the ground potential.

  As shown in FIG. 7B, in order to form the non-volatile flash memory cell F_MC, N is formed on the main surface of the P-type silicon substrate Sub of the semiconductor integrated circuit 1 of the first embodiment shown in FIG. A type well region N-Well and a P type well region P-Well are formed in order.

A pair of N-type high impurity concentration regions N ⁺ are formed inside the P-type well region P-Well, and the left N-type high impurity concentration region N ⁺ is connected to the bit line BL0 so as to function as the drain of the selection transistor QnS. The right N-type high impurity concentration region N ⁺ is connected to the ground potential GND so as to function as the source of the memory transistor QnM.

Inside the P-type well region P-Well, a pair of N-type low impurity concentration regions N ⁻ are formed between a pair of N-type high impurity concentration regions N ⁺ , and the left N-type low impurity concentration region N ⁻ The right N-type low impurity concentration region N ⁻ functions as a low impurity concentration source region of the memory transistor QnM.

A pair of N-type low impurity concentration regions N ^- gate oxide film Gate_Oxide on the main surface of the P-type well region P-Well between is formed as a gate insulating film, the upper portion of the gate oxide film Gate_Oxide gates of the select transistors QnS A polycrystalline silicon layer is formed as the electrode QnS_G.

  Three-layer stacked gate insulating film of an oxide film, a nitride film, and an oxide film as a charge storage layer on the side surface of the gate electrode QnS_G of the selection transistor QnS and the P-well region P-Well main surface in the removed portion of the gate oxide film Gate_Oxide (ONO) is formed, and a polycrystalline silicon layer as the gate electrode QnM_G of the memory transistor QnM is formed on the three-layer stacked gate insulating film (ONO).

  The gate electrode QnS_G of the selection transistor QnS is connected to the selection gate line SG0, and the gate electrode QnM_G of the memory transistor QnM is connected to the memory gate line MG0.

<< Electrical Characteristics of Split-Gate Nonvolatile Flash Memory Cell >>
8 shows the electrical characteristics of the nonvolatile flash memory cell F_MC constituting the split gate type memory cell of the built-in nonvolatile memory 12 included in the CPU core 10 of the semiconductor integrated circuit 1 of the first embodiment shown in FIG. FIG.

  As shown in FIG. 8A, the electrical characteristics of the memory operation of the nonvolatile flash memory cell F_MC including the select transistor QnS and the memory transistor QnM connected in series between the bit line BL0 and the ground potential are shown in FIG. B).

  By applying a high-level word selection signal to the selection gate line SG0 shown in FIG. 8A, the selection transistor QnS is controlled to be in an on state. On the other hand, the memory transistor QnM can be programmed (written) to either the high threshold voltage VthH or the low threshold voltage VthL. That is, the memory transistor QnM is programmed to the high threshold voltage VthH by injecting negatively charged electrons into the electron trap level present in the nitride film of the three-layer stacked gate insulating film (ONO) of the memory transistor QnM. . The memory transistor QnM is programmed to the low threshold voltage VthL by injecting positive holes into the hole trap level present in the nitride film of the three-layer stacked gate insulating film (ONO) of the memory transistor QnM. . That is, by applying a positive high voltage to the memory gate line MG0 during the program (write) operation of the nonvolatile flash memory cell F_MC, it exists in the nitride film of the three-layer stacked gate insulating film (ONO) of the memory transistor QnM. Negative charge electrons are injected into the electron trap level, and the memory transistor QnM is programmed to the high threshold voltage VthH. In addition, a large negative voltage is applied to the memory gate line MG0 during the program (write) operation of the nonvolatile flash memory cell F_MC, so that it exists in the nitride film of the three-layer stacked gate insulating film (ONO) of the memory transistor QnM. The positive hole is injected into the hole trap level, and the memory transistor QnM is programmed to the low threshold voltage VthL. That is, since the high threshold voltage VthH is a positive threshold, the memory transistor QnM programmed to the high threshold voltage VthH enters the enhancement mode. Also. Since the low threshold voltage VthL is a negative threshold, the memory transistor QnM programmed to the low threshold voltage VthL is in the depletion mode.

  In the read operation of the nonvolatile flash memory cell F_MC, the selection transistor QnS is controlled to be turned on by applying a high-level word selection signal to the selection gate line SG0, and as shown in FIG. A bias voltage Vbias having a voltage level between the threshold voltage VthH and the low threshold voltage VthL is applied to the memory gate line MG0. When the memory transistor QnM of the non-volatile flash memory cell F_MC is programmed to the high threshold voltage VthH, the memory transistor QnM is turned off in response to the bias voltage Vbias, and between the bit line BL0 and the ground potential. The read current is zero for the select transistor QnS and the memory transistor QnM connected in series. On the other hand, when the memory transistor QnM of the nonvolatile flash memory cell F_MC is programmed to the low threshold voltage VthL, the memory transistor QnM is relatively large in response to the bias voltage Vbias as shown in FIG. A read current Iread flows. Therefore, when the memory transistor QnM of the nonvolatile flash memory cell F_MC is programmed to the low threshold voltage VthL, the data is read also to the selection transistor QnS and the memory transistor QnM connected in series between the bit line BL0 and the ground potential. A current Iread flows.

  As a result, the built-in nonvolatile memory 12 included in the CPU core 10 of the semiconductor integrated circuit 1 of the first embodiment is replaced by the nonvolatile flash memory cell F_MC constituting the split gate type memory cell shown in FIGS. By configuring, it becomes possible to increase the read current of the memory cell, and to realize the high speed of the read operation of the built-in nonvolatile memory 12.

<< Single transistor nonvolatile flash memory cell as a comparative reference >>
FIG. 9 is a diagram showing a structure of a non-volatile flash memory cell F_MC constituting a single transistor type memory cell as a comparative reference example of the present invention.

  As shown in FIG. 9A, the nonvolatile flash memory cell F_MC includes a single memory transistor Qn connected between the bit line BL0 and the ground potential. In the single memory transistor Qn, a floating gate FG as a charge storage layer is formed on the surface of the channel between the source and drain via a gate insulating film, and is controlled on the surface of the floating gate FG via an interlayer insulating film. A gate CG is formed.

  When a positive voltage is applied to the control gate CG, negative charge electrons are injected from the channel into the charge storage layer, and the MOS transistor has a high threshold voltage VthH as shown in FIG. Is called. On the other hand, when a negative voltage is applied to the control gate CG, negatively charged electrons are emitted from the charge storage layer, and the MOS transistor has a low threshold voltage VthL as shown in FIG. When a single transistor is employed in the NOR flash memory, both the low threshold voltage VthL and the high threshold voltage VthH are set to the enhancement mode. For example, when the low threshold voltage VthL is set to the depletion mode, a leak current always flows between the bit line and the ground potential in the NOR flash memory.

  In the read operation of the single transistor type nonvolatile flash memory cell F_MC, the voltage level between the high threshold voltage VthH and the low threshold voltage VthL is applied to the control gate CG as shown in FIG. The bias voltage Vbias having is applied to the memory gate line CG0. When the memory transistor Qn of the non-volatile flash memory cell F_MC is programmed to the high threshold voltage VthH, the memory transistor Qn is turned off in response to the bias voltage Vbias, and between the bit line BL0 and the ground potential. The read current is zero for the select transistor QnS and the memory transistor Qn connected in series. On the other hand, when the memory transistor Qn of the nonvolatile flash memory cell F_MC is programmed to the low threshold voltage VthL, the memory transistor QnM is relatively in response to the bias voltage Vbias as shown in FIG. A small read current Iread flows. Therefore, when the memory transistor Qn of the single transistor type nonvolatile flash memory cell F_MC is programmed to the low threshold voltage VthL, the memory transistor Qn connected between the bit line BL0 and the ground potential is relatively small. A read current Iread flows.

  As a result, the built-in nonvolatile memory 12 included in the CPU core 10 of the semiconductor integrated circuit 1 of the first embodiment is configured by the nonvolatile flash memory cell F_MC constituting the single transistor type memory cell shown in FIG. In this case, the read current of the memory cell becomes small, and it becomes impossible to realize the high speed read operation of the built-in nonvolatile memory 12.

<Configuration of single-chip microcomputer>
FIG. 10 is a diagram showing a configuration of the semiconductor integrated circuit 1 configured as a single-chip microcomputer including the CPU core 10 according to the first embodiment.

  The processing unit 11 of the CPU core 10 according to the first embodiment shown in FIG. 10 includes a central processing unit (CPU), a floating point arithmetic unit (FPU), and a digital multiplier (MULT). The CPU core 10 according to the first embodiment shown in FIG. 10 includes a built-in nonvolatile memory 12, a built-in volatile memory 18, an internal power supply voltage detection circuit 16, and a fetch interrupt controller 17. Further, the CPU core 10 includes an internal address bus Int_Adr_Bus and an internal data bus Int_Dt_Bus. The operation of the CPU core 10 according to the first embodiment shown in FIG. 10 is the same as the operation of the CPU core 10 according to the first embodiment shown in FIG. The built-in volatile memory 18 is constituted by an on-chip RAM (random access memory).

《Peripheral core and analog core》
A peripheral core 20 and an analog core 30 are connected to the internal address bus Int_Adr_Bus and the internal data bus Int_Dt_Bus of the CPU core 10.

  As shown in FIG. 10, the peripheral core 20 includes a direct memory access controller (DMAC) 21, a bus state controller (BSC) 22, an interrupt controller (ICU) 23, a timer (Timer) 24, and a controller area network (CAN) 25. And an external port (Ext_Port) 26 and a serial communication interface (SCI) 27.

  A direct memory access controller (DMAC) 21 performs direct data transfer between the built-in volatile memory 18 and an external memory or input / output device (I / O) of the semiconductor integrated circuit 1 in accordance with an instruction from the central processing unit (CPU). By doing so, the central processing unit (CPU) can perform other tasks during this data transfer.

  A bus state controller (BSC) 22 can access an external memory such as an SRAM or a ROM to which the semiconductor integrated circuit 1 is connected via a peripheral address bus Ph_Adr_Bus, a peripheral data bus Ph_Da_Bus, and an external port (Exp_Port). Is.

  The interrupt controller (ICU) 23 supplies an interrupt request IRQ from an external input / output device connected to the semiconductor integrated circuit 1 and other peripheral devices to the central processing unit (CPU) 11A. An external interrupt request IRQ is supplied to the interrupt controller (ICU) 23 via the external port (Exp_Port) and the peripheral data bus Ph_Da_Bus, and in response to the interrupt request IRQ from the interrupt controller (ICU) 23, the central processing unit ( The CPU 11A executes interrupt processing after interrupting normal processing being executed before that time. When the execution of the interrupt process is completed, the central processing unit (CPU) 11A resumes the interrupted normal process.

  The timer (Timer) 24 is a hardware time measuring device such as a watch dog timer. For example, when the timer (Timer) 24 executes time measurement for timeout processing and the processing of the central processing unit (CPU) 11A is in a hang-up state, exception processing such as system reset is executed. It is.

  The controller area network (CAN) 25 is used for transferring information such as speed, engine speed, brake status, and failure diagnosis information in automobiles, and is designed and interconnected to improve noise resistance. It is used for data transfer between. In addition, it is also widely used for transferring control information of equipment, and can be used in the field of robots such as transport machines, factories, and machine tools.

  The external port (Ext_Port) 26 is used to access an external device of the semiconductor integrated circuit 1 as described above.

  The serial communication interface (SCI) 27 enables serial data communication with an external device of the semiconductor integrated circuit 1.

  An analog / digital converter (ADC) 31 included in the analog core 30 converts an analog input signal supplied from the outside of the semiconductor integrated circuit 1 into a digital signal, and the converted digital signal is directly connected to the peripheral data bus Ph_Da_Bus. The data is supplied to the CPU core 10 via the memory access controller 21 or the bus state controller 22.

  A digital / analog converter (DAC) 32 included in the analog core 30 converts a digital signal generated from the CPU core 10 into an analog signal, and supplies the converted analog signal to the outside of the semiconductor integrated circuit 1.

  As mentioned above, the invention made by the present inventor has been specifically described based on various embodiments. However, the present invention is not limited thereto, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, the built-in nonvolatile memory (Flash ROM) 12 of the semiconductor integrated circuit 1 according to the first embodiment shown in FIGS. 1 and 10 only stores a control program for the central processing unit (CPU) 11A. Instead, it is also possible to store the calculation results by the central processing unit 11A, the floating point calculation unit 11B, and the digital multiplier (MULT). For example, information on the travel distance of an automobile, engine control information of an automobile, and the like must be stored and held in a nonvolatile memory even after the semiconductor integrated circuit 1 is powered off. The storage in the built-in nonvolatile memory (Flash ROM) 12 is extremely useful.

  Further, the semiconductor integrated circuit 1 including the central processing unit 11A, the built-in nonvolatile memory 12, the internal power supply voltage detection circuit 16, and the fetch interrupt controller 17 is only applied to a single chip microcomputer mounted in an automobile, a hybrid vehicle or the like. Instead, it can be applied to microcontrollers and system LSIs for home appliances and industrial applications.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor integrated circuit 10 ... CPU core 11A ... Central processing unit (CPU)
11B Floating point unit (FPU)
12 ... Built-in non-volatile memory (Flash ROM)
13A, B, C ... Internal power supply circuit 14A, B ... Internal power switch 15 ... Reference voltage generation circuit 16 ... Internal power supply voltage detection circuit 17 ... Fetch interrupt controller (Fetch_ICU)
GND: ground wiring Int_Adr_Bus ... internal address bus Int_Dt_Bus ... internal data bus 18 ... built-in volatile memory 20 ... peripheral core 21 ... direct memory access controller (DMAC)
22 ... Bus state controller (BSC)
23 ... Interrupt controller (ICU)
24 ... Timer
25 ... Controller Area Network (CAN)
26: External port (Ext_Port)
27 ... Serial Communication Interface (SCI)
30 ... Analog core 31 ... Analog to digital converter (ADC)
32 ... Digital-to-analog converter (DAC)

Claims (20)

The semiconductor integrated circuit includes a central processing unit, a built-in nonvolatile memory, an internal power supply circuit, and an internal power supply voltage detection circuit,
The built-in nonvolatile memory can store a program executed by the central processing unit,
The internal power supply circuit generates an internal operating voltage and can supply the internal operating voltage to the built-in nonvolatile memory;
The internal power supply voltage detection circuit can detect that the internal operating voltage is lowered to a level at which the read operation of the built-in nonvolatile memory becomes dangerous. In response to the detection result, the central processing unit performs the built-in nonvolatile memory. The read operation of the memory is stopped,
The internal power supply voltage detection circuit can detect that the internal operation voltage rises to a level at which the read operation of the built-in nonvolatile memory becomes safe after the internal operation voltage is lowered, and in response to the detection result, A semiconductor integrated circuit in which the reading operation of the built-in nonvolatile memory by the central processing unit is resumed. In claim 1,
The internal operating voltage drops below a first threshold value set at a voltage level higher than the voltage level of the operating lower limit voltage of the internal operating voltage at which the reading operation of the built-in nonvolatile memory becomes impossible. The internal power supply voltage detection circuit can be detected,
The internal operating voltage rises above a second threshold set to a voltage level higher than the voltage level of the first threshold after the internal operating voltage drops below the first threshold. The internal power supply voltage detection circuit can be detected,
The internal power supply voltage detection circuit detects that the internal operating voltage drops below the first threshold, and the internal power supply voltage detection circuit generates a first detection result,
The reading of the built-in nonvolatile memory by the central processing unit in response to the first detection result generated from the internal power supply voltage detection circuit when the internal operating voltage drops below the first threshold value Operation is stopped,
The internal power supply voltage detection circuit detects that the internal operating voltage rises above the second threshold, and the internal power supply voltage detection circuit generates a second detection result,
The reading of the built-in nonvolatile memory by the central processing unit in response to the second detection result generated from the internal power supply voltage detection circuit when the internal operating voltage rises above the second threshold value A semiconductor integrated circuit whose operation is resumed. In claim 2,
The central processing unit includes an instruction fetch unit that executes an instruction fetch operation of the program stored in the built-in nonvolatile memory by executing the read operation of the built-in nonvolatile memory,
In response to the first detection result generated from the internal power supply voltage detection circuit when the internal operating voltage drops below the first threshold, the instruction fetch operation by the instruction fetch unit is stopped,
In response to the second detection result generated from the internal power supply voltage detection circuit when the internal operation voltage rises above the second threshold value, the instruction fetch operation by the instruction fetch unit is resumed. Semiconductor integrated circuit. In claim 3,
The semiconductor integrated circuit further comprises a fetch interrupt controller,
The fetch interrupt controller is supplied with the first detection result generated from the internal power supply voltage detection circuit and the second detection result generated from the internal power supply voltage detection circuit,
In response to the first detection result generated from the internal power supply voltage detection circuit when the internal operating voltage drops below the first threshold value, the fetch interrupt controller is configured to execute the instruction fetch by the instruction fetch unit. Stop working,
In response to the second detection result generated from the internal power supply voltage detection circuit when the internal operating voltage rises above the second threshold, the fetch interrupt controller receives the instruction fetch by the central processing unit. A semiconductor integrated circuit which resumes the instruction fetch operation by a unit. In claim 4,
The semiconductor integrated circuit executes a pipeline operation including at least an instruction fetch stage, an instruction decode stage, an instruction execution stage, and a memory access stage,
The instruction fetch stage is executed by the instruction fetch operation of the instruction fetch unit;
The instruction decode stage performs decoding of an instruction fetched by the instruction fetch operation of the instruction fetch stage,
The instruction execution stage executes the instruction decoded in the instruction decode stage,
The memory access stage is a semiconductor integrated circuit for executing execution of storing the execution result of the instruction executed in the instruction execution stage in a memory. In claim 5,
With respect to an instruction to be fetched by the instruction fetch operation of the instruction fetch unit during a period when the internal operating voltage has dropped below the first threshold, during the instruction execution stage of the instruction to be fetched A semiconductor integrated circuit in which no operation is performed. In claim 4,
The semiconductor integrated circuit further comprises other functional blocks,
The internal power supply circuit can further supply the internal operating voltage to the central processing unit and the other functional blocks,
The operation voltage of the central processing unit and the operation voltage of the other functional block are superimposed on the internal operation voltage supplied to the built-in nonvolatile memory, and the voltage level of the superimposed internal operation voltage is set to the internal power supply. The voltage detection circuit can be detected,
The internal power supply voltage detection circuit detects that the superimposed internal operating voltage drops below the first threshold, and the internal power supply voltage detection circuit generates the first detection result,
A semiconductor integrated circuit in which the internal power supply voltage detection circuit detects that the superimposed internal operating voltage rises above the second threshold, and the internal power supply voltage detection circuit generates a second detection result. In claim 7,
The other functional block is a semiconductor integrated circuit which is a floating point arithmetic unit. In claim 4,
The built-in nonvolatile memory is a semiconductor integrated circuit which is a NOR type nonvolatile memory in which a plurality of nonvolatile memory cells are connected in parallel to each bit line of a plurality of bit lines. In claim 9,
Each of the plurality of nonvolatile memory cells is a semiconductor integrated circuit which is a split gate nonvolatile memory cell including a selection transistor and a memory transistor connected in series between each bit line and a ground potential. In claim 10,
The memory transistor is a semiconductor integrated circuit having a MONOS type structure using a three-layer gate insulating film of a first oxide film, a nitride film, and a second oxide film. In claim 11,
The built-in nonvolatile memory is a semiconductor integrated circuit capable of storing an instruction execution result by the central processing unit. In claim 11,
The CPU core including the central processing unit, the built-in nonvolatile memory, the internal power supply circuit, the internal power supply voltage detection circuit, and the fetch interrupt controller includes at least a direct memory access controller, a bus state controller, and an interrupt controller. Peripheral core is connected,
A semiconductor integrated circuit in which an analog core including at least an analog / digital converter and a digital / analog converter is further connected to the CPU core. In claim 13,
The semiconductor integrated circuit comprising the CPU core, the peripheral core, and the analog core is a semiconductor integrated circuit that is a single chip microcomputer. A method of operating a semiconductor integrated circuit comprising a central processing unit, a built-in nonvolatile memory, an internal power supply circuit, and an internal power supply voltage detection circuit,
The built-in nonvolatile memory can store a program executed by the central processing unit,
The internal power supply circuit generates an internal operating voltage and can supply the internal operating voltage to the built-in nonvolatile memory;
The internal power supply voltage detection circuit can detect that the internal operating voltage is lowered to a level at which the read operation of the built-in nonvolatile memory becomes dangerous. In response to the detection result, the central processing unit performs the built-in nonvolatile memory. The read operation of the memory is stopped,
The internal power supply voltage detection circuit can detect that the internal operation voltage rises to a level at which the read operation of the built-in nonvolatile memory becomes safe after the internal operation voltage is lowered, and in response to the detection result, A method of operating a semiconductor integrated circuit in which the read operation of the built-in nonvolatile memory by a central processing unit is resumed. In claim 15,
The internal operating voltage drops below a first threshold value set at a voltage level higher than the voltage level of the operating lower limit voltage of the internal operating voltage at which the reading operation of the built-in nonvolatile memory becomes impossible. The internal power supply voltage detection circuit can be detected,
The internal operating voltage rises above a second threshold set to a voltage level higher than the voltage level of the first threshold after the internal operating voltage drops below the first threshold. The internal power supply voltage detection circuit can be detected,
The internal power supply voltage detection circuit detects that the internal operating voltage drops below the first threshold, and the internal power supply voltage detection circuit generates a first detection result,
The reading of the built-in nonvolatile memory by the central processing unit in response to the first detection result generated from the internal power supply voltage detection circuit when the internal operating voltage drops below the first threshold value Operation is stopped,
The internal power supply voltage detection circuit detects that the internal operating voltage rises above the second threshold, and the internal power supply voltage detection circuit generates a second detection result,
The reading of the built-in nonvolatile memory by the central processing unit in response to the second detection result generated from the internal power supply voltage detection circuit when the internal operating voltage rises above the second threshold value A method of operating a semiconductor integrated circuit whose operation is resumed. In claim 16,
The central processing unit includes an instruction fetch unit that executes an instruction fetch operation of the program stored in the built-in nonvolatile memory by executing the read operation of the built-in nonvolatile memory,
In response to the first detection result generated from the internal power supply voltage detection circuit when the internal operating voltage drops below the first threshold, the instruction fetch operation by the instruction fetch unit is stopped,
In response to the second detection result generated from the internal power supply voltage detection circuit when the internal operation voltage rises above the second threshold value, the instruction fetch operation by the instruction fetch unit is resumed. A method of operating a semiconductor integrated circuit. In claim 17,
The semiconductor integrated circuit further comprises a fetch interrupt controller,
The fetch interrupt controller is supplied with the first detection result generated from the internal power supply voltage detection circuit and the second detection result generated from the internal power supply voltage detection circuit,
In response to the first detection result generated from the internal power supply voltage detection circuit when the internal operating voltage drops below the first threshold value, the fetch interrupt controller is configured to execute the instruction fetch by the instruction fetch unit. Stop working,
In response to the second detection result generated from the internal power supply voltage detection circuit when the internal operating voltage rises above the second threshold, the fetch interrupt controller receives the instruction fetch by the central processing unit. A method for operating a semiconductor integrated circuit, wherein the instruction fetch operation by a unit is resumed. In claim 18,
The semiconductor integrated circuit executes a pipeline operation including at least an instruction fetch stage, an instruction decode stage, an instruction execution stage, and a memory access stage,
The instruction fetch stage is executed by the instruction fetch operation of the instruction fetch unit;
The instruction decode stage performs decoding of an instruction fetched by the instruction fetch operation of the instruction fetch stage,
The instruction execution stage executes the instruction decoded in the instruction decode stage,
The memory access stage is a method of operating a semiconductor integrated circuit, wherein the execution result of the instruction executed in the instruction execution stage is stored in a memory. In claim 19,
With respect to an instruction to be fetched by the instruction fetch operation of the instruction fetch unit during a period when the internal operating voltage has dropped below the first threshold, during the instruction execution stage of the instruction to be fetched A method of operating a semiconductor integrated circuit in which no operation is performed.

Images