JP2014120614A - Method of manufacturing silicon carbide semiconductor device, and deposition device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor device having stable characteristics.SOLUTION: By supplying a first addition gas for giving a first conductivity type into a deposition chamber 30 via a first path 21 while heating a substrate and supplying a material gas into the deposition chamber 30, a first silicon carbide layer having the first conductivity type is formed on the substrate 70. By supplying a second addition gas for giving a second conductivity type into the deposition chamber 30 via a second path 22 independent from the first path 21 while supplying the material gas into the deposition chamber, a second silicon carbide layer having the second conductivity type is formed on the substrate 70. After forming the first and second silicon carbide layers, a purge gas for purging the first addition gas is introduced from a third path 23 connected to the first path 21 into the first path 21.

Description

  The present invention relates to a method for manufacturing a silicon carbide semiconductor device and a film forming apparatus.

JP 2008-159947 A discloses a film forming apparatus for forming a silicon carbide (SiC) layer. This film forming apparatus includes a processing container and one gas line connected to the processing container. Each gas supply source of SiH ₄ , C ₃ H ₈ , H ₂ , TMA (trimethylaluminum) and N ₂ is connected to one gas line.

JP 2008-159947 A

According to the film forming apparatus disclosed in the above publication, supply of N ₂ for imparting n-type to SiC and TMA for imparting p-type to a processing container is performed from one gas line. . When TMA flows through one gas line, the cleanliness of the gas line is likely to decrease. One reason for this is that TMA is a liquid at room temperature and therefore easily adheres to the inner surface of the gas line. When a p-type layer having a high impurity concentration is formed, it is necessary to supply more TMA at the time of film formation, so that the cleanliness of the gas line is particularly likely to decrease. Due to the decrease in cleanliness of one gas line, the characteristics of the formed silicon carbide layer vary. In particular, when an n-type layer having a low impurity concentration, such as a drift layer, is formed, if TMA that contributes to the p-type is mixed, the effective impurity concentration greatly varies. As a result, the variation in characteristics of the silicon carbide semiconductor device also increases.

  The present invention has been made to solve such problems, and an object of the present invention is to manufacture a silicon carbide semiconductor device having stable characteristics.

  The method for manufacturing a silicon carbide semiconductor device of the present invention includes the following steps. A substrate is placed in a deposition chamber for chemical vapor deposition. The heating of the substrate is started. While heating the substrate and supplying the raw material gas for generating silicon carbide into the film formation chamber, the first additive gas for imparting the first conductivity type is passed through the first path. By supplying the film into the deposition chamber, a first silicon carbide layer having the first conductivity type is formed on the substrate. While heating the substrate and supplying the source gas for generating silicon carbide into the film formation chamber, the second additive gas for imparting the second conductivity type is made independent of the first path. The second silicon carbide layer having the second conductivity type is formed on the substrate by supplying the film into the film formation chamber via the two paths. After forming the first and second silicon carbide layers, a purge gas for purging the first additive gas is introduced from the third path connected to the first path into the first path.

  According to the manufacturing method, the second path is independent from the first path for transporting the first additive gas for imparting the first conductivity type. Therefore, when the second silicon carbide layer having the second conductivity type is formed using the second path, the influence of the cleanliness of the first path on the impurity concentration can be suppressed. Further, by maintaining the cleanliness of the first path by purging the first path, the impurity concentration of the silicon carbide layer is stabilized even when the silicon carbide semiconductor device is repeatedly manufactured. Therefore, a silicon carbide semiconductor device having stable characteristics can be manufactured.

  Preferably, the source gas is supplied from the second path into the film formation chamber. As a result, the gas supply path can be simplified.

  Preferably, the step of introducing the purge gas includes a step of cooling the substrate with the purge gas after stopping the heating of the substrate. Thereby, the process of purging and the process of lowering the temperature of the substrate can be performed simultaneously. Therefore, the manufacturing efficiency of the silicon carbide semiconductor device can be increased.

  Preferably, the first additive gas includes trimethylaluminum. In this case, the influence of the decrease in the cleanliness of the first path due to trimethylaluminum, which is particularly problematic, is suppressed for the reason described above.

  Preferably, the purge gas contains at least one of hydrogen gas and rare gas. Thereby, purging can be performed with a gas having little influence on the film formation.

  The first path may have an end portion connected to the supply source of the first additive gas and an intermediate portion into which the purge gas is introduced. Preferably, the distance between the end portion and the intermediate portion in the first path is less than 100 mm. As a result, the length of the portion of the first path that is difficult to be purged can be reduced to less than 100 mm.

  Preferably, when the second silicon carbide layer is formed, the first path is blocked between the intermediate portion and the growth chamber. Thereby, the influence of the first path on the formation of the second silicon carbide layer can be further suppressed.

  The film forming apparatus of the present invention is for forming a silicon carbide layer on a substrate. The film forming apparatus includes a film forming chamber, a support portion, a heater, a first path, a second path, and a third path. The film formation chamber can be supplied with a source gas for generating silicon carbide by a chemical vapor deposition method. The support portion is for supporting the substrate in the film forming chamber. The heater is for heating the substrate supported by the support portion. The first path is for supplying a first additive gas for imparting a first conductivity type to silicon carbide into the film formation chamber. The second path is for supplying a second additive gas for imparting the second conductivity type to silicon carbide into the film formation chamber, and is independent of the first path. The third path is connected to the first path and is for introducing a purge gas for purging the first additive gas into the first path.

  According to the film forming apparatus, the second path is independent of the first path. Therefore, when the second silicon carbide layer is formed using the second path, the influence of the cleanliness of the first path can be suppressed. Further, the cleanliness of the first path is maintained by purging the first path, so that the first and second silicon carbide layers can be formed even when the formation of the first and second silicon carbide layers is repeated. Characteristics are stabilized. Therefore, a silicon carbide semiconductor device having stable characteristics can be manufactured.

  Preferably, the film forming apparatus is configured such that the source gas can be supplied into the film forming chamber from the second path. As a result, the gas supply path can be simplified.

  As described above, according to the present invention, a silicon carbide semiconductor device having stable characteristics can be manufactured.

It is a schematic diagram of the film-forming apparatus in one embodiment of this invention. It is a schematic diagram of the film-forming apparatus of a comparative example. 1 is a partial cross sectional view schematically showing a configuration of a silicon carbide semiconductor device in one embodiment of the present invention. FIG. 4 is a partial perspective view schematically showing a shape of a silicon carbide substrate included in the silicon carbide semiconductor device of FIG. 3. FIG. 4 is a partial cross sectional view schematically showing a first step of the method for manufacturing the silicon carbide semiconductor device of FIG. 3. FIG. 4 is a partial cross sectional view schematically showing a second step of the method for manufacturing the silicon carbide semiconductor device of FIG. 3. FIG. 4 is a partial cross sectional view schematically showing a third step of the method for manufacturing the silicon carbide semiconductor device of FIG. 3. FIG. 4 is a partial cross sectional view schematically showing a fourth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 3. FIG. 10 is a partial cross sectional view schematically showing a fifth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 3. FIG. 12 is a partial cross sectional view schematically showing a sixth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 3. FIG. 12 is a partial cross sectional view schematically showing a seventh step of the method for manufacturing the silicon carbide semiconductor device of FIG. 3. FIG. 12 is a partial cross sectional view schematically showing an eighth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 3. FIG. 12 is a partial cross sectional view schematically showing a ninth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 3.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated. In the crystallographic description in this specification, individual planes are indicated by (), and aggregate planes are indicated by {}. In addition, a negative crystallographic index is usually expressed by adding a “-” (bar) above a number, but in this specification a negative sign is added before the number. Yes.

(Deposition system)
As shown in FIG. 1, a CVD (Chemical Vapor Deposition) apparatus 500 (film forming apparatus) is used to form an epitaxial layer 80 (silicon carbide layer) on a single crystal substrate 70 (substrate). Is. The CVD apparatus 500 includes a TMA supply source 11, an N ₂ supply source 12, a purge gas supply source 13, a C ₃ H ₈ supply source 14, a SiH ₄ supply source 15, an H ₂ supply source 16, and a TMA line 21. (First path), main line 22 (second path), purge line 23 (third path), raw material line 24, exhaust line 29, growth chamber 30, and stage 31 (support section) ), A heater 32, a pump 33, and a valve 34.

  The growth chamber 30 can be supplied with a source gas for generating SiC by a CVD method. The stage 31 is for supporting the single crystal substrate 70 in the growth chamber 30. The heater 32 is for heating the single crystal substrate 70 supported by the stage 31.

  The TMA line 21 is for supplying a TMA gas (first additive gas) for imparting p-type (first conductivity type) to SiC into the growth chamber 30. A TMA supply source 11 is connected to an end PE on the upstream side of the TMA line 21. The TMA supply source 11 is, for example, a cylinder filled with a mixed gas of TMA gas and hydrogen gas. A growth chamber 30 is connected to the downstream end PS of the TMA line 21.

The main line 22 is for supplying N ₂ gas (second additive gas) for imparting n-type (second conductivity type different from the first conductivity type) to SiC into the growth chamber 30. is there. An N ₂ supply source 12 is connected to the upstream side of the main line 22. The main line 22 is independent from the TMA line 21.

  The purge line 23 is for introducing a purge gas for purging the TMA gas into the TMA line 21. A purge gas supply source 13 is connected to the upstream side of the purge line 23. The purge gas is preferably hydrogen gas or a rare gas. Argon is preferable as the rare gas. The purge line 23 is connected to the TMA line 21 at an intermediate portion PM between the end portions PE and PS of the TMA line 21. The distance LH between the end portion PE and the intermediate portion PM in the TMA line 21 is preferably less than 100 mm.

The raw material line 24 is for transporting SiC raw material gas. A C ₃ H ₈ supply source 14, a SiH ₄ supply source 15, and an H ₂ supply source 16, which are SiC source gas supply sources, are arranged on the upstream side of the raw material line 24. The raw material line 24 is connected to the intermediate portion PB of the main line 22. Thus, the CVD apparatus 500 is configured such that the source gas can be supplied from the main line 22 into the growth chamber 30.

(Configuration of silicon carbide semiconductor device)
As shown in FIGS. 3 and 4, MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 200 (silicon carbide semiconductor device) includes a single crystal substrate 70, an epitaxial layer 80, a gate oxide film 91 (gate insulating film), A gate electrode 92, an interlayer insulating film 93, a source electrode 94, a source wiring layer 95, and a drain electrode 98 are included. Single crystal substrate 70 is made of n-type silicon carbide, and preferably has polytype 4H. Epitaxial layer 80 is provided on single crystal substrate 70 and constitutes main surface MS. Epitaxial layer 80 includes an n drift layer 81, a p base layer 82, an n source layer 83, and a p contact region 84.

N drift layer 81 is provided on single crystal substrate 70. N drift layer 81 has n type. The impurity concentration of n drift layer 81 is preferably lower than the impurity concentrations of single crystal substrate 70 and n source layer 83. The donor concentration of n drift layer 81 is preferably not less than 1 × 10 ¹⁵ cm ^{−3 and not} more than 5 × 10 ¹⁶ cm ⁻³ , for example, 8 × 10 ¹⁵ cm ⁻³ . The p base layer 82 has p type. The p base layer 82 is provided on the n drift layer 81. The impurity concentration of the p base layer 82 is, for example, 1 × 10 ¹⁸ cm ⁻³ . N source layer 83 has n type. N source layer 83 is provided on p base layer 82 so as to be separated from n drift layer 81 by p base layer 82. The p contact region 84 has p type. The p contact region 84 is connected to the p base layer 82.

  A trench TR is provided in the main surface MS of the epitaxial layer 80. Trench TR has side wall surface SW and bottom surface BT. Sidewall surface SW passes through n source layer 83 and p base layer 82 and reaches n drift layer 81. Sidewall surface SW includes a channel surface of MOSFET 200 on p base layer 82.

  Sidewall surface SW is inclined with respect to main surface MS of epitaxial layer 80, whereby trench TR extends in a taper shape toward the opening. Side wall surface SW preferably includes a {0-33-8} plane, and more preferably includes a (0-33-8) plane, particularly in a portion on p base layer 82. Bottom surface BT is located on n drift layer 81.

  Gate oxide film 91 covers each of sidewall surface SW and bottom surface BT of trench TR. The gate electrode 92 is provided on the gate oxide film 91. Source electrode 94 is in contact with each of n source layer 83 and p contact region 84. The source wiring layer 95 is in contact with the source electrode 94. Source wiring layer 95 is, for example, an aluminum layer. The interlayer insulating film 93 insulates between the gate electrode 92 and the source wiring layer 95.

(Method for manufacturing silicon carbide semiconductor device)
Next, a method for manufacturing MOSFET 200 (FIG. 3) will be described below.

  As shown in FIG. 1, a single crystal substrate 70 having a flat surface is disposed in a growth chamber 30 (FIG. 1) of a CVD apparatus 500. This surface preferably has an off angle within 8 degrees from the {000-1} plane, and more preferably has an off angle within 8 degrees from the (000-1) plane. Next, heating of single crystal substrate 70 is started. Specifically, the single crystal substrate 70 is heated to the film formation temperature by the heater 32. The film forming temperature is preferably about 1400 ° C. or higher, and more preferably about 1500 ° C. or higher. The film forming temperature is preferably about 2000 ° C. or lower.

  A source gas for generating SiC is supplied into the growth chamber 30 via the source line 24 while heating the single crystal substrate 70. While performing this supply, nitrogen gas for imparting n-type is supplied into the growth chamber 30 via the main line 22 independent of the TMA line 21. Thus, n drift layer 81 is formed on single crystal substrate 70 as shown in FIG.

  Next, in the same manner as described above, a raw material gas for generating SiC is supplied into the growth chamber 30 via the raw material line 24 while heating the single crystal substrate 70. While performing this supply, TMA gas for imparting p-type is supplied into the growth chamber 30 via the TMA line 21. Thus, p base layer 82 (first silicon carbide layer) is formed on single crystal substrate 70 as shown in FIG.

  Next, in the same manner as described above, a raw material gas for generating SiC is supplied into the growth chamber 30 via the raw material line 24 while heating the single crystal substrate 70. While performing this supply, nitrogen gas for imparting n-type is supplied into the growth chamber 30 via the main line 22 independent of the TMA line 21. Thus, n source layer 83 (second silicon carbide layer) is formed on single crystal substrate 70 as shown in FIG. Preferably, when the n source layer 83 is formed, the TMA line 21 is blocked by the valve 34 between the intermediate portion PM and the growth chamber 30.

Next, cooling is performed to lower the temperature of the single crystal substrate 70 provided with the n drift layer 81, the p base layer 82, and the n source layer 83 from the film formation temperature. Specifically, heating of single crystal substrate 70 is stopped by turning off heater 32. Next, hydrogen gas as a cooling gas is supplied from the H ₂ supply source 16 via the raw material line 24. At the same time, the TMA line 21 is purged. Specifically, a purge gas for purging the TMA gas is introduced from the purge line 23 connected to the TMA line 21 into the TMA line 21. This purge gas flows into the growth chamber 70 and contributes to cooling of the single crystal substrate 70.

  As shown in FIG. 8, a p contact region 84 is formed by ion implantation. Next, a heat treatment for activating the impurities is performed. The temperature of this heat treatment is preferably 1500 ° C. or higher and 1900 ° C. or lower, for example, about 1700 ° C. The heat treatment time is, for example, about 30 minutes. The atmosphere of the heat treatment is preferably an inert gas atmosphere, for example, an argon (Ar) atmosphere.

  As shown in FIG. 9, the main surface MS of the epitaxial layer 80 is covered with a mask layer 40 (silicon dioxide layer) made of silicon dioxide. Preferably, mask layer 40 is a thermal oxide film on main surface MS. Mask layer 40 has an opening OP corresponding to the position of trench TR (FIG. 1).

  As shown in FIG. 10, thermal etching using the mask layer 40 is performed. That is, the reactive gas is supplied under heating to the epitaxial layer 80 having the main surface MS covered with the mask layer 40 in which the opening OP is formed. The reactive gas is capable of reacting with silicon carbide under heating, and preferably contains a halogen gas, such as chlorine gas. The reactive gas may further contain oxygen gas. The reactive gas may contain a carrier gas. As the carrier gas, for example, nitrogen gas, argon gas or helium gas can be used. The epitaxial layer 80 is heated at, for example, about 700 ° C. or more and about 1000 ° C. or less. By this thermal etching, trench TR having sidewall surface SW is formed in main surface MS of epitaxial layer 80. The etching rate of silicon carbide in this thermal etching is, for example, about 70 μm / hour. In this case, since the mask layer 40 is made of silicon dioxide, its consumption is suppressed. Preferably, when the trench TR is formed, a special surface is self-formed on the side wall surface SW, particularly on the p base layer 82. Next, the mask layer 40 is removed by an arbitrary method such as etching.

  As shown in FIG. 11, gate oxide film 91 is formed on sidewall surface SW and bottom surface BT of trench TR. The gate oxide film 91 is preferably formed by thermal oxidation.

  After the formation of the gate oxide film 91, NO annealing using nitrogen monoxide (NO) gas as an atmospheric gas may be performed. The temperature profile has, for example, conditions of a temperature of 1100 ° C. to 1300 ° C. and a holding time of about 1 hour. Thereby, nitrogen atoms are introduced into the interface region between gate oxide film 91 and p base layer 82. As a result, the formation of interface states in the interface region is suppressed, so that channel mobility can be improved. As long as such nitrogen atoms can be introduced, a gas other than NO gas may be used as the atmospheric gas. Ar annealing using argon (Ar) as an atmospheric gas may be further performed after the NO annealing. The heating temperature for Ar annealing is preferably higher than the heating temperature for NO annealing and lower than the melting point of the gate oxide film 91. The time during which this heating temperature is maintained is, for example, about 1 hour. Thereby, the formation of interface states in the interface region between gate oxide film 91 and p base layer 82 is further suppressed. Note that other inert gas such as nitrogen gas may be used as the atmospheric gas instead of Ar gas.

  As shown in FIG. 12, gate electrode 92 is formed on gate oxide film 91. Specifically, gate electrode 92 is formed on gate oxide film 91 so as to fill the region inside trench TR with gate oxide film 91 interposed therebetween. The gate electrode 92 can be formed by, for example, film formation of conductor or doped polysilicon and CMP (Chemical Mechanical Polishing).

  Referring to FIG. 13, interlayer insulating film 93 is formed on gate electrode 92 and gate oxide film 91 so as to cover the exposed surface of gate electrode 92. Etching is performed so that openings are formed in the interlayer insulating film 93 and the gate oxide film 91. Through this opening, each of n source layer 83 and p contact region 84 is exposed on main surface MS. Next, source electrode 94 in contact with each of n source layer 83 and n contact region 84 is formed on main surface MS. A drain electrode 98 is formed on n drift layer 81 through single crystal substrate 70.

  Referring to FIG. 3 again, source wiring layer 95 is formed. Thereby, MOSFET 200 is obtained.

(Comparative film forming apparatus)
As shown in FIG. 2, the main line 22 of the film forming apparatus 599 of the comparative example is connected to the intermediate portion PM of the TMA line 21. Therefore, in the comparative example, the main line 22 is not independent from the TMA line 21. As a result, the gas for imparting n-type and the gas for imparting p-type are supplied to the growth chamber 30 from the end PS of the common line. Therefore, when the n-type n source layer 83 having the n-type is formed using the main line 22, the effect of the cleanliness of the TMA line 21 on the impurity concentration is increased. Further, when the MOSFET 200 is repeatedly manufactured, the effective impurity concentration is difficult to be stabilized in the film forming process (FIGS. 5 to 7) of the n drift layer 81, the p base layer 82, and the n source layer 83. In particular, the n drift layer 81 having a low impurity concentration tends to increase the effective impurity concentration fluctuation ratio. Therefore, it is difficult to manufacture MOSFET 200 with stable characteristics.

(Operational effect of the present embodiment)
Unlike the comparative example, according to the present embodiment, the main line 22 is independent from the TMA line 21 for transporting the TMA gas for imparting the p-type. Therefore, when the n-type n source layer 83 having the n-type is formed using the main line 22, the influence of the cleanliness of the TMA line 21 on the impurity concentration can be suppressed. Further, by maintaining the cleanliness of the TMA line 21 by purging the TMA line 21, even when the MOSFET 200 is repeatedly manufactured, the impurity concentration of the n drift layer 81, the p base layer 82, and the n source layer 83 is stabilized. Is done. In particular, the effective impurity concentration of the n drift layer 81 having a low impurity concentration is remarkably stabilized. Therefore, MOSFET 200 with stable characteristics can be manufactured.

  The source gas is supplied from the main line 22 into the growth chamber 30. Thereby, the gas supply path can be simplified as compared with the case where a dedicated line for supplying the source gas into the growth chamber is provided. Further, nitrogen gas for imparting n-type can be supplied into the growth chamber 30 as a mixed gas with a raw material gas for generating SiC.

  The TMA line 21 has an intermediate part PM into which purge gas is introduced. Thereby, the TMA line 21 can be purged. Thereby, the TMA line 21 can be cleaned.

  The distance between the end portion PE and the intermediate portion PM in the TMA line 21 is less than 100 mm. Thereby, the length of the portion which is hard to be purged in the TMA line 21 can be reduced to less than 100 mm.

  The single crystal substrate 70 is cooled by the purge gas. Thereby, the process of purging and the process of lowering the temperature of the single crystal substrate 70 can be performed simultaneously. Therefore, the manufacturing efficiency of MOSFET 200 can be increased.

  The purge gas contains at least one of hydrogen gas and rare gas. Thereby, purging can be performed with a gas having little influence on the film formation.

  When the n source layer 83 is formed, the TMA line 21 is blocked by the valve 34 between the intermediate portion PM and the growth chamber 30. Thereby, the influence of the TMA line 21 on the formation of the n source layer 83 can be further suppressed.

  The valve 34 may be omitted. That is, the above-described blocking may not be performed. In this case, a decrease in cleanliness due to accumulation of TMA in the valve 34 can be avoided.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

11 TMA supply source, 12 N ₂ supply source, 13 purge gas supply source, 14 C ₃ H ₈ supply source, 15 SiH ₄ supply source, 16 H ₂ supply source, 21 TMA line (first path), 22 main line ( (Second path), 23 purge line (third path), 24 raw material line, 29 exhaust line, 30 growth chamber, 31 stage (support), 32 heater, 33 pump, 34 valve, 40 mask layer, 70 single Crystal substrate (substrate), 80 epitaxial layer, 81 n drift layer, 82 p base layer (first silicon carbide layer), 83 n source layer (second silicon carbide layer), 84 p contact region, 91 gate oxide film (Gate insulating film), 92 gate electrode, 93 interlayer insulating film, 94 source electrode, 95 source wiring layer, 98 drain electrode, 200 MOSFET (silicon carbide semiconductor device), 500 C D apparatus (film formation apparatus), BT bottom, MS major surface, OP opening, PB intermediate portion, PE, PS end, SW sidewall surfaces, TR trench.

Claims (9)

Placing a substrate in a growth chamber for chemical vapor deposition;
Starting the heating of the substrate;
While heating the substrate and supplying a source gas for generating silicon carbide into the growth chamber, a first additive gas for imparting a first conductivity type is passed through the first path. Forming a first silicon carbide layer having the first conductivity type on the substrate by supplying into the growth chamber;
While heating the substrate and supplying a source gas for generating silicon carbide into the growth chamber, a second additive gas for imparting a second conductivity type is independent of the first path. Forming a second silicon carbide layer having the second conductivity type on the substrate by supplying it into the growth chamber via the second path,
After forming the first and second silicon carbide layers, a purge gas for purging the first additive gas is introduced from the third path connected to the first path into the first path. A method for manufacturing a silicon carbide semiconductor device, comprising: a step.   The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the source gas is supplied into the growth chamber from the second path.   The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein the step of introducing the purge gas includes a step of cooling the substrate with the purge gas after heating of the substrate is stopped.   The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the first additive gas includes trimethylaluminum.   The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the purge gas includes at least one of hydrogen gas and rare gas.   The first path has an end connected to the supply source of the first additive gas, and an intermediate part into which the purge gas is introduced, and the end part and the intermediate part in the first path The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein a distance between and is less than 100 mm.   The method for manufacturing a silicon carbide semiconductor device according to claim 6, wherein the step of forming the second silicon carbide layer includes a step of blocking the first path between the intermediate portion and the growth chamber. A film forming apparatus for forming a silicon carbide layer on a substrate,
A growth chamber that can be supplied with a source gas for producing silicon carbide by chemical vapor deposition;
A support for supporting the substrate in the growth chamber;
A heater for heating the substrate supported by the support;
A first path for supplying a first additive gas for imparting a first conductivity type to silicon carbide into the growth chamber;
A second path independent of the first path for supplying a second additive gas for imparting a second conductivity type to silicon carbide into the growth chamber;
And a third path connected to the first path for introducing a purge gas for purging the first additive gas into the first path.   The film forming apparatus according to claim 8, wherein the source gas is configured to be supplied from the second path into the growth chamber.

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