JP2014116407A - Variable capacitance element module - Google Patents

Variable capacitance element module Download PDF

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JP2014116407A
JP2014116407A JP2012268371A JP2012268371A JP2014116407A JP 2014116407 A JP2014116407 A JP 2014116407A JP 2012268371 A JP2012268371 A JP 2012268371A JP 2012268371 A JP2012268371 A JP 2012268371A JP 2014116407 A JP2014116407 A JP 2014116407A
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variable capacitance
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capacitance element
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JP5978969B2 (en
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Noboru Kato
登 加藤
Noriyuki Ueki
紀行 植木
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Murata Manufacturing Co Ltd
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Abstract

PROBLEM TO BE SOLVED: To provide a variable capacitance element module with a high ESD resistance property.SOLUTION: A substrate 30 is formed in a shape of a rectangular parallelepiped plate having a first side BS1 and a second side BS2 opposing each other with a variable capacitance element 14 interposed therebetween. A first substrate-side input/output terminal EP1 to connect a first input/output terminal P1 of the variable capacitance element 14 thereto and a second substrate-side input/output terminal EP2 to connect a second input/output terminal P2 of the variable capacitance element 14 thereto are disposed at positions along the first side BS1, and a substrate-side control voltage input terminal EVt to connect a control voltage input terminal Vt of the variable capacitance element 14 thereto and a substrate-side ground terminal EG to connect a ground terminal GND of the variable capacitance element 14 thereto are disposed at positions along the second side BS2. A first ESD protection element 17A is disposed between the first substrate-side input/output terminal EP1 and the substrate-side control voltage input terminal EVt, and a second ESD protection element 17B is disposed between the second substrate-side input/output terminal EP2 and the substrate-side ground terminal EG.

Description

本発明は、例えばＲＦＩＤ（Radio Frequency Identification）システムや近距離無線通信（NFC：Near Field Communication）システム等の通信装置に用いられる可変容量素子モジュールに関するものである。   The present invention relates to a variable capacitance element module used in a communication device such as an RFID (Radio Frequency Identification) system or a near field communication (NFC) system.

従来、特許文献１，２などにおいて、制御電圧の印加により誘電率が変化する可変容量素子が提案されている。これらの可変容量素子は、金属、強誘電体材料、金属の積層構造（ＭＩＭ構造）をとり、低電圧で大きな容量変化量が得られるように薄膜の強誘電体を備えている。   Conventionally, in Patent Documents 1 and 2 and the like, variable capacitance elements whose permittivity changes by application of a control voltage have been proposed. These variable capacitance elements have a laminated structure (MIM structure) of metal, a ferroelectric material, and a metal, and are provided with a thin film ferroelectric so that a large capacitance change amount can be obtained at a low voltage.

特許第４５０２６０９号公報Japanese Patent No. 4502609 特許第５０００６６０号公報Japanese Patent No. 550660

強誘電体膜を備える可変容量素子は、MEMSによる可変容量素子や可変容量ダイオードのような半導体の可変容量素子に比べて、耐ＥＳＤ（Electro-Static Discharge）特性が低いことがその欠点とされてきた。   A variable capacitance element having a ferroelectric film has been considered to have a low ESD (Electro-Static Discharge) characteristic compared to a semiconductor variable capacitance element such as a MEMS variable capacitance element or a variable capacitance diode. It was.

強誘電体膜の膜厚を薄くすると制御感度（制御電圧変化に対する容量値変化の比）が高まるが、強誘電体膜の薄膜化に伴い、耐ＥＳＤ特性が劣化する。すなわち耐ＥＳＤ特性を超えるＥＳＤが生じると、そのサージが強誘電体膜にかかって、強誘電体膜が絶縁破壊される。そのため、耐ＥＳＤの観点から、強誘電体膜の薄膜化には制約が生じ、したがって、制御感度もその制限を受ける。   When the thickness of the ferroelectric film is reduced, control sensitivity (ratio of change in capacitance value with respect to change in control voltage) increases. However, as the ferroelectric film is made thinner, the ESD resistance is deteriorated. That is, when ESD exceeding the ESD resistance characteristic occurs, the surge is applied to the ferroelectric film, and the ferroelectric film is dielectrically broken down. For this reason, from the viewpoint of ESD resistance, there is a restriction on the thinning of the ferroelectric film, and thus the control sensitivity is also restricted.

本発明の目的は、耐ＥＳＤ特性の高い可変容量素子モジュールを提供することにある。   An object of the present invention is to provide a variable capacitance element module having high ESD resistance.

本発明の可変容量素子モジュールは次のように構成する。   The variable capacitance element module of the present invention is configured as follows.

（１）可変容量素子、第１のＥＳＤ保護素子、第２のＥＳＤ保護素子、およびこれらが実装される共通の基板を備え、
前記可変容量素子は、電界によって誘電率が変化する強誘電体膜と、この強誘電体膜を挟んで電圧を印加するキャパシタ電極と、第１の入出力端子と、第２の入出力端子と、制御電圧入力端子と、グランド端子とを備え、
前記第１のＥＳＤ保護素子は、第１端が前記第１の入出力端子に接続され、第２端が前記グランド端子に接続されていて、
前記第２のＥＳＤ保護素子は、第１端が前記第２の入出力端子に接続され、第２端が前記グランド端子に接続されていることを特徴とする。 (1) A variable capacitance element, a first ESD protection element, a second ESD protection element, and a common substrate on which these are mounted,
The variable capacitance element includes a ferroelectric film whose dielectric constant is changed by an electric field, a capacitor electrode for applying a voltage across the ferroelectric film, a first input / output terminal, and a second input / output terminal. A control voltage input terminal and a ground terminal,
The first ESD protection element has a first end connected to the first input / output terminal and a second end connected to the ground terminal;
The second ESD protection element has a first end connected to the second input / output terminal and a second end connected to the ground terminal.

上記構成により、可変容量素子の入出力端とグランドとの間にＥＳＤ保護素子が接続されているので、外部から可変容量素子の入出力端にＥＳＤによるサージが入っても、サージ電流はＥＳＤ保護素子へ導かれる。そのため、可変容量素子に過電圧が印加されず破壊されにくくなる。また、可変容量素子と２つのＥＳＤ保護素子とを別体で配線基板に実装した構成に比べて、可変容量素子とＥＳＤ保護素子との間の配線距離を短くできるので、その配線にＥＳＤが入り込みにくくなり、その点でも高い耐ＥＳＤ特性が得られる。   With the above configuration, an ESD protection element is connected between the input / output end of the variable capacitance element and the ground, so even if an ESD surge enters the input / output end of the variable capacitance element from the outside, the surge current is protected against ESD. Guided to the element. Therefore, an overvoltage is not applied to the variable capacitance element and it is difficult to be destroyed. Also, compared to a configuration in which the variable capacitance element and the two ESD protection elements are separately mounted on the wiring board, the wiring distance between the variable capacitance element and the ESD protection element can be shortened, so that ESD enters the wiring. In this respect, high ESD resistance can be obtained.

（２）前記第１のＥＳＤ保護素子および前記第２のＥＳＤ保護素子は前記可変容量素子を介する対称位置に配置されていることが好ましい。この構造により、熱負荷によって、基板に対する可変容量素子の実装位置に生じる機械的歪みと、基板に対する２つのＥＳＤ保護素子の実装位置に生じる機械的歪みとが対称に分散されて、熱負荷に対する耐性が高い。 (2) It is preferable that the first ESD protection element and the second ESD protection element are arranged at symmetrical positions via the variable capacitance element. With this structure, the mechanical strain generated at the mounting position of the variable capacitance element with respect to the substrate by the thermal load and the mechanical strain generated at the mounting position of the two ESD protection elements with respect to the substrate are symmetrically distributed, thereby being resistant to the thermal load. Is expensive.

（３）前記基板は前記可変容量素子を介して対向する第１辺および第２辺を有する直方体板状であり、第１辺に沿った位置に、前記可変容量素子の第１の入出力端子が接続される第１の基板側入出力端子、および前記可変容量素子の第２の入出力端子が接続される第２の基板側入出力端子が配置され、第２辺に沿った位置に、前記可変容量素子の制御電圧入力端子が接続される基板側制御電圧入力端子、および前記可変容量素子のグランド端子が接続される基板側グランド端子が配置され、
前記第１のＥＳＤ保護素子は前記第１の基板側入出力端子と前記基板側制御電圧入力端子との間に配置され、前記第２のＥＳＤ保護素子は前記第２の基板側入出力端子と前記基板側グランド端子との間に配置されていることが好ましい。 (3) The substrate has a rectangular parallelepiped plate shape having a first side and a second side facing each other with the variable capacitance element interposed therebetween, and the first input / output terminal of the variable capacitance element is positioned along the first side. Are connected to the first substrate side input / output terminal and the second substrate side input / output terminal to which the second input / output terminal of the variable capacitance element is connected, and at a position along the second side, A substrate side control voltage input terminal to which the control voltage input terminal of the variable capacitance element is connected, and a substrate side ground terminal to which the ground terminal of the variable capacitance element is connected are arranged.
The first ESD protection element is disposed between the first substrate-side input / output terminal and the substrate-side control voltage input terminal, and the second ESD protection element is connected to the second substrate-side input / output terminal. It is preferable to be disposed between the substrate-side ground terminals.

上記構成により、第１・第２の入出力端子の近傍に、ＥＳＤ保護素子をそれぞれ配置できるので、可変容量素子とＥＳＤ保護素子との配線長が短く、ＥＳＤ保護効果が大きい。   With the above configuration, since the ESD protection elements can be arranged in the vicinity of the first and second input / output terminals, the wiring length between the variable capacitance element and the ESD protection element is short, and the ESD protection effect is large.

（４）（３）において、前記可変容量素子は、前記制御電圧入力端子と前記可変容量素子のキャパシタ電極との間に接続されたチョーク抵抗を備え、
前記可変容量素子は互いに対向する第１辺および第２辺を有する直方体板状であり、第１辺に沿って前記第１の入出力端子および前記第２の入出力端子が配置され、第２辺に沿って前記制御電圧入力端子および前記グランド端子が配置され、
前記可変容量素子は、その第１辺が前記基板の第１辺寄りで、且つ第２辺が前記基板の第２辺寄りとなるように前記基板に実装されていることが好ましい。 (4) In (3), the variable capacitance element includes a choke resistor connected between the control voltage input terminal and a capacitor electrode of the variable capacitance element,
The variable capacitance element has a rectangular parallelepiped plate shape having a first side and a second side facing each other, and the first input / output terminal and the second input / output terminal are arranged along the first side, The control voltage input terminal and the ground terminal are arranged along a side,
The variable capacitance element is preferably mounted on the substrate such that the first side is closer to the first side of the substrate and the second side is closer to the second side of the substrate.

上記の構成により、一方のＥＳＤ保護素子と基板側グランド端子との接続経路が可変容量素子の制御電圧入力端子付近を通ることになる。この接続経路にＥＳＤ電流が流れても、制御電圧入力端子と可変容量素子の強誘電体膜との間にはチョーク抵抗が挿入されているので、ＥＳＤ保護素子による保護効果の低下は小さい。   With the above configuration, the connection path between one ESD protection element and the substrate-side ground terminal passes through the vicinity of the control voltage input terminal of the variable capacitance element. Even if an ESD current flows through this connection path, since the choke resistor is inserted between the control voltage input terminal and the ferroelectric film of the variable capacitance element, the degradation of the protection effect by the ESD protection element is small.

（５）（１）において、前記基板は前記可変容量素子を介して対向する第１辺および第２辺を有する直方体板状であり、第１辺に沿った位置に、前記可変容量素子の第１の入出力端子が接続される第１の基板側入出力端子、および前記可変容量素子の第２の入出力端子が接続される第２の基板側入出力端子が配置され、第２辺に沿った位置に、前記可変容量素子の制御電圧入力端子が接続される基板側制御電圧入力端子、および前記可変容量素子のグランド端子が接続される基板側グランド端子が配置され、
前記第１・第２のＥＳＤ保護素子は、単一のＥＳＤ保護チップ部品として構成されていて、
第１の基板側入出力端子と基板側グランド端子との間に前記ＥＳＤ保護チップ部品が配置されていることが好ましい。 (5) In (1), the substrate has a rectangular parallelepiped plate shape having a first side and a second side that are opposed to each other with the variable capacitance element interposed therebetween. A first substrate-side input / output terminal to which one input / output terminal is connected, and a second substrate-side input / output terminal to which the second input / output terminal of the variable capacitance element is connected are arranged on the second side. A board-side control voltage input terminal to which the control voltage input terminal of the variable capacitance element is connected and a substrate-side ground terminal to which the ground terminal of the variable capacitance element is connected are disposed along the position,
The first and second ESD protection elements are configured as a single ESD protection chip component,
It is preferable that the ESD protection chip component is disposed between the first substrate side input / output terminal and the substrate side ground terminal.

上記構成により、基板への実装素子数が２つになり、全体に小型化できる。   With the above configuration, the number of elements mounted on the substrate is two, and the overall size can be reduced.

本発明によれば、制御感度が高く、耐ＥＳＤ特性の高い可変容量素子モジュールが得られる。   According to the present invention, a variable capacitance element module having high control sensitivity and high ESD resistance can be obtained.

図１は第１の実施形態に係る可変容量素子モジュール９１の回路図である。FIG. 1 is a circuit diagram of the variable capacitance element module 91 according to the first embodiment. 図２は可変容量素子１４の主要部の断面図である。FIG. 2 is a cross-sectional view of the main part of the variable capacitance element 14. 図３は可変容量素子１４の抵抗膜パターンの例を示す図である。FIG. 3 is a diagram illustrating an example of a resistive film pattern of the variable capacitance element 14. 図４は可変容量素子モジュール９１の主要部の分解斜視図である。FIG. 4 is an exploded perspective view of the main part of the variable capacitance element module 91. 図５は可変容量素子モジュール９１の平面図である。FIG. 5 is a plan view of the variable capacitance element module 91. 図６は可変容量素子モジュール９１の断面図である。FIG. 6 is a cross-sectional view of the variable capacitance element module 91. 図７は第２の実施形態に係る可変容量素子モジュール９２の分解斜視図である。FIG. 7 is an exploded perspective view of the variable capacitance element module 92 according to the second embodiment. 図８は第２の実施形態の可変容量素子モジュール９２の断面図である。FIG. 8 is a cross-sectional view of the variable capacitance element module 92 according to the second embodiment. 図９は第３の実施形態に係る可変容量素子モジュール９３の分解斜視図である。FIG. 9 is an exploded perspective view of the variable capacitance element module 93 according to the third embodiment. 図１０は第４の実施形態に係る可変容量素子モジュール９４の分解斜視図である。FIG. 10 is an exploded perspective view of the variable capacitance element module 94 according to the fourth embodiment. 図１１は、可変容量素子モジュールを備える通信回路の回路図である。FIG. 11 is a circuit diagram of a communication circuit including a variable capacitance element module.

《第１の実施形態》
図１は第１の実施形態に係る可変容量素子モジュール９１の回路図である。この可変容量素子モジュール９１は可変容量素子１４と２つのＥＳＤ保護素子１７Ａ，１７Ｂとを含んでいる。 << First Embodiment >>
FIG. 1 is a circuit diagram of the variable capacitance element module 91 according to the first embodiment. The variable capacitance element module 91 includes a variable capacitance element 14 and two ESD protection elements 17A and 17B.

可変容量素子１４は、制御電圧入力端子Ｖｔとグランド端子ＧＮＤ間に印加される制御電圧に応じて第１の入出力端子Ｐ１−第２の入出力端子Ｐ２間の容量値が定まる。   The variable capacitance element 14 has a capacitance value between the first input / output terminal P1 and the second input / output terminal P2 according to a control voltage applied between the control voltage input terminal Vt and the ground terminal GND.

可変容量素子１４は、複数の容量素子Ｃ１〜Ｃ６および抵抗Ｒ１１〜Ｒ１９を備えている。容量素子Ｃ１〜Ｃ６のそれぞれは、電界によって誘電率が変化する強誘電体膜と、この強誘電体膜を挟んで電圧を印加するキャパシタ電極とで構成される強誘電体キャパシタである。強誘電体膜は印加される電界の強度に応じて分極量が変化して、見かけ上の誘電率が変化するので、制御電圧によって容量値を定められる。各キャパシタ電極にはＲＦ抵抗素子Ｒ１１〜Ｒ１９を介して制御電圧が印加される。ＲＦ抵抗素子Ｒ１１〜Ｒ１９の抵抗値は等しい。これらのＲＦ抵抗素子Ｒ１１〜Ｒ１９は、容量素子Ｃ１〜Ｃ６のそれぞれに制御電圧を印加するとともに、端子Ｐ１−Ｐ２間に印加されるＲＦ信号が制御電圧入力端子Ｖｔおよびグランド端子ＧＮＤへ漏れるのを抑制するチョーク抵抗として作用する。   The variable capacitance element 14 includes a plurality of capacitance elements C1 to C6 and resistors R11 to R19. Each of the capacitive elements C1 to C6 is a ferroelectric capacitor composed of a ferroelectric film whose dielectric constant changes with an electric field and a capacitor electrode to which a voltage is applied across the ferroelectric film. Since the amount of polarization of the ferroelectric film changes according to the strength of the applied electric field and the apparent dielectric constant changes, the capacitance value can be determined by the control voltage. A control voltage is applied to each capacitor electrode via RF resistance elements R11 to R19. The resistance values of the RF resistance elements R11 to R19 are equal. These RF resistance elements R11 to R19 apply a control voltage to the capacitive elements C1 to C6, respectively, and prevent an RF signal applied between the terminals P1 and P2 from leaking to the control voltage input terminal Vt and the ground terminal GND. Acts as a choke resistor to suppress.

第１の入出力端子Ｐ１とグランド端子ＧＮＤとの間にはＥＳＤ保護素子１７Ａが接続されていて、第２の入出力端子Ｐ２とグランド端子ＧＮＤとの間にはＥＳＤ保護素子１７Ｂが接続されている。外部から可変容量素子１４の入出力端子Ｐ１，Ｐ２にＥＳＤによるサージが入っても、ＥＳＤの電流はＥＳＤ保護素子１７Ａ，１７Ｂを通ってグランドへ落ちる。そのため、可変容量素子１４の容量素子Ｃ１〜Ｃ６に過電圧が印加されず、容量素子Ｃ１〜Ｃ６は保護される。   An ESD protection element 17A is connected between the first input / output terminal P1 and the ground terminal GND, and an ESD protection element 17B is connected between the second input / output terminal P2 and the ground terminal GND. Yes. Even if an ESD surge is applied to the input / output terminals P1 and P2 of the variable capacitance element 14 from the outside, the ESD current falls to the ground through the ESD protection elements 17A and 17B. Therefore, no overvoltage is applied to the capacitive elements C1 to C6 of the variable capacitive element 14, and the capacitive elements C1 to C6 are protected.

図２は可変容量素子１４の主要部の断面図である。図２において基板ＳＩは表面にSiO2膜が形成されたSi基板である。この基板ＳＩ上に強誘電体膜ＦＳ１、キャパシタ電極ＰＴ１、強誘電体膜ＦＳ２、キャパシタ電極ＰＴ２、強誘電体膜ＦＳ３が順に形成されている。 FIG. 2 is a cross-sectional view of the main part of the variable capacitance element 14. In FIG. 2, the substrate SI is a Si substrate having a SiO 2 film formed on the surface. A ferroelectric film FS1, a capacitor electrode PT1, a ferroelectric film FS2, a capacitor electrode PT2, and a ferroelectric film FS3 are sequentially formed on the substrate SI.

これらの強誘電体膜ＦＳ１，ＦＳ２，ＦＳ３およびキャパシタ電極ＰＴ１，ＰＴ２の積層膜の上部には耐湿保護膜ＰＣ１が被覆されている。この耐湿保護膜ＰＣ１の上部には更に有機保護膜ＰＣ２が形成されている。   A moisture-resistant protective film PC1 is coated on top of the laminated film of these ferroelectric films FS1, FS2, FS3 and capacitor electrodes PT1, PT2. An organic protective film PC2 is further formed on the moisture-resistant protective film PC1.

有機保護膜ＰＣ２の上部には配線膜ＴＩ１が形成されている。また、この配線膜ＴＩ１はコンタクトホールを介してキャパシタ電極ＰＴ１，ＰＴ２の所定箇所に接続されている。さらに、配線膜ＴＩ１は、耐湿保護膜ＰＣ１および有機保護膜ＰＣ２の周囲を覆うように形成されている。   A wiring film TI1 is formed on the organic protective film PC2. Further, the wiring film TI1 is connected to a predetermined portion of the capacitor electrodes PT1, PT2 through a contact hole. Further, the wiring film TI1 is formed so as to cover the periphery of the moisture-resistant protective film PC1 and the organic protective film PC2.

配線膜ＴＩ１の表面には層間絶縁膜ＳＲ１が形成されている。この層間絶縁膜ＳＲ１の表面に抵抗膜パターンＲＥ１が形成されている。この抵抗膜パターンＲＥ１の表面は層間絶縁膜ＳＲ２で被覆されている。   An interlayer insulating film SR1 is formed on the surface of the wiring film TI1. A resistance film pattern RE1 is formed on the surface of the interlayer insulating film SR1. The surface of the resistance film pattern RE1 is covered with an interlayer insulating film SR2.

抵抗膜パターンＲＥ１は、薄膜プロセス（フォトリソグラフィおよびエッチング技術を利用したプロセス）または厚膜プロセス（スクリーン印刷等の印刷技術を利用したプロセス）で形成されている。各抵抗素子の抵抗値は、抵抗膜パターンの幅、長さおよび厚みによって定められる。   The resistive film pattern RE1 is formed by a thin film process (a process using photolithography and etching techniques) or a thick film process (a process using printing techniques such as screen printing). The resistance value of each resistive element is determined by the width, length and thickness of the resistive film pattern.

層間絶縁膜ＳＲ２の表面には配線膜ＴＩ２が形成されている。また、この配線膜ＴＩ２は、層間絶縁膜ＳＲ１，ＳＲ２に形成されたコンタクトホールを介して配線膜ＴＩ１に接続されている。   A wiring film TI2 is formed on the surface of the interlayer insulating film SR2. The wiring film TI2 is connected to the wiring film TI1 through a contact hole formed in the interlayer insulating films SR1 and SR2.

層間絶縁膜ＳＲ２の表面にはソルダーレジスト膜ＳＲ４が被覆されている。そして、このソルダーレジスト膜ＳＲ４の開口で且つ配線膜ＴＩ２の表面には外部接続電極ＥＥが形成されている。   The surface of the interlayer insulating film SR2 is covered with a solder resist film SR4. An external connection electrode EE is formed in the opening of the solder resist film SR4 and on the surface of the wiring film TI2.

前記強誘電体膜ＦＳ１は基板ＳＩおよび耐湿保護膜ＰＣ１に対する密着用・拡散防止用の絶縁膜である。また、強誘電体膜ＦＳ３は耐湿保護膜ＰＣ１に対する密着用の絶縁膜である。前記キャパシタ電極ＰＴ１，ＰＴ２に使用される導電性材料には、導電性が良好で耐酸化性に優れた高融点の貴金属材料、例えば、Pt，Auを用いることができる。   The ferroelectric film FS1 is an insulating film for adhesion and diffusion prevention with respect to the substrate SI and the moisture-resistant protective film PC1. The ferroelectric film FS3 is an insulating film for adhesion to the moisture resistant protective film PC1. As the conductive material used for the capacitor electrodes PT1 and PT2, a high melting point noble metal material having good conductivity and excellent oxidation resistance, for example, Pt and Au can be used.

また、前記強誘電体膜ＦＳ１，ＦＳ２，ＦＳ３に使用される薄膜材料には、高誘電率を有する誘電体材料が使用される。例えばペロブスカイト化合物やビスマス層状化合物等を使用することができる。   In addition, a dielectric material having a high dielectric constant is used as a thin film material used for the ferroelectric films FS1, FS2, and FS3. For example, a perovskite compound or a bismuth layered compound can be used.

また、配線膜ＴＩ１，ＴＩ２は、Ti／Cu／Tiの三層からなる。また、外部接続電極ＥＥは、Au／Niの二層からなる。   The wiring films TI1 and TI2 are composed of three layers of Ti / Cu / Ti. The external connection electrode EE is composed of two layers of Au / Ni.

前記耐湿保護膜ＰＣ１は有機保護膜ＰＣ２から放出される水分がキャパシタ部に浸入するのを防止する。また、有機保護膜ＰＣ２は外部からの機械的応力を吸収する。   The moisture-resistant protective film PC1 prevents moisture released from the organic protective film PC2 from entering the capacitor portion. The organic protective film PC2 absorbs mechanical stress from the outside.

前記抵抗膜パターンＲＥ１の抵抗材料は例えばニクロムである。   The resistance material of the resistance film pattern RE1 is, for example, nichrome.

図３は可変容量素子１４の抵抗膜パターンの例を示す図である。図３において、入出力端子Ｐ１，Ｐ２、制御電圧入力端子Ｖｔ、グランド端子ＧＮＤ、および抵抗膜パターンＲ１１〜Ｒ１９は図１において同一符号で表したものに対応する。   FIG. 3 is a diagram illustrating an example of a resistive film pattern of the variable capacitance element 14. In FIG. 3, input / output terminals P1, P2, control voltage input terminal Vt, ground terminal GND, and resistive film patterns R11 to R19 correspond to those denoted by the same reference numerals in FIG.

図４は可変容量素子モジュール９１の主要部の分解斜視図、図５は可変容量素子モジュール９１の平面図である。図４・図５中の回路記号は回路と各端子との関係を概念的に表すものである。   4 is an exploded perspective view of the main part of the variable capacitance element module 91, and FIG. 5 is a plan view of the variable capacitance element module 91. The circuit symbols in FIGS. 4 and 5 conceptually represent the relationship between the circuit and each terminal.

基板３０は複数の基材の積層体である。基板３０は可変容量素子を介して対向する第１辺ＢＳ１および第２辺ＢＳ２を有する直方体板状であり、第１辺ＢＳ１に沿った位置に、可変容量素子１４の第１の入出力端子Ｐ１が接続される第１の基板側入出力端子ＥＰ１、および可変容量素子１４の第２の入出力端子Ｐ２が接続される第２の基板側入出力端子ＥＰ２が配置され、第２辺ＢＳ２に沿った位置に、可変容量素子１４の制御電圧入力端子Ｖｔが接続される基板側制御電圧入力端子ＥＶｔ、および可変容量素子１４のグランド端子ＧＮＤが接続される基板側グランド端子ＥＧが配置されている。   The substrate 30 is a laminate of a plurality of base materials. The substrate 30 has a rectangular parallelepiped plate shape having a first side BS1 and a second side BS2 that are opposed to each other with the variable capacitance element interposed therebetween, and the first input / output terminal P1 of the variable capacitance element 14 is positioned along the first side BS1. Are connected to the first substrate-side input / output terminal EP1 to which the second capacitor I / O is connected, and the second substrate-side input / output terminal EP2 to which the second input / output terminal P2 of the variable capacitance element 14 is connected, along the second side BS2. The board side control voltage input terminal EVt to which the control voltage input terminal Vt of the variable capacitance element 14 is connected and the board side ground terminal EG to which the ground terminal GND of the variable capacitance element 14 is connected are arranged at the positions.

第１のＥＳＤ保護素子１７Ａは第１の基板側入出力端子ＥＰ１と基板側制御電圧入力端子ＥＶｔとの間に配置され、第２のＥＳＤ保護素子１７Ｂは第２の基板側入出力端子ＥＰ２と基板側グランド端子ＥＧとの間に配置（実装）されている。また、第１のＥＳＤ保護素子１７Ａおよび第２のＥＳＤ保護素子１７Ｂは可変容量素子１４を介する対称位置（を挟む位置）に配置されている。   The first ESD protection element 17A is disposed between the first substrate side input / output terminal EP1 and the substrate side control voltage input terminal EVt, and the second ESD protection element 17B is connected to the second substrate side input / output terminal EP2. It is arranged (mounted) between the substrate side ground terminal EG. In addition, the first ESD protection element 17A and the second ESD protection element 17B are arranged at symmetrical positions (positions sandwiching them) with the variable capacitance element 14 in between.

また、可変容量素子１４は、互いに対向する第１辺ＣＳ１および第２辺ＣＳ２を有する直方体板状であり、第１辺ＣＳ１に沿って第１の入出力端子Ｐ１および第２の入出力端子Ｐ２が配置され、第２辺ＣＳ２に沿って制御電圧入力端子Ｖｔおよびグランド端子ＧＮＤが配置されている。そして、可変容量素子１４は、その第１辺ＣＳ１が基板３０の第１辺ＢＳ１寄りで、且つ第２辺ＣＳ２が基板３０の第２辺ＢＳ２寄りとなるように、基板３０に実装されている。   The variable capacitance element 14 has a rectangular parallelepiped plate shape having a first side CS1 and a second side CS2 facing each other, and the first input / output terminal P1 and the second input / output terminal P2 along the first side CS1. Are arranged, and the control voltage input terminal Vt and the ground terminal GND are arranged along the second side CS2. The variable capacitance element 14 is mounted on the substrate 30 such that the first side CS1 is closer to the first side BS1 of the substrate 30 and the second side CS2 is closer to the second side BS2 of the substrate 30. .

ＥＳＤ保護素子１７Ａ，１７Ｂはバリスタ、ダイオード、ツェナーダイオード等のシリコンＥＳＤデバイスや、放電ギャップをセラミック基板内に内蔵したセラミックＥＳＤデバイスである。   The ESD protection elements 17A and 17B are silicon ESD devices such as varistors, diodes, and Zener diodes, and ceramic ESD devices in which a discharge gap is built in a ceramic substrate.

図６は可変容量素子モジュール９１の断面図である。図４、図５に示した基板３０上に可変容量素子１４およびＥＳＤ保護素子１７Ａ，１７Ｂがダイボンディングされ、これらの素子の端子と基板上の端子とがワイヤーボンディングされ、その後、図６に示すようにカバー４０が被覆される。カバー４０は基板３０の周辺に対して接着される。可変容量素子１４の基材と、ＥＳＤ保護素子１７Ａ，１７Ｂの基材は同じであるか、または線膨張係数が±４０％以内で等しいものである。例えばシリコン基板、サファイア基板、ＧａＡｓ基板等である。これにより、基板３０に対する熱的膨張収縮が面方向で均一となるので、熱負荷によって可変容量素子とＥＳＤ保護素子との間で機械的なひずみが生じにくく、クラックの発生が抑制できる。また、基板３０およびカバー４０はいずれも樹脂製であるが、これらの線膨張係数についても、可変容量素子１４およびＥＳＤ保護素子１７Ａ，１７Ｂの基材の線膨張係数に対して±４０％以内で等しいことが好ましい。そのことにより、基板の反りが抑えられ、平坦性を保てる。   FIG. 6 is a cross-sectional view of the variable capacitance element module 91. The variable capacitance element 14 and the ESD protection elements 17A and 17B are die-bonded on the substrate 30 shown in FIGS. 4 and 5, the terminals of these elements and the terminals on the substrate are wire-bonded, and then shown in FIG. Thus, the cover 40 is covered. The cover 40 is bonded to the periphery of the substrate 30. The base material of the variable capacitance element 14 and the base material of the ESD protection elements 17A and 17B are the same, or the linear expansion coefficients are equal within ± 40%. For example, a silicon substrate, a sapphire substrate, a GaAs substrate, or the like. Thereby, the thermal expansion and contraction with respect to the substrate 30 becomes uniform in the surface direction, so that mechanical strain hardly occurs between the variable capacitance element and the ESD protection element due to the thermal load, and the generation of cracks can be suppressed. The substrate 30 and the cover 40 are both made of resin, but their linear expansion coefficients are also within ± 40% with respect to the linear expansion coefficients of the base material of the variable capacitance element 14 and the ESD protection elements 17A and 17B. Preferably equal. Thereby, the warpage of the substrate can be suppressed and the flatness can be maintained.

図４、図５に表れているように、可変容量素子１４の第１辺ＣＳ１に沿って第１の入出力端子Ｐ１および第２の入出力端子Ｐ２が配置され、第２辺ＣＳ２に沿って制御電圧入力端子Ｖｔおよびグランド端子ＧＮＤが配置されていて、可変容量素子１４は、その第１辺ＣＳ１が基板３０の第１辺ＢＳ１寄りで、且つ第２辺ＣＳ２が基板３０の第２辺ＢＳ２寄りとなるように、基板３０に実装されているので、下記の利点がある。   As shown in FIGS. 4 and 5, the first input / output terminal P1 and the second input / output terminal P2 are arranged along the first side CS1 of the variable capacitance element 14, and along the second side CS2. The control voltage input terminal Vt and the ground terminal GND are arranged. The variable capacitor 14 has a first side CS1 closer to the first side BS1 of the substrate 30 and a second side CS2 of the second side BS2 of the substrate 30. Since it is mounted on the substrate 30 so as to be closer, there are the following advantages.

図５において、例えば第１の基板側入出力端子ＥＰ１からＥＳＤが入ると、矢印Ａで示すように、ＥＳＤ保護素子１７Ａを介する電流はワイヤーＷ１を通って、矢印Ｂで示すように基板側グランド端子ＥＧへ流れる（抜ける）。可変容量素子１４の制御電圧入力端子Ｖｔと基板側制御電圧入力端子ＥＶｔとの間を接続するワイヤーＷ２は上記ワイヤーＷ１と交差するかたちで近接する。そのため、ワイヤーＷ１とＷ２は電磁界結合して、ワイヤーＷ１に流れるサージ電流でワイヤーＷ２にも矢印Ｃで示すようにサージ電流が誘導される場合がある。このワイヤーＷ２を介するサージは可変容量素子１４の制御電圧入力端子Ｖｔへ印加されるが、この可変容量素子１４の端子Ｖｔと、可変容量素子１４内の強誘電体膜との間、および強誘電体膜とグランド端子との間にはチョーク抵抗（図１中のＲ１１〜Ｒ１９参照）が存在するので、直接強誘電体膜には高電圧が印加されることはなく、強誘電体膜はＥＳＤによる破壊から免れる。   In FIG. 5, for example, when an ESD enters from the first board side input / output terminal EP1, the current through the ESD protection element 17A passes through the wire W1 as shown by the arrow A and the board side ground as shown by the arrow B. It flows (exits) to the terminal EG. A wire W2 connecting the control voltage input terminal Vt and the substrate side control voltage input terminal EVt of the variable capacitance element 14 comes close to the wire W1 in a crossing manner. Therefore, the wires W1 and W2 are electromagnetically coupled, and a surge current may be induced in the wire W2 as indicated by an arrow C due to the surge current flowing in the wire W1. The surge through the wire W2 is applied to the control voltage input terminal Vt of the variable capacitance element 14, and it is between the terminal Vt of the variable capacitance element 14 and the ferroelectric film in the variable capacitance element 14, and the ferroelectric. Since a choke resistor (see R11 to R19 in FIG. 1) exists between the body film and the ground terminal, a high voltage is not directly applied to the ferroelectric film, and the ferroelectric film is an ESD. Escape from destruction by.

《第２の実施形態》
図７は第２の実施形態に係る可変容量素子モジュール９２の分解斜視図である。図７中の回路記号は回路と各端子との関係を概念的に表すものである。この第２の実施形態では、基板３０上に対する各素子の実装構造が第１の実施形態とは異なる。可変容量素子１４およびＥＳＤ保護素子１７Ａ，１７Ｂの下面には、いずれもフリップチップボンディングするためのバンプが形成されている。そして、基板３０上には可変容量素子１４、ＥＳＤ保護素子１７Ａ，１７Ｂの実装用電極および配線パターンが形成されている。 << Second Embodiment >>
FIG. 7 is an exploded perspective view of the variable capacitance element module 92 according to the second embodiment. The circuit symbol in FIG. 7 conceptually represents the relationship between the circuit and each terminal. In the second embodiment, the mounting structure of each element on the substrate 30 is different from that of the first embodiment. Bumps for flip chip bonding are formed on the lower surfaces of the variable capacitance element 14 and the ESD protection elements 17A and 17B. On the substrate 30, mounting electrodes and wiring patterns for the variable capacitance element 14 and the ESD protection elements 17A and 17B are formed.

図８は第２の実施形態の可変容量素子モジュール９２の断面図である。このように、基板３０に可変容量素子１４およびＥＳＤ保護素子１７Ａ，１７Ｂがフリップチップボンディングされ、基板３０上の全面が封止樹脂４１で封止される。   FIG. 8 is a cross-sectional view of the variable capacitance element module 92 according to the second embodiment. Thus, the variable capacitance element 14 and the ESD protection elements 17A and 17B are flip-chip bonded to the substrate 30 and the entire surface of the substrate 30 is sealed with the sealing resin 41.

《第３の実施形態》
図９は第３の実施形態に係る可変容量素子モジュール９３の分解斜視図である。図９中の回路記号は回路と各端子との関係を概念的に表すものである。この第３の実施形態では、基板３０上に対する各素子の実装構造が第１・第２の実施形態とは異なる。基板３０上には、第１の基板側入出力端子ＥＰ１、第２の基板側入出力端子ＥＰ２、基板側制御電圧入力端子ＥＶｔ、基板側グランド端子ＥＧおよび配線パターンが形成されている。基板３０上には可変容量素子１４およびＥＳＤ保護素子１７Ａ，１７Ｂがダイボンディングされていて、これらの素子の端子と基板上の端子とがワイヤーボンディングされている。 << Third Embodiment >>
FIG. 9 is an exploded perspective view of the variable capacitance element module 93 according to the third embodiment. The circuit symbols in FIG. 9 conceptually represent the relationship between the circuit and each terminal. In the third embodiment, the mounting structure of each element on the substrate 30 is different from the first and second embodiments. On the substrate 30, a first substrate side input / output terminal EP1, a second substrate side input / output terminal EP2, a substrate side control voltage input terminal EVt, a substrate side ground terminal EG, and a wiring pattern are formed. On the substrate 30, the variable capacitance element 14 and the ESD protection elements 17A and 17B are die-bonded, and the terminals of these elements and the terminals on the substrate are wire-bonded.

この構造によれば、図５に示したワイヤーＷ１，Ｗ２のように、ワイヤーがクロスする箇所が生じないので、製造が容易となる。   According to this structure, unlike the wires W1 and W2 shown in FIG.

《第４の実施形態》
図１０は第４の実施形態に係る可変容量素子モジュール９４の分解斜視図である。図１０中の回路記号は回路と各端子との関係を概念的に表すものである。この第４の実施形態では、２つのＥＳＤ保護素子が単一のＥＳＤ保護チップ部品として構成されたものを用いている。基板３０上には、ＥＳＤ保護チップ部品１７および可変容量素子１４がダイボンディングされ、これらの素子の端子と基板上の端子とがワイヤーボンディングされている。 << Fourth Embodiment >>
FIG. 10 is an exploded perspective view of the variable capacitance element module 94 according to the fourth embodiment. The circuit symbols in FIG. 10 conceptually represent the relationship between the circuit and each terminal. In the fourth embodiment, two ESD protection elements configured as a single ESD protection chip component are used. On the substrate 30, the ESD protection chip component 17 and the variable capacitance element 14 are die-bonded, and the terminals of these elements and the terminals on the substrate are wire-bonded.

この構造によれば、基板上へ実装する素子数が少なく、モジュール全体を小型化できる。   According to this structure, the number of elements to be mounted on the substrate is small, and the entire module can be miniaturized.

《第５の実施形態》
図１１は、可変容量素子モジュールを備える通信回路の回路図である。この通信回路はＮＦＣモジュールの一例である。通信回路は、ＲＦＩＣ１１、アンテナコイル１３、および可変容量素子モジュール９１を備えている。図１１においてアンテナコイル１３は、放射素子として機能するものであり、通信相手側コイルアンテナと磁界結合する。 << Fifth Embodiment >>
FIG. 11 is a circuit diagram of a communication circuit including a variable capacitance element module. This communication circuit is an example of an NFC module. The communication circuit includes an RFIC 11, an antenna coil 13, and a variable capacitance element module 91. In FIG. 11, the antenna coil 13 functions as a radiating element, and is magnetically coupled to the communication counterpart coil antenna.

キャパシタＣ２１，Ｃ２２はＲＦＩＣ１１とアンテナコイル１３との結合度調整用の素子である。また、インダクタＬ１１，Ｌ１２およびキャパシタＣ１１，Ｃ１２，Ｃ２０は送信フィルタを構成している。例えば通信回路がカードモードで動作する場合、ＲＦＩＣ１１はパッシブ動作するので、ＲＸ端子への入力信号から電源電圧を生成するとともに受信信号を読み取り、送信時にはＴＸ端子に接続されている回路（負荷）を負荷変調する。また、例えば通信回路がリーダライタモードで動作する場合には、ＲＦＩＣ１１はアクティブ動作するので、送信時にＲＸ端子を開放してＴＸ端子から送信信号を送信し、受信時にはＴＸ端子を開放してＲＸ端子から受信信号を入力する。ＲＦＩＣ１１はＤＡコンバータ１２を介して可変容量素子モジュール９１へ制御電圧を与える。このように、通信回路は動作モードに応じて、ＲＦＩＣ１１からアンテナコイル１３側を見たインピーダンスが変化する。動作モードに応じてアンテナ回路の共振周波数が最適となるように、（ＲＦＩＣ１１からアンテナコイル側を見たインピーダンスが整合するように、）可変容量素子モジュール９１の容量値が制御される。   Capacitors C21 and C22 are elements for adjusting the degree of coupling between the RFIC 11 and the antenna coil 13. The inductors L11 and L12 and the capacitors C11, C12, and C20 constitute a transmission filter. For example, when the communication circuit operates in the card mode, the RFIC 11 operates passively. Therefore, the power supply voltage is generated from the input signal to the RX terminal, the received signal is read, and a circuit (load) connected to the TX terminal is transmitted during transmission. Modulate the load. For example, when the communication circuit operates in the reader / writer mode, the RFIC 11 operates in an active manner. Therefore, the RX terminal is opened at the time of transmission to transmit a transmission signal from the TX terminal, and the TX terminal is opened at the time of reception to receive the RX terminal. Input the received signal. The RFIC 11 supplies a control voltage to the variable capacitance element module 91 via the DA converter 12. As described above, the impedance of the communication circuit when the antenna coil 13 is viewed from the RFIC 11 changes according to the operation mode. The capacitance value of the variable capacitance element module 91 is controlled so that the resonance frequency of the antenna circuit is optimized in accordance with the operation mode (so that the impedance when the antenna coil side is viewed from the RFIC 11 is matched).

ＥＰ１…第１の基板側入出力端子
ＥＰ２…第２の基板側入出力端子
ＥＶｔ…基板側制御電圧入力端子
ＦＳ１，ＦＳ２，ＦＳ３…強誘電体膜
ＧＮＤ…グランド端子
Ｐ１…第１の入出力端子
Ｐ２…第２の入出力端子
ＰＴ１，ＰＴ２…キャパシタ電極
Ｒ１１〜Ｒ１９…ＲＦ抵抗素子
Ｖｔ…制御電圧入力端子
Ｗ１，Ｗ２…ワイヤー
１３…アンテナコイル
１４…可変容量素子
１７…ＥＳＤ保護チップ部品
１７Ａ，１７Ｂ…ＥＳＤ保護素子
３０…基板
４０…カバー
４１…封止樹脂
９１〜９４…可変容量素子モジュール EP1 ... first substrate side input / output terminal EP2 ... second substrate side input / output terminal EVt ... substrate side control voltage input terminals FS1, FS2, FS3 ... ferroelectric film GND ... ground terminal P1 ... first input / output terminal P2 ... second input / output terminals PT1, PT2 ... capacitor electrodes R11-R19 ... RF resistance element Vt ... control voltage input terminals W1, W2 ... wire 13 ... antenna coil 14 ... variable capacitance element 17 ... ESD protection chip components 17A, 17B ... ESD protection element 30 ... Substrate 40 ... Cover 41 ... Sealing resins 91 to 94 ... Variable capacitance element module

Claims (5)

可変容量素子、第１のＥＳＤ保護素子、第２のＥＳＤ保護素子、およびこれらが実装される共通の基板を備え、
前記可変容量素子は、電界によって誘電率が変化する強誘電体膜と、この強誘電体膜を挟んで電圧を印加するキャパシタ電極と、第１の入出力端子と、第２の入出力端子と、制御電圧入力端子と、グランド端子とを備え、
前記第１のＥＳＤ保護素子の第１端と前記第１の入出力端子とが接続され、前記第１のＥＳＤ保護素子の第２端と前記グランド端子とが接続され、
前記第２のＥＳＤ保護素子の第１端と前記第２の入出力端子とが接続され、前記第２のＥＳＤ保護素子の第２端と前記グランド端子とが接続されていることを特徴とする可変容量素子モジュール。 A variable capacitance element, a first ESD protection element, a second ESD protection element, and a common substrate on which these are mounted;
The variable capacitance element includes a ferroelectric film whose dielectric constant is changed by an electric field, a capacitor electrode for applying a voltage across the ferroelectric film, a first input / output terminal, and a second input / output terminal. A control voltage input terminal and a ground terminal,
A first end of the first ESD protection element is connected to the first input / output terminal; a second end of the first ESD protection element is connected to the ground terminal;
A first end of the second ESD protection element is connected to the second input / output terminal, and a second end of the second ESD protection element is connected to the ground terminal. Variable capacitance element module. 前記第１のＥＳＤ保護素子および前記第２のＥＳＤ保護素子は前記可変容量素子を介する対称位置に配置されている、請求項１に記載の可変容量素子モジュール。   The variable capacitance element module according to claim 1, wherein the first ESD protection element and the second ESD protection element are arranged at symmetrical positions via the variable capacitance element. 前記基板は前記可変容量素子を介して対向する第１辺および第２辺を有する直方体板状であり、第１辺に沿った位置に、前記可変容量素子の第１の入出力端子が接続される第１の基板側入出力端子、および前記可変容量素子の第２の入出力端子が接続される第２の基板側入出力端子が配置され、第２辺に沿った位置に、前記可変容量素子の制御電圧入力端子が接続される基板側制御電圧入力端子、および前記可変容量素子のグランド端子が接続される基板側グランド端子が配置され、
前記第１のＥＳＤ保護素子は前記第１の基板側入出力端子と前記基板側制御電圧入力端子との間に配置され、前記第２のＥＳＤ保護素子は前記第２の基板側入出力端子と前記基板側グランド端子との間に配置された、請求項２に記載の可変容量素子モジュール。 The substrate has a rectangular parallelepiped plate shape having a first side and a second side facing each other with the variable capacitance element interposed therebetween, and a first input / output terminal of the variable capacitance element is connected to a position along the first side. A first substrate side input / output terminal and a second substrate side input / output terminal to which the second input / output terminal of the variable capacitance element is connected are disposed, and the variable capacitor is disposed at a position along the second side. A substrate-side control voltage input terminal to which the control voltage input terminal of the element is connected, and a substrate-side ground terminal to which the ground terminal of the variable capacitance element is connected;
The first ESD protection element is disposed between the first substrate-side input / output terminal and the substrate-side control voltage input terminal, and the second ESD protection element is connected to the second substrate-side input / output terminal. The variable capacitance element module according to claim 2, which is disposed between the substrate-side ground terminal. 前記可変容量素子は、前記制御電圧入力端子と前記可変容量素子のキャパシタ電極との間に接続されたチョーク抵抗を備え、
前記可変容量素子は互いに対向する第１辺および第２辺を有する直方体板状であり、第１辺に沿って前記第１の入出力端子および前記第２の入出力端子が配置され、第２辺に沿って前記制御電圧入力端子および前記グランド端子が配置され、
前記可変容量素子は、その第１辺が前記基板の第１辺寄りで、且つ第２辺が前記基板の第２辺寄りとなるように前記基板に実装されている、請求項３に記載の可変容量素子モジュール。 The variable capacitance element includes a choke resistor connected between the control voltage input terminal and a capacitor electrode of the variable capacitance element,
The variable capacitance element has a rectangular parallelepiped plate shape having a first side and a second side facing each other, and the first input / output terminal and the second input / output terminal are arranged along the first side, The control voltage input terminal and the ground terminal are arranged along a side,
4. The variable capacitance element according to claim 3, wherein the variable capacitance element is mounted on the substrate such that the first side is closer to the first side of the substrate and the second side is closer to the second side of the substrate. Variable capacitance element module. 前記基板は前記可変容量素子を介して対向する第１辺および第２辺を有する直方体板状であり、第１辺に沿った位置に、前記可変容量素子の第１の入出力端子が接続される第１の基板側入出力端子、および前記可変容量素子の第２の入出力端子が接続される第２の基板側入出力端子が配置され、第２辺に沿った位置に、前記可変容量素子の制御電圧入力端子が接続される基板側制御電圧入力端子、および前記可変容量素子のグランド端子が接続される基板側グランド端子が配置され、
前記第１・第２のＥＳＤ保護素子は、単一のＥＳＤ保護チップ部品として構成されていて、
第１の基板側入出力端子と基板側グランド端子との間に前記ＥＳＤ保護チップ部品が配置された、請求項１に記載の可変容量素子モジュール。 The substrate has a rectangular parallelepiped plate shape having a first side and a second side facing each other with the variable capacitance element interposed therebetween, and a first input / output terminal of the variable capacitance element is connected to a position along the first side. A first substrate side input / output terminal and a second substrate side input / output terminal to which the second input / output terminal of the variable capacitance element is connected are disposed, and the variable capacitor is disposed at a position along the second side. A substrate-side control voltage input terminal to which the control voltage input terminal of the element is connected, and a substrate-side ground terminal to which the ground terminal of the variable capacitance element is connected;
The first and second ESD protection elements are configured as a single ESD protection chip component,
The variable capacitance element module according to claim 1, wherein the ESD protection chip component is disposed between a first substrate side input / output terminal and a substrate side ground terminal.
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