JP2014116048A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce influences of power source noise between clock buffers.SOLUTION: A semiconductor device comprises: clock wiring 41, 42 transmitting clock signals CK, CKB therethrough; clock buffers 51, 52 buffering the clock signals CK, CKB; power supply wiring V1, S1 supplying working voltage to the clock buffer 51; and power supply wiring V2, S2 supplying the working voltage to the clock buffer 52. The power supply wiring V1, V2 is branched at a branch point 31B located near a power terminal 31 while the power supply wiring S1, S2 is branched at a branch point 32B located near a power terminal 32. According to the invention, reduction in influences of power source noise between the clock buffers adjacent to each other causes each clock buffer to operate in designed conditions.

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a plurality of clock buffers for buffering clock signals.

  Many DRAMs (Dynamic Random Access Memory), which are typical semiconductor memory devices, have a center pad structure in which a pad electrode is located at the center of a semiconductor substrate. On the other hand, in a DRAM having a large number of pad electrodes, an edge pad structure in which pad electrodes are arranged along two opposing sides of a semiconductor substrate may be employed (see Patent Document 1).

  In a DRAM having an edge pad structure, it is necessary to transmit a clock signal input from one side of a semiconductor substrate to a peripheral circuit arranged in the vicinity of the other side. It will be long. For this reason, in order to ensure the signal quality of the clock signal on the clock wiring, a plurality of clock buffers for buffering the clock signal may be inserted on the clock wiring.

JP 2011-108352 A

  However, depending on the frequency of the clock signal, power supply noise caused by switching of one clock buffer may affect another clock buffer. When such a phenomenon occurs, a difference occurs in the transmission speed of the clock signal on the clock wiring depending on the frequency of the clock signal.

  According to another aspect of the present invention, there is provided a semiconductor device comprising: a clock wiring for transmitting a clock signal; first and second clock buffers for buffering the clock signal; and operating voltages for the first and second clock buffers. A power supply line to be supplied, and the first power supply line has a length longer than a length of a first wiring part connecting the first clock buffer and the second clock buffer in the clock line. The length of the second wiring portion connecting the clock buffer and the second clock buffer is longer.

  A semiconductor device according to another aspect of the present invention includes a first power supply terminal, a first power supply line connected to the first power supply terminal, and a second branch provided from the first power supply line. And a third power supply line, a first clock buffer having a power supply node connected to the second power supply line, a clock signal supplied to the input node, and an input node to the output node of the first clock buffer. And a second clock buffer having a power supply node connected to the third power supply wiring, and a branch point of the second and third power supply wirings is located in the vicinity of the first power supply wiring. It is characterized by that.

  A semiconductor device according to still another aspect of the present invention includes first and second power supply terminals to which the same potential is supplied, a first power supply line connected to the first power supply terminal, and the second power supply terminal. A second power supply wiring connected to the power supply terminal, a clock signal is supplied to the input node, a power supply node connected to the first power supply wiring, and an input node connected to the first clock A second clock buffer connected to an output node of the buffer and having a power supply node connected to the second power supply wiring, wherein the first power supply wiring and the second power supply wiring are arranged on a semiconductor substrate. It is characterized by being separated.

  According to the present invention, since power supply noise generated by switching of a certain clock buffer is hardly transmitted to adjacent clock buffers, each clock buffer can be operated under designed conditions. As a result, the transmission speed of the clock signal on the clock wiring can be made substantially constant regardless of the frequency of the clock signal.

1 is a schematic plan view showing a layout of a semiconductor device according to a preferred embodiment of the present invention. 1 is a schematic plan view for explaining a configuration of a semiconductor device according to a first embodiment of the present invention. 5 is a circuit diagram of clock buffers 51 to 54 according to the first embodiment. FIG. It is a typical top view for demonstrating the structure of the semiconductor device by the 1st prototype which the present inventors considered in the process leading to invention. It is a wave form diagram for demonstrating the relationship between a power supply noise and the output waveform of a clock buffer. It is a typical top view for demonstrating the structure of the semiconductor device by the 2nd prototype which the present inventors considered in the process leading to invention. It is a circuit diagram of the clock buffers 51-54 by a 2nd prototype. 6 is a graph showing a waveform of power supply noise in the second prototype, where (a) is a waveform of the ground voltage VSS appearing at the power supply node of the clock buffer 51, and (b) is a ground voltage VSS appearing at the power supply node of the clock buffer 52. It is a waveform. It is a graph which shows the relationship between the amount of delays of a clock buffer in a 2nd prototype, and a clock cycle. 5 is a graph showing a waveform of power supply noise in the first embodiment, where (a) is a waveform of the ground voltage VSS appearing at the power supply node of the clock buffer 51, and (b) is a ground voltage appearing at the power supply node of the clock buffer 52. It is a waveform of VSS. It is a graph which shows the relationship between the delay amount of a clock buffer and clock cycle in 1st Embodiment. It is a typical top view for demonstrating the structure of the semiconductor device by the 2nd Embodiment of this invention. It is a wave form diagram of clock signals CLK0-CLK3. It is a circuit diagram of the clock buffers 51-54 in 2nd Embodiment. It is a typical top view for demonstrating the structure of the semiconductor device by the 3rd Embodiment of this invention. It is a typical top view for demonstrating the structure of the semiconductor device by the 4th Embodiment of this invention. It is a typical top view for demonstrating the structure of the semiconductor device by the 5th Embodiment of this invention. It is a circuit diagram of the semiconductor device by the 6th Embodiment of this invention. FIG. 19 is a circuit diagram of a latch circuit LT using the buffer circuit BUF shown in FIG. 18. It is a typical top view for demonstrating the structure of the semiconductor device by the 7th Embodiment of this invention.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a schematic plan view showing a layout of a semiconductor device according to a preferred embodiment of the present invention.

  The semiconductor device according to the present embodiment is a DRAM, but the application target of the present invention is not limited to this. Therefore, the present invention can be applied to semiconductor memory devices other than DRAM, such as flash memory and ReRAM, and the present invention can also be applied to logic semiconductor devices such as CPUs.

  As shown in FIG. 1, the semiconductor device according to the present embodiment includes a semiconductor chip including a memory area MA in which four memory banks BK0 to BK3 are formed and peripheral circuit areas located on both sides in the Y direction of the memory area MA. It is configured.

  The peripheral circuit region includes a peripheral circuit region PSIDE including a pad area DQPAD disposed along the peripheral portion of the semiconductor chip, and is disposed along the peripheral portion of the semiconductor chip opposite to the peripheral circuit region PSIDE. And a peripheral circuit region FSIDE including. In many DRAMs, a pad area is provided at the center of the semiconductor chip. However, when the number of data input / output terminals is large, it is difficult to provide a pad area at the center of the semiconductor chip. In such a case, as shown in the drawing, a plurality of pad areas are provided on the peripheral edge of the semiconductor chip.

  In the pad area DQPAD, a data input / output terminal, a power supply terminal, and the like are arranged. In the peripheral circuit area PSIDE, an output buffer for outputting read data to the data input / output terminal, an input receiver for receiving write data supplied via the data input / output terminal, and the like are formed.

  On the other hand, an address terminal, a command terminal, a clock terminal, a power supply terminal, and the like are arranged in the pad area CAPAD. In the peripheral circuit area FSIDE, an input receiver that receives an address signal, a command signal, a clock signal, and the like supplied via these signal terminals, and a latch circuit that latches the address signal and the command signal in synchronization with the clock signal Etc. are formed.

  The memory area MA is disposed between the peripheral circuit area PSIDE and the peripheral circuit area FSIDE. The memory banks BK0 to BK3 formed in the memory area MA are arranged in order along the direction (Y direction) connecting the peripheral circuit area PSIDE and the peripheral circuit area FSIDE.

  Each of the memory banks BK0 to BK3 provided in the memory area MA includes a memory cell array area ARY, a row decoder XDEC provided adjacent to the memory cell array area ARY in the X direction (a direction orthogonal to the Y direction), A column decoder YDEC provided adjacent to the memory cell array region ARY in the Y direction, and a plurality of main amplifiers AMP provided adjacent to the column decoder region in the Y direction are provided.

  FIG. 2 is a schematic plan view for explaining the configuration of the semiconductor device according to the first embodiment of the present invention. In FIG. 2, the peripheral circuit areas PSIDE and FSIDE are shown in an enlarged manner, and the area of these peripheral circuit areas PSIDE and FSIDE is actually very small compared to the memory area MA.

  FIG. 2 illustrates several power terminals 11 to 16 included in the pad area DQPAD, and clock terminals 21 and 22 and several power terminals 31 to 36 included in the pad area CAPAD. The power supply terminals 11, 13, 15, 31, 33, and 35 are all terminals to which the power supply potential VDD is supplied, and the power supply terminals 12, 14, 16, 32, 34, and 36 are all supplied with the ground potential VSS. Terminal. The clock terminals 21 and 22 are terminals to which clock signals CK and CKB are supplied, respectively. The clock signals CK and CKB are complementary signals. Other external terminals such as data input / output terminals and address terminals are not shown.

  As shown in FIG. 2, clock lines 41 and 42 are connected to the clock terminals 21 and 22, respectively. The clock wirings 41 and 42 are connected to a plurality of clock circuits 70 arranged in the peripheral circuit area FSIDE, and are connected to the clock wirings 61 and 62 arranged in the peripheral circuit area PSIDE via a plurality of clock buffers 51 to 54. It is connected. Clock buffers 55 and 56 are also inserted in the clock wirings 61 and 62. The clock signals CK and CKB buffered by the clock buffers 55 and 56 are supplied to clock circuits 71 and 72, respectively.

  The clock circuit 70 is a circuit that uses the clock signals CK and CKB in the peripheral circuit region FSIDE. Since the clock circuit 70 is disposed in the peripheral circuit region FSIDE provided with the clock terminals 21 and 22, there is little need to buffer the clock signals CK and CKB supplied to the clock circuit 70. On the other hand, the clock circuits 71 and 72 are circuits that use the clock signals CK and CKB in the peripheral circuit region PSIDE, and are arranged in the peripheral circuit region PSIDE that is separated from the clock terminals 21 and 22. Therefore, the clock signals 71 and 72 are supplied with the clock signals CK and CKB buffered by the clock buffers 51 to 56.

  As shown in FIG. 2, the clock buffers 51 to 54 are connected to one of the power supply wirings V1 and V2 and one of the power supply wirings S1 and S2. The power supply lines V1 and V2 are both connected to the power supply terminals 11 and 31, and the power supply lines V1 and V2 at the branch point 11B located near the power supply terminal 11 and the branch point 31B located near the power supply terminal 31. Branch to Similarly, the power supply wires S1 and S2 are both connected to the power supply terminals 12 and 32, and the power supply wires at the branch point 12B located near the power supply terminal 12 and the branch point 32B located near the power supply terminal 32. Branches to S1 and S2. The vicinity of the power supply terminal needs to be closer to the power supply terminal than at least the corresponding clock buffer, but is preferably as close to the power supply terminal as possible.

  These power supply wirings V1, V2, S1, and S2 are dedicated wirings for the clock buffers 51 to 54, and are not connected to other circuits in this embodiment. For example, the circuit 80 arranged in the peripheral circuit region FSIDE is connected to the power supply wirings V0 and S0, and operates based on the power supply potential supplied through these power supply wirings V0 and S0. The power supply wiring V0 is connected to the power supply terminals 33 and 35, and is separated from the power supply wirings V1 and V2. Similarly, the power supply line S0 is connected to the power supply terminals 34 and 36, and is separated from the power supply lines S1 and S2. Therefore, power supply noise generated by the operation of the circuit 80 is not transmitted to the clock buffers 51 to 54 on the chip.

  On the other hand, the clock buffer 55 is connected to the power supply lines V4 and S4, and operates based on the power supply potential supplied via these power supply lines V4 and S4. The power supply wirings V4 and S4 are connected to power supply terminals 13 and 14, respectively. Similarly, the clock buffer 56 is connected to the power supply lines V5 and S5, and operates based on the power supply potential supplied via these power supply lines V5 and S5. The power supply wirings V5 and S5 are connected to power supply terminals 15 and 16, respectively. The power supply terminals 13 to 16 are also connected to other circuits (not shown) arranged in the peripheral circuit region PSIDE, but all of the branch points 13B to 16B to the power supply wirings V4, V5, S4 and S5 are provided. Since it is located in the vicinity of ˜16, the influence of the power supply noise generated by the operation of the other circuit on the clock buffers 55 and 56 is minimized.

  As shown in FIG. 2, the clock buffers 51 and 53 are connected to the power supply lines V1 and S1, and the clock buffers 52 and 54 are connected to the power supply lines V2 and S2. That is, the clock buffers 51 to 54 connected in series in this order are alternately connected to the power supply wirings V1 and S1 and the power supply wirings V2 and S2.

  FIG. 3 is a circuit diagram of the clock buffers 51-54.

  As shown in FIG. 3, each of the clock buffers 51 to 54 includes two inverter circuits INV. One inverter circuit is a circuit that buffers the clock signal CK, and the other inverter circuit is a circuit that buffers the clock signal CKB. Output nodes 51oA and 51oB of the first-stage clock buffer 51 are connected to input nodes 52iA and 52iB of the next-stage clock buffer 52, and output nodes 52oA and 52oB of the clock buffer 52 are input nodes 53iA and 53iB of the next-stage clock buffer 53. The output nodes 53oA and 53oB of the clock buffer 53 are connected to the input nodes 54iA and 54iB of the clock buffer 54 at the next stage.

  The power supply nodes of the clock buffers 51 and 53, that is, the source of the P-channel MOS transistor and the source of the N-channel MOS transistor are connected to the power supply lines V1 and S1, respectively. The source of the P-channel MOS transistor and the source of the N-channel MOS transistor are connected to the power supply lines V2 and S2, respectively. With this configuration, power supply noise caused by switching of a certain clock buffer is not directly transmitted to the adjacent clock buffer. For example, the power supply noise generated by the clock buffer 52 is not directly transmitted to the preceding-stage clock buffer 51 or the next-stage clock buffer 53 as indicated by arrows Nv and Ns.

  On the other hand, between the clock buffers that are not adjacent, for example, between the clock buffer 51 and the clock buffer 53, there is an influence of power supply noise. However, since there is a certain distance between clock buffers that are not adjacent to each other, when power supply noise generated by the operation of a certain clock buffer (for example, clock buffer 51) reaches another clock buffer (for example, clock buffer 53). The power supply noise is attenuated to some extent, or the power supply noise arrives at a timing different from the operation timing of other clock buffers (for example, the clock buffer 53). For this reason, there is little influence of power supply noise between clock buffers that are not adjacent to each other.

  On the other hand, power noise can be transmitted between adjacent clock buffers via the branch points 11B, 12B, 31B, and 32B of the power supply wiring, but the power supply path via the branch points 11B, 12B, 31B, and 32B is extremely However, it has almost no effect. That is, when power supply noise generated by the operation of a certain clock buffer (for example, clock buffer 51) reaches another clock buffer (for example, clock buffer 52) via branch points (for example, branch points 31B and 32B), The noise is almost attenuated. For this reason, there is almost no influence of power supply noise between adjacent clock buffers.

In order to obtain such an effect, it is preferable to design the length of the power supply wiring connecting the adjacent clock buffers to be longer than the length of the clock wiring connecting the adjacent clock buffers. That is, the length of the clock wiring connecting a certain clock buffer (for example, the clock buffer 51) and the adjacent clock buffer (for example, the clock buffer 52) is L0, and the power supply node of the certain clock buffer (for example, the clock buffer 51) When the distance between the branch points 31B and 32B is L1, and the distance between the power supply node of another clock buffer (for example, the clock buffer 52) and the branch points 31B and 32B is L2,
L0 <L1 + L2 (Condition A)
To design.

In particular,
L0 <L1 or L0 <L2 (Condition B)
It is more preferable to design
L0 <L1 and L0 <L2 (Condition C)
It is even more preferable to design it.
In the present embodiment, the conditions A and B are satisfied between all the clock buffers, and the condition C is satisfied between the clock buffers 52 and 53.

  In the present invention, the length L0 may be referred to as “the length of the first wiring portion”, and L1 + L2 may be referred to as “the length of the second wiring portion”. In addition, a section from a certain power supply terminal (for example, power supply terminal 31) to a corresponding branch point (for example, branch point 31B) is referred to as “first section” or “sixth section”, and one of two adjacent clock buffers (for example, The section between the power supply node of the clock buffer 51) and the branch point 31B is the “second section” or “seventh section”, and the power supply node of the other of the two adjacent clock buffers (for example, the clock buffer 52) and the branch A section with the point 31B may be referred to as a “third section” or an “eighth section”. Further, the power supply nodes of two clock buffers (for example, clock buffers 51 and 53) connected to the same power supply wiring may be referred to as “fourth section” or “fifth section”.

  With the configuration described above, the interference of the power supply noise between the clock buffers is greatly suppressed. Therefore, the clock signals CK and CKB can be transmitted over a long distance while maintaining the signal quality of the clock signals CK and CKB. Is possible.

  FIG. 4 is a schematic plan view for explaining the configuration of the semiconductor device according to the first prototype that the inventors have considered in the process leading to the invention.

  In the semiconductor device shown in FIG. 4, the power supply lines V1, V2, S1, and S2 for the clock buffers 51 to 54 are deleted, and the clock buffers 51 to 56 are connected to the power supply lines V0 and S0 that are shared with the circuit 80. . In the case of such a configuration, there is a possibility that power supply noise generated with the operation of the circuit 80 is transmitted to the clock buffers 51 to 56 through the power supply wirings V0 and S0.

  For example, if the output waveforms of the clock buffers 51 to 54 when the power supply noise is not generated as shown in FIG. 5A are represented by the waveform A, the VDD is caused by the power supply noise as shown in FIG. When the voltage between −VSS increases momentarily, the drive capability of the clock buffers 51 to 54 increases, and the output waveform changes to the waveform B. The waveform B is steeper than the waveform A, and therefore the transmission speed of the clock signals CK and CKB is faster than the design value. Conversely, as shown in FIG. 5C, when the voltage between VDD and VSS is momentarily reduced due to power supply noise, the drive capability of the clock buffers 51 to 54 is reduced, and the output waveform changes to the waveform C. It will change. The waveform C is gentler than the waveform A, and therefore the transmission speed of the clock signals CK and CKB is slower than the design value.

  Thus, when the power supply voltage supplied to the clock buffers 51 to 54 fluctuates due to noise, the transmission speed of the clock signals CK and CKB deviates from the design value. In this case, the operation margin of various circuits (for example, the clock circuits 71 and 72) using the clock signals CK and CKB as timing signals is lowered, and there is a possibility that malfunction may occur in some cases.

  FIG. 6 is a schematic plan view for explaining the configuration of the semiconductor device according to the second prototype considered by the inventors in the course of reaching the invention.

  In the semiconductor device shown in FIG. 6, unlike the semiconductor device shown in FIG. 4, dedicated power supply wirings V <b> 1 and S <b> 1 are assigned to the clock buffers 51 to 54. Therefore, power supply noise generated by the operation of other circuits is not transmitted to the clock buffers 51 to 54 via the power supply lines V1 and S1. However, in the semiconductor device shown in FIG. 6, unlike the semiconductor device according to the present embodiment shown in FIG. 2, the same power supply wirings V1 and S1 are used for the clock buffers 51 to 54, respectively. For this reason, as shown in FIG. 7, for example, power supply noises Nv and Ns generated by switching of the clock buffer 51 are transmitted to the clock buffer 52 at the next stage, and the output waveform of the clock buffer 52 may deviate from the design value. .

  FIG. 8 is a graph showing the waveform of the power supply noise in the second prototype, where (a) shows the waveform of the ground voltage VSS appearing at the power supply node of the clock buffer 51, and (b) appears at the power supply node of the clock buffer 52. It is a waveform of the ground voltage VSS.

  As shown in FIG. 8, the ground voltage VSS appearing at the power supply node of the clock buffer 51 and the ground voltage VSS appearing at the power supply node of the clock buffer 52 have noise components having different phases. The reason why such a phase difference occurs is that the clock signals CK and CKB are transmitted in the order of the clock buffers 51 to 54, so that the generation timing of the power supply noise is different for each of the clock buffers 51 to 54.

  In FIG. 8, a broken line indicates a voltage waveform when the period of the clock signals CK and CKB is 4 ns (250 MHz), and a solid line indicates that the period of the clock signals CK and CKB is 1 ns (1 GHz). ) Is a voltage waveform (the same applies to FIG. 10 described later). Here, as shown by broken lines, when the period of the clock signals CK and CKB is long (when the frequency is low), the generated power noise is substantially attenuated in one clock cycle, so that the power noise and the clock signals CK and CKB There is not much interference. On the other hand, when the period of the clock signals CK and CKB is short (when the frequency is high) as shown by the solid line, the next clock edge arrives before the generated power supply noise is attenuated. The signals CK and CKB interfere with each other. As a result, the peak of the power supply noise becomes larger, and a difference of ΔV occurs as compared with the case where the period of the clock signals CK and CKB is 4 ns.

  FIG. 9 is a graph showing the relationship between the delay amount of the clock buffer and the clock cycle in the second prototype.

  As shown in FIG. 9, in the second prototype, it can be seen that the shorter the period of the clock signals CK and CKB (the higher the frequency), the greater the delay amount of the clock buffer. As described above, in the second prototype, the delay amount of the clock buffer varies depending on the frequencies of the clock signals CK and CKB, so that it is difficult to design the clock signals CK and CKB so that a plurality of frequencies can be used.

  FIG. 10 is a graph showing the waveform of the power supply noise in this embodiment, where (a) shows the waveform of the ground voltage VSS appearing at the power supply node of the clock buffer 51, and (b) shows the ground appearing at the power supply node of the clock buffer 52. It is a waveform of the voltage VSS.

  As shown in FIG. 10, also in this embodiment, the ground voltage VSS appearing at the power supply node of the clock buffer 51 and the ground voltage VSS appearing at the power supply node of the clock buffer 52 have noise components having different phases. . However, in this embodiment, the peak of the power supply noise when the cycle of the clock signals CK and CKB is 4 ns (250 MHz) and the peak of the power supply noise when the cycle of the clock signals CK and CKB is 1 ns (1 GHz). Almost matches. This is because the power supply wiring is not shared between the adjacent clock buffers, and therefore interference between the power supply noise and the clock signals CK and CKB does not occur between the adjacent clock buffers.

  FIG. 11 is a graph showing the relationship between the delay amount of the clock buffer and the clock cycle in this embodiment.

  As shown in FIG. 11, in the semiconductor device according to the present embodiment, the delay amount of the clock buffer is substantially constant regardless of the period of the clock signals CK and CKB. Therefore, even when a plurality of types of clock signals CK and CKB can be used, the design does not become difficult. In FIG. 11, when the number of transfers of the clock signals CK and CKB is small (1 to 4 times), the amount of delay of the clock buffer differs depending on the frequency of the clock signals CK and CKB. Since the stable clock signals CK and CKB after the signal is transferred are used, there is no problem.

  As described above, since the semiconductor device according to the present embodiment separates the power supply wiring between the adjacent clock buffers, the influence of the power supply noise between the adjacent clock buffers can be prevented. This makes it possible to achieve a substantially constant transfer rate regardless of the frequency of the clock signals CK and CKB to be used.

  Next, a second embodiment of the present invention will be described.

  FIG. 12 is a schematic plan view for explaining the configuration of the semiconductor device according to the second embodiment of the present invention.

  The semiconductor device shown in FIG. 12 is different from the first embodiment in that a frequency dividing circuit 91 is connected in front of the clock buffer 51 and a frequency multiplier 92 is connected in front of the clock buffer 54. As shown in FIG. 13, the frequency divider 91 is a circuit that generates four-phase clock signals CLK0 to CLK3 based on the clock signals CK and CKB. The rising edges of the clock signals CLK0 to CLK3 are clock signals CK and CLK3, respectively. Synchronize with different rising or falling edges of CKB. As a result, the phases of the clock signals CLK0 to CLK3 are different from each other, and the frequency thereof is half that of the clock signals CK and CKB. The multiplier circuit 92 is a circuit for regenerating the clock signals CK and CKB based on the four-phase clock signals CLK0 to CLK3. The clock signals CK and CKB reproduced by the multiplication circuit 92 are supplied to the data input / output circuits 57 and 58. The data input / output circuits 57 and 58 are circuits that output data read from the memory area to the data terminals 17 and 18 in synchronization with the clock signals CK and CKB, respectively.

  FIG. 14 is a circuit diagram of the clock buffers 51 to 54 in the second embodiment.

  As shown in FIG. 14, in this embodiment, each of the clock buffers 51 to 54 is configured by four inverter circuits INV. The power supply nodes of the inverter circuits constituting the clock buffers 51 and 53 are connected to the power supply wirings V1 and S1, and the power supply nodes of the inverter circuits constituting the clock buffers 52 and 54 are connected to the power supply wirings V2 and S2. Yes. With this configuration, similarly to the first embodiment, it is possible to prevent the influence of power supply noise between adjacent clock buffers. In addition, in the present embodiment, the frequency of the clock signals CLK0 to CLK3 transmitted on the clock wiring having a long distance connecting the peripheral circuit region FSIDE and the peripheral circuit region PSIDE is reduced, so that the first embodiment It is also possible to reduce current consumption compared to the above.

  Next, a third embodiment of the present invention will be described.

  FIG. 15 is a schematic plan view for explaining the configuration of the semiconductor device according to the third embodiment of the present invention.

  As shown in FIG. 15, the semiconductor device according to the present embodiment includes nine clock buffers 101 to 109 connected in series, and clock buffers 110 and 111 connected in parallel at the subsequent stage of the clock buffer 109. Three power supply lines V1 to V3 are branched from the branch points 11B and 31B, and three power supply lines S1 to S3 are branched from the branch points 12B and 32B. The power supply nodes of the clock buffers 101, 104, 107 are connected to the power supply wirings V1, S1, and the power supply nodes of the clock buffers 102, 105, 108 are connected to the power supply wirings V2, S2, and the clock buffers 103, 106, The 109 power supply nodes are connected to the power supply wirings V3 and S3.

  In this embodiment, the number of clock buffers is large, and therefore the distance between adjacent clock buffers is shorter than in the first and second embodiments. However, in this embodiment, since three types of power supply wirings V1 to V3 and S1 to S3 are used, the influence of power supply noise not only between adjacent clock buffers but also between two adjacent clock buffers is prevented. The In the present embodiment, since the same power supply wiring is used between three adjacent clock buffers, power supply noise can affect each other, but the distance between the three adjacent clock buffers is sufficiently large. The transmitted power noise is greatly attenuated. As a result, even when the distance between adjacent clock buffers is short, the same effect as in the first and second embodiments can be obtained.

  Next, a fourth embodiment of the present invention will be described.

  FIG. 16 is a schematic plan view for explaining the configuration of the semiconductor device according to the fourth embodiment of the present invention.

  As shown in FIG. 16, in the semiconductor device according to the present embodiment, the power supply node of the clock buffer 51 is connected to the power supply wirings V1 and S1, and the power supply node of the clock buffer 52 is connected to the power supply wirings V2 and S2. 53 power supply nodes are connected to the power supply wirings V11 and S11, and the power supply node of the clock buffer 54 is connected to the power supply wirings V12 and S12. Similarly to the first embodiment, the power supply wirings V1 and V2 are both connected to the power supply terminal 31 and branch at the branch point 31B, and the power supply wirings S1 and S2 are both connected to the power supply terminal 32 and the branch point 32B. Wiring branches at On the other hand, the power supply lines V11 and V12 are both connected to the power supply terminal 11 and branched at the branch point 11B, and the power supply lines S11 and S12 are both connected to the power supply terminal 12 and branched at the branch point 12B. is there.

  In the present embodiment, the power supply wirings V1, V2 and the power supply wirings V11, V12 are separated on the chip. Similarly, the power supply lines S1, S2 and the power supply lines S11, S12 are separated on the chip. As a result, the power supply noise generated in the clock buffers 51 and 52 hardly affects the clock buffers 53 and 54. The reverse is also true. As a result, the influence of power supply noise generated in a certain clock buffer on other clock buffers is further reduced. In addition, since the length required for the power supply wiring is also shortened, there is a margin in the wiring layout in the wiring layer.

  Since the power supply terminals 11 and 31 are terminals to which the same power supply potential VDD is supplied, both are short-circuited on the package or module substrate on which the semiconductor device is mounted. The same applies to the power supply terminals 12 and 32. However, the route through the package and the module substrate has a very long wiring distance and a large parasitic capacitance. Therefore, transmission of power supply noise through such a route can be almost ignored.

  Next, a fifth embodiment of the present invention will be described.

  FIG. 17 is a schematic plan view for explaining the configuration of the semiconductor device according to the fifth embodiment of the present invention.

  As shown in FIG. 17, in the semiconductor device according to the present embodiment, several clock circuits 73 are connected to the power supply wirings V1, V2, S1, and S2. Like the clock circuit 70, the clock circuit 73 is a circuit that uses the clock signals CK and CKB, but is a circuit that is unlikely to be a source of power supply noise. As described above, a circuit that is unlikely to be a source of power supply noise may be connected to the power supply wirings V1, V2, S1, and S2. An example of a circuit that is unlikely to be a source of power supply noise is a circuit that does not have a transistor with high driving capability.

  Next, a sixth embodiment of the present invention will be described.

  FIG. 18 is a circuit diagram of a semiconductor device according to the sixth embodiment of the present invention.

  In the first to fifth embodiments already described, the clock buffer inserted in the long-distance clock wiring is targeted. However, as shown in FIG. 18, two-stage inverter circuits INV1 and INV2 are connected in series. The present invention can also be applied to a simple buffer circuit BUF. In the buffer circuit BUF shown in FIG. 18, the power supply node of the first-stage inverter circuit INV1 is connected to the power supply wirings V1 and S1, and the power supply node of the next-stage inverter circuit INV2 is connected to the power supply wirings V2 and S2. As a result, the power supply noise of the first-stage inverter circuit INV1 and the next-stage inverter circuit INV2 does not affect each other, so that the clock signal CK can be buffered while maintaining high signal quality.

  FIG. 19 is a circuit diagram of a latch circuit LT using the buffer circuit BUF shown in FIG.

  The latch circuit LT shown in FIG. 19 has a configuration in which two inverter circuits INV3 and INV4 are circularly connected, and a transfer gate is provided between a terminal to which an input signal IN is supplied and an input node of the inverter circuit INV3. TG1 is connected, and a transfer gate TG2 is connected between the output node of the inverter circuit INV4 and the input node of the inverter circuit INV3. The transfer gates TG1 and TG2 are circuits that conduct exclusively in synchronization with the clock signal CK. With this configuration, the input signal IN is latched in synchronization with the clock signal CK, and the latched signal is output as the output signal OUT. .

  The operations of the transfer gates TG1 and TG2 are controlled by the buffer circuit BUF. Thus, the present invention can also be applied to the buffer circuit BUF for generating a complementary clock signal used for the latch circuit LT.

  Next, a seventh embodiment of the present invention will be described.

  FIG. 20 is a schematic plan view for explaining the configuration of the semiconductor device according to the seventh embodiment of the present invention.

  The semiconductor device illustrated in FIG. 20 is an ASIC (Application Specific Integrated Circuit) and includes a plurality of functional blocks 121 to 125. Each of the functional blocks 121 to 125 is a circuit that realizes different functions, and the operation is performed in synchronization with the clock signals CK and CKB supplied to the chip. As shown in FIG. 20, each of the functional blocks 121 to 125 includes clock buffers 131 to 135, respectively. Here, the wiring distance of the clock wiring connecting the clock buffer 134 and the clock buffer 135 is relatively short, and there is a possibility that power supply noise may affect between the clock buffers. In such a case, if the power supply wirings V21 and S21 for the clock buffer 134 and the power supply wirings V22 and S22 for the clock buffer 135 are branched in the vicinity of the power supply terminals 37 and 38, the influence of the power supply noise between them. Can be prevented.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

11-16, 31-38 Power supply terminals 17, 18 Data terminals 13B-16B, 31B, 32B Branch points 21, 22 Clock terminals 41, 42, 61, 62 Clock wiring 51-56, 101-111, 131-135 Clock buffer 57, 58 Data input / output circuit 70-73 Clock circuit 80 Circuit 91 Frequency dividing circuit 92 Multiplication circuit 121-125 Function block BUF Buffer circuit CAPAD, DQPAD Pad area FSIDE, PSIDE Peripheral circuit area INV, INV1-INV4 Inverter circuit LT Latch circuit MA memory area S0 to S5, S11, S12, V0 to V53, V11, V12 Power supply wiring TG1, TG2 Transfer gate

Claims (15)

A clock wiring for transmitting the clock signal;
First and second clock buffers for buffering the clock signal;
Power supply wiring for supplying an operating voltage to the first and second clock buffers,
The first clock buffer and the second clock buffer in the power supply wiring are longer than the length of the first wiring portion connecting the first clock buffer and the second clock buffer in the clock wiring. A semiconductor device characterized in that the length of the second wiring portion connecting the two is longer. The power supply wiring includes a first section connecting a power supply terminal to which the operating voltage is supplied from the outside and a branch point, and a second section connecting the branch point and a power supply node of the first clock buffer. And a third section connecting the branch point and the power supply node of the second clock buffer,
2. The semiconductor device according to claim 1, wherein the length of at least one of the second and third sections is longer than the length of the first wiring portion.   3. The semiconductor device according to claim 2, wherein the lengths of the second and third sections are both longer than the length of the first wiring portion.   4. The semiconductor device according to claim 2, wherein the branch point is disposed at a position closer to the power supply terminal than the first and second clock buffers. 5.   5. The semiconductor device according to claim 2, wherein the first and second clock buffers are inserted in series with the clock wiring. 6. A third clock buffer for buffering the clock signal;
An output node of the first clock buffer is connected to an input node of the second clock buffer;
An output node of the second clock buffer is connected to an input node of the third clock buffer;
The power supply wiring is a section different from the first to third sections, and further includes a fourth section connecting the power supply node of the first clock buffer and the power supply node of the third clock buffer. 6. The semiconductor device according to claim 5, further comprising: A fourth clock buffer for buffering the clock signal;
An output node of the third clock buffer is connected to an input node of the fourth clock buffer;
The power supply wiring is a section different from the first to fourth sections, and further includes a fifth section connecting the power supply node of the second clock buffer and the power supply node of the fourth clock buffer. The semiconductor device according to claim 6, further comprising:   The power supply wiring includes: a sixth section connecting another power supply terminal to which the operating voltage is supplied from the outside and another branch point; and another branch point and a power supply node of the third clock buffer. 8. The semiconductor device according to claim 7, further comprising a seventh section to be connected and an eighth section for connecting the another branch point and a power supply node of the fourth clock buffer.   The power supply terminal is disposed along a first side of the semiconductor substrate, and the another power supply terminal is disposed along a second side different from the first side of the semiconductor substrate. The semiconductor device according to claim 8, characterized in that: A first power terminal;
A first power supply line connected to the first power supply terminal;
Second and third power supply wirings branched from the first power supply wiring;
A first clock buffer in which a clock signal is supplied to an input node and a power supply node is connected to the second power supply wiring;
A second clock buffer having an input node connected to the output node of the first clock buffer and a power supply node connected to the third power supply wiring;
A branching point of the second and third power supply wirings is located in the vicinity of the first power supply wiring. A second power terminal;
A fourth power supply line connected to the second power supply terminal, and
11. The semiconductor device according to claim 10, wherein the second and third power supply wirings are connected to the fourth power supply wiring in the vicinity of the second power supply wiring. A second power terminal;
A fourth power supply line connected to the second power supply terminal;
Fifth and sixth power supply lines provided by branching from the second power supply line;
A third clock buffer in which a clock signal output from the second clock buffer is supplied to an input node, and a power supply node is connected to the fifth power supply wiring;
A fourth clock buffer having an input node connected to an output node of the third clock buffer and a power supply node connected to the sixth power supply wiring;
A branch point of the fifth and sixth power supply wirings is located in the vicinity of the second power supply wiring,
The semiconductor device according to claim 10, wherein the first to third power supply wirings and the fourth to sixth power supply wirings are separated on a semiconductor substrate.   The first power supply terminal is disposed along a first side of the semiconductor substrate, and the second power supply terminal is disposed along a second side different from the first side of the semiconductor substrate. The semiconductor device according to claim 11, wherein the semiconductor device is provided. First and second power supply terminals to which the same potential is supplied;
A first power supply line connected to the first power supply terminal;
A second power supply line connected to the second power supply terminal;
A first clock buffer in which a clock signal is supplied to an input node and a power supply node is connected to the first power supply wiring;
A second clock buffer having an input node connected to the output node of the first clock buffer and a power supply node connected to the second power supply wiring;
The semiconductor device, wherein the first power supply wiring and the second power supply wiring are separated on a semiconductor substrate.   The first power supply terminal is disposed along a first side of the semiconductor substrate, and the second power supply terminal is disposed along a second side different from the first side of the semiconductor substrate. 15. The semiconductor device according to claim 14, wherein:

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