JP6413882B2 - Convoy progression type storage device and computer system - Google Patents

Description

  The present invention relates to a formation progression storage device and a computer system.

As a semiconductor memory device, in a memory cell in which memory cells are arranged in a matrix in columns and rows, data supplied in parallel in synchronization with the clock to the memory cells arranged in the column direction is synchronized with the clock. In addition, there is a formation progression type storage device that performs the readout operation by making the formation advance in parallel in the row direction (for example, Patent Document 1).
In this Patent Document 1, a row progression storage device inputs a group of data supplied in parallel from the output terminals of storage cells arranged in the column direction in synchronization with the clock to an arithmetic logic operation circuit, and performs arithmetic logic operation. A computer system that performs sequential logical operations in synchronization with a clock using data input to a circuit is described.

With the above configuration, the data stored in the memory cells of the column progression type storage device are arranged in the row direction in parallel in synchronization with the clock signal, and are actively output sequentially from the output terminal to the arithmetic logic circuit as a data group. Is done. Then, the arithmetic logic unit can execute the arithmetic logic operation by the data group sequentially supplied.
As a result, by using the formation progression type storage device, the computer system can supply the data group to the arithmetic logic operation circuit in synchronization with the clock for performing the arithmetic processing of the arithmetic logic operation circuit. This can be shortened compared to the time required for memory access. The computer system as described above can speed up the arithmetic processing of the logical operation circuit corresponding to the shortened memory access.

Further, when the data group includes instructions, the flow of instructions supplied to the processor which is a logical operation circuit is defined in one direction in the formation signal type storage device that stores the instructions. On the other hand, in the case of data included in a data group, in the formation signal type storage device that stores data, the data flow in both directions of supplying data to the processor and outputting the processing result from the processor. Is defined.
With the above configuration, since the instruction and the data are supplied in parallel in synchronization with the driving clock of the processor, the computer system can speed up the calculation and the transfer of the data of the calculation result in the processor.

Special table 2012-533784 gazette

  However, in the row progression storage device of Patent Document 1, when data is advanced in the row direction in synchronization with the clock in the memory cells arranged in the row direction, the clock is simultaneously applied to the memory cells arranged in the row direction. As a result, a problem of data penetration occurs between memory cells. For example, when data is written from the memory cell in the previous column to the memory cell in the subsequent column, the data in the memory cell in the previous column is written in the memory cell in the previous column, and the data in the memory cell in the previous column is written in the memory cell in the subsequent column. It will change in the middle. As a result, the data in the memory cells in the rear row may be rewritten, and the data in the formation may change.

In order to solve the above-described problem, the above computer system needs to write the data in the memory cell in the previous column to the memory cell in the previous column after writing the data in the memory cell in the previous column in the memory cell in the subsequent column. .
Therefore, the computer system described above delays the clock supplied to the control terminal of the subsequent-stage storage cell with respect to the clock supplied to the control terminal of the subsequent-stage storage cell. It is necessary to insert a delay element with respect to a clock signal line for supplying a clock between the control terminal of the memory cell.
However, when a delay element is inserted in the clock signal line, an area for forming a delay element that satisfies the delay time is required, which may increase the area of the storage device formation region.

  The row progression storage device according to an embodiment of the present invention includes a plurality of storage units each including a terminal portion including a data input terminal, the data output terminal, and a control terminal to which a pulse signal for controlling reading of the data is input. A plurality of column storage blocks in which cells are arranged in the column direction among rows and columns; and the column storage block in which the cells are arranged in the row direction among the plurality of column storage blocks. A data line connecting the output terminal of the memory cell of the block and the input terminal of the memory cell of the column storage block in the back column for each row of the memory cell; and the column storage block of the back column Sequentially connecting the control terminal of the first memory cell at one end in the column direction to the control terminal of the second memory cell at the other end in the column direction among the plurality of memory cells; Of the control terminals of the second memory cells and the memory cells included in the column memory block of the previous column, the third memory cells arranged in the same row as the row in which the first memory cells are arranged And a pulse signal line connecting the control terminal.

  A computer system according to an embodiment of the present invention includes a pulse generation circuit that generates a pulse signal, an arithmetic logic circuit that performs an arithmetic operation corresponding to the pulse signal, a data input terminal, the data output terminal, A plurality of storage cells each including a terminal portion including a control terminal to which the pulse signal for controlling reading of the data is input, a plurality of column storage blocks arranged in the column direction among rows and columns; In the column storage block arranged in the row direction among the plurality of column storage blocks, the output terminal of the storage cell of the column storage block and the input of the storage cell of the column storage block in the subsequent column A data line that connects a terminal to each row of the memory cells; and a plurality of memory cells of the column memory block in the rear column, of the one end in the column direction. The control terminal of the memory cell is sequentially connected to the control terminal of the second memory cell at the other end in the column direction, and is included in the control terminal of the second memory cell and the column memory block of the previous column. A row progression type storage device comprising: a pulse signal line connecting the control terminal of a third memory cell arranged in the same row as the row where the first memory cell is arranged among the memory cells. And the output terminal of the memory cell in the column storage block of the last column is connected to the arithmetic logic circuit, and one input terminal of the memory cell in the column storage block of the first column is A set of data groups is input, and in synchronization with the pulse signal, the data advances in a row between the memory cells in the row direction, and the data groups that have been advanced in a row are output in parallel to the arithmetic logic circuit. Shi It said arithmetic logic circuit, and executes the arithmetic logic operation using the data input in synchronism with the pulse signal from the convoy progressive storage device.

It is a block diagram which shows the structural example of the formation progression type | mold storage apparatus 1 by the 1st Embodiment of this invention. It is a figure which shows an example of the structure which formed the memory cell M in the row progression type | mold storage apparatus 1 by 1st Embodiment by D latch. FIG. 3 is a diagram illustrating a structure example of a switch transistor Trn in FIG. 2. It is a block diagram which shows the structural example of 1 A of formation progression type | mold storage apparatuses by the 2nd Embodiment of this invention. It is a figure which shows an example of the structure which formed the memory cell MA in the row progression type | formula memory | storage device 1A by 2nd Embodiment by D latch. It is a figure which shows the layout pattern of switch transistor Trn0 in the memory cell MA which concerns on this embodiment, and the transistor which comprises the inverter CINV1 and the inverter CINV2. It is a block diagram which shows the structural example of the formation progress type | mold storage apparatus 1B by the 3rd Embodiment of this invention. It is a figure which shows the structural example of the computer system 100 using the formation progress type | mold storage apparatus by embodiment of this invention.

<First Embodiment>
A first embodiment of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram showing a configuration example of a convoy progression type storage device 1 according to the first embodiment of the present invention. The row progression storage device 1 receives a data input terminal D, a data output terminal Q, a control terminal C to which a pulse signal P for controlling reading of data is input, and an inverted pulse signal PB which is an inverted signal of the pulse signal. The memory cells M _nm (n ≧ 2, m ≧ 2) including the control terminal CB are arranged in a matrix. For example, as shown in FIG. 1, a plurality of memory cells M are arranged in two dimensions (two directions) in n columns and m rows.
In the row progression type storage device 1, each of the memory cells M _{n, k} arranged in a matrix is divided into column units, and is divided into _n blocks from the column storage block BM ₁ to the column storage block BM _n. (1 ≦ j ≦ n, 1 ≦ k ≦ m). Each of the column storage blocks BM _j includes the storage cells M _{j, 1} to M _{j, m} arranged in the column direction, and includes m storage cells M _{n, k} in the row direction. The row progression storage device 1 is formed by arranging. In FIG. 1, the column direction is the y direction, the row direction is the x direction, and the data advances in a row in the x direction (for example, a predetermined direction).

Further, the row progression storage device 1 has an input terminal TI ₁ to an input terminal TI _m for inputting data from other devices, and an output for outputting the m rows of data in parallel to the other devices. and an output terminal tO _m from the terminal tO ₁ are provided.
The platoon progression storage device 1 is provided with a pulse signal input terminal TP to which a pulse signal P for controlling writing of data input to the input terminal D is supplied to the control terminal C of each memory cell M. ing. A pulse signal line PL that supplies a pulse signal P input from a pulse signal input terminal TP is connected to the control terminal C of each memory cell M. Further, an inverted pulse signal line PBL that supplies an inverted pulse signal PB that is an inverted signal of the pulse signal P input from the pulse signal input terminal TP is connected to the control terminal CB of each memory cell M.

Each of the memory cells M _{j, k} to M _{n, k} has an output terminal Q and a data signal line of the other memory cells in the column memory block BM of the adjacent previous column in which the input terminals D are arranged in the row direction. The output terminal Q is connected by the LD, and the output terminal Q is connected by the data signal line LD to the input terminal D of another storage cell in the adjacent column storage block BM.
Also connected to the input terminal D is an input terminal TI _k of each of the memory cells M _{1, k} of sequence storage block BM ₁ is a front row, last column of the row memory block BM _n memory cells M _{n, k} output terminal Q is connected to an output terminal tO _k.

In addition, each of the m pieces of data is input from the input terminal TI ₁ to the input terminal TI _{m in} parallel to the row progression storage device 1 in synchronization with the pulse signal. Further, in each of the memory cells M _{j, k} arranged in the row direction, data inputted in synchronization with the pulse signal P from the input terminal TI _k to the respective input terminals C are sequentially transmitted through the data signal lines LD. Are sequentially transferred in the row direction, that is, from the memory cell M _{j, k} to each of the memory cells M _{j + 1, k} . Thus, in the row progressive storage device 1, m pieces of data inputted in parallel to the input terminal TI _m from the input terminal TI _1, the column memory from sequence storage block BM ₁ column to storage blocks BM _n block BM memory cells M _j in _j, each _k in the row direction, are sequentially convoy traveling in synchronism with the pulse signal P, is transferred from each of the input terminals TI _m toward the output terminal tO _m.

In the pulse signal line PL, each of the buffer BF _n−1 to the buffer BF ₁ for waveform shaping is inserted between the column storage block BM _n−1 and the column storage block BM _1. Yes.
Further, the inversion pulse signal line PBL is provided for each column storage block BM _j . Further, each of the inverters INV _n to INV _{1 is provided} for each of the column storage block BM _n to the column storage block BM1. The inverter INV _n uses the pulse signal P supplied from the pulse input terminal TP as an inverted pulse signal PB, to the inverted pulse signal line PBL connected to the control terminal CB of the memory cell M _{n, k} in the column memory block BM _n . Output. Each of the inverters INV _n-1 to INV ₁ inverts the pulse signals P output from the column storage block BM _n to the column storage block BM ₂ in the subsequent column, and is connected to each other as a pulse signal PB. Output to the inverted pulse signal line PBL of the block BM _j .

As described above, in the present embodiment, the pulse signal line P supplied to the pulse input terminal TP is supplied from the control terminal C of each storage element M _{n, k} in the column storage block BM _n of the last column to the frontmost column. The connection terminals C of all the storage cells M _{j, k} are sequentially connected between the adjacent column storage blocks BM _j up to the control terminal C of the storage element M of each of the storage cells M _{1, k} in the column storage block BM ₁ . They are connected so as to be arranged in series on the wiring.
In the present embodiment, the row direction in which the data is transmitted in the sequence of sequence storage block BM _j, from the opposite direction of the rear row sequence storage block BM j _{+ 1,} the inverted pulse signal string storage block A _j of the adjacent front row as PB propagates, the pulse signal lines PL are sequentially connected in the order of the sequence storage block BM _j front row adjacent the rear row sequence storage block BM j _{+ 1.}

For example, the sequence storage block BM _n, the pulse signal line PL, the memory cell _{M n} at one end of the string storage block BM _{n, m} through the memory cell _{M n, 1} of the other end, the memory cell _{M n, m} → storage Cell M _{n, m−1} → memory cell M _{n, m−2} →... → memory element M _{n, k} →... → memory cell M _{n, 2} → memory cell M _{n, 1} It is connected to _{n, k} control terminals C. For this reason, the pulse signal P is _{supplied from} the control terminal C of the memory cell M _{n, m} → the control terminal C of the memory cell M _{n, m−1} → the control terminal C of the memory cell M _{n, m−2} →→ the memory element M. Propagation proceeds in the order of the memory cells M _{n, k in} the order of the control terminals C of _{n, k} →... → the control terminal C of the memory cell M _{n, 2} → the control terminal C of the memory cell M _{n, 1} .

The buffer BF _n−1 has an input terminal connected to the pulse signal line PL that is turned back from the control terminal C of the memory cell M _{n, 1} . Then, the buffer BF _n−1 shapes the pulse signal supplied to the input terminal, and outputs the pulse signal to the column storage block BM _n−1 in the previous column. In sequence storage block _{BM n-1,} the pulse signal line PL, similarly to the sequence storage block BM _n, sequence storage block _{BM 7n-1} of the one end in the memory cell _{M n-1,} the other end of the memory cell from the _m M Up to _n−1,1 , memory cell M _{n−1, m} → memory cell M _{n−1, m−1} → memory cell M _{n−1, m−2} →... → memory cell M _{n−1, k} →. The memory cell M _n−1,2 is connected to the control terminal C of each memory cell M _{j, k in} order of the memory cell M _n−1,1 → the memory cell M _n−1,1 . Therefore, the sequence storage block _{BM n-1,} the pulse signal P, the memory cell _{M n-1,} the control terminal of the _m C → storage cells _{M n-1,} the control terminal of the _m-1 C → memory cell _{M n- 1,} control terminal C of _m-2 ,... → control terminal C of memory cell M _{n-1, k} → ... → control terminal C of memory cell M _n-1,2 → control of memory cell M _n-1,1 Propagate in the order of terminal C.

Hereinafter, likewise, the column memory block _{BM n-2} from to sequence storage block BM _1, each sequence storage block BM memory cells disposed at one end in the _{j M j,} memory cells are arranged from _m at the other _{M j,} The control terminals C of the memory cells M _{j, k} up to ₁ are sequentially connected to the pulse signal line PL.
Therefore, in the present embodiment, each storage cell M _{j, k} in the column storage block BM _j can be regarded as a model of a distribution constant (distribution constant) in the circuit simulation when viewed from the output terminal of the buffer BF _j . The control terminal C is connected to the pulse signal line PL and is not connected so as to be regarded as a model of a lumped constant (lumped constant circuit). That is, in the present embodiment, as viewed from the output terminal of the buffer BF _j , the distribution in the circuit simulation in which the control terminals C of the memory cells M _{j, k} in the column memory block BM _j are distributed on the pulse signal line PL. The control terminal C of the memory cell M _{j, k} is connected to the pulse signal line PL so that it can be regarded as a model of the delay component as a constant.

As described above _, the control from the memory cell M _{j, m at} one end to the memory cell M _{j, 1 at} the other end in each column storage block BM _j in the order from the column storage block in the previous column to the adjacent column storage block. The control signal PL is wired so as to sequentially connect the terminals C.
In each column storage block BM _j , the memory cells M _{j, m at} one end are arranged in the same row, and similarly, the memory cells M _{j, 1} at the other end are arranged in the same row. Further, the resistance component between the control terminals C of adjacent memory cells M _{j, k} in the pulse signal line PL and the capacitance component of the control terminal C of the memory cells M _{j, k} are, as described above, the delay of the distributed constant in the circuit simulation. A control terminal C is connected to the pulse signal line PL so as to be regarded as a component model.

Therefore, the pulse signal P is sequentially delayed for each control terminal C of each storage cell M _{j, k} in the column storage block BM _j . Then, in each column storage block BM _j , the pulse signal P output from the buffer BF _j is transmitted from the control terminal C of the memory cell M _{j, m} at one end to the other end due to the delay component that can be regarded as the model of the distributed constant. Is delayed until it is input to the next-stage buffer BF _j−1 via the control terminal C of the storage cell M _{j, 1} . This delay time Td corresponds to the control terminal C of the memory cell M _{j, m} in the last row of the column memory block BM _j and the memory cell M _{j, 1 in the} foremost row when m data are advanced in m rows. This is a delay time of propagation of the pulse signal to and from the control terminal C, and is set shorter than the pitch interval of the pulse signal. That is, the delay component of the pulse signal between the adjacent column storage blocks to prevent the data from being lost when the data row progresses is generated by the resistance component of the pulse signal line PL and the capacitance component of the control terminal C. And the delay component corresponding to the model of the distributed constant formed by

The delay component is composed of a capacitance component of the control terminal C connected to the pulse signal line PL and a resistance component in the connection between the control terminal C and the pulse signal line PL, and adjacent memory arranged in each row. Between the cells M _{j, k} , the pulse signal P input to the control terminal C of the memory cell M _{j, k in} the previous column is transmitted to the control terminal C of the memory cell M _{j + 1, k in} the adjacent rear column. Input is delayed by the delay time Td by the delay component in the PL.
Further, since the pulse signal P output from the column storage block BM _{j + 1 in} the subsequent column via the buffer BF _j is inverted by the inverter INV _j , the inverted pulse signal PB is inverted in each column storage block in the same manner as the pulse signal P. in BM _j, the pulse signal P inputted front row of the memory cell _{M j,} the control terminal CB of _k adjacent the back row of the memory cell _{M j +,} the control terminals CB of _k, and time delay of the delay time Td Is input.

As a result, a clock is not applied to the memory cells arranged in the row direction at the same time, and there is a problem of data penetration progressing in the row direction between the memory cells in the adjacent front column and the memory cells in the rear column. Does not occur.
That is, according to the above-described configuration, each of the storage cells M _{j, k} of the subsequent column storage block BM _j reads data and then the storage cell in the adjacent subsequent column storage block BM _j−1 after the delay time Td. Each of M _{j−1, k} reads data. As a result, the delay time Td is slightly longer than the time until data is read in each storage cell M _{j, k} in the subsequent column storage block BM _j and the data in these storage cells M _{j, k} is stabilized. Is set. As a result, the memory cell _{M j} of the front row of the column memory block BM _j, from _k, when the memory cell _{M j + 1} of the rear row sequence storage block _{BM j + 1, k} the data is written, the second previous row sequence storage block BM _j-1 of the memory cell _{M j-1, k} data front row sequence storage block BM _j of the memory cell _{M j,} is written to _k, the memory cell _{M j} of the front row of the column memory block BM _{j, k} of the data Can be prevented from changing during the writing to the memory cell M _{j + 1, k} of the column memory block BM _{j + 1 in} the subsequent column.

As described above, in the present embodiment, a pulse between adjacent column storage blocks for preventing data omission between adjacent storage cells M _{j, k} that occurs when a data row progresses. A signal delay is generated by a pulse signal line PL having a delay component corresponding to the distributed constant model formed by the resistance component in the connection between the control terminal C and the pulse signal line PL and the capacitance component of the control terminal C. Since it is used, there is no need to provide a delay circuit as in the prior art, and it is possible to reduce the components of the formation progression storage device 1 and to reduce the layout area of the formation progression storage device 1. In addition, since it is not necessary to provide a delay circuit as in the prior art, and power consumption by the delay circuit is eliminated, the row progression storage apparatus 1 can reduce power consumption as compared with the prior art.

In the present embodiment, in the column storage block BM _n , the pulse signal line PL is connected to the storage cell M _{n, m} at one end of the column storage block BM _n to the storage cell M _{n, 1} at the other end. M _{n, m} → memory cell M _{n, m−1} → memory cell M _{n, m−2} →... → memory element M _{n, k} →... → memory cell M _{n, 2} → memory cell M _{n, 1} Are connected to the control terminal C of each memory cell M _{n, k} . However, not limited to this configuration, the pulse signal line PL extends from the memory cell M _{n, 1} at one end of the column memory block BM _n to the memory cell M _{n, m} at the other end to the memory cell M _{n, 1} → Memory cell M _{n, 2} →... → Memory element M _{n, k} →... → Memory cell M _{n, m−2} → Memory cell M _{n, m−1} → Memory cell M _{n, m} in this order. It is good also as a structure connected to the control terminal C of _{Mn, k} .

Correspondingly, the input terminal l is connected to the buffer signal BF _n−1 to the pulse signal line PL that is turned back from the control terminal C of the memory cell M _{n, m} . Then, the buffer BF _n−1 shapes the pulse signal supplied to the input terminal, and outputs the pulse signal to the column storage block BM _n−1 in the previous column. In the column storage block BM _n−1 , the pulse signal line PL is, like the column storage block BM _n , the storage cell M _n−1,1 → the storage cell M _{n−1, 2} ... →→ the storage cell M _{n−1. , K} →... → memory cell M _{n−1, m−2} → memory cell M _{n−1, m−1} → memory cell M _{n−1, m in} the order of control terminals of each memory cell M _{j, k} Connected to C. For this reason, in the column memory block BM _n−1 , the pulse signal P is transmitted from the control terminal C of the memory cell M _n−1,1 → the control terminal C of the memory cell M _n−1 , _→→ the memory cell M _{n−. 1,} control terminal C → ... → control terminal C of memory cell M _{n−1, m−2} → control terminal C of memory cell M _{n−1, m−1} → control of memory cell M _{n−1, m} Propagate in the order of terminal C.

Hereinafter, likewise, the column memory block _{BM n-2} from to sequence storage block BM _1, each sequence storage block BM memory cells disposed at one end in the _{j M j, 1} are disposed at the other end from the storage cell _{M j,} The control terminals C of the memory cells M _{j, k} up to _m are sequentially connected to the pulse signal line PL.
Therefore, in the present embodiment, as in the first embodiment described above, the column storage block BM can be regarded as a model of a distribution constant (distribution constant) in circuit simulation as viewed from the output terminal of the buffer BF _j. each memory cell M _j in _j, have been connected to the pulse signal line PL to the control terminal C of each of _k, not like connections regarded as a model of lumped (lumped constant circuit). For example, in the present embodiment, as viewed from the output terminal of the buffer BF _j , the distribution in the circuit simulation in which the control terminals C of the storage cells M _{j, k} in the column storage block BM _j are distributed on the pulse signal line PL. The pulse signal line PL is connected to the control terminal C of the memory cell M _{j, k} so that it can be regarded as a delay component as a constant model. For example, in this case, the buffer BF _j has a function of shaping a pulse signal whose waveform is broken due to the influence of the delay component. Therefore, the buffer BF _j is inserted for each optimum number of memory cells M in view of the amount of the delay component and the frequency of the pulse signal.

FIG. 2 is a diagram showing an example of a configuration in which the memory cell M in FIG. 1 is formed by a D latch (D (Delay) -LATCH).
In FIG. 2, the memory cell M includes a switch transistor Trp, a switch transistor Trn, an inverter CINV, and a clocked inverter CKINV.
Switching transistor Tr _p is a p-channel type MOS (metal oxide semiconductor) transistor whose gate is connected to the control terminal C. The switch transistor Tr _n is an n-channel MOS transistor whose gate is connected to the output terminal CB. Switching transistor Tr _p and the switch transistor Tr _n is interposed between the input terminal of the input terminal D and an inverter CINV in parallel. The switch transistor Trp has a gate electrode connected to the control terminal C (FIG. 1). The switch transistor Trn has a gate electrode connected to the control terminal CB. The clock inverter CINV has an input terminal connected to the output terminal Q, and an output terminal connected to each of the output terminal QB and the input terminal of the clocked inverter CKINV.

  The clocked inverter CKINV has an output terminal connected to the input terminal of the inverter CINV, a clock terminal CP connected to the control terminal C, and a clock bar terminal CM connected to the control terminal CM. The clocked inverter CKINV operates as an inverter in a state where an “H” level signal is input to the clock terminal CP and an “L” level signal is input to the clock bar terminal CM. On the other hand, the clocked inverter CKINV has an output terminal in a high impedance state when an “L” level signal is input to the clock terminal CP and an “H” level signal is input to the clock bar terminal CM.

  The D latch is supplied to the input terminal D when the pulse signal P applied to the control terminal C is at “L” level and the inverted pulse signal PB applied to the control terminal CB is at “H” level. Data is read into the input terminal of the inverter INV. At this time, each of the switch transistor Trp and the switch transistor Trn is turned on, and the data supplied to the input terminal D is output to the input terminal of the inverter CINV. Thereby, the inverter CINV inverts the data input from the input terminal D and outputs the inverted data to the input terminal of the clocked inverter CKINV. The clocked inverter CKINV has an output terminal having high impedance because the pulse signal P of “L” level is applied to the clock terminal CP and the inverted pulse signal PB of “H” level is applied to the clock bar terminal CM. . As a result, the clocked inverter CKINV maintains the level of data input from the input terminal D.

On the other hand, the D latch is in a data reading state when the pulse signal P applied to the control terminal C is at “H” level and the inverted pulse signal PB applied to the control terminal CB is at “L” level. Data read from the input terminal D is held in a state where the pulse signal P is at the “L” level and the inverted pulse signal PB is at the “H” level. At this time, each of the switch transistors Tr _p and the switch transistor Tr _n is turned off, and between the input terminal of the input terminal D and an inverter CINV a high impedance state. Further, the clocked inverter CKINV has an “H” level pulse signal P applied to the clock terminal CP and an “L” level inverted pulse signal PB applied to the clock bar terminal CM. Is inverted and output to the input terminal of the inverter CINV. Thus, to the input terminal of the inverter CINV, there is no new data is supplied via the switch transistor Tr _p and the switch transistor Tr _n, to the input terminal of the inverter CINV clocked inverter CKINV, inverter Since the data obtained by inverting the data read by CINV is further inverted and input, the D latch holds the read data.

FIG. 3 is a diagram showing a structural example of the switch transistor Tr _n in FIG. FIGS. 3 (a) shows a plan view of a switching transistor Tr _n (the layout). The p-type well 100 on a semiconductor substrate, the switching transistor Tr _n is formed. The switch transistor Tr _n includes a gate electrode 103, a source diffusion layer 101, and a drain diffusion layer 102. The source diffusion layer 101 is connected to the input terminal of the inverter CINC by a wiring 108 through a via (via hole) 107. The drain diffusion layer 102 is connected to the input terminal D by the wiring 110 through the via 109. The longitudinal direction of the one end of the gate electrode 103 through the via 104, the wiring 106_1 (pulse signal line PL) by the longitudinal direction of the other end of the gate electrode 103 of the switching transistor Tr _n of one another adjacent D latch Connected to. On the other hand, the other end in the longitudinal direction of the gate electrode 103 through the via 104, the longitudinal direction of the one end of the gate electrode 103 of the switching transistor Tr _n of the other adjacent D latched by the wiring 106_2 (pulse signal line PL) Connected to.

FIG. 3B shows a cross section taken along line AA of the switch transistor Tr _n in FIG. The gate electrode 103 is formed on the p-well 100 formed on the semiconductor substrate. An interlayer insulating film 112 is formed on the gate electrode 103. A via 104 for making contact with one end in the longitudinal direction of the gate electrode 103 is formed in the interlayer insulating film 112, and a via 105 for making contact with the other end is formed. As described above, one end of the contact region 103_1 of the gate electrode 103 is connected to the wiring 106_1 through the via 104. On the other hand, the other end of the contact region 103_1 of the gate electrode 103 is connected to the wiring 106_2 through the via 105.

FIG. 3C shows an equivalent circuit of the switch transistor Tr _n in FIG. In FIG. 3C, a resistor 104_R is a resistance component of the via 104 provided between the wiring 106_1 and the contact region 103_1. Similarly, the resistor 105_R is a resistance component of the via 105 provided between the wiring 106_2 and the contact region 103_1. Capacitor 103_C includes a gate electrode 103, a p-well 100, which is not shown is formed by a gate oxide film provided between the gate electrode 103 and p-well 100, the capacitance of the parasitic capacitor of the switch transistor Tr _n It is an ingredient. Each of the resistance values of the resistors 104_R and 105_R and the capacitance value of the capacitor 103_C realize a delay component that can be regarded as a model of a distributed constant in the circuit simulation of the pulse signal line PL.

With the configuration described above, in each column storage block BM _j , each of the capacitance component and the resistance component corresponding to the delay component that the pulse signal line PL can be regarded as a distributed constant model in circuit simulation is the gate of the switch transistor Tr _n in the D latch. The capacitance component in the electrode 103 and the resistance component in the via 104 and the via 105 with respect to the gate electrode 103. That is, the capacity of the control terminal C of the memory cell M _{j, k} corresponds to the gate capacity of the gate electrode 103 of the switch transistor Tr _n . The resistance of the control terminal C of the memory cell M _{j, k} is a resistance component in each of the via 104 and the via 105 of the gate electrode 103 described above. The resistance value of each resistance component of the via 104 and the via 105 can be controlled by the type of the conductor formed in the via hole, the inner diameter of the via hole, or the like. Thus, by adjusting the resistance value of the resistance component in the delay component of the pulse signal line PL that is regarded as a model of the distributed constant in the circuit simulation, the delay component of the distributed constant in the circuit simulation in each column storage block BM _j described above. It is possible to arbitrarily control the delay time Td of the pulse signal line PL that can be considered as follows.

In the present embodiment, the example in which the memory cell M _{j, k} is configured by the D latch has been described. However, the present invention is not limited to this, and the characteristic that data is output when writing to the memory cell M _{j, k} is shown. It can be used for any device that has a MOS transistor.

<Second Embodiment>
Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.
FIG. 4 is a block diagram showing a configuration example of a convoy progression-type storage device 1A according to the second embodiment of the present invention. The row progression storage device 1A includes a storage cell MA _{j, k} (n ≧ j ≧ 1) including a data input terminal D, a data output terminal Q, and a control terminal CB to which a pulse signal P for controlling the reading of data is input. , M ≧ k ≧ 1) are arranged in a matrix. That is, the memory cells MA are arranged in n columns and m rows. In FIG. 4, the same components as those in FIG. 1 are denoted by the same reference numerals. Hereinafter, configurations and operations different from those of the first embodiment will be described.

The memory cells MA _{j, k} arranged in a matrix of the row progression type storage device 1A are divided into _n blocks from the column storage block BMA ₁ to the column storage block BMA _n . This column memory block BMA _n is configured to include memory cells MA _n1 to MA _nm arranged in the column direction, and by forming n columns in the row direction, a column progression type memory device 1A is formed. Yes. In FIG. 4, the column direction is the y direction, the row direction is the x direction, and the data advances in a row in the x direction.
Each of the m pieces of data is input from the input terminal TI ₁ to the input terminal TI _{m in} parallel to the row progression storage device 1 in synchronization with the inverted pulse signal PB. In the memory cells M _nm arranged in the row direction, data input from the input terminal TI _m is synchronized with the pulse signal P in the row direction, that is, from the memory cell MA _1m to the memory cell via the data signal line LD. Sequentially transferred to each of the MA _nm . Accordingly, in the row progression storage device 1A, m pieces of data input in parallel from the input terminal TI ₁ to the input terminal TI _m are stored in the column storage blocks BMA ₁ to BMA _n . Each of them is transferred in the row direction, that is, in a sequential manner in synchronization with the pulse signal P from each of the input terminals TI _m toward the output terminal TO _m .

Inverter INVTP is provided between the pulse input terminal TP column storage block BMA _n. Since the inverter INVTP applies the inverted pulse signal PB to each storage cell MA _{j, k of} each column storage block BMA _j , the logic of the pulse signal P supplied via the pulse input terminal TP is set. Inverted and output as an inverted pulse signal PB.
Further, each of the buffer BFA ₁ to the buffer BFA _n−1 is connected to each column storage block BMA _{j in} the inverted pulse signal line PBL in the same manner as the buffers BF ₁ to BF _{n−1 of} the first embodiment, respectively. It is provided for waveform shaping of each inversion pulse signal PB supplied to the control terminal CB of each memory cell MA _{j, k} .

As described above, in the present embodiment, the logic of the pulse signal line P supplied to the pulse input terminal TP is inverted by the inverter INVTP, and is output as the inverted pulse signal PB to the inverted pulse signal line PBL.
Then, the inversion pulse signal line PBL is connected to each of the storage cells MA _{1 and k} in the column storage block BMA ₁ in the foremost column from each control terminal CB of the storage element MA _{n and k} in the column storage block BMA _n in the last column. The connection terminals CB of all the memory cells M _{j, k} are sequentially connected between adjacent column storage blocks BM _j to the control terminals CB of the memory elements MA _{j, k} so as to be arranged in series on the wiring. ing.
In this embodiment, as in the first embodiment, the row direction in which the data is transmitted in the sequence of sequence storage block BMA _j, from the opposite direction of the rear row sequence storage block BMA j + _1, the adjacent front row The inverted pulse signal lines PBB are sequentially connected in order from the column storage block BMA _{j + 1 in} the subsequent column to the column storage block BMA _{j in} the adjacent column adjacent to the column storage block A _{j so} that the inverted pulse signal PB propagates to the column storage block A _j .

For example, the sequence storage block BMA _n, the inverted pulse signal line PBL is the memory cell _{MA n} at one end of the string storage block BMA _{n, m} through the memory cell _{MA n, 1} of the other end, the memory cell _{MA n, m} → Memory cell MA _{n, m−1} → memory cell MA _{n, m−2} →... → memory element MA _{n, k} →... → memory cell MA _{n, 2} → memory cell MA _{n, 1} in this order. It is connected to the control terminal C of M _{n, k} . Therefore, the inverted pulse signal PB is the memory cell _{MA n,} a control terminal of the _m C → storage cell _{MA n,} a control terminal of the _m-1 C → memory cell _{MA n, m-2} of the control terminal C → ... → storage device Propagation is performed in the order of the memory cells MA _{n, k in} the order of the control terminal C of the MA _{n, k} →... → the control terminal C of the memory cell MA _{n, 2} → the control terminal C of the memory cell MA _{n, 1} .

The buffer BF _n−1 has an input terminal connected to the inverted pulse signal line PBL that is turned back from the control terminal C of the memory cell M _{n, 1} . Then, the buffer BF _n−1 shapes the inverted pulse signal PBL supplied to the input terminal, and outputs it to the column storage block BMA _n−1 in the previous column. In sequence storage block _{BMA n-1,} the inverted pulse signal line PBL is string storage block BMA as with _n, sequence storage block _BMA in _7n-1 of the end memory cells _{MA n-1,} from _m the other end of the memory cell Up to MA _n−1,1 , memory cell MA _{n−1, m} → memory cell MA _{n−1, m−1} → memory cell MA _{n−1, m−2} →... → memory cell MA _{n−1, k} → ... → memory cell MA _{n−1, 2} → memory cell MA _n−1,1 are connected to the control terminal C of each memory cell MA _{j, k in this} order. Therefore, the sequence storage block _{BMA n-1,} the inverted pulse signal PB is storage cells _{MA n-1,} the control terminal of the control terminal C → storage cell _{MA n-1, m-1} of the _m C → storage cell MA _{n −1, m−2} control terminal C →... → memory cell MA _{n−1, k} control terminal C →... → memory cell MA _n−1,2 control terminal C → memory cell MA _n−1,1 . Propagate in the order of the control terminal C.

Hereinafter, similarly, from the column storage block BMA _n−2 to the column storage block BMA ₁ , the storage cell MA _j disposed at one end of each column storage block BMA _j, the storage cell MA _j disposed at the other end of the column storage block BMA _j, The control terminals C of the memory cells MA _{j, k} up to ₁ are sequentially connected to the inverted pulse signal line PBL. Therefore, in the present embodiment, each storage cell MA _{j, k} in the column storage block BM _j can be regarded as a model of a distribution constant (distribution constant) in circuit simulation as viewed from the output terminal of the buffer BF _j . The control terminal C is connected to the pulse signal line PL and is not connected so as to be regarded as a model of a lumped constant (lumped constant circuit). That is, in this embodiment, as viewed from the output terminal of the buffer BF _j , circuit simulation in which the control terminals C of the storage cells MA _{j, k} in the column storage block BMA _j are distributed on the inverted pulse signal line PBL. The control terminal C of the memory cell MA _{j, k} is connected to the inverted pulse signal line PBL so that it can be regarded as a model of the delay component of the distributed constant in FIG.

As described above, in the order of the front row sequence storage unit block adjacent the back row sequence storage block, and control of each sequence storage block BMA end of the memory cell MA in _{j j,} from _m the other end of the memory cell MA _{j, 1} The control signal PL is wired so as to sequentially connect the terminals C.
In each column storage block BMA _j , one end of the storage cells MA _{j, m} is arranged in the same row, and similarly, the other end of the storage cells MA _{j, 1} is arranged in the same row. The storage cell MA j adjacent the inverted pulse signal line _PBL, the resistance component and the memory cell MA j between the control terminal C of _k, the capacitance component of the control terminal C of _k, as described above, distributed in the circuit simulation constants The control terminal C is connected to the inverted pulse signal line PBL so that it can be regarded as a model of the delay component.

Therefore, the inversion pulse signal PB is sequentially delayed for each control terminal C of each storage cell MA _{j, k} in the column storage block BMA _j . In each column storage block BMA _j , the inverted pulse signal PB output from the buffer BF _j is transmitted from the control terminal C of the storage cell MA _{j, m} at one end to the other by the delay component that can be regarded as the model of the distributed constant. There is a delay until the data is input to the next-stage buffer BF _j−1 via the control terminal C of the end memory cell MA _{j, 1} . This delay time Td corresponds to the control terminal C of the memory cell MA _{j, m} in the last row of the column memory block BMA _j and the memory cell MA _{j, 1 in the} foremost row when m data is advanced in m rows. This is a delay time of propagation of the pulse signal to and from the control terminal C, and is set shorter than the pitch interval of the pulse signal. That is, the generation of the delay of the pulse signal between the adjacent column storage blocks to prevent the data from being lost when the data row progresses, the resistance component of the inverted pulse signal line PBL and the capacitance of the control terminal C And a delay component corresponding to the model of the distributed constant formed by the components.

As described above, in the present embodiment, pulses between adjacent column storage blocks for preventing data omission between adjacent storage cells MA _{j, k} that occur during data row progression. Since the delay component corresponding to the model of the distributed constant formed by the resistance component of the inverted pulse signal line PBL and the capacitance component of the control terminal C is used for the generation of the signal delay, a delay circuit is provided as in the prior art. There is no need, and it becomes possible to reduce the components of the formation progression storage device 1A, and the layout area of the formation progression storage device 1A can be reduced.

The storage cell _{MA j} in the second _{embodiment, k} is the memory cell _{M j} in the first _{embodiment, k} is different from the storage cell _{MA j,} configuration of _k memory cells _{M j,} for _k It is in the point that it is simplified. Hereinafter, the configuration of the memory cells MA _{j, k} will be described with reference to the drawings.
FIG. 5 is a diagram showing an example of a configuration in which the memory cell MA is formed by a D latch in the formation progression type storage device 1A according to the second embodiment.
In FIG. 5, the memory cell MA _{j, k} includes a switch transistor Tr _n0 , an inverter CINV _1, and an inverter CINV ₂ . Eliminating the switching transistor Tr _p in the first embodiment has a configuration obtained by changing the clocked inverter INV to the inverter CINV _2.

The inverter CINV ₁ is configured as a logic inverting circuit by connecting each of the transistor Tr _p1 and the transistor Tr _n1 in series. Similarly, the inverter CINV ₂ is configured as a logic inversion circuit by connecting each of the transistor Tr _p2 and the transistor Tr _n2 in series. In the inverter CINV ₁ , a connection point between the gate electrode of the transistor Tr _{p1 and} the gate electrode of the transistor Tr _n1 is an input terminal, and a connection point between the drain of the transistor Tr _{p1 and} the drain of the transistor Tr _n1 is an output terminal. Similarly, the inverter CINV ₂ is a connection point input terminal of the gate electrode of the gate electrode and the transistor _{Tr n2} of the transistor _{Tr p2,} the connection point of the drain of the drain and the transistor _{Tr n2} of the transistor _{Tr p2} is an output terminal.

The switch transistor _Trp0 is an n-channel MOS transistor whose gate electrode is connected to the control terminal CB. The switch transistor Tr _n0 is interposed between the input terminal D and the input terminal of the inverter CINV ₁ . The inverter CINV ₁ has an input terminal connected to the output terminal Q, and an output terminal connected to each of the output terminal QB and the input terminal of the inverter CINV ₂ . The inverter CINV ₂ has an output terminal connected to the input terminal of the inverter CINV ₁ .

The D latch as the memory cell MA _{j, k} receives data supplied to the input terminal D via the switch transistor Tr _n0 when the inverted pulse signal PB of “H” level is applied to the control terminal CB. read to the input terminal of the inverter INV _1. At this time, the switch transistor Tr _n1 is turned on and outputs data supplied to the input terminal D to the input terminal of the inverter CINV ₁ . Thereby, the inverter CINV ₁ inverts the data input from the input terminal D, and outputs the inverted data to the input terminal of the inverter CINV ₂ and the output terminal QB. The inverter CINV ₂ inverts the data inverted by the inverter CINV ₂ again and outputs it to the inverter CINV ₁ . For this reason, when the inverted pulse signal PB of “H” level is applied to the control terminal CB, each of the inverter CINV ₁ and the inverter CINV ₂ is input from the input terminal D to invert the logic of the input data. The level of the data is written to the D latch.

On the other hand, the D latch reads from the input terminal D when the “L” level inversion pulse signal PB is applied to the control terminal CB and when the “H” level inversion pulse signal PB is applied to the control terminal CB. Retain data. At this time, the switch transistor Tr _n0 is turned off, and a high impedance state is established between the input terminal D and the input terminal of the inverter CINV ₁ . Similarly, a high impedance state is established between the input terminal D and the input terminal of the inverter CINV ₁ . Thus, to the input terminal of the inverter CINV _1, there is no new data is supplied via the switch transistor _{Tr n0,} the inverter CINV ₁ is an input terminal of the inverter CINV _2, inverters CINV ₁ is read Since the data obtained by inverting the data is further inverted and input, the D latch holds the read data.

In the case of the configuration of the D latch shown in FIG. 5, the layout area of the memory cell can be further reduced and the degree of integration of the memory cell can be improved as compared with the D latch of the first embodiment.
However, by omitting the switch transistor Tr _p in the first embodiment, because of the parasitic resistance (voltage drop corresponding to the threshold value) of the switch transistor Tr _n0 , the “H” level data is transferred to the front row at a sufficient voltage level. Cannot be transmitted from the storage cell MA _{j-1, k} to the storage cell MA _{j, k} . As a result, the data transmission speed between adjacent column storage blocks BMA _j decreases, and the data logic may change during the transmission.
For the reason described above, in this embodiment, the “H” level voltage of the inversion pulse signal PB applied to the gate electrode of the switch transistor Tr _n0 is used as another circuit (inverter CINV ₁₎ of the memory cell MA _{j, k.} And CINV ₂ or the like). That is, a voltage obtained by adding the threshold voltage of the switch transistor Tr _{n0 to} the power supply voltage or a voltage exceeding the added voltage is set as the “H” level voltage of the inverted pulse signal PB.

For this reason, the inverter INVTP and each of the buffers BFA1 to BFA8 are supplied with a voltage obtained by boosting the power supply voltage supplied to the other circuits of the memory cell MA as the power supply voltage.
As described above, by setting the "H" level voltage of the inverted pulse signal PB which definitive applied to the switch transistor Tr _n0, to cancel the parasitic resistance of the switch transistor Tr _n0 due to the influence of the threshold voltage, the switch transistor Tr _n0 Since the ON resistance of the transistor is equal to that of the p-channel transistor, “H” level data can be transmitted from the memory cell MA _{j−1, k in the} previous _column to the memory cell MA _{j, k} with a sufficient voltage level. it can.
Further, when the threshold voltage of the switch transistor Tr _n0 is added to the power supply voltage of another circuit of the memory cell MA _{j, k} , the maximum threshold voltage is considered in consideration of the fluctuation width of the threshold voltage due to manufacturing variation of the switch transistor Trp0. , The data propagation characteristics of the switch transistor Tr _n0 can be made uniform, the write characteristics of the memory cells Mj, k can be matched, the period of the pulse signal P can be optimized, and the data propagation speed can be increased. Can be improved.

  With the above-described configuration, the number of transistors used for the first embodiment is reduced, so that the layout area of the memory cell is reduced, and the degree of integration of the memory cell is further improved as compared with the first embodiment. be able to.

FIG. 6 is a diagram showing a layout pattern of the switch transistor Tr _n0 in the memory cell MA and each transistor constituting the inverter CINV ₁ and the inverter CINV ₂ . In FIG. 6, each memory cell MA is configured by a pattern layout of unit cells 500. The unit cell 500 of the memory cell MA _{j, k} includes a region 501 showing a p-well pattern forming an n-channel transistor, a region 502 showing a p-well pattern forming an n-channel transistor, and a p-channel transistor. And a region 503 showing an n-well pattern for forming the n well.
Here, the switch transistor Tr _n0 is formed in the p-well of the region 501. In the p well of the region 502, each of the transistor Tr _n1 and the transistor Tr _n2 is formed. In the n-well of region 503, each of transistor Tr _p1 and transistor Tr _p2 is formed.

  The region 504 is a space necessary for separating the p-well of the region 501 from the p-well of the region 502 and the n-well of the region 503. Here, each of the region 501 and the region 502 is a p-well, and an n-channel transistor is formed, but the power supply voltage of the formed transistor is different. For this reason, the region 501 and the region 502 are formed in different p-wells, and a space 504 for separating the wells is required between the wells. The region 505 is a well separation space that separates the well of the region 502 and the well of the region 503.

In the present embodiment, the unit cell 500 that is one layout pattern of the memory cells MA _{j, k} is arranged in both the x direction and the y direction at the boundary line with the layout pattern of the adjacent memory cells MA _{j, k.} They are arranged with mirror inversion (rotated 180 ° around each boundary line). That is, the layout pattern of the memory cells MA _{j, k} of the row progression storage device 1A is formed by inverting the unit cells 500 of one memory cell M _{j, k} vertically and horizontally.
Thereby, in both the x direction and the y direction, each transistor between two adjacent memory cells can share a well.
That is, when the unit cells 500 are simply shifted and arranged without mirror inversion with respect to the x direction, between the adjacent unit cells 500, the p well of the region 501, the p well of the region 502, and the region 503 In order to separate the n well, it is necessary to provide a space similar to the region 504.

Therefore, according to the present embodiment, the unit cell 500 is arranged in the mirror-inverted arrangement with respect to the boundary line of the layout pattern of the adjacent memory cells to form the row progression storage device 1A in the x and y directions. It is not necessary to provide a space similar to the above-described region 504 between the layout regions of adjacent memory cells, and the space for this well separation can be reduced.
Therefore, according to this embodiment, the memory cell MA _j, in the layout pattern of the array of _k, it is possible to reduce the space for the well isolation, a memory cell MA j in the row progressive memory device _1A, the _k The degree of integration can be improved.

<Third Embodiment>
Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.
FIG. 7 is a block diagram showing a configuration example of a convoy progression type storage device 1B according to the third embodiment of the present invention. In FIG. 7, the column progression storage device 1B subdivides the column storage block BM of the column progression storage device 1 of FIG. 1 so that the memory cells M arranged in m rows are divided into m1 rows and m2 rows. It is divided into a column storage block BM1 and a sub column storage block BM2. For example, the sub-column block BM1 ₁ is composed of the memory cells M in the m1 row from the memory cells _M1,1 to the memory cells M1 _{, m1} . The sub-column block BM2 ₁ is composed of the memory cells M1 _{, m1 + 1} to the memory cells M1 _, and the memory cells M in m2 rows (m1 + m2 = m). In FIG. 7, the column direction is the y direction, the row direction is the x direction, and the data advances in a row in the x direction.

  As a result, the convoy progression storage device 1B includes the convoy progression storage unit 1B1 in which the sub column storage blocks BM1 are arranged in the row direction, and the convoy progression storage unit 1B2 in which the sub column storage blocks BM2 are arranged in the row direction. Is done. The pulse signal line PL is connected to the pulse input terminal TP, and supplies the pulse signal line PL1 for supplying a pulse signal to the formation progression type storage unit 1B1 and the pulse signal to the formation progression type storage unit 1B2. It is separated from the pulse signal line PL2.

In the column progression storage unit 1B1, the pulse signal line PL1 wired from the last column sub-column storage block BM1 _n to the control terminal C of each storage cell M _{j, k} of the _first column sub-column storage block BM1 ₁ includes: Buffers BF1 _n-1 to BF1 ₁ are respectively inserted between adjacent sub storage blocks BM1 _j . Further, the convoy progressive memory unit 1B1, a pulse input terminal TP each memory cell of the first row of the sub-sequence storage block BM1 ₁ from M _j, each pulse signal line PBL1 which is wired to the control terminal CB of _k, Inverter INV1 _n to inverter INV1 ₁ are respectively inserted to supply the inverted pulse signal PB to the control terminal CB of the memory cell M of each sub column storage block BM1 _j .

Similarly, the sub memory block adjacent to the pulse signal line PL2 wired from the last column sub column memory block BM2 _n to the control terminal C of each memory cell M _{j, k} of the _first column sub column memory block BM2 ₁ Buffers BF2 _n-1 to BF2 ₁ are respectively inserted between BM2 _j . Further, in the row progression type storage unit 1B2, each of the pulse signal lines PBL2 wired from the pulse input terminal TP to the control terminal CB of each storage cell Mj _{, k} of the sub-column storage block BM2 _{1 in} the foremost column includes: Inverter INV2 _n to inverter INV2 ₁ are respectively inserted to supply the inverted pulse signal PB to the control terminal CB of the memory cell M of each sub column storage block BM2 _j .

In the column progression storage unit 1B1, the pulse signal line PL1 is connected to the control terminal C of the memory cell M _{n−1, m1} arranged in the last row of the sub column storage block BM1 _n−1 via the buffer BF1 _n−1 . Connected.
Similarly to the column progression type storage device 1, the pulse signal line PL1 is connected to the sub column of the last column from the control terminal C of the memory cell M _{n, m1} arranged in the last row of the sub column storage block BM1 _n of the last column. After wiring to the control terminal C of the memory cell M _{n, 1} arranged in the foremost row of the column storage block BM1 _n , storage of the last row in the sub column storage block BM1 _j of the previous column sequentially adjacent via the buffer BF1 _j It is connected to the control terminal C of the cell _{Mj, m1} .

In this way, the pulse signal line PL1 is connected to the last row of the adjacent front column sub-column storage block BM1 _j from the control terminal C of the _first row storage cell _j-1 , ₁ of the rear _- row sub-column storage block BM1 _j-1. Are connected to the control terminal C of the memory cell M _{j, m1} of the first row and sequentially connected to the control terminal C of the memory cell M _1,1 of the _first row of the sub column storage block BM1 ₁ of the front row.
Similarly, the pulse signal line PL2 is connected from the control terminal C of the storage cell _{j-1, m1 + 1} in the foremost row of the sub column storage block BM2 _{j-1 in} the subsequent column to the last of the sub column storage block BM2 _{j in} the adjacent previous column. row of the memory cell M _j, are sequentially connected by folding back to the control terminal C of _m, is connected to the control terminal C of the memory cell M _{1, m1 + 1} of the foremost row of the sub-sequence storage block BM2 ₁ of the front row.

In the present embodiment, in the convoy progressive memory device 1 and ranks progressive memory device 1A, the data based on the pulse signal P at m rows, when to convoy proceed toward the respective input terminals TI _m to the output terminal TO _m The delay time Td of propagation of the pulse signal P between the control terminal C of the memory cell M _{j, m} in the last row of the column storage block BMj and the control terminal C of the memory cell M _{j, 1 in} the front row is a pulse signal. When it becomes longer than the pitch interval of P, the column storage block BM _j is divided into a plurality of sub column storage blocks BM1 and sub columns in the column direction so as to correspond to the pitch interval of the pulse signal P by the configuration of the column progression type storage device 1B. dividing each of the row memory block BM2, memory cells M _j in each sub-sequence storage block BM1 and sub-string storage block _BM2, the number of rows _k, needed for the pulse signal P In correspondence with the pitch adjusting the delay time Td by.
Thus, according to the present embodiment, in the memory cell M _{j, k} of each sub-column memory block, the memory cell M _{j-2, k in} the previous column is compared with the memory cell M _{j-1, k} in the previous column. Before the data is read, the delay time is made to correspond to the period of the pulse signal P set corresponding to the time when the data of the memory cell M _{j−1, k in} the previous column can be read from the memory cell M _{j, k} . Since Td can be adjusted, m rows of data can be read within the same period of the pulse signal P.

<Application of the formation progression type storage device>
FIG. 8 is a diagram illustrating a configuration example of a computer system 100 using the formation progression storage device 1 according to the embodiment of the present invention.
In FIG. 8, the computer system 100 is configured to include a formation progression storage device 1 and a computer 2. The computer 2 includes a pulse generation circuit 21 and an arithmetic logic operation circuit 22. The pulse generation circuit 21 generates a pulse signal P and outputs the pulse signal P to each of the arithmetic logic operation circuit 22 and the formation progression storage device 1. As a result, the formation progression storage device 1 advances m formations that are input in parallel to the input terminal TI _k from the outside in synchronization with the pulse signal P in m rows, and from the output terminal TO _k. Data is sequentially supplied to the arithmetic logic circuit 22 in synchronization with the pulse signal P.

  In addition, the arithmetic logic operation circuit 22 sequentially reads data from the formation progression type storage device 1 in synchronization with the pulse signal P, and for example, the internal sequential circuit performs data operation processing in synchronization with the pulse signal P. For this reason, the arithmetic of the present embodiment is compared with a conventional computer in which a predetermined address is accessed by addressing to sequentially read data and the arithmetic logic circuit needs to wait until all data necessary for the operation is read. The logical operation circuit 22 can perform data reading from the row progression storage device 1 and data operation processing by the internal arithmetic logic operation circuit 22 in synchronization with the same pulse signal P. Data calculation processing can be performed at higher speed.

That is, in a general computer, since there is a bottleneck of access to a storage device that performs random access such as the above-described DRAM (dynamic random access memory) and SRAM (static random access memory), the arithmetic processing in the computer Even if the pulse signal P, which is the clock of the above, is increased in speed, the speed is limited by the access time to the storage device.
However, the computer in the present embodiment eliminates the bottleneck in random access to the storage device by using the formation progression storage device 1, and increases the frequency of the pulse signal of the arithmetic processing inside the computer. Unlike the above computer, the increase in the speed of the pulse signal P inside the computer can be reflected in the reading of data from the storage device, and the entire arithmetic processing including the data reading process can be accelerated.

In order to read the data described above, the row progression storage device 1 is set so that the delay time Td is equal to or less than the cycle of the pulse signal P. In addition, as described above, the cycle of the pulse signal P is determined so that each storage cell M _{j, k} has a storage cell in the previous column with respect to the storage cell M _{j−1, k} in the previous column. Before the data of M _{j−2, k} is read _, the data of the memory cell M _{j−1, k in} the previous column is set corresponding to the time during which the memory cell M _{j, k} can be read.

Further, the row progression storage device 1 is configured such that the data output from the column storage block BM _n of the last column can be switched to a ring shape that is read again into the column storage block BM ₁ of the front row, and the computer 2 performs pulse switching. If calculation processing is performed in synchronization with the signal P, data is supplied to the computer 2 in parallel and the computer 2 is processed. On the other hand, if calculation using data is not performed in the processing of the computer 2, it is read. You may comprise so that the data which circulate may be circulated.
In addition, in the case of stream data such as streaming data or image data, the row progression storage device 1 includes a memory cell used for adding a flag bit as an index indicating which is the start position of the data. It is out.

  If the computer 2 is a processor (CPU (central processing unit)) or DSP (digital signal processor) used for image processing of an imaging device having an image sensor or arithmetic processing of a wearable device (wearable computer), etc. In the data sequentially supplied by the type storage device 1, it may be configured such that the range of the supplied data is an instruction to execute the arithmetic processing and the unit of data, and is indicated by the result of integrating the flag bit data. The data of this flag bit is written in the formation progression type storage device 1 together with the data. Here, wearable devices are computers that can be worn and carried, such as smartphones, advanced mobile phones and portable game machines, IC (integrated circuit) cards, and other devices that have data calculation functions inside. Including.

Further, in this embodiment, the row progression storage device 1 has been described as an external storage device of the computer 2, but it may be formed as an internal storage device in the same chip as the computer 2. In addition, the row progression storage device 1 in the present embodiment is provided in a portable information terminal (eg, an imaging device or a display device) such as a digital camera or a wearable device, and is connected to a computer in the device. It may be. In this case, the portable information terminal (for example, the imaging device or the display device) is configured to include the formation progression type storage device 1 in the present embodiment. In addition, the portable information terminal (eg, imaging device or display device) includes a row progression storage device 1, a computer 2, an image output unit that outputs image data processed by the computer 2, and the image And a display unit that displays data.
In the above description, the row progression storage device 1 is used as the row progression storage device. However, instead of the row progression storage device 1, either the row progression storage device 1A or the row progression storage device 1B A configuration using these may also be used.

  The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and includes design and the like within a scope not departing from the gist of the present invention.

DESCRIPTION OF SYMBOLS 1,1A, 1B ... Convoy progress type | mold storage apparatus 1B1, 1B2 ... Convoy progress type | mold memory | storage part 2 ... Computer 21 ... Pulse generation circuit 22 ... Arithmetic logic operation circuit 100 ... Computer system 500 ... Unit cell 501,502,503,504 505... Region BF ₁ , BF ₂ , BF _j , BF _n−1 , BF _{1 1} , BF _{1 2} , BF 1 _j , BF 1 _n−1 , BF 2 ₁ , BF 2 ₂ , BF 2 _j , BF 2 _n−1, buffer BM ₁ , BM ₂ , BM ₃ , BM _n−1 , BM _n , BMA ₁ , BMA ₂ , BMA ₃ , BMA _n−1 , BMA _n ..., Column storage blocks BM1 ₁ , BM1 ₂ , BM1 ₃ , BM1 _n−1 , BM1 _n , BM2 ₁ , BM2 ₂ , BM2 ₃ , BM2 _n−1 , BM2 _n ... Sub-column storage block INV ₁ , INV ₂ , INV _j , INV _n−1 , INV _n , INV1 ₁ , INV1 ₂ , INV1 _j , INV1 _n−1 , INV1 _n , INV2 ₁ , INV2 ₂ , INV2 _j , INV2 _n−1 , INV2 _n , INVTP... Inverter M _1,1 , M _1,2 , M1 _{, k} , M1 _{, m} , _{Mj, 1} , _{Mj, k} , _{Mj, m} , _Mn-1,1 , _{Mn-1, m} , _{Mn, 1} , _{Mn, k} , M _{n, m−1} , M _{n, m} , MA _1,1 , MA _1,2 , MA _{1, k} , MA _{1, m} , MA _{j, 1} , MA _{j, k} , MA _{j, m} , MA _{n− 1} , ₁ , MA _{n−1, m} , MA _{n, 1} , MA _{n, k} , MA _{n, m−1} , MA _{n, m} ... Memory cell PL, PL1, PL2... Pulse signal lines PBL, PBL1, PBL2. inverted pulse signal line _{TI 1, TI 2, TI k} , TI m-1, TI m ... ON Terminals _{TO 1, TO 2, TO k} , TO m-1, TO m ... output terminal TP ... pulse input terminal

Claims (9)

A plurality of memory cells each including a terminal portion including a data input terminal, a data output terminal, and a control terminal to which a pulse signal for controlling reading of the data is input are arranged in the direction of the column among rows and columns A plurality of column storage blocks to be
In the column storage block arranged in the row direction among the plurality of column storage blocks, the output terminal of the storage cell of the column storage block and the input of the storage cell of the column storage block in the subsequent column A data line connecting a terminal to each row of the memory cells;
Among the plurality of memory cells of the column memory block in the rear column, the control terminal of the first memory cell at one end in the column direction to the control terminal of the second memory cell at the other end in the column direction sequentially. Connected and arranged in the same row as the row in which the first memory cells are arranged among the control terminals of the second memory cells and the memory cells included in the column memory block of the previous column A train progression storage device comprising: a pulse signal line that connects the control terminal of the third storage cell. The data stored in the storage cell of the column storage block is stored in the column storage block of the previous column from the storage cell of the column storage block of the previous column. The formation progression storage device according to claim 1, wherein the formation progresses in synchronization with the pulse signal with respect to the storage cells in the same row as the cells. The delay time of the pulse signal between the storage cell at one end of the column storage block and the storage cell at the other end is shorter than the pitch interval of the pulse signal. Convoy progression type storage device. When controlling the frequency of the pulse signal, the sub-column storage block has the number of the memory cells in which the delay time of the pulse signal between the memory cell at the one end and the memory cell at the other end is shorter than the cycle of the pulse signal. The row progression storage device according to any one of claims 1 to 3, wherein the column storage block is divided into two and the pulse signal line is wired for each of the sub column storage blocks. The row progression storage device according to any one of claims 1 to 4, wherein the storage cell is a D latch formed of a MOS transistor. The write transistor of the D latch is formed of an n-type MOS transistor, and an H level voltage of the pulse signal input to the gate is set higher than a power supply voltage in the D latch. Item 6. The row progression storage device according to item 5. In the layout arrangement of each transistor constituting the column storage block, n-type MOS transistors used for writing in the column storage block by sequentially arranging the pattern of unit cells of the adjacent column storage block by mirror inversion, p 7. The row progression storage device according to claim 6, wherein each of the n-type MOS transistor and the other n-type transistor is arranged so as to share each well and each transistor of the column storage block adjacent to each other. The row progression storage device according to claim 6 or 7, wherein the pulse signal line has a structure in which a gate of the writing transistor is interposed, and the gate is used as a resistance component and a capacitance component. . A pulse generation circuit for generating a pulse signal;
An arithmetic logic circuit that performs an arithmetic operation in response to the pulse signal;
A plurality of storage cells each including a terminal portion including a data input terminal, a data output terminal, and a control terminal to which the pulse signal for controlling reading of the data is input are arranged in the direction of the column among rows and columns. A plurality of column storage blocks arranged, and the column storage block arranged in the row direction among the plurality of column storage blocks, the output terminals of the storage cells of the column storage block, and Of the plurality of storage cells of the column storage block in the rear column, one end in the column direction of the data lines connecting the input terminals of the storage cells of the column storage block for each row of the storage cells The control terminal of the first memory cell is sequentially connected to the control terminal of the second memory cell at the other end in the column direction, and the control terminal of the second memory cell and the column of the previous column A pulse signal line connecting the control terminal of a third memory cell arranged in the same row as the row in which the first memory cells are arranged among the memory cells included in the memory block; Convoy progression type storage device,
With
The output terminal of the storage cell in the column storage block of the last column is connected to the arithmetic logic circuit, and a set of data groups is provided to each of the input terminals of the storage cell in the column storage block of the first column. Entered,
In synchronization with the pulse signal, the data is advanced between the memory cells in the row direction, and the data group that has been advanced is output to the arithmetic logic circuit in parallel.
The computer system, wherein the arithmetic logic circuit executes an arithmetic logic operation using the data input in synchronization with the pulse signal from the row progression storage device.

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