JP2014112585A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2014112585A
JP2014112585A JP2012266140A JP2012266140A JP2014112585A JP 2014112585 A JP2014112585 A JP 2014112585A JP 2012266140 A JP2012266140 A JP 2012266140A JP 2012266140 A JP2012266140 A JP 2012266140A JP 2014112585 A JP2014112585 A JP 2014112585A
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semiconductor chip
semiconductor device
circuit
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JP5812974B2 (en
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Koichi Masuda
晃一 増田
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H01L24/71—Means for bonding not being attached to, or not being formed on, the surface to be connected
    • H01L24/72—Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that is small in size, has a lot of flexibility in a circuit layout, and is assembled easily.SOLUTION: A mounting substrate 40 has a circuit board 20 on which a semiconductor chip 30 is mounted. A lid 50 is provided with a through hole TH. The lid 50 has a circuit pattern 52. At least a part of the circuit pattern 52 is positioned on a rear surface S1. A junction part 61 of a connection member 60 is bonded onto a mounting substrate 40. A terminal part 62 of the connection member 60 is pressed against the circuit pattern 52 on the rear surface S1 of the lid 50. A screw part 63 of the connection member 60 is inserted into the through hole TH. A clamp 70 is disposed on a surface S2 of the lid 50. The clamp 70 has a screw hole SH. The screw part 63 is screwed into the screw hole SH.

Description

本発明は、半導体装置に関するものであり、特に、実装基板が配置された容器を有する半導体装置に関するものである。   The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a container in which a mounting substrate is disposed.

実装基板が配置された容器を有するパワーデバイスモジュール（半導体装置）は、広く用いられている。モジュールの回路は、実装基板に加えさらに、容器を塞ぐように配置された基板にも設けられ得る。これにより、回路が設けられる領域が広く確保できるので、半導体装置の大きさを小さくすることができる。   A power device module (semiconductor device) having a container in which a mounting substrate is arranged is widely used. In addition to the mounting substrate, the module circuit may be provided on a substrate disposed so as to close the container. As a result, a wide region in which the circuit is provided can be secured, so that the size of the semiconductor device can be reduced.

特開平６−４５７２１号公報によれば、混成集積回路装置（半導体装置）は、小信号系の回路素子が搭載された第１の基板と、パワー系の回路素子が搭載された第２の基板と、両基板を離間するケース材と、両基板を接続する弾性力を有する接続手段とを有する。接続手段は、ケース材に形成され、接続手段を保持するための孔に収納されている。第１の基板はケース材に螺子止めによって押止されており、これにより接続手段が圧縮される。この圧縮力によって接続手段が、両基板上に形成された両接続用パッドに接続される。これにより両基板が相互に接続される。この公報によれば、混成集積回路装置の完成後において、容易に基板の取り替えができ、しかも製造作業性を従来よりも著しく向上させることができる、とされている。   According to Japanese Patent Laid-Open No. 6-45721, a hybrid integrated circuit device (semiconductor device) includes a first substrate on which small signal circuit elements are mounted and a second substrate on which power circuit elements are mounted. And a case material that separates the two substrates, and a connecting means having an elastic force for connecting the two substrates. The connecting means is formed in the case material and is accommodated in a hole for holding the connecting means. The first substrate is pressed against the case material by screwing, thereby compressing the connecting means. The connecting means is connected to both connection pads formed on both substrates by this compressive force. Thereby, both substrates are connected to each other. According to this publication, after completion of the hybrid integrated circuit device, the substrate can be easily replaced, and the manufacturing workability can be remarkably improved as compared with the prior art.

特開平６−４５７２１号公報JP-A-6-45721

上記従来の技術によると、第１の基板（蓋）の螺子止めによる固定によって、第１および第２の基板の間で接続手段（接続部材）が圧縮される。これにより接続手段に圧縮力が加わる。この圧縮力によって接続手段が第１の基板に押し付けられることで接続手段が第１の基板に固定される。このため、接続手段の位置が規制されていないとすると、特に接続手段が圧縮される際に、第１の基板上における接続手段の位置が容易にずれてしまう。これを防止するためには、接続手段の位置を規制する構造を設ける必要がある。上記公報においてはこのような構造として、接続手段を収容する孔がケース材に形成されている。このような構造をケース材に設けると半導体装置の大きさが大きくなってしまう。またこのような構造をケース材に設ける位置は、基板およびケース材の配置によって制限を受けやすいことから、接続手段を電気特性上望ましい位置に設けることが困難な場合が多い。すなわち回路レイアウトの自由度が低い。   According to the conventional technique, the connecting means (connecting member) is compressed between the first and second substrates by fixing the first substrate (lid) by screwing. This applies a compressive force to the connecting means. The connecting means is pressed against the first substrate by this compressive force, so that the connecting means is fixed to the first substrate. For this reason, if the position of the connection means is not regulated, the position of the connection means on the first substrate is easily shifted, particularly when the connection means is compressed. In order to prevent this, it is necessary to provide a structure for regulating the position of the connecting means. In the above publication, a hole for accommodating the connecting means is formed in the case material as such a structure. When such a structure is provided in the case material, the size of the semiconductor device is increased. In addition, since the position where such a structure is provided in the case material is likely to be limited by the arrangement of the substrate and the case material, it is often difficult to provide the connection means at a desired position in terms of electrical characteristics. That is, the degree of freedom in circuit layout is low.

本発明は、上記の課題に鑑みてなされたものであり、その目的は、大きさが小さく、回路レイアウトの自由度が高く、組立が容易な半導体装置を提供することである。   The present invention has been made in view of the above problems, and an object thereof is to provide a semiconductor device that is small in size, has a high degree of freedom in circuit layout, and is easy to assemble.

本発明の半導体装置は、容器と、実装基板と、蓋と、接続部材と、締具とを有する。容器は開口部を有する。実装基板は容器内に配置されている。実装基板は半導体チップおよび回路基板を有する。回路基板には半導体チップが実装されている。蓋は、裏面と、裏面と反対の表面とを有する。裏面は容器に面している。蓋は容器の開口部を塞いでいる。蓋には貫通孔が設けられている。蓋は回路パターンを有する。回路パターンの少なくとも一部は裏面上に位置している。接続部材は、接合部と、端子部と、螺子部とを有する。接合部は実装基板上に接合されている。端子部は蓋の裏面上において回路パターンに押し付けられている。螺子部は蓋の貫通孔に挿入されている。締具は蓋の表面上に配置されている。締具は螺子孔を有する。螺子孔には接続部材の螺子部が捩じ込まれている。   The semiconductor device of the present invention includes a container, a mounting substrate, a lid, a connection member, and a fastener. The container has an opening. The mounting substrate is disposed in the container. The mounting board has a semiconductor chip and a circuit board. A semiconductor chip is mounted on the circuit board. The lid has a back surface and a surface opposite to the back surface. The back side faces the container. The lid closes the opening of the container. A through hole is provided in the lid. The lid has a circuit pattern. At least a part of the circuit pattern is located on the back surface. The connecting member has a joint portion, a terminal portion, and a screw portion. The joint is joined on the mounting substrate. The terminal portion is pressed against the circuit pattern on the back surface of the lid. The screw part is inserted into the through hole of the lid. The fastener is disposed on the surface of the lid. The fastener has a screw hole. The screw portion of the connecting member is screwed into the screw hole.

本発明によれば、接続部材の位置を規制する構造が、蓋の貫通孔によって簡易に設けられる。よってこのような構造が容器に設けられる場合に比して、半導体装置の大きさを小さくすることができ、かつ回路レイアウトの自由度を高めることができる。   According to the present invention, the structure for regulating the position of the connecting member is simply provided by the through hole of the lid. Therefore, the size of the semiconductor device can be reduced and the degree of freedom in circuit layout can be increased as compared with the case where such a structure is provided in the container.

また蓋の表面上に配置された締具の螺子孔に接続部材が捩じ込まれることで、接続部材を固定するとともに、蓋を固定することができる。よって半導体装置の組立が容易となる。   Further, the connecting member is screwed into the screw hole of the fastener disposed on the surface of the lid, so that the connecting member can be fixed and the lid can be fixed. Therefore, the assembly of the semiconductor device is facilitated.

本発明の実施の形態１における半導体装置の構成を概略的に示す平面図である。1 is a plan view schematically showing a configuration of a semiconductor device in a first embodiment of the present invention. 図１の線ＩＩ−ＩＩに沿う概略的な断面図である。FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG. 1. 図２の半導体装置が有する接続部材の構成を概略的に示す斜視図である。FIG. 3 is a perspective view schematically showing a configuration of a connection member included in the semiconductor device of FIG. 2. 図２の半導体装置が有する締具の構成を概略的に示す斜視図である。FIG. 3 is a perspective view schematically showing a configuration of a fastener included in the semiconductor device of FIG. 2. 図２の変形例を示す概略断面図である。It is a schematic sectional drawing which shows the modification of FIG. 図２の炭化珪素半導体装置に対応する等価回路を示す図である。FIG. 3 is a diagram showing an equivalent circuit corresponding to the silicon carbide semiconductor device of FIG. 2. 図５の炭化珪素半導体装置に対応する等価回路を示す図である。FIG. 6 shows an equivalent circuit corresponding to the silicon carbide semiconductor device of FIG. 5. 図７の回路における電流の流れを説明する図である。It is a figure explaining the flow of the electric current in the circuit of FIG. 本発明の実施の形態２における半導体装置の構成を概略的に示す断面図である。It is sectional drawing which shows schematically the structure of the semiconductor device in Embodiment 2 of this invention.

以下、本発明の実施の形態について図に基づいて説明する。
（実施の形態１）
図１および図２を参照して、パワーデバイスモジュール１０１（炭化珪素半導体装置）は、容器１０と、実装基板４０と、蓋５０と、金属柱６０（接続部材）と、螺子キャップ７０（締具）と、はんだ部９１、９２と、主端子８１〜８３（主端子８０と総称する）と、制御端子８９とを有する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
1 and 2, power device module 101 (silicon carbide semiconductor device) includes container 10, mounting substrate 40, lid 50, metal pillar 60 (connection member), and screw cap 70 (fastener). ), Solder portions 91 and 92, main terminals 81 to 83 (collectively referred to as main terminal 80), and a control terminal 89.

容器１０は、蓋５０によって塞がれた開口部ＯＰを有する。容器１０は、底面をなすベース１１と、側面をなす枠１２とを有する。ベース１１は、導体からなることが好ましく、金属からなることがより好ましく、たとえば銅からなる。枠１２は、絶縁体からなることが好ましく、たとえば樹脂からなる。   The container 10 has an opening OP that is closed by a lid 50. The container 10 has a base 11 forming a bottom surface and a frame 12 forming a side surface. The base 11 is preferably made of a conductor, more preferably made of metal, for example, copper. The frame 12 is preferably made of an insulator, for example, resin.

実装基板４０は容器１０内に配置されている。実装基板４０は、回路基板２０と、半導体チップ３０と、ボンディングワイヤ３１と、はんだ部３２とを有する。実装基板４０の回路基板２０は、ベース１１上にはんだ部９１によって接合されている。   The mounting substrate 40 is disposed in the container 10. The mounting board 40 includes a circuit board 20, a semiconductor chip 30, a bonding wire 31, and a solder part 32. The circuit board 20 of the mounting board 40 is joined to the base 11 by a solder portion 91.

回路基板２０は、絶縁基板２１と、表面パターン２２と、裏面パターン２３とを有する。絶縁基板２１は、絶縁体からなり、たとえばセラミック基板である。表面パターン２２および裏面パターン２３は、導体からなり、金属からなることが好ましく、たとえば銅からなる。   The circuit board 20 has an insulating substrate 21, a front surface pattern 22, and a back surface pattern 23. The insulating substrate 21 is made of an insulator and is, for example, a ceramic substrate. The front surface pattern 22 and the back surface pattern 23 are made of a conductor, preferably made of metal, for example, copper.

半導体チップ３０は回路基板２０上にはんだ部３２によって実装されている。はんだ部３２によって半導体チップ３０は回路基板２０に電気的に接続されている。またさらなる電気的接続のために、図２に示すように、半導体チップ３０と表面パターン２２とがボンディングワイヤ３１によって接続されていてもよい。ボンディングワイヤ３１は、たとえばアルミニウムからなる。半導体チップ３０は、パワーデバイス用のものである。半導体チップ３０は、たとえば、ゲートを有するトランジスタであり、本実施の形態においてはＩＧＢＴ（Insulated Gate Bipolar Transistor）である。   The semiconductor chip 30 is mounted on the circuit board 20 by a solder portion 32. The semiconductor chip 30 is electrically connected to the circuit board 20 by the solder portion 32. For further electrical connection, the semiconductor chip 30 and the surface pattern 22 may be connected by a bonding wire 31 as shown in FIG. The bonding wire 31 is made of, for example, aluminum. The semiconductor chip 30 is for a power device. The semiconductor chip 30 is a transistor having a gate, for example, and is an IGBT (Insulated Gate Bipolar Transistor) in the present embodiment.

蓋５０は、裏面Ｓ１と、裏面Ｓ１と反対の表面Ｓ２とを有する。裏面Ｓ１は容器１０に面している。蓋５０は板状部５１および回路パターン５２を有する。板状部５１は絶縁体からなる。板状部５１は、回路パターン５２を保持する絶縁基板としての機能を有する。回路パターン５２は、導体からなり、金属からなることが好ましく、たとえば銅からなる。回路パターン５２の少なくとも一部は裏面Ｓ１上に位置している。回路パターン５２は、図２に示すようにその全体が裏面Ｓ１上に位置してもよい。あるいは回路パターン５２の一部が板状部５１の内部に埋め込まれていてもよい。蓋５０には貫通孔ＴＨが設けられている。   The lid 50 has a back surface S1 and a surface S2 opposite to the back surface S1. The back surface S1 faces the container 10. The lid 50 has a plate-like portion 51 and a circuit pattern 52. The plate-like portion 51 is made of an insulator. The plate-like portion 51 functions as an insulating substrate that holds the circuit pattern 52. The circuit pattern 52 is made of a conductor and is preferably made of metal, for example, copper. At least a part of the circuit pattern 52 is located on the back surface S1. The entire circuit pattern 52 may be located on the back surface S1 as shown in FIG. Alternatively, a part of the circuit pattern 52 may be embedded in the plate-like portion 51. The lid 50 is provided with a through hole TH.

金属柱６０（図３）は、ピン部６１（接合部）と、フランジ部６２（端子部）と、螺子部６３とを有する。ピン部６１は実装基板４０上に位置Ｐ１において接合されている。本実施の形態においてはピン部６１は実装基板４０の回路基板２０に接合されている。螺子部６３は蓋５０の貫通孔ＴＨに挿入されている。   The metal column 60 (FIG. 3) includes a pin portion 61 (joining portion), a flange portion 62 (terminal portion), and a screw portion 63. The pin portion 61 is joined to the mounting substrate 40 at the position P1. In the present embodiment, the pin portion 61 is bonded to the circuit board 20 of the mounting board 40. The screw part 63 is inserted into the through hole TH of the lid 50.

螺子キャップ７０（図４）は、蓋５０の表面Ｓ２上に配置されている。螺子キャップ７０は螺子孔ＳＨを有する。螺子孔ＳＨには金属柱６０の螺子部６３が捩じ込まれている。螺子キャップ７０と金属柱６０のフランジ部６２とは貫通穴ＴＨの縁において蓋５０を挟んでいる。螺子キャップ７０が締められることによって、螺子キャップ７０とフランジ部６２との間隔が小さくなる。その結果、フランジ部６２が蓋５０の裏面Ｓ１上において回路パターン５２に押し付けられている。螺子キャップ７０は、蓋５０の表面Ｓ２において金属柱６０の螺子部６３が露出しないように、表面Ｓ２上において螺子部６３を覆っている。螺子キャップ７０は、絶縁体からなることが好ましく、たとえば樹脂からなる。   The screw cap 70 (FIG. 4) is disposed on the surface S <b> 2 of the lid 50. The screw cap 70 has a screw hole SH. The screw part 63 of the metal pillar 60 is screwed into the screw hole SH. The screw cap 70 and the flange portion 62 of the metal column 60 sandwich the lid 50 at the edge of the through hole TH. When the screw cap 70 is tightened, the interval between the screw cap 70 and the flange portion 62 is reduced. As a result, the flange portion 62 is pressed against the circuit pattern 52 on the back surface S <b> 1 of the lid 50. The screw cap 70 covers the screw part 63 on the surface S <b> 2 so that the screw part 63 of the metal pillar 60 is not exposed on the surface S <b> 2 of the lid 50. The screw cap 70 is preferably made of an insulator, for example, resin.

本実施の形態においては、半導体チップ３０の主電流を制御する機能を有するゲート電極が、表面パターン２２および金属柱６０を介して制御端子８９に接続されている。これにより半導体チップ３０は、金属柱６０のピン部６１を介して入力された外部信号に応じて、主電流のスイッチングを行うことができる。   In the present embodiment, the gate electrode having the function of controlling the main current of the semiconductor chip 30 is connected to the control terminal 89 via the surface pattern 22 and the metal pillar 60. As a result, the semiconductor chip 30 can switch the main current in accordance with an external signal input via the pin portion 61 of the metal pillar 60.

本実施の形態のパワーデバイスモジュール１０１によれば、蓋５０の表面Ｓ２上に配置された螺子キャップ７０の螺子孔ＳＨに金属柱６０が捩じ込まれている。よって螺子キャップ７０を締めることによって、金属柱６０を固定するとともに、蓋５０も固定することができる。よってパワーデバイスモジュール１０１の組立が容易となる。   According to the power device module 101 of the present embodiment, the metal pillar 60 is screwed into the screw hole SH of the screw cap 70 disposed on the surface S2 of the lid 50. Therefore, by tightening the screw cap 70, the metal pillar 60 can be fixed and the lid 50 can also be fixed. Therefore, the power device module 101 can be easily assembled.

また金属柱６０の位置を規制する構造が蓋５０の貫通孔ＴＨによって簡易に設けられる。よってこのような構造が容器１０に設けられる場合に比して、パワーデバイスモジュール１０１の大きさを小さくすることができ、また回路レイアウトの自由度を高めることができる。回路レイアウトの自由度が高められることによる利点の例について、以下に具体的に説明する。   Further, a structure for regulating the position of the metal pillar 60 is simply provided by the through hole TH of the lid 50. Therefore, compared with the case where such a structure is provided in the container 10, the size of the power device module 101 can be reduced, and the degree of freedom in circuit layout can be increased. An example of an advantage obtained by increasing the degree of freedom of circuit layout will be specifically described below.

本実施の形態においては、半導体チップ３０のゲート電極へ制御信号を入力するために、制御端子８９につながった金属柱６０が回路基板２０の表面パターン２２に位置Ｐ１で接続されている。この接続位置を位置Ｐ１からより主端子８０に近い位置Ｐ２に変更することで得られるパワーデバイスモジュール１０２（図５）においては、回路における負帰還がより強められる。よって、金属柱６０が表面パターン２２に接続される位置が位置Ｐ１およびＰ２の間で調整されることで、負帰還を調整することができる。負帰還を調整することで、パワーデバイスモジュールの特性を調整することができる。   In the present embodiment, in order to input a control signal to the gate electrode of the semiconductor chip 30, the metal pillar 60 connected to the control terminal 89 is connected to the surface pattern 22 of the circuit board 20 at the position P1. In the power device module 102 (FIG. 5) obtained by changing the connection position from the position P1 to the position P2 closer to the main terminal 80, negative feedback in the circuit is further strengthened. Therefore, the negative feedback can be adjusted by adjusting the position where the metal pillar 60 is connected to the surface pattern 22 between the positions P1 and P2. The characteristics of the power device module can be adjusted by adjusting the negative feedback.

図６の等価回路はパワーデバイスモジュール１０１（図２）に対応しており、負帰還が実質的に無視できる状態を示している。図７の等価回路はパワーデバイスモジュール１０２（図５）に対応しており、図６におけるエミッタ配線およびゲート配線の間が一点鎖線で示すように離されることによって負帰還が無視できない程度に強められた状態を示している。負帰還の強さは、表面パターン２２またはボンディングワイヤ３１に起因した寄生インダクタンスの大きさに対応している。なお図６および図７においては、負荷として誘導発電機ＩＭが接続されている。   The equivalent circuit of FIG. 6 corresponds to the power device module 101 (FIG. 2), and shows a state in which negative feedback can be substantially ignored. The equivalent circuit of FIG. 7 corresponds to the power device module 102 (FIG. 5), and the negative feedback is strengthened to a degree that cannot be ignored by separating the emitter wiring and the gate wiring in FIG. Shows the state. The strength of the negative feedback corresponds to the magnitude of the parasitic inductance caused by the surface pattern 22 or the bonding wire 31. 6 and 7, an induction generator IM is connected as a load.

トランジスタの入力電圧Ｖｇは、負帰還有りの場合、
Ｖｇ＝Ｖｇ１＝ＶＧ−ＶＬ＝ＶＧ−ＬＳ×ｄｉ／ｄｔ
であり、負帰還無しの場合、
Ｖｇ＝Ｖｇ２
である。ここで、iは出力電流であり、ＶＧは外部入力電圧であり、Ｖｇはトランジスタの入力電圧(駆動電圧)であり、ＬＳは寄生インダクタンスであり、ＶＬは寄生インダクタンスＬＳにより発生するドロップ電圧でありＶＬ＝ＬＳ×ｄｉ／ｄｔである。よって負帰還有の場合、ＶＬが負帰還となり、ｉおよびＬＳが大きいほど負帰還が強くなる（Ｖｇ１＜Ｖｇ２）。 The input voltage Vg of the transistor is
Vg = Vg1 = VG-VL = VG-LS × di / dt
If there is no negative feedback,
Vg = Vg2
It is. Here, i is an output current, VG is an external input voltage, Vg is an input voltage (drive voltage) of the transistor, LS is a parasitic inductance, and VL is a drop voltage generated by the parasitic inductance LS. VL = LS × di / dt. Therefore, when negative feedback is present, VL becomes negative feedback, and the larger i and LS, the stronger the negative feedback (Vg1 <Vg2).

ｄｉ／ｄｔは、トランジスタをターンオンまたはターンオフする時に大きな絶対値を有する。   di / dt has a large absolute value when the transistor is turned on or off.

図８を参照して、トランジスタの増幅率をｈｆｅ、入力電流をｉｇとすると、
ｉ＝ｈｆｅ×ｉｇ
となる。入力電流ｉｇのうちコレクタへ流れる電流をｉｇｃとしエミッタへ流れる電流をｉｇｅとすると、キルヒホッフの法則より、
ｉ＝ｈｆｅ（（ＶＧ−Ｖｇ１−ＶＬ）／Ｒ−ｉｇｃ）
が満たされる。よって、ＶＬが大きくなればｉは小さくなる。またｄｉ／ｄｔはｉの時間変化率なので、ｉが小さくなるとｄｉ／ｄｔも小さくなる。ターンオフのときは、図８における電流および電圧の向き（符号）は図中矢印とは逆になる。またサージ電圧は、回路のインピーダンスＬとターンオフ時の−ｄｉ／ｄｔとの積、すなわちＬ×（−ｄｉ／ｄｔ）に対応する。よって負帰還が強められることによりｄｉ／ｄｔが小さくなれば、サージ電圧も小さくなる。 Referring to FIG. 8, when the amplification factor of the transistor is hfe and the input current is ig,
i = hfe × ig
It becomes. Assuming that the current flowing to the collector of the input current ig is igg and the current flowing to the emitter is igg, from Kirchhoff's law,
i = hfe ((VG−Vg1−VL) / R−igc)
Is satisfied. Therefore, as VL increases, i decreases. Moreover, since di / dt is a rate of change of i with time, di / dt also decreases as i decreases. At the turn-off time, the directions (signs) of the current and voltage in FIG. 8 are opposite to the arrows in the figure. The surge voltage corresponds to the product of the circuit impedance L and -di / dt at turn-off, that is, L × (-di / dt). Therefore, if di / dt is reduced by strengthening negative feedback, the surge voltage is also reduced.

以上のように、ｄｉ／ｄｔまたはサージ電圧のようなパワーデバイスモジュールの特性が、負帰還の強さによって調整され得る。本実施の形態によれば、金属柱６０（図２または図５）の位置の自由度が高いので、金属柱６０の位置調整により負帰還の強さを容易に調整することができる。よってパワーデバイスモジュールの特性を容易に調整することができる。   As described above, the characteristics of the power device module such as di / dt or surge voltage can be adjusted by the strength of the negative feedback. According to the present embodiment, since the degree of freedom of the position of the metal column 60 (FIG. 2 or FIG. 5) is high, the strength of the negative feedback can be easily adjusted by adjusting the position of the metal column 60. Therefore, the characteristics of the power device module can be easily adjusted.

（実施の形態２）
図９に示すように、パワーデバイスモジュール１０３（炭化珪素半導体装置）においては、パワーデバイスモジュール１０１は、半導体チップ３０に直接接合されたリード部材９０をさらに有する。リード部材９０は、導体からなり、好ましくは金属からなり、たとえば銅からなる。リード部材９０と半導体チップ３０との接合は、たとえば、超音波接合により行うことができる。金属柱６０のピン部６１はリード部材９０を介して半導体チップ３０に接合されている。ピン部６１とリード部材９０との接合は、たとえばはんだ付けにより行うことができる。なお、他の構成については、上述した実施の形態１の構成とほぼ同じであるため、同一または対応する要素について同一の符号を付し、その説明を繰り返さない。 (Embodiment 2)
As shown in FIG. 9, in power device module 103 (silicon carbide semiconductor device), power device module 101 further includes a lead member 90 that is directly bonded to semiconductor chip 30. The lead member 90 is made of a conductor, preferably made of metal, for example, copper. The lead member 90 and the semiconductor chip 30 can be joined by, for example, ultrasonic joining. The pin portion 61 of the metal pillar 60 is joined to the semiconductor chip 30 via the lead member 90. The pin portion 61 and the lead member 90 can be joined by, for example, soldering. Since other configurations are substantially the same as those of the first embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof is not repeated.

本実施の形態によれば、金属柱６０を、表面パターン２２を介することなく半導体チップ３０に電気的に接続することができる。また金属柱６０が半導体チップ３０にリード部材９０を介して接続されることで、金属柱６０の接続を容易に行なうことができる。なおリード部材９０を省略して、金属柱６０が半導体チップ３０に直接接合されてもよい。   According to the present embodiment, the metal pillar 60 can be electrically connected to the semiconductor chip 30 without using the surface pattern 22. Further, since the metal pillar 60 is connected to the semiconductor chip 30 via the lead member 90, the metal pillar 60 can be easily connected. The lead member 90 may be omitted, and the metal pillar 60 may be directly bonded to the semiconductor chip 30.

上記各実施の形態においては、金属柱６０は制御端子８９に接続されるが、金属柱６０は、主電流の端子である主端子８０に接続されてもよい。この場合、金属柱６０中を主電流が流れることができる。また半導体チップ３０は、たとえばＭＩＳＦＥＴ（Metal Insulator Semiconductor Field Effect Transistor）など、ＩＧＢＴ以外のトランジスタであってもよく、またダイオードなど、トランジスタ以外の半導体チップであってもよい。   In each of the above embodiments, the metal column 60 is connected to the control terminal 89, but the metal column 60 may be connected to a main terminal 80 which is a main current terminal. In this case, the main current can flow through the metal pillar 60. The semiconductor chip 30 may be a transistor other than an IGBT such as a MISFET (Metal Insulator Semiconductor Field Effect Transistor), or may be a semiconductor chip other than a transistor such as a diode.

今回開示された実施の形態はすべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は上記した説明ではなくて特許請求の範囲によって示され、特許請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。   The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

１０ 容器、１１ ベース、１２ 枠、２０ 回路基板、２１ 絶縁基板、２２ 表面パターン、２３ 裏面パターン、３０ 半導体チップ、３１ ボンディングワイヤ、３２，９１，９２ はんだ部、４０ 実装基板、５０ 蓋、５１ 板状部、５２ 回路パターン、６０ 金属柱（接続部材）、６１ ピン部（接合部）、６２ フランジ部（端子部）、６３ 螺子部、７０ 螺子キャップ（締具）、８０，８１〜８３ 主端子、８９ 制御端子、９０ リード部材、１０１，１０２，１０３ パワーデバイスモジュール（半導体装置）、ＯＰ 開口部、Ｓ１ 裏面、Ｓ２ 表面、ＳＨ 螺子孔、ＴＨ 貫通孔。   10 containers, 11 bases, 12 frames, 20 circuit boards, 21 insulating boards, 22 surface patterns, 23 back patterns, 30 semiconductor chips, 31 bonding wires, 32, 91, 92 solder parts, 40 mounting boards, 50 lids, 51 boards Shaped part, 52 circuit pattern, 60 metal pillar (connecting member), 61 pin part (joining part), 62 flange part (terminal part), 63 screw part, 70 screw cap (fastener), 80, 81-83 main terminal 89 control terminal, 90 lead member, 101, 102, 103 power device module (semiconductor device), OP opening, S1 back surface, S2 surface, SH screw hole, TH through hole.

Claims (5)

開口部を有する容器と、
前記容器内に配置された実装基板とを備え、前記実装基板は、半導体チップと、前記半導体チップが実装された回路基板とを有し、さらに
前記容器に面する裏面と、前記裏面と反対の表面とを有し、前記容器の前記開口部を塞ぐ蓋を備え、前記蓋には貫通孔が設けられており、前記蓋は回路パターンを有し、前記回路パターンの少なくとも一部は前記裏面上に位置し、さらに
前記実装基板上に接合された接合部と、前記蓋の前記裏面上において前記回路パターンに押し付けられた端子部と、前記蓋の前記貫通孔に挿入された螺子部とを有する接続部材と、
前記蓋の前記表面上に配置された締具とを備え、前記締具は、前記接続部材の前記螺子部が捩じ込まれた螺子孔を有する、半導体装置。 A container having an opening;
A mounting board disposed in the container, the mounting board having a semiconductor chip and a circuit board on which the semiconductor chip is mounted, and a back surface facing the container, opposite to the back surface A lid that closes the opening of the container, the lid is provided with a through hole, the lid has a circuit pattern, and at least a part of the circuit pattern is on the back surface And a joint portion joined to the mounting substrate, a terminal portion pressed against the circuit pattern on the back surface of the lid, and a screw portion inserted into the through-hole of the lid. A connecting member;
And a fastener disposed on the surface of the lid, wherein the fastener has a screw hole into which the screw portion of the connection member is screwed. 前記接続部材の前記接合部は、前記実装基板の前記回路基板に接合されている、請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the joint portion of the connection member is joined to the circuit board of the mounting substrate. 前記接続部材の前記接合部は、前記実装基板の前記半導体チップに接合されている、請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the joint portion of the connection member is joined to the semiconductor chip of the mounting substrate. 前記半導体チップに直接接合されたリード部材をさらに備え、
前記接続部材の前記接合部は、前記リード部材を介して前記半導体チップに接合されている、請求項３に記載の半導体装置。 A lead member directly joined to the semiconductor chip;
The semiconductor device according to claim 3, wherein the joint portion of the connection member is joined to the semiconductor chip via the lead member. 前記半導体チップは、前記接続部材の前記接合部を介して入力された外部信号に応じて主電流のスイッチングを行うものである、請求項１〜４のいずれか１項に記載の半導体装置。   5. The semiconductor device according to claim 1, wherein the semiconductor chip performs main current switching in accordance with an external signal input through the joint portion of the connection member.
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