JP2014112457A5

JP2014112457A5 -

Info

Publication number: JP2014112457A5
Application number: JP2014002556A
Authority: JP
Filing date: 2014-01-09
Publication date: 2014-07-31

Claims

A plurality of circuit blocks;
A control circuit that controls a start timing when the plurality of circuit blocks perform circuit operation;
The control circuit adjusts the start timing for each of the plurality of circuit blocks when a circuit operation in which the plurality of circuit blocks consumes a large amount of power supply current is performed in parallel within a predetermined period, whereby a power supply current waveform is predetermined. The semiconductor device is controlled so as to have a waveform shape of

The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the predetermined waveform shape is a sine half-wave waveform.

The semiconductor device according to claim 1,
When the number of circuit operations performed in parallel by the plurality of circuit blocks is N, and the time interval between the circuit operations performed I-th and I + 1-th is T (I),
The time interval T (I) is
T (I) = T (N−I) and I = N / 2 or less, and T (I) <T (I−1)
The semiconductor device characterized by satisfy | filling.

The semiconductor device according to claim 1,
The circuit operation performed in parallel by the plurality of circuit blocks is the same type of operation, respectively.

The semiconductor device according to claim 1,
Each of the plurality of circuit blocks is a DRAM memory bank formed on the same semiconductor chip,
A semiconductor device characterized in that a circuit operation performed in parallel by the plurality of DRAM memory banks is a refresh operation.

The semiconductor device according to claim 1,
Each of the plurality of circuit blocks is a DRAM chip mounted on the same module wiring board,
The circuit operation performed in parallel by the plurality of DRAM chips is a refresh operation,
2. The semiconductor device according to claim 1, wherein the control circuit is realized by a buffer IC mounted on the module wiring board.

A method of operating a semiconductor device having a plurality of circuit blocks,
Controlling the start timing when the plurality of circuit blocks perform circuit operation;
The control is
When the circuit operations in which the plurality of circuit blocks consume a large amount of power supply current are performed in parallel within a fixed period, the power supply current waveform has a predetermined waveform shape by adjusting the start timing for each of the plurality of circuit blocks. A method for operating a semiconductor device, characterized in that control is performed as described above .

The operation method of the semiconductor device according to claim 1.
The method of operating a semiconductor device, wherein the predetermined waveform shape is a sine half-wave waveform.

A plurality of semiconductor devices;
A control device that controls a start timing when the plurality of semiconductor devices perform device operations;
The control device adjusts the start timing for each of the plurality of semiconductor devices when the plurality of semiconductor devices perform a device operation that consumes a large amount of power current in parallel within a predetermined period, whereby a power source current waveform is predetermined. An information processing system that is controlled so as to have a waveform shape.

The information processing system according to claim 9,
The information processing system according to claim 1, wherein the predetermined waveform shape is a sine half-wave waveform.

The information processing system according to claim 9,
When the number of device operations performed in parallel by the plurality of semiconductor devices is N, and the time interval between the I-th and I + 1-th device operations is T (I),
The time interval T (I) is
T (I) = T (N−I) and I = N / 2 or less, and T (I) <T (I−1)
An information processing system characterized by satisfying

The information processing system according to claim 9,
The information processing system, wherein the plurality of semiconductor devices and the control device are mounted on a wiring board.

The information processing system according to claim 9,
Each of the plurality of semiconductor devices is a DRAM chip mounted on the same wiring board,
The apparatus operation performed in parallel by the plurality of DRAM chips is a refresh operation.

The information processing system according to claim 9,
Each of the plurality of semiconductor devices is a DRAM module mounted on the same wiring board,
The apparatus operation performed in parallel by the plurality of DRAM modules is a refresh operation.

A plurality of memory banks each including a plurality of word lines, a plurality of bit lines, and a plurality of DRAM memory cells disposed at intersections of the plurality of word lines and the plurality of bit lines;
A refresh control circuit for controlling a refresh operation of the plurality of memory banks,
Each of the plurality of memory banks activates and / or deactivates a predetermined word line in the memory bank using a refresh signal corresponding to the memory bank as a trigger,
The refresh control circuit receives a common refresh signal generated in response to an external command input or an internal command generation, and shifts the common refresh signal at different timings for the plurality of memory banks. The refresh signal having a different timing for each memory bank is generated, and at this time, the timing of the refresh signal is adjusted so that a power supply current waveform accompanying the refresh operation has a predetermined waveform shape apparatus.

The semiconductor device according to claim 15, wherein
The semiconductor device according to claim 1, wherein the predetermined waveform shape is a sine half-wave waveform.

The semiconductor device according to claim 15, wherein
When the number of the plurality of memory banks is N, and the timing interval of the refresh signal generated toward the Ith and I + 1th different memory banks is T (I),
The timing interval T (I) is
T (I) = T (N−I) and I = N / 2 or less, and T (I) <T (I−1)
The semiconductor device characterized by satisfy | filling.

The semiconductor device according to claim 15, wherein
The refresh control circuit includes a plurality of delay circuits that sequentially delay the common refresh signal by serial connection,
2. The semiconductor device according to claim 1, wherein the timing of the refresh signal is generated using delay times of the plurality of delay circuits.

The semiconductor device according to claim 18.
The plurality of delay circuits include a flip-flop circuit that performs a shift operation according to a clock signal,
2. The semiconductor device according to claim 1, wherein the timing of the refresh signal is generated using the number of stages of the flip-flop circuit and / or a propagation delay time.

The semiconductor device according to claim 15, wherein
2. The semiconductor device according to claim 1, wherein the refresh control circuit includes a plurality of variable delay circuits capable of sequentially delaying the common refresh signal by serial connection and changing each delay time by setting.