JP2014112457A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing power source noise.SOLUTION: A DRAM memory comprises 8 memory banks MBK0 to MBK7, for instance. The DRAM memory is controlled so as to perform refresh operation for each of the memory banks MBK0 to MBK7 with different time difference respectively. Concretely, time difference tRF_1 between the MBK0 and MBK1 which become an initial stage is made large, time difference is stepwise reduced up to the time difference tRF_4 between the MBK3 and MBK4 which become an intermediate stage, and after that adversely the difference is stepwise increased up to time difference tRF_7 between the MBK6 and MBK7 which become a final stage. Thus, a power source current waveform associated with the refresh operation becomes sinusoidal, thereby power source noise can be reduced in accordance with reduction in harmonic components.

Description

  The present invention relates to a semiconductor device and an information processing system, and more particularly to a technique for reducing power supply noise in a semiconductor device such as a memory device or a processor device or an information processing system combining such semiconductor devices.

  For example, Patent Document 1 describes a memory control system that reduces excessive power consumption by shifting the refresh timing for each memory bank in a memory including a plurality of memory banks. Specifically, the refresh timing for each memory bank is shifted in units of one cycle of the clock cycle by using the shift operation of the flip-flop circuit.

  Similarly to Patent Document 1, Patent Document 2 discloses a memory control circuit that reduces excessive power consumption by shifting the refresh timing for each memory bank with respect to a memory including a plurality of memory banks. Have been described. The memory control circuit includes a control register and a counter that performs a shift operation, a bank separation circuit that receives these outputs and performs a logical operation, and the like, and shifts the refresh timing for each memory bank in units of a fixed period by the counter. Furthermore, for example, it is possible to perform refreshing by two banks while shifting the refresh timing by setting the control register.

  Further, Patent Document 3 describes a semiconductor memory device configured to refresh only a partial array selected according to an external command when performing self-refresh. Specifically, an internal address generation circuit that generates an internal refresh address operates a range of address bits in accordance with an external command. By making the partial array selectable in this way, the period between distributed refreshes can be extended and the power consumption can be reduced.

JP-A-6-214881 Japanese Patent Laid-Open No. 7-122065 JP 2003-91989

  Generally, in various semiconductor devices (semiconductor devices), as the generation progresses, lower power supply voltage and higher speed are performed, so that power supply noise due to a sudden current change greatly hinders stable device operation. It has become to. For example, in a semiconductor memory device such as a DDR-SDRAM (Double Data Rate-Synchronous Dynamic Random Access Memory), similarly, as the generation progresses to DDR, DDR2, and DDR3, the design technique of power supply noise holds the key to stable operation. It is becoming.

  The DRAM power supply is broadly divided into a core system (VDD) and an I / O system (VDDQ). With regard to the DRAM core system power supply, a refresh operation with a large current consumption is a main noise factor. The refresh operation is a recharge of electric charge to the data storage capacitor which is a storage unit of the DRAM, and this is an operation that must be performed within a certain time interval in order for the DRAM to retain the stored contents. It is.

  This refresh operation is performed, for example, by issuing a REF at a fixed time interval when an auto-refresh command (REF command) is issued from the outside, or in the case of a so-called self-refresh operation. When the REF command is issued, normally, specific word lines in all banks (Bank) in the DRAM are simultaneously activated. Specifically, the REF command is internally converted into an ACT command (word line activation) and a PRE command (word line deactivation and bit line precharge), and this ACT command is applied to all Banks. And the PRE command are issued. Further, the specific word line (word line address) at this time is automatically generated by a built-in refresh counter circuit or the like.

  Thus, when specific word lines in all banks are activated simultaneously, a large current consumption flows instantaneously and a large power supply noise occurs. FIG. 19 shows an example of a refresh operation in a semiconductor device studied as a premise of the present invention, and FIGS. 19A and 19B are explanatory diagrams showing different operation examples. 20 shows an example of the power supply waveform in FIG. 19, where (a) shows the power supply current waveform and (b) shows the power supply voltage waveform. Here, for example, an 8-bank semiconductor device (DRAM) is taken as an example.

  First, in FIG. 19B (referred to as [CaseB]), ACT commands are issued simultaneously for all banks (Bank 0 to Bank 7), and after a predetermined time has passed, PRE commands are issued simultaneously for all banks. In this case, as shown in [Case B] in FIG. 20A, a large current is generated when the ACT command is issued and when the PRE command is issued. As shown in [Case B] in FIG. 20B, the power supply voltage greatly fluctuates with the rapid generation of current, which becomes power supply noise and adversely affects device operation.

In order to reduce such power supply noise, it is beneficial to use the techniques described in Patent Documents 1 and 2. In these techniques, as shown in FIG. 19A (referred to as [Case A]), the interval at which the ACT command is issued is shifted by tRF_min for each bank. Similarly, the interval at which the PRE command is issued is also different for each bank. Is shifted by tRF_min. Here, a period “tRFC_min” that is a series of cycles is a period that is generally determined by specifications as a period that must be secured at least from the issuance of the REF command to the issuance of the next REF command. The period “tRC” is also a period that is generally determined by specifications as a period that must be secured at least from the issuance of the ACT command to the issuance of the PRE command. In order to satisfy this specification, it is necessary to issue the ACT command and the PRE command to all banks within “tRFC_min”. However, if the above-described tRF_min is set within the value calculated by the equation (1). Can meet this specification.
tRF_min = (tRFC_min−tRC) / (number of banks−1) (1)
When the method as shown in FIG. 19A is used, the current accompanying the refresh operation can be averaged as shown in [Case A] in FIG. 20A. Current and the like can be greatly reduced. As a result, as shown in [Case A] in FIG. 20B, the power supply voltage is less swayed than [Case B], and power noise can be reduced.

  However, in the systems such as Patent Documents 1 and 2, a trapezoidal current waveform is generated as shown in [Case A] of FIG. The noise frequency of the refresh noise has a 10 MHz band as a fundamental wave because the time required for refresh is on the order of, for example, 100 ns. In general, the impedance of the power feeding system is mainly composed of inductance (L) in the several tens of MHz band (that is, the higher the frequency, the larger the impedance increases), so the magnitude of the harmonic component greatly affects the amount of noise. To do. In that respect, the trapezoidal waveform has a large harmonic component, and particularly when the generation of the semiconductor device further progresses, there is a possibility that the stable operation of the device is greatly hindered by the power supply noise accompanying the harmonic component.

  Accordingly, one object of the present invention is to provide a semiconductor device and an information processing system capable of reducing power supply noise. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A semiconductor device according to an embodiment of the present invention instructs a plurality of circuit units that perform circuit operations in parallel, and a start timing and / or an end timing when each circuit unit performs a circuit operation with a large amount of current. And a control unit. When instructing the start timing and / or end timing, the control unit gives instructions at different timings for each circuit unit. The timing at this time is adjusted so that the power supply current waveform accompanying the start and / or end of the operation of each circuit unit becomes a sine wave-like waveform. Specifically, for example, the time difference from the start timing of the first circuit unit, which is the first number, to the start timing of the second circuit unit is large, and then this time difference is stepped toward the intermediate number. After that, the time difference is adjusted so as to increase stepwise toward the last number.

  As a result, harmonic components of the power supply current waveform can be reduced, and power supply noise can be reduced. Each circuit unit may be, for example, each circuit block in one semiconductor chip, or each device (for example, a semiconductor IC) included in one system. More preferably, for example, each circuit unit can be a memory bank in one DRAM chip, and the control unit can be a refresh control circuit. In this case, the refresh control circuit adjusts the refresh start timing and / or refresh end timing for each memory bank so as to have the time difference as described above. As a result, it is possible to easily reduce power supply noise accompanying refresh, which is usually a large noise source. This principle will be described in more detail with reference to FIG. FIG. 8A shows a power supply system impedance profile of a general semiconductor chip. The tens of MHz band is a region where the inductance of the substrate or LSI package is dominant, and it is generally difficult to lower the impedance here (for example, a high-cost package is required), so the impedance Z in this frequency range Indicates a rising characteristic (inductance of inductance: ZL = 2πf · L). Since the noise voltage is determined by the product of the current and the impedance, it is desirable for reducing the noise voltage to keep the current component low in the frequency range where the impedance increases. For this reason, a sinusoidal mountain-shaped waveform such as a solid line is preferable rather than a current waveform close to a rectangular wave as indicated by a broken line in FIG. 8C. By changing the waveform in this way, FIG. As shown in (b), the harmonic component of the current can be reduced, and as a result, the noise voltage can be kept low.

  The effects obtained by typical inventions among the inventions disclosed in this application will be briefly described. Power supply noise in a semiconductor device and an information processing system can be reduced.

FIG. 2 shows an example of the configuration of the semiconductor device according to the first embodiment of the present invention, where (a) is an overall block diagram, and (b) is a circuit diagram showing an example of the configuration in the memory bank of (a). . FIG. 2 is an explanatory diagram showing an example of a refresh operation method in the semiconductor device of FIG. 1. 2 shows an example of a power supply waveform in FIG. 2, (a) shows a power supply current waveform in the case of FIG. 19 (a) as a comparative example, (b) shows a power supply current waveform in the case of FIG. It is a power supply voltage waveform corresponding to a) and (b). In the semiconductor device of FIG. 1, one example of the refresh control circuit is shown, (a) is a circuit diagram showing a configuration example of the main part, and (b) is a waveform diagram showing an operation example of (a). FIG. 2 shows another example of the refresh control circuit in the semiconductor device of FIG. 1, (a) is a circuit diagram showing a configuration example of the main part, and (b) is a waveform diagram showing an operation example of (a). It is. FIG. 10 is a circuit diagram showing still another configuration example of a main part in the refresh control circuit in the semiconductor device of FIG. 1. FIG. 5 is a circuit diagram showing a configuration example of a main part of a refresh control circuit of FIG. 1 in a semiconductor device according to a second embodiment of the present invention. 4A and 4B are diagrams illustrating the principle of the effect of the present invention, in which FIG. 4A is a graph illustrating an example of frequency characteristics of a power feeding system impedance, and FIG. 4B is a diagram illustrating a current spectrum of a current waveform of FIG. It is explanatory drawing which shows the basic concept in the semiconductor device or information processing system by Embodiment 3 of this invention. FIG. 10 is a block diagram showing a configuration example of a semiconductor device according to a third embodiment of the present invention. In the information processing system by Embodiment 3 of this invention, it is an external view which shows the example of a structure. It is a block diagram which shows the other structural example in the information processing system by Embodiment 3 of this invention. In the information processing system by Embodiment 3 of this invention, it is an external view which shows the further another structural example. In the semiconductor device by Embodiment 3 of this invention, it is a top view which shows the further another structural example. FIG. 10 is an explanatory diagram showing an operation example of the semiconductor device of FIG. In the semiconductor device by Embodiment 3 of this invention, it is a perspective view which shows the further another structural example. In the semiconductor device or information processing system according to Embodiment 3 of the present invention, still another example is shown, (a) is a block diagram showing a configuration example thereof, and (b) is an operation example of (a). It is explanatory drawing shown. In the semiconductor device or information processing system by Embodiment 4 of this invention, the basic concept is shown, (a) is explanatory drawing which shows the operation example, (b) is a power supply at the time of using (a) It is a wave form diagram which shows an example of a current waveform. An example of the refresh operation in the semiconductor device studied as a premise of the present invention is shown, and (a) and (b) are explanatory diagrams showing different operation examples. 19 shows an example of a power supply waveform in FIG. 19, where (a) is a power supply current waveform and (b) is a power supply voltage waveform.

  In the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant, and one is the other. Some or all of the modifications, details, supplementary explanations, and the like are related. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
FIG. 1 shows an example of the configuration of the semiconductor device according to the first embodiment of the present invention. FIG. 1A is an overall block diagram, and FIG. 1B shows an example of the configuration in the memory bank of FIG. It is a circuit diagram. The semiconductor device (semiconductor chip, semiconductor IC) CP_D in FIG. 1A is, for example, a DRAM chip formed on one semiconductor chip. The semiconductor device CP_D includes a plurality (here, eight) of memory banks MBK0 to MBK7 and a refresh control circuit REF_CTL. REF_CTL outputs refresh signals REFS0 to REFS7 to MBK0 to MBK7, respectively, for example, when an auto-refresh command REF is input from the outside or when REF is generated internally during self-refresh.

  As shown in FIG. 1B, each of the memory banks MBK0 to MBK7 includes a plurality of word lines WL0, WL1,... And a plurality of bit line pairs (BL0, / BL0), (BL1, / BL1),. And a plurality of memory cells MC arranged at the intersections of the word line and the bit line pair. Each memory cell MC connects the bit line BL corresponding to itself to the capacitor Cs via the transistor MT when the word line WL corresponding to the memory cell MC is activated. Each memory bank MBK includes a word driver circuit WD that drives the word line WL, a plurality of sense amplifier circuits SA that amplify the potential difference between each bit line pair (BL, / BL), and each bit line pair (BL, / BL) includes a plurality of precharge circuits PC and the like.

  Each memory bank MBK (for example, MBK0) activates a specific word line WL via the word driver circuit WD when receiving a refresh signal REFS (for example, REFS0) from REF_CTL. The specification of the word line WL at this time is determined by a refresh address generation circuit (refresh counter circuit) included in REF_CTL (not shown). The REF_CTL deactivates the word line WL via the WD after a predetermined time required to recharge the capacitor Cs connected to the word line, and each bit line pair (BL , / BL) is precharged via the precharge circuit PC.

  FIG. 2 is an explanatory diagram showing an example of the refresh operation method in the semiconductor device of FIG. As shown in FIG. 2, refresh signals REFS0 to REFS7 are input to the respective memory banks MBK0 to MBK7 at different timings in a delayed manner from MBK0 to MBK7. REFS is substantially decomposed into an instruction (ACT command) for activating word line WL and an instruction (PRE command) for deactivating WL and precharging bit line BL.

  Here, the time difference between the ACT commands in MBK0 and MBK1 (that is, the time difference in the start timing of the refresh operation) is tRF_1, the time difference between the ACT commands in MBK1 and MBK2 is tRF_2, and so on. Is tRF_7. Further, the time tRC from the ACT command to the PRE command is constant, and accordingly, the time difference between the PRE commands in MBK0 to MBK7 (that is, the time difference of the refresh operation end timing) is the same as in the case of the ACT command.

In such an operation, the semiconductor device of FIG. 1 is mainly characterized in that the start timing and end timing of the refresh operation are set so as to satisfy Equation (2).
(TRF_1 = tRF_7)> (tRF_2 = tRF_6)> (tRF_3 = tRF_5)> tRF_4 (2)
In other words, if the number of MBKs is N and the time interval of the refresh operation performed at the I-th and (I + 1) -th is T (I), the expression (2) is expressed as “T (I) = T (N− I) and I ≦ N / 2, and T (I) <T (I−1) ”holds. Note that the period “tRFC_min” in FIG. 2 is a period that needs to be secured at least from the issuance of the REF command (that is, the start of the refresh operation to all banks) until the next REF command is issued. This is the period specified in. Therefore, as shown in FIG. 2, it is necessary to complete the refresh operation of MBK0 to MBK7 within tRFC_min while shifting the timing according to the relationship of Expression (2).

  3 shows an example of the power supply waveform in FIG. 2. FIG. 3A shows a power supply current waveform in FIG. 19A as a comparative example, FIG. 3B shows a power supply current waveform in FIG. c) is a power supply voltage waveform corresponding to (a) and (b). As shown in FIG. 3A, when the refresh timing of FIG. 19A is used, the current waveform has a trapezoidal shape. By using the refresh timing of FIG. 2, the refresh timing shown in FIG. As shown, a substantially sinusoidal current waveform is obtained. Thus, as shown in FIG. 3C, the magnitude of each power supply noise is 390 mV at the maximum in the case of FIG. 19A, for example, 260 mV at the maximum in FIG. Therefore, noise reduction of 30% to 40% can be realized.

  This is because the harmonic component can be reduced by controlling the current waveform to be substantially sinusoidal. As described above, the impedance of the power supply system usually has an inductance (L) component mainly as the frequency becomes higher. Therefore, as the current spectrum of the higher harmonic component becomes larger, a larger power supply noise is generated by the (L) component. become. Therefore, by bringing the current waveform close to a sine wave, harmonic components can be reduced and power supply noise can be reduced. In this sense, it is desirable to set the magnitude of each tRF that satisfies Equation (2) so that the current waveform is closer to a sine wave.

  4 shows an example of the refresh control circuit REF_CTL in the semiconductor device of FIG. 1. FIG. 4A is a circuit diagram showing a configuration example of the main part, and FIG. 4B shows an operation example of FIG. It is a waveform diagram. The refresh control circuit REF_CTL1 shown in FIG. 4A includes a selector circuit SEL1 and a plurality of serially connected flip-flop circuits FF0 [0], FF1 [0] to FF1 [2], FF2 [0], FF2 [1. ], FF7 [2], and a plurality of OR circuits OR10 to OR17. “N” of the flip-flop circuit FFn [m] is 0 to 7, and “m” is appropriately set according to the value of “n”.

  The operation mode of the refresh control circuit REF_CTL1 is set in SEL1. That is, when the upper node of SEL1 is selected by the selection signal S1, the inputted common refresh signal REFC is transmitted to one input terminal of each of the OR circuits OR10 to OR17. There is no input at the other input terminals of the OR circuits OR10 to OR17. Therefore, a refresh signal having substantially the same timing as the common refresh signal REFC shown in FIG. 4B is applied to each of the memory banks MBK0 to MBK7. In the present embodiment, in each of the memory banks MBK0 to MBK7, the ACT command is issued at the rising edge of the applied refresh signal, the word line is activated, and the PRE command is issued at the falling edge of the refresh signal. Bit line precharge occurs.

  When the lower node of SEL1 is selected by the selection signal S1, the operation mode is applied in which the refresh signals having the non-uniform time differences described above with reference to FIGS. 2 and 3 are applied to the memory banks MBK0 to MBK7. . That is, REFC is transmitted to the input of the flip-flop circuit FF0 [0]. The output of FF0 [0], which is the result of the latch operation of FF0 [0] by the clock signal CLK, is supplied to the memory bank MBK0 via the OR circuit OR10. Thereby, the refresh signal REFS0 to the memory bank MBK0 is substantially synchronized with the rising edge of the clock signal CLK. Note that Tpd in FIG. 4B indicates an output delay of the flip-flop circuit with respect to the clock signal, a delay caused when passing through the OR circuit, and the like. The refresh signal REFS1 supplied to the adjacent memory bank MBK1 is further output from an output tap via three flip-flops FF1 [0], FF1 [1], and FF1 [2] connected in series via an OR circuit OR11. Pulled out. Therefore, the time difference tRF_1 between REFS1 and REFS0 is 3Tf when the clock cycle is Tf. Further, the refresh signal REFS2 supplied to the adjacent memory bank MBK2 is further extracted from the output tap via the two flip-flops FF2 [0] and FF2 [1] via the OR circuit OR12. The time difference tRF_2 is 2Tf. Thereafter, the number of flip-flop circuits between the taps from which the refresh signal is extracted becomes 1, and increases to 3 again at the farthest tap.

  As described above, in the circuit of FIG. 4A, each tap position from which a signal is extracted from a column of flip-flop circuits that sequentially shift the common refresh signal REFC is selected, and the number of flip-flop circuits between the adjacent taps is changed. Thus, the refresh signals REFS0 to REFS7 having the time intervals of non-uniform intervals as described in FIGS. 2 and 3 are obtained. Although not particularly limited, for example, Tf is about 10 ns, tRC in FIG. 2 is about 60 ns, and tRFC_min is about 120 ns. In this case, for example, tRF_1 may be set to a value of 20 ns to 30 ns using three stages of flip-flop circuits FF1 [0] to FF1 [2], as shown in FIG.

  As described above, the refresh timing shown in FIG. 2 can be easily realized by using the refresh control circuit REF_CTL1 as shown in FIG. Note that the path on the side not passing through each flip-flop circuit FF in the output of the selector circuit SEL1 is provided in case there is a case where it is desired to perform refresh operations on all the memory banks MBK at the same time. Do not mean.

  5 shows another example of the refresh control circuit REF_CTL in the semiconductor device of FIG. 1. FIG. 5A is a circuit diagram showing a configuration example of the main part, and FIG. 5B is an operation of FIG. It is a wave form diagram which shows an example. The refresh control circuit REF_CTL2 illustrated in FIG. 5A includes a selector circuit SEL2, a plurality of delay circuits DLY21 to DLY27, a plurality of OR circuits OR20 to OR27, and the like. SEL2 receives the common refresh signal REFC for all the bank memories MBK, selects it based on the selection signal S2, and outputs it. When one is selected by the selection signal S2, REFC is transmitted to one input of OR20 to OR27. When the other is selected by S2, REFC is transmitted to the input of DLY21 and the other input of OR20.

  The output of DLY21 is connected to the other input of OR21 and the input of DLY22. DLY22 has its output connected to the other input of OR22 and the input of DLY23. Similarly, DLY27 outputs the output of DLY26. While being input, its output is connected to the other input of the OR 27. The outputs of OR20 to OR27 become refresh signals REFS0 to REFS7, respectively, and are transmitted to MBK0 to MBK7.

  In such a configuration, the delay times Tdly of DLY21 to DLY27 are designed to tRF_1 to tRF_7 shown in FIG. As a result, as shown in FIG. 5 (b), after OR20 outputs REFS0 at substantially the same timing as REFC and delays tRF_1 therefrom, OR21 outputs REFS1 and further delays tRF_2 therefrom. The OR 22 outputs REFS2, and thereafter the same operation as shown in FIG. 2 is performed. Each of DLY21 to DLY27 can be realized by, for example, a plurality of stages of inverter connections. Thus, by using the refresh control circuit REF_CTL2 as shown in FIG. 5, the refresh timing of FIG. 2 can be easily realized.

  FIG. 6 is a circuit diagram showing still another configuration example of the main part of the refresh control circuit REF_CTL in the semiconductor device of FIG. The refresh control circuit REF_CTL3 shown in FIG. 6 includes a counter circuit CUNT, comparison circuits (CMP0s, CMP0r) to (CMP7s, CMP7r), SR flip-flop circuits SR0 to SR7, and the like. For example, the CUNT performs a counting operation with a clock signal CLK having a period of several ns using the common refresh signal REFC as a reset and start trigger. CMP0s sets SR0 when the count value reaches the set value t0, and CMP0r resets SR0 when the count value reaches, for example, the set value “t0 + tRC”. The output of SR0 becomes REFS0 and is transmitted to the memory bank MBK0.

  CMP1s sets SR1 when the count value reaches, for example, “t0 + tRF_1”, and CMP1r resets SR1 when the count value reaches, for example, “t0 + tRF_1 + tRC”. The output of SR1 becomes REFS1 and is transmitted to MBK1. In the same manner, the output of SR7 having the output of CMP7s as the set input and the output of CMP7r as the reset input becomes REFS7 and is transmitted to MBK7. With this configuration, the refresh timing as shown in FIG. 2 can be easily realized. If it is desired to set the timing with a higher resolution than the CLK cycle, for example, the delay circuit DLY as shown in FIG. 5 may be added to the outputs of SR0 to SR1.

  As described above, typically the power supply noise can be reduced by using the semiconductor device of the first embodiment. Of course, the configuration of the refresh control circuit REF_CTL is not limited to the configuration described above, and can be variously modified as long as it includes a digital delay circuit and an analog delay circuit for setting tRF in FIG. For example, the Tpd of each flip-flop circuit FF in the configuration example of FIG. 4 is made the same, and a rough delay time is set by a digital delay depending on the number of stages, and this is combined with an analog delay circuit as shown in FIG. You can also set the time. Further, the refresh control circuit REF_CTL of the first embodiment determines the activation and deactivation timing of the word line with only one refresh signal REFS, but REFS is used as a trigger signal for activating the word line. It is also possible to separate the trigger signal for deactivation and shift the timing only at the time of activation, only at the time of deactivation, or both.

(Embodiment 2)
FIG. 7 is a circuit diagram showing a configuration example of a main part of the refresh control circuit REF_CTL of FIG. 1 in the semiconductor device according to the second embodiment of the present invention. The main feature of the refresh control circuit REF_CTL4 shown in FIG. 7 is that the delay circuits DLY21 to DLY27 in the refresh control circuit REF_CTL2 of FIG. 5 described above are changed to variable delay circuits VDLY21 to VDLY27. Since other configurations are the same as those in FIG. 5, detailed description thereof is omitted. The VDLY21 to VDLY27 are circuits that can set arbitrary delay times according to the selection signals S21 to S27, respectively.

  By using the refresh control circuit REF_CTL4 as shown in FIG. 7, the fundamental frequency and the waveform shape can be changed. As a result, power supply noise can be reduced in mounting forms having various power supply system impedance profiles. Can be adjusted to a current waveform that can be reduced most efficiently.

  As described above, power supply noise can be reduced typically by using the semiconductor device of the second embodiment. In addition, power supply noise can be reduced flexibly for impedance characteristics of various power feeding systems. Of course, the configuration example of FIG. 7 is not limited to this. For example, it can be replaced by making the expected value of the comparison circuit CMP in the configuration example of FIG. 6 variable, and can be realized by using various variable digital delay circuits and variable analog delay circuits.

(Embodiment 3)
In the first embodiment described above, the refresh timing is shifted as shown in FIG. 2 to reduce the power supply noise by generating a sinusoidal current waveform. However, this method is not limited to the refresh operation and is used in various situations. It is applicable to. In other words, in a situation where currents flow by simultaneous operation of a plurality of circuit units, the power supply noise reduction effect can be obtained by shifting the operation timing of each circuit unit so that the current waveform approaches a sine wave. In the third embodiment, an example of these various scenes is given.

  FIG. 9 is an explanatory diagram showing the basic concept of the semiconductor device or information processing system according to the third embodiment of the present invention. As shown in FIG. 9, in the semiconductor device or information processing system of the third embodiment, the operation timings of a plurality of circuit units (eight in this case) CR0 to CR7 are shifted as in the case of FIG. It has become a feature. In FIG. 9, the operation to be shifted is, for example, an operation with a relatively large amount of current performed within a certain period, such as the above-described refresh operation, and an operation with a relatively small amount of current in other periods. Or the amount of current is almost zero (that is, the operation is stopped). The CR0 to CR7 may be the same type of circuit unit or different types of circuit units, and the target operation may be the same operation or different operation.

Here, the period from the start timing (and / or end timing) of the target operation of CR0 to the start timing (and / or end timing) of the target operation of CR1 is tjob_1, and similarly, the period from CR1 to CR2 is tjob_2. Thereafter, similarly, the period from CR6 to CR7 is set to tjob_7. Then, as in the case of FIG. 2, each period tjob is set according to the relationship of Expression (3).
(Tjob_1 = tjob_7)> (tjob_2 = tjob_6)> (tjob_3 = tjob_5)> tjob_4 (3)
FIG. 10 is a block diagram showing a configuration example of the semiconductor device according to the third embodiment of the present invention. A semiconductor device CP shown in FIG. 10 includes, for example, eight circuit units CR0 to CR7 in one semiconductor chip, and further includes a clock signal control circuit CK_CTL. Each of CR0 to CR7 is not particularly limited, but is a processor, for example. CK_CTL supplies clock signals CK0 to CK7 to CR0 to CR7, respectively, thereby causing a multiprocessor operation and the like.

  Here, CK_CTL supplies a relatively low-frequency clock signal CK0 to CK7 and requires high-speed processing operation when performing low-speed processing operation to reduce power consumption according to software or hardware scheduling, for example. In such a case, clock signals CK0 to CK7 having a relatively high frequency are supplied. Therefore, CK_CTL shifts the transition timing of CR0 to CR7 at the timing as shown in FIG. 9, for example, in the process of transition from the low speed processing operation to the high speed processing operation. As a result, power supply noise can be reduced.

  FIG. 11 is an outline view showing a configuration example of the information processing system according to the third embodiment of the present invention. In the information processing system shown in FIG. 11, for example, a plurality of (here, five) processor boards (wiring boards) PCB_P1 to PCB_P5 are connected on a control board (wiring board) PCB_C, and the entire operation is performed by parallel operation of these PCB_P1 to PCB_P5. As a multi-processor operation. In such a system, the power supply noise of the entire system can be reduced by shifting the start timing of processing with a relatively large amount of current performed by each processor board as shown in FIG.

  FIG. 12 is a block diagram showing another configuration example in the information processing system according to the third embodiment of the present invention. FIG. 13 shows still another configuration in the information processing system according to the third embodiment of the present invention. FIG. The information processing system shown in FIG. 12 includes a plurality of (here, three) DRAM-ICs (DRAM1 to DRAM3) on a wiring board (for example, a mother board) PCB, and a control IC (memory controller IC) CIC that controls their operation. Has been implemented. Further, the information processing system shown in FIG. 13 includes a plurality of (in this case, three) DRAM modules MM1 to MM3 and a control IC (memory controller IC) CIC that controls their operation on a wiring board (for example, a motherboard) PCB. Has been implemented.

  For example, in the system of FIG. 12, the CIC shifts the timing of the auto-refresh command REF output to each DRAM-IC (DRAM1 to DRAM3) at the timing shown in FIG. Thereby, the DRAM1 to DRAM3 perform the refresh operation at different timings. On the other hand, in the system of FIG. 13, the CIC shifts the timing of the auto-refresh command REF output to each of the DRAM modules MM1 to MM3 at the timing as shown in FIG. Thereby, the MM1 to MM3 perform the refresh operation at different timings. That is, in these systems, the CIC includes the circuits shown in FIGS. 4 to 6 described above. As a result, the power supply noise of the entire system can be reduced.

  FIG. 14 is a plan view showing still another configuration example of the semiconductor device according to the third embodiment of the present invention. The semiconductor device shown in FIG. 14 is a DRAM module MM. For example, eight DRAM-ICs (DRAM0 to DRAM7) and a buffer for buffering a signal from the external terminal PN1 and outputting it to each DRAM-IC. An IC (BIC) is mounted. In such a configuration, the BIC receives the signal from the external terminal PN1, determines the auto-refresh command REF, and shifts and outputs the command for each DRAM-IC. That is, the BIC includes the circuits as shown in FIGS. As a result, power supply noise in the DRAM module can be reduced.

  FIG. 15 is an explanatory diagram showing an operation example of the semiconductor device CP_D of FIG. 1 in the semiconductor device according to the third embodiment of the present invention. The operation example shown in FIG. 15 is characterized in that, for example, when performing a so-called concentrated refresh operation, the intervals when the word lines WL are sequentially activated in each memory bank are shifted. That is, for example, the interval between WL0 and WL1 is wide, the interval becomes narrower as WL1 and WL2 and WL2 and WL3 are reached, and conversely the interval becomes wider gradually after passing a certain word line. By using such an operation, it is possible to generate a sinusoidal current waveform for a long period of time, and to reduce harmonic components associated therewith, so that it is possible to reduce power supply noise.

  FIG. 16 is a perspective view showing still another configuration example of the semiconductor device according to the third embodiment of the present invention. The semiconductor device shown in FIG. 16 has a configuration in which a control semiconductor chip CP_C and a plurality (four in this case) of processing semiconductor chips CP_CR1 to CP_CR4 are stacked and mounted on a package substrate (wiring substrate) PBD having an external terminal PN2. It is an example. The processing semiconductor chips CP_CR1 to CP_CR4 are, for example, a processor chip or a DRAM chip. CP_C includes an internal terminal IPN, and controls CP_CR1 to CP_CR4 via the IPN. The IPN corresponds to, for example, a terminal that outputs a clock signal for performing the operation described in FIG. 10, a terminal that outputs a refresh signal for performing the operation described in FIG.

  FIG. 17 shows still another example of the semiconductor device or information processing system according to the third embodiment of the present invention, where (a) is a block diagram showing an example of the configuration, and (b) is (a). It is explanatory drawing which shows the operation example. The semiconductor device or the information processing system shown in FIG. 17A includes a plurality (eight in this case) of processing units UN1 to UN8 and a regulator unit VREG that are connected to each other via a bus BS. UN1 to UN8 and VREG are formed on, for example, one semiconductor chip CP. Alternatively, UN1 to UN8 and VREG are formed by separate semiconductor chips (that is, separate ICs) and mounted on the wiring board PCB.

  VREG supplies predetermined power supply voltages PON1 to PON8 to UN1 to UN8. At this time, as shown in FIG. 17B, the VREG performs control to shift the supply start timing of each power supply voltage so that the power supply current waveform becomes a sine wave shape instead of simultaneously. For example, in a microcomputer or the like, there are cases where operations such as temporarily shutting off or restoring the power supply of some internal modules (processing units) are performed in order to reduce power consumption. When power is supplied for the first time or when the power supply is restored from the cut-off state as described above, the power supply noise can be reduced by using the timing shown in FIG.

  As described above, power supply noise can be reduced typically by using the semiconductor device of the third embodiment.

(Embodiment 4)
In the fourth embodiment, an operation example obtained by modifying the operation example of FIG. 9 described in the third embodiment will be described. FIG. 18 shows the basic concept of the semiconductor device or information processing system according to the fourth embodiment of the present invention. FIG. 18A is an explanatory diagram showing an example of the operation, and FIG. 18B uses FIG. It is a wave form diagram which shows an example of the power supply current waveform in the case of being.

In the operation example shown in FIG. 18A, the operation example of FIG. 9 is the timing for generating the power source current waveform corresponding to the half cycle (0 to 180 °) of the sine wave, but further half ( It is the timing for generating a power supply current waveform of 0 to 90 °. Here, taking five circuit units CR0 to CR4 as an example, let tjob_1 be the time difference between the timing at which CR0 starts (and / or ends) the processing with a large amount of current and the timing at CR1. Similarly, the time difference between CR1 and CR2 is set to tjob_2, and thereafter the time difference between CR3 and CR4 is set to tjob_4. In this case, in the operation example of FIG. 18A, the timing is set according to the relationship of Expression (4).
tjob_1>tjob_2>tjob_3> tjob_4 (4)
When such an operation example is used, a current waveform corresponding to ¼ of a sine wave can be generated as shown in FIG. However, in this case, a harmonic component is generated when the power supply current waveform falls, but a certain level of power supply noise reduction effect can be obtained.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention.

The semiconductor device and the information processing system according to the present embodiment are technologies that are particularly useful when applied to a product including a DRAM such as a DRAM-IC, a DRAM module, a board on which a DRAM is mounted, and the like. The present invention can be widely applied to semiconductor devices such as processors and microcomputers and information processing systems generally equipped with various semiconductor components.
(Appendix)
[Appendix 1]
A plurality of circuit blocks;
A control circuit that controls a start timing when the plurality of circuit blocks perform circuit operation;
The control circuit adjusts the start timing for each of the plurality of circuit blocks when the circuit operation in which the plurality of circuit blocks consumes a large amount of power supply current is performed in parallel within a certain period of time, so that the power supply current waveform is sinusoidal. A semiconductor device which is controlled so as to have a wave-like mountain waveform.
[Appendix 2]
In the semiconductor device according to attachment 1,
When the number of circuit operations performed in parallel by the plurality of circuit blocks is N, and the time interval between the circuit operations performed I-th and I + 1-th is T (I),
The time interval T (I) is
T (I) = T (N−I) and I = N / 2 or less, and T (I) <T (I−1)
The semiconductor device characterized by satisfy | filling.
[Appendix 3]
In the semiconductor device according to attachment 1,
The circuit operation performed in parallel by the plurality of circuit blocks is the same type of operation, respectively.
[Appendix 4]
In the semiconductor device according to attachment 1,
The plurality of circuit blocks and the control circuit are formed on the same semiconductor chip.
[Appendix 5]
In the semiconductor device according to attachment 1,
The plurality of circuit blocks and the control circuit are formed on a plurality of semiconductor chips and mounted in the same package.
[Appendix 6]
In the semiconductor device according to attachment 1,
Each of the plurality of circuit blocks is a DRAM memory bank formed on the same semiconductor chip,
A semiconductor device characterized in that a circuit operation performed in parallel by the plurality of DRAM memory banks is a refresh operation.
[Appendix 7]
In the semiconductor device according to attachment 1,
Each of the plurality of circuit blocks is a DRAM chip mounted on the same module wiring board,
The circuit operation performed in parallel by the plurality of DRAM chips is a refresh operation,
2. The semiconductor device according to claim 1, wherein the control circuit is realized by a buffer IC mounted on the module wiring board.
[Appendix 8]
A plurality of semiconductor devices;
A control device that controls a start timing when the plurality of semiconductor devices perform device operations;
The control device adjusts the start timing for each of the plurality of semiconductor devices when the plurality of semiconductor devices perform a device operation in which a large amount of power supply current is consumed in parallel within a predetermined period, whereby a power source current waveform is sinusoidal. An information processing system that is controlled to have a wave-like mountain-shaped waveform.
[Appendix 9]
In the information processing system according to attachment 8,
When the number of device operations performed in parallel by the plurality of semiconductor devices is N, and the time interval between the I-th and I + 1-th device operations is T (I),
The time interval T (I) is
T (I) = T (N−I) and I = N / 2 or less, and T (I) <T (I−1)
An information processing system characterized by satisfying
[Appendix 10]
In the information processing system according to attachment 8,
The information processing system, wherein the plurality of semiconductor devices and the control device are mounted on a wiring board.
[Appendix 11]
In the information processing system according to attachment 8,
Each of the plurality of semiconductor devices is a DRAM chip mounted on the same wiring board,
The apparatus operation performed in parallel by the plurality of DRAM chips is a refresh operation.
[Appendix 12]
In the information processing system according to attachment 8,
Each of the plurality of semiconductor devices is a DRAM module mounted on the same wiring board,
The apparatus operation performed in parallel by the plurality of DRAM modules is a refresh operation.
[Appendix 13]
A plurality of memory banks each including a plurality of word lines, a plurality of bit lines, and a plurality of DRAM memory cells disposed at intersections of the plurality of word lines and the plurality of bit lines;
A refresh control circuit for controlling a refresh operation of the plurality of memory banks,
Each of the plurality of memory banks activates and / or deactivates a predetermined word line in the memory bank using a refresh signal corresponding to the memory bank as a trigger,
The refresh control circuit receives a common refresh signal generated in response to an external command input or an internal command generation, and shifts the common refresh signal at different timings for the plurality of memory banks. The refresh signal having a different timing for each memory bank is generated, and at this time, the timing of the refresh signal is adjusted so that the power supply current waveform accompanying the refresh operation becomes a sinusoidal waveform. A featured semiconductor device.
[Appendix 14]
In the semiconductor device according to attachment 13,
When the number of the plurality of memory banks is N, and the timing interval of the refresh signal generated toward the Ith and I + 1th different memory banks is T (I),
The timing interval T (I) is
T (I) = T (N−I) and I = N / 2 or less, and T (I) <T (I−1)
The semiconductor device characterized by satisfy | filling.
[Appendix 15]
In the semiconductor device according to attachment 14,
The refresh control circuit includes a plurality of delay circuits that sequentially delay the common refresh signal by serial connection,
2. The semiconductor device according to claim 1, wherein the timing of the refresh signal is generated using delay times of the plurality of delay circuits.
[Appendix 16]
In the semiconductor device according to attachment 15,
The plurality of delay circuits include a flip-flop circuit that performs a shift operation according to a clock signal,
2. The semiconductor device according to claim 1, wherein the timing of the refresh signal is generated using the number of stages of the flip-flop circuit and / or a propagation delay time.
[Appendix 17]
In the semiconductor device according to attachment 13,
2. The semiconductor device according to claim 1, wherein the refresh control circuit includes a plurality of variable delay circuits capable of sequentially delaying the common refresh signal by serial connection and changing each delay time by setting.

MBK memory bank CP semiconductor chip REFS refresh signal REF_CTL refresh control circuit WL word line BL bit line WD word driver circuit MC memory cell MT transistor Cs capacitance SA sense amplifier circuit PC precharge circuit SEL selector circuit S selection signal OR OR circuit REFC common Refresh signal CLK clock signal FF flip-flop circuit DLY delay circuit CUNT counter circuit CMP comparison circuit SR SR flip-flop circuit VDLY variable delay circuit CR circuit unit CK_CTL clock signal control circuit PCB wiring board CIC control IC
MM DRAM module BIC Buffer IC
PN External terminal IPN Internal terminal PBD Package substrate UN Processing unit PON Power supply voltage

Claims (1)

A plurality of circuit blocks;
A control circuit that controls a start timing when the plurality of circuit blocks perform circuit operation;
The control circuit adjusts the start timing for each of the plurality of circuit blocks when the circuit operation in which the plurality of circuit blocks consumes a large amount of power supply current is performed in parallel within a certain period of time, so that the power supply current waveform is sinusoidal. A semiconductor device which is controlled so as to have a wave-like mountain waveform.

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