JPH06214881A - Memory control system - Google Patents

Abstract

PURPOSE:To provide a memory control system for considerably reducing power consumption by performing refresh while shifting timing for each memory bank and for enabling refresh corresponding to the state of use. CONSTITUTION:This control system for the plural memory banks of an information processor is provided with a decoder 11, selectors 16a-16d equipped with first input terminals connected on the outputside, second input terminals for inputting row address strobe signals and second input terminals for inputting row address strobe signals shifting the timing for respective memory banks 17a-17d and disposed corresponding to the respective banks 17a-17d and the banks 17a-17d respectively connected to these selectors, and the refresh operations of the respective memory banks 17a-17d are executed while shifting the timing for the respective memory banks 17a-17d.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device,
In particular, it relates to a memory control system in a main memory device.

[0002]

2. Description of the Related Art Conventionally, DRAM (Dynamic RA)
When a refresh operation is performed in a main memory device having a plurality of banks using M), all banks of the main memory device are refreshed at the same time.
FIG. 3 is a configuration diagram of a memory control circuit in such a conventional main memory device having a plurality of banks.

In this figure, 1 is a decoder, and 2a to 2a.
d is an OR gate, 3a to 3d are AND gates, 4a to 4
d is a memory bank. RAS is a start signal of the row address strobe signal. AD0 to AD1 are arbitrary 2 bits (bits) of the memory access address and are select signals of the memory bank. The REF signal is a signal that becomes ON (REF = 1) during the refresh operation,
RAS0 to RAS3 are row address strobe signals supplied to each memory bank.

The operation at the time of executing refresh will be described with reference to the timing chart of FIG. Here, FIG. 4 (a)
Is a clock signal, FIG. 4 (b) is a REF signal, and FIG. 4 (c).
Are timing signals of select signals AD0 to AD1 of the memory bank, FIG. 4 (d) is a RAS signal, and FIGS. 4 (e) to 4 (h) are timing charts of row address strobe signals.

First, the REF signal is turned on (REF = 1) as shown in FIG. 4B, and the RAS signal is activated in the next cycle as shown in FIG. 4D. As a result,
As shown in FIG. 4C, the signals RAS0 to RAS3 shown in FIGS. 4E to 4H are activated and the memory banks 4a to 4d are activated regardless of the values of the select signals AD0 to AD1 of the memory banks. Are refreshed at the same time.

[0006]

However, in the conventional main memory device having the above-described structure, all memory banks perform the refresh operation at the same time, and therefore, there is a disadvantage that excessive power is instantaneously consumed. Has become a big problem for increasing the capacity and reducing the power consumption. In order to solve the problem that excessive power consumption is involved in the refresh operation in the main memory device having a plurality of banks described above, the present invention shifts the timing for each memory bank or refresh operation for each memory bank. It is an object of the present invention to provide a memory control method capable of reducing excessive power consumption at the time of refresh operation.

Further, according to the present invention, all the memory banks of the prior art are refreshed at the same time, that is, a so-called normal refresh mode (excessive power is consumed at the time of refresh, but the refresh execution cycle is short), and each of the above memory banks. By changing the timing for each bank or switching the low power refresh mode (which does not consume excessive power during refresh, but the refresh execution cycle is long) that performs the refresh operation for each bank by software or hardware, It is an object of the present invention to provide a memory control system for a main storage device that suits the purpose of use.

[0008]

In order to achieve the above object, the present invention is a memory control system in a main memory device having a plurality of memory banks of an information processing device, wherein the decoder is connected to an output side of the decoder. AND gate arranged corresponding to each of the memory banks, and a second input terminal to which a row address strobe signal is inputted, and an output side of the AND gate. A first input terminal, a second input terminal to which a row address strobe signal whose timing is shifted for each memory bank is input, and a third input terminal to which a refresh signal is input, A selector is provided corresponding to each of the memory banks, and a memory bank connected to each of the selectors is provided. Slide the is obtained by so as to perform a refresh operation for each memory bank.

Further, in the memory control system in the main memory device having a plurality of memory banks of the information processing device, a decoder, a first input terminal connected to the output side of the decoder, and a second mode signal to which a mode signal is input. OR gates arranged corresponding to the respective memory banks having input terminals, first input terminals connected to the output side of the OR gates, and second row address strobe signals to be input. An AND gate having an input terminal and arranged corresponding to each of the memory banks, a first input terminal connected to the output side of the AND gate, and the timings of the respective memory banks are shifted. It has a second input terminal to which a row address strobe signal is input and a third input terminal to which a refresh signal is input, and is arranged corresponding to each memory bank. And a memory bank connected to the selector, the first mode in which the refresh operation of each memory bank is performed by shifting the timing for each memory bank, and the refresh operation of each memory bank. It is possible to switch between the second mode for simultaneously executing the above.

[0010]

According to the present invention, as described above, in the memory control system in the main memory device having a plurality of memory banks of the information processing device, the refresh operation of each memory bank is performed by shifting the timing for each memory bank. Since it is executed, it is possible to reduce excessive power consumption at the time of refresh activation and power supply noise due to the power consumption, and to achieve large capacity and low power consumption.

Further, it is possible to shift the timing for each memory bank and switch between a first mode in which the refresh operation of each memory bank is executed and a second mode in which the refresh operation of each memory bank is simultaneously executed. Therefore, in view of the power consumption state of the entire information processing apparatus, even if the excessive power consumption at the time of refresh is sacrificed, the first mode is set when the refresh execution cycle is desired to be shortened and the refresh execution cycle is set to be long. ,
If you want to suppress excessive power during refresh, you can switch to the second mode, that is, you can easily select the mode that matches the usage state and purpose of use, and you can see the throughput while checking the power consumption state of the information processing device. Can be improved.

[0012]

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram of a memory control circuit in a main memory device having a plurality of banks according to the first embodiment of the present invention, and FIG. 2 is a timing chart of a refresh operation of each memory bank in the main memory device having the plurality of banks. .

Here, the AD0 to AD1 signals are arbitrary 2 bits of the address at the time of memory access, and RAS0
~ RAS3 signal is a row address strobe signal supplied to each memory bank (MBNK0 to 3).
The signal is a signal for starting the RAS0 to RAS3 signals. Also, the REF signal is turned on (REF
= 1).

During normal memory read / write, R
The EF signal remains OFF (REF = 0) and AD0
~ After the AD1 signal is determined, memory access is executed to an arbitrary memory bank. In these figures, reference numeral 11 denotes a decoder. The decoder 11 has arbitrary 2 bits (bits) of a memory access address and AD0 to AD1 signals which are memory bank select signals are A to AD.
It is input to the B terminal, and the decode signal is output from the output terminals 0 to 3. These decode signals are input to the first input terminals of the AND gates 12a to 12d, respectively. On the other hand, the RAS signal (row address strobe signal) is input to the second input terminals of the AND gates 12a to 12d, respectively.

The output signals from the AND gates 12a to 12d are output to the selectors 16a to 1 respectively.
6d connected to the first input terminal of the selector 16
The RAS signal is input to the second input terminal of a, and the flip-flop 1 is input to the second input terminal of the selector 16b.
The RAS signal whose timing t ₁ is deviated by 3 is input, the RAS signal whose timing t ₂ is further deviated by the flip-flop 14 is input to the second input terminal of the selector 16c, and the second input terminal of the selector 16d is input. Is the timing when the flip-flop 15 shifts the timing t ₃ further.
The AS signal is input.

Therefore, when the refresh signal (REF signal) is input to the selectors 16a to 16d, the selector 1
As shown in FIGS. 2 (e) to 2 (h), RAS0 to RAS3 whose timings are shifted are output to 6a to 16d, and the memory banks 17a to 17d shift the timing for each memory bank to change the memory. The bank refresh operation is executed.

Further, the operation at the time of refresh will be described with reference to the timing chart of FIG.
Corresponding to the clock signal shown in (a), the REF signal becomes ON (REF = 1) as shown in FIG. 2B, and at the same time, as shown in FIG. Determine. (In the refresh operation, AD0 to AD1 can be anything.) In the next cycle, as shown in FIG. 2D, the RAS signal is activated and the flip-flop (FF0
~ FF2) After the timing is changed by 13 ~ 15,
RAS0-RA as shown in FIGS. 2 (e)-(h) via the selectors (SL0-SL3) 16a-16d.
The S3 signal is generated and supplied to each of the memory banks 17a to 17d at each timing to perform the refresh operation.

As described above, in this embodiment, since the refresh is performed by shifting the timing for each memory bank, excessive power consumption at the time of refresh can be avoided. That is, low power refresh can be performed. Also, in this embodiment, RAS
The 0 signal and the RAS1 signal are shifted so as to partially wrap. However, if the refresh execution cycle can be lengthened, the RAS0 signal and the RAS1 signal are shifted so as not to completely wrap and the timing change by the flip-flop is performed. It may be performed. By doing so, the refresh operation can be executed for each memory bank.

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 5 is a block diagram of a memory control circuit in a main memory device having a plurality of banks according to the second embodiment of the present invention, and FIG. 6 is a timing chart of a refresh operation of each memory bank in the main memory device having the plurality of banks. . Here, a so-called normal refresh mode circuit for refreshing all memory banks at the same time is added to the circuit of the first embodiment so that switching to the low power refresh mode can be performed. .

In these figures, reference numeral 21 is a decoder, which is an arbitrary 2 bits (bit) of an address at the time of memory access, and AD0 to AD1 signals which are select signals of a memory bank are AB. The signal is input to the terminal, and the decode signal is output from the output terminals 0 to 3.
These decoded signals are respectively OR gates 22a to 2a.
It is input to the first input terminal of 2d. On the other hand, the mode signal (MODE signal) is input to the first input terminal of the AND gate 23, the refresh (REF signal) is input to the second input terminal thereof, and the output signal of the AND gate 23 is the OR gate. It is input to the second input terminals 22a to 22d, respectively.

The output signals of the OR gates 22a to 22d are input to the first input terminals of the AND gates 28a to 28d, respectively. On the other hand, the RAS signal (row address strobe signal) is input to the second input terminals of the AND gates 28a to 28d, respectively. Also, the AND gate 28
The respective output signals from a to 28d are connected to the first input terminals of the respective selectors 29a to 29d, while the RAS signal is input to the second input terminal of the selector 29a and the second input terminal of the selector 29b is input. RA with the timing t ₁ shifted to the input terminal of 2 by the flip-flop 25
The S signal is input, the RAS signal whose timing t ₂ is further shifted by the flip-flop 26 is input to the second input terminal of the selector 29c, and the timing t ₂ is further input to the second input terminal of the selector 29d by the flip-flop 27. _The RAS signal with a shift of ₃ is input.

The inverted MODE signal is input to the first input terminal of the AND gate 24, and the refresh signal is input to the second input terminal thereof. The output signal of the AND gate 24 is input to the third input terminals of the selectors 29a to 29d. Therefore, when the refresh signal (REF signal) is input to the selectors 29a to 29d, the selectors 29a to 29d output RAS0 to RAS3, respectively, which are shifted in timing, as shown in FIGS. 6 (e) to (i). The memory banks 30a to 30d perform a refresh operation of each memory bank by shifting the timing for each memory bank.

Next, the operation of refreshing the memory bank will be described with reference to FIG. First, FIG. 6 (a)
Corresponding to the clock signal shown in FIG. 6, the mode (MODE) signal is ON (MODE signal =
1), the AND gate 23 is opened, and the REF signal is transmitted through the OR gates 22a to 22d to the AND gate 28.
It is input to the first input terminals of a to 28d. Then, this REF signal is opened by the RAS signal input to the second input terminals of the AND gates 28a to 28d, and the AND gates 28a to 28d are opened to enter the normal refresh mode.

That is, as shown in FIG.
The F signal is turned on (REF = 1), and the RAS signal is activated in the next cycle as shown in FIG. 6 (e). As a result, as shown in FIG. 6D, irrespective of the values of the select signals AD0 to AD1 of the memory banks, FIG.
The signals of RAS0 to RAS3 shown in (i) are activated, and the memory banks 30a to 30d are simultaneously refreshed.

Further, the mode (MODE) signal is OFF
When it is switched to (MODE signal = 0), the AND gate 23 is closed, so that the REF signal becomes the OR gate 2
It is not sent to 2a to 22d. On the other hand, AND gate 2
In MODE 4, since the MODE signal "0" is inverted and becomes "1", the AND gate 24 is opened and the REF signal is sent to the selectors 29a to 29d. Then, low power refresh can be performed in the same manner as in the first embodiment described above.

That is, first, in response to the clock signal shown in FIG. 6A, as shown in FIG.
The signal becomes 0, the REF signal becomes ON (RFF = 1) as shown in FIG. 6C, and at the same time, the AD0 to AD1 signals are fixed as shown in FIG. 6D. (In the refresh operation, AD0 to AD1 may be anything.) In the next cycle, as shown in FIG. 6 (e), the RAS signal is activated, the timing is changed by the flip-flops (FF0 to FF2) 25 to 27, and then the selector is selected. (SL0-SL
3) The signals RAS0 to RAS3 as shown in FIGS. 6F to 6I are passed through 29a to 29d and supplied to the memory banks 30a to 30d at the respective timings to perform the refresh operation.

As described above, by switching the mode (MODE) signal, the normal refresh mode and the low power refresh mode can be switched.
This MODE signal monitors, for example, the overall power consumption state of the information processing apparatus by a central processing unit (not shown), and when viewed from the overall power consumption state of the information processing apparatus, excessive power consumption at the time of refreshing is observed. If you want to shorten the refresh execution cycle even at the expense of MODE,
When the signal is turned on to enter the normal refresh mode and the refresh execution cycle is long, but the excessive power during refreshing is desired to be suppressed, the MODE signal is turned off to enter the low power refresh mode. That is,
A mode can be easily selected according to the usage state and purpose of use.

The present invention is not limited to the above embodiments, and various modifications can be made based on the spirit of the present invention, and they are not excluded from the scope of the present invention.

[0029]

As described in detail above, according to the present invention, the following effects can be obtained. (1) In the main memory device having a plurality of banks of the information processing device, the timing is shifted for each memory bank, which causes excessive power consumption at the time of refresh activation, and
It is possible to provide a highly reliable memory control system for a main storage device that reduces power supply noise, has a large capacity, low power consumption, and is highly reliable.

(2) By shifting the timing for each memory bank, it is possible to switch between the first mode in which the refresh operation of each memory bank is executed and the second mode in which the refresh operation of each memory bank is simultaneously executed. Therefore, in view of the power consumption state of the entire information processing apparatus, if the refresh execution cycle is desired to be shortened even if the excessive power consumption at the time of refresh is sacrificed,
In the first mode, if you want to suppress excessive power during refreshing even if the refresh execution cycle is long,
It is possible to improve the throughput while switching to the second mode, that is, by controlling the memory of the main storage device according to the usage state and purpose of use, while observing the power consumption state of the information processing device.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a memory control circuit in a main memory device having a plurality of banks according to a first embodiment of the present invention.

FIG. 2 is a timing chart of a refresh operation of each memory bank in the main memory device having a plurality of banks according to the first embodiment of the present invention.

FIG. 3 is a configuration diagram of a memory control circuit in a conventional main memory device having a plurality of banks.

FIG. 4 is a timing chart of a refresh operation of each memory bank in a conventional main memory device having a plurality of banks.

FIG. 5 is a configuration diagram of a memory control circuit in a main memory device having a plurality of banks according to a second embodiment of the present invention.

FIG. 6 is a timing chart of a refresh operation of each memory bank in the main memory device having a plurality of banks according to the second embodiment of the present invention.

[Explanation of symbols]

11,21 Decoders 12a to 12d, 23, 24, 28a to 28d AN
D gate 13-15, 25-27 Flip-flop 16a-16d, 29a-29d Selector 17a-17d, 30a-30d Memory bank 22a-22d OR gate

Claims (2)

[Claims] 1. A memory control system in a main memory device having a plurality of memory banks of an information processing device, comprising:
A decoder, (b) a first input terminal connected to the output side of the decoder, and a second input terminal to which a row address strobe signal is input, and arranged corresponding to each memory bank. AND gate (c), a first input terminal connected to the output side of the AND gate, and a second input terminal to which a row address strobe signal whose timing is shifted for each memory bank is input. A selector having a third input terminal to which a refresh signal is input and arranged corresponding to each of the memory banks, and (d) a memory bank connected to each of the selectors, e) A memory control method in which the refresh operation of each memory bank is executed by shifting the timing for each memory bank. 2. A memory control method in a main memory device having a plurality of memory banks of an information processing device, comprising:
An OR gate arranged corresponding to each memory bank having a decoder, (b) a first input terminal connected to the output side of the decoder, and a second input terminal to which a mode signal is input. And (c) a first input terminal connected to the output side of the OR gate and a second input terminal to which a row address strobe signal is input, which are arranged corresponding to each of the memory banks. AND gate, and (d) the AND gate
A first input terminal connected to the output side of the gate, a second input terminal to which a row address strobe signal whose timing is shifted for each memory bank is input, and a third input to which a refresh signal is input A selector having a terminal and arranged corresponding to each of the memory banks;
(E) a memory bank connected to each of the selectors; (f) a first mode in which the refresh operation of each memory bank is executed by shifting the timing of each memory bank; A memory control method characterized in that a second mode in which a refresh operation is simultaneously executed can be switched.