JP2014108169A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine capable of performing a game using time information to be updated at adjusted update timing even if the update timing of time information used for a performance is adjusted.SOLUTION: An RTC device generates a divided frequency obtained by dividing an oscillation frequency oscillated by an oscillator, and sets state change timing for changing from a non-active state where utilization of time information has not been enabled by a CE signal to an active state where utilization of time information is enabled during time other than frequency division delay time until a first divided frequency, and a second divided frequency differing from the first divided frequency after generation of the first divided frequency from among divided frequencies. A liquid crystal control CPU adjusts input/output timing of time information clocked by the RTC device, based on the divided frequency for identifying the frequency division delay time used for setting the state change timing.

Description

  The present invention relates to a gaming machine.

  In a gaming machine that uses a game medium to perform a game, a lottery process for determining the acquisition state of the game medium is performed by entering the game medium into an area called a starting point for a bonus lottery process. By winning, you can get a lot of game media. At this time, in the gaming machine, various effects are performed in order to provide a high interest to the player.

  If the same performance is performed in each game as the performance at this time, the player becomes bored.

  In Patent Document 1, it is described that time information is acquired by operating a condition device used to operate an accessory continuous operation device, and the effect contents after the operation of the accessory continuous operation device is described. It is possible to enhance interest by determining using the acquired time information.

  Patent Document 2 describes outputting a clock signal used as a timing of control processing performed on the main control board using a crystal oscillator in paragraphs [0645] to [0654] of the specification. In addition, it is described that a divided frequency is output from a predetermined terminal of the crystal oscillator.

JP 2012-02942 A JP 2012-217743 A

  In the prior art disclosed in Patent Document 1, since time information is simply measured using a timer or the like, the time that is timed has an error with respect to the original accurate time. Sometimes. The time error at this time may be caused by various factors. For example, in addition to being caused by noise such as electromagnetic waves generated from devices such as other control boards, the characteristics of the timer that measures time There is a place.

  Further, as disclosed in Patent Document 2, a crystal oscillator or the like is generally used for generating a clock signal used for determining processing timing.

  If each game machine is individually performed using time information, it is sufficient to use the time information of each game machine. However, in the case where each game machine performs an effect using the time information of each of the plurality of game machines, a unified effect as a whole is performed due to an error generated in each game machine. It may be difficult to recognize the error, and the error may cause discomfort to the player.

  In order to cope with this, when the timing means such as a timer for timing time information is adjusted at an arbitrary timing, the timer etc. periodically The acquired time information will be shifted in each gaming machine.

  Accordingly, the present invention is capable of playing a game using time information updated at the adjusted update timing even when the update timing of the time information used for production is adjusted. An object is to provide a gaming machine.

  In order to achieve the above-mentioned object, the invention of claim 1 uses the timing control unit that performs timing control of game designation time information used in a game, and the game designation time information that is time-controlled by the timing control unit. A display control unit that performs display control of an effect image used for the effect in the game, and the timing control unit calculates the oscillation frequency by causing the oscillator to oscillate an oscillation frequency used for updating the game designation time information related to the game. A frequency dividing unit that generates a divided frequency, a first divided frequency of the divided frequencies divided by the divided frequency generating unit, and after the first divided frequency is generated Use of the game specified time information at a time other than the frequency division delay time until the second frequency division frequency different from the first frequency division frequency is generated by the frequency division frequency generation means. State change timing setting means for setting a state change timing for changing from a state that is not enabled to a state in which the use of the game specified time information is enabled, and the display control unit includes the oscillation frequency or Based on the frequency division frequency that specifies the frequency division delay time used for setting the state change timing by the state change timing setting means, the input / output timing of the game designation time information time-controlled in the time-control unit is adjusted. Timing adjustment means.

  Further, in the invention of claim 2, in the invention of claim 1, the timing adjusting means is an oscillation that is oscillated by the oscillator from an oscillation timing of a signal that makes the use of the game specified time information valid. The read timing of the game designated time information is adjusted after the time required for the frequency unit period has elapsed.

  The invention according to claim 3 is the signal cycle time according to claim 2, wherein the timing adjusting means makes the use of the game designated time information valid in the unit cycle time of the oscillation frequency. After the elapse of time, the timing for reading out the game designated time information is adjusted.

  According to the present invention, even when the update timing of time information used for production is adjusted, a game using the time information updated at the adjusted update timing can be performed. There is an effect.

The front view of the gaming machine in the embodiment of the present invention. The perspective view of the state which open | released the glass frame provided in the front surface of the game machine in embodiment of this invention. The perspective view of the back surface side of the gaming machine in the embodiment of the present invention. The block diagram which shows the whole structure of the game machine in embodiment of this invention. The figure which shows an example of the determination table which performs the hit determination for every special symbol and normal symbol performed in the gaming machine in the embodiment of the present invention. The figure which shows an example of the symbol determination table which determines the stop symbol of the special symbol in the gaming machine in the embodiment of the present invention. The figure which shows an example of the big hit game completion | finish setting data table for determining the game state after the big hit game performed with the game machine in embodiment of this invention is complete | finished. The figure which shows an example of the special electric accessory operating mode determination table for determining the big winning opening opening mode determination table. The figure which shows the structure of the special prize opening release mode determination table determined using the special electric accessory operation mode determination table shown in FIG. The figure which shows the fluctuation pattern determination table which determines the fluctuation pattern of a special symbol. The figure which shows an example of the effect pattern determination table for determining the fluctuation | variation aspect of the effect symbol displayed in a 1st liquid crystal display device and a 2nd liquid crystal display device. The block diagram which shows the structure of the frame buffer used in the image control board of the game machine in embodiment of this invention. The figure which shows the animation information used in the image control board of the game machine in embodiment of this invention. An example of a display list including drawing control commands used on an image control board of a gaming machine according to an embodiment of the present invention. The flowchart which shows the detailed flow of the main process performed with the main control board of the game machine in embodiment of this invention. The flowchart which shows the detailed flow of the timer interruption process performed with the main control board of the game machine in embodiment of this invention. The flowchart which shows the detailed flow of the special figure special electric control process performed with the main control board of the game machine in embodiment of this invention. The flowchart which shows the detailed flow of the special symbol memory | storage determination process performed with the main control board of the game machine in embodiment of this invention. The flowchart which shows the detailed flow of the main process performed with the presentation control board of the gaming machine in the embodiment of the present invention. The flowchart which shows the detailed flow of the timer interruption process performed with the presentation control board of the gaming machine in the embodiment of the present invention. The flowchart which shows the detailed flow of the command analysis process performed with the presentation control board of the gaming machine in the embodiment of the present invention. The flowchart which shows the continuation of the flowchart which shows the detailed flow of the command analysis process performed with the presentation control board of the gaming machine in the embodiment of the present invention. The flowchart which shows the detailed flow of the main process performed in the image control board of the game machine in embodiment of this invention. The flowchart which shows the detailed flow of the interruption process performed in the image control board of the game machine in embodiment of this invention. The block diagram which shows the detailed structure of the RTC apparatus which comprises the game machine in embodiment of this invention. The timing chart in the update process of the time information performed in the gaming machine in the embodiment of the present invention. The timing chart in the update process of the time information performed in the gaming machine in the embodiment of the present invention. The timing chart in the update process of the time information performed in the gaming machine in the embodiment of the present invention. The timing chart in the update process of the time information performed in the gaming machine in the embodiment of the present invention. The flowchart which shows the detailed flow of the main process performed in the RTC apparatus of the game machine in embodiment of this invention. The flowchart which shows the detailed flow of the timing control process which comprises the main process performed in the RTC apparatus shown in FIG. The example of the flowchart which shows the detailed flow of the state change timing setting process shown in FIG. FIG. 32 is another example of a flowchart showing a detailed flow of the state change timing setting process shown in FIG. 31. The flowchart which shows the detailed flow of the output process of the time information which the RTC apparatus which the game machine in embodiment of this invention comprises performs. The block diagram which shows the detailed structure of liquid crystal control CPU which the game machine in embodiment of this invention comprises. FIG. 3 is a configuration block diagram of timing control processing performed in the gaming machine according to the embodiment of the present invention. The flowchart which shows the detailed flow of the process performed in the delay control apparatus shown in FIG. The figure which shows the transition state of the production mode in which the gaming machine in embodiment of this invention changes. The figure which shows an example of the timing chart described about the relationship between specific production | presentation mode and a design fluctuation. The figure which shows the example which displayed the effect design by the dot display on the liquid crystal display device of the game machine in embodiment of this invention. The figure which shows the state in which the some game machine was each arranged in the right-and-left horizontal line across the channel | path.

  Hereinafter, an embodiment of a gaming machine according to the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is an example of a device configuration diagram of a gaming machine 1 configured by applying the gaming machine according to the embodiment of the present invention. FIG. 2 shows the gaming machine 1 in a state where the glass frame of the present invention is opened. FIG. 3 is a perspective view of the back side of one gaming machine 1.

  The gaming machine 1 includes an outer frame 60 attached to an island facility of a game store, and a glass frame 50 that is rotatably supported by the outer frame 60 (see FIGS. 1 and 2). Further, the outer frame 60 is provided with a game board 2 in which a game area 6 in which game balls flow down is formed. In the glass frame 50, an operation handle 3 for launching a game ball toward the game area 6 by being rotated, an audio output device 32 including a speaker, an effect lighting device 34 having a plurality of lamps, An effect button 35 for changing the effect mode by pressing operation and a cross key 36 capable of pressing operation in at least two directions (usually four directions) are provided.

  Further, the glass frame 50 is provided with a tray 40 for storing a plurality of game balls, and the tray 40 has a downward slope so that the game balls flow down toward the operation handle 3. (See FIG. 2). A receiving opening for receiving a game ball is provided at the end of the downward slope of the tray 40, and the game ball received in the receiving opening is driven by the ball feed solenoid 4b, so that the glass frame 50 One game ball is sent to the ball feed opening 41 provided on the back surface one by one.

  Then, the game ball sent out to the ball feed opening 41 is guided to the end of the downward slope of the launch rail 42 by the launch rail 42 having a downward slope toward the launching member 4c. A stopper 43 for stopping and stopping the game ball is provided above the end of the firing rail 42 that is inclined downward, and the game ball sent out from the ball feed opening 41 is the end of the downward inclination of the launch rail 42. One game ball is stopped at the section (see FIG. 2).

  Then, when the player rotates the operation handle 3, the launch volume 3b directly connected to the operation handle 3 also rotates, and the launch intensity of the game ball is adjusted by the launch volume 3b, and the launch is performed with the adjusted launch intensity. The launch member 4c directly connected to the solenoid 4a for rotation rotates. As the launch member 4c rotates, the launch ball 4c launches the game ball stored at the end of the downward slope of the launch rail 42, and the game ball is launched into the game area 6.

  When the game ball fired as described above rises between the rails 5a and 5b from the launch rail 42 and exceeds the ball return prevention piece 5c, the game ball reaches the game area 6 and then freely falls within the game area 6. . At this time, the game ball falls unpredictably by a plurality of nails and windmills provided in the game area 6.

  The game area 6 is provided with a plurality of general winning awards 12.

  Each of these general winning ports 12 is provided with a general winning port detecting switch 12a. When the general winning port detecting switch 12a detects a winning of a game ball, a predetermined winning ball (for example, ten game balls) is provided. To be paid out.

  Further, in the area below the center of the game area 6, there are a first start port 14 and a second start port 15 that constitute a start area into which game balls can enter, and a second large area in which game balls can enter. A winning opening 17 is provided.

  The second start port 15 includes a pair of second start port movable pieces 15b, and the pair of second start port movable pieces 15b is maintained in a closed state. The pair of second start opening movable pieces 15b are controlled to move to the “second mode” in which the pair is opened.

  At this time, when the second start port 15 is controlled to the second mode, the pair of second start port movable pieces 15b function as a tray, and a game ball wins the second start port 15. It becomes easy. That is, when the second start port 15 is in the first mode, there is no game ball winning opportunity, and when it is in the second mode, the game ball winning opportunity is increased as compared to the first mode.

  Here, the first start port 14 is provided with a first start port detection switch 14a for detecting the entrance of a game ball, and the second start port 15 is provided with a second start port detection switch for detecting the entrance of a game ball. 15a is provided. When the first start port detection switch 14a or the second start port detection switch 15a detects the entry of a game ball, a special symbol determination random number value is acquired, and a right acquisition lottery (to be described later) Hereinafter, “Lottery for jackpot” is performed.

  In addition, when the first start port detection switch 14a or the second start port detection switch 15a detects the entry of a game ball, the predetermined start port detection switch 12a has a predetermined value in the same manner as when the general winning port detection switch 12a detects the winning of a game ball. Prize balls (for example, three game balls) are paid out.

  Further, the second grand prize winning port 17 is constituted by an opening formed in the game board 2.

  A movable piece 17b for the second big prize opening is provided at the right end of the second big prize opening 17, and the second big prize prize is moved by moving one of the movable pieces 17b for the second big prize opening as a fulcrum. An open state that makes it easy to win the mouth 17 and a closed state that cannot win a prize are controlled.

  When the movable piece 17b for the second big prize opening is opened, the movable piece 17b for the second big prize opening functions as a tray for guiding the game ball into the second big prize opening 17, and the game ball is the second. It is possible to enter the big winning opening 17. The second big prize opening 17 is provided with a second big prize opening detection switch 17a. When the second big prize opening detection switch 17a detects the entry of a game ball, a predetermined prize ball ( For example, 15 game balls) are paid out.

  Furthermore, in the area on the right side of the game area 6, there are provided a normal symbol gate 13 constituting a normal area through which game balls can pass and a first grand prize opening 16 through which game balls can enter.

  For this reason, if the operation handle 3 is rotated largely and a game ball is not launched with a greater force than the game ball is launched in the left area of the game area 6, the game will be displayed in the normal symbol gate 13 and the first big prize opening 16. The ball is configured not to pass or win.

  In particular, even if the short game state, which will be described later, is entered, if the game ball flows down to the left side of the game area 6, the game ball will not normally pass through the symbol gate 13, so that it is at the second start port 15. The pair of second start opening movable pieces 15b are not opened, and it is difficult for a game ball to win the second start opening 15.

  The normal symbol gate 13 is provided with a gate detection switch 13a for detecting the passage of the game ball. When the gate detection switch 13a detects the passage of the game ball, the normal symbol determination random number value is acquired, which will be described later. “Normal lottery” is performed. This normal symbol gate 13 is also provided in the area on the right side of the game area.

  The first grand prize opening 16 is normally kept closed by the first big prize opening opening / closing door 16b, and it is impossible to enter a game ball. In contrast, when a special game, which will be described later, is started, the first grand prize opening opening / closing door 16b is opened, and the first big prize opening opening / closing door 16b puts the game ball in the first big winning opening 16; It functions as a receiving tray that guides the game ball and can enter the first grand prize opening 16. The first grand prize opening 16 is provided with a first big prize opening detection switch 16a. When the first big prize opening detection switch 16a detects the entry of a game ball, a predetermined prize ball (for example, 15 Game balls).

  Furthermore, at the bottom of the game area 6, the player does not enter any of the general winning opening 12, the first starting opening 14, the second starting opening 15, the first major winning opening 16, and the second major winning opening 17. An out port 11 is provided for discharging the game balls.

  In addition, a decoration member 7 that affects the flow of the game ball is provided in the center of the game area 6. A first liquid crystal display device 31 (hereinafter also referred to as “main liquid crystal”) configured by an LCD (Liquid Crystal Display) or the like is provided at a substantially central portion of the decorative member 7, and the first liquid crystal display device. A decoration device 33 a is provided above 31. A second liquid crystal display device 37 (33b) (hereinafter also referred to as “sub liquid crystal”) having a size smaller than that of the first liquid crystal display device 31 is provided above the first liquid crystal display device 31.

  The decoration device 33a and the second liquid crystal display device 37 (33b) are driven by the effect drive device 33. That is, the second liquid crystal display device 37 (33b) has a function and a drive for displaying the effect image. It has the function to do. The second liquid crystal display device 37 (33 b) displays an effect image by a signal from the image control board 150 and is driven by the effect driving device 33.

  In FIG. 1 and FIG. 1, an example of the second liquid crystal display device 37 having a size (4.3 inches) smaller than the size (19 inches) of the first liquid crystal display device 31 is shown as an example. The second liquid crystal display device 37 may be larger in size than the first liquid crystal display device 31.

  The first liquid crystal display device 31 displays a demo image during standby when no effects are being performed, or displays an image according to the progress of the game. Among them, three effect symbols 38 for informing a lottery lottery result to be described later are displayed, and a combination of specific effect symbols 38 (for example, 777) is stopped and displayed as a result of the jackpot lottery. A big hit is announced.

  More specifically, when a game ball enters the first start port 14 or the second start port 15, the three effect symbols 38 are displayed in a variable manner by scroll display (rotation display), and a predetermined time has elapsed. Later, the scrolling is stopped, and the effect design 38 is stopped and displayed. Further, by displaying an effect image composed of characters or the like during the variation display of the effect symbol 38, a high expectation that the player may win a big hit is given to the player.

  The decoration device 33a or the like driven by the effect drive device 33 gives a player a sense of expectation by an operation mode using the effect image.

  The decoration device 33a driven by the effect drive device 33 can move in the vertical direction simultaneously with the second liquid crystal display device 37 (33b) (of course, it is not limited to the vertical direction and can be moved in the vertical and horizontal directions). Thus, the movement in the vertical direction moves to the front surface of the first liquid crystal display device 31. The decoration device 33a is equipped with an effect lighting device 34 and lights up in conjunction with the movement of the decoration device 33a or independently.

  Similarly to the decoration device 33a, the second liquid crystal display device 37 (33b) can be moved by being driven by the effect drive device 33, and the second liquid crystal display device 37 shown in FIG. Is shown in a state of being stored in a horizontally-oriented manner with the up and down direction.

  In the state of this horizontal orientation, the second liquid crystal display device 37 moves to the front surface of the substantially central portion of the first liquid crystal display device by the lowering operation.

  Furthermore, in addition to the above-described various production devices, the audio output device 32 outputs BGM (background music), SE (sound effects), etc., and produces productions using sound. The illumination direction and the emission color of the light are changed to produce effects by illumination, and are provided at a plurality of positions.

  In the lower right of the game area 6, a first special symbol display device 20, a second special symbol display device 21, a normal symbol display device 22, a first special symbol hold indicator 23, a second special symbol hold indicator 24, a normal A symbol hold indicator 25 is provided.

  The first special symbol display device 20 informs the result of the jackpot lottery performed when a game ball has entered the first start port 14, and is a plurality of lighting composed of LEDs or the like. It is comprised by the member. One or more predetermined lighting members blink according to the result of the lottery lottery, and the lighting members in the blinking state are lit simultaneously with the stop display of the effect symbol 38.

  The first special symbol display device 20 can also be configured by a 7-segment LED. That is, a plurality of special symbols corresponding to the jackpot lottery result are provided, and the lottery result is notified to the player by displaying the special symbol corresponding to the jackpot lottery result on the first special symbol display device 20. I am doing so. For example, “7” is displayed when the jackpot is won, and “−” is displayed when the player wins. “7” and “−” displayed in this way are special symbols, but these special symbols are not displayed immediately, but are displayed in a stopped state after being displayed for a predetermined time. .

  Here, the “successful lottery” means that when a game ball enters the first start port 14 or the second start port 15, a special symbol determination random number value is acquired, and the acquired special symbol determination random value is acquired. Is a random number value corresponding to “big hit” or a random number value corresponding to “small hit”. The jackpot lottery result is not immediately notified to the player, and the first special symbol display device 20 displays a variation such as blinking of the special symbol, and when the predetermined variation time has passed, the jackpot lottery result The special symbol corresponding to is stopped and displayed so that the player is notified of the lottery result.

  The second special symbol display device 21 is for notifying a lottery result of a jackpot that is performed when a game ball enters the second start port 15, and the display mode is the above-described first display mode. This is the same as the special symbol display mode in the special symbol display device 20.

  Further, in this embodiment, “big hit” means that a right to win a big hit game is obtained in a big win lottery performed on condition that a game ball has entered the first start port 14 or the second start port 15 Say what you did. In the “hit game”, a round game in which the first big prize opening 16 or the second big prize opening 17 is opened is performed a predetermined number of times (for example, 15 times). A predetermined time is set for the maximum opening time of the first grand prize port 16 or the second grand prize port 17 in each round game, and during this time, the first grand prize port 16 or the second grand prize port 17 is set. When a predetermined number of game balls (for example, nine) enter, one round game is completed.

  In other words, the “big hit game” is a game in which a game ball can enter the first grand prize winning opening 16 or the second big winning prize opening 17 and the player can acquire a winning ball according to the winning prize.

  The normal symbol display device 22 is for notifying the lottery result of the normal symbol that is performed when the game ball passes through the normal symbol gate 13. As will be described in detail later, when the winning symbol is won by the normal symbol lottery, the normal symbol display device 22 is turned on, and then the second start port 15 is controlled to the second mode for a predetermined time.

  Here, “normal symbol lottery” means that when a game ball passes through the normal symbol gate 13, the normal symbol determination random number value is acquired, and the acquired normal symbol determination random value corresponds to “winning”. This is a process for determining whether or not a random value. The lottery result of the normal symbol is not always notified immediately after the game ball passes through the normal symbol gate 13, but the normal symbol display device 22 displays a variation such as blinking of the normal symbol. When the fluctuation time elapses, the normal symbol corresponding to the lottery result of the normal symbol is stopped and displayed so that the player is notified of the lottery result.

  Furthermore, if a game ball enters the first start port 14 or the second start port 15 during special symbol fluctuation display or a special game to be described later, and if a big win lottery cannot be performed immediately, a certain condition The right to win a jackpot will be withheld.

  More specifically, the random number value for special symbol determination acquired when the game ball enters the first start port 14 is stored as the first hold, and when the game ball enters the second start port 15 The acquired special symbol determination random number value is stored as the second hold.

  For both of these holds (first hold and second hold), the upper limit hold number is set to four, and the hold numbers are respectively set to the first special symbol hold indicator 23 and the second special symbol hold indicator 24. Is displayed.

  When there is one first hold, the leftmost LED of the first special symbol hold indicator 23 lights up, and when there are two first holds, the leftmost end of the first special symbol hold indicator 23 The two LEDs turn on. When there are three first holds, three LEDs blink from the leftmost end of the first special symbol hold indicator 23 and the right LED is lit. When there are four first holds, the first Four LEDs blink from the leftmost end of the special symbol hold indicator 23.

  The second special symbol hold indicator 24 also displays the number of second hold on hold in the same manner as described above.

  The upper limit reserved number of normal symbols is also set to four, and the reserved number of normal symbols is displayed in the same manner as the first special symbol hold indicator 23 and the second special symbol hold indicator 24. Displayed on the instrument 25.

  The glass frame 50 supports a glass plate 52 that covers the game area 6 so as to be visible in front of the game board 2 (player side). The glass plate 52 is detachably fixed to the glass frame 50.

  The glass frame 50 is connected to the outer frame 60 via a hinge mechanism 51 on one end side in the left-right direction (for example, the left side facing the gaming machine 1). The end side (for example, the right side facing the gaming machine 1) can be rotated in a direction to release from the outer frame 60. The glass frame 50 covers the game board 2 together with the glass plate 52, and can be opened like a door with the hinge mechanism 51 as a fulcrum to open the inner part of the outer frame 60 including the game board 2.

  On the other end side of the glass frame 50, a lock mechanism for fixing the other end side of the glass frame 50 to the outer frame 60 is provided. The fixing by the lock mechanism can be released by a dedicated key. The glass frame 50 is also provided with a door opening switch 133 that detects whether or not the glass frame 50 is opened from the outer frame 60.

  On the back surface of the gaming machine 1, as shown in FIG. 3, a main control board 110, an effect control board 120, a payout control board 130, a power supply board 170, a game information output terminal board 30, and the like are provided. The power supply board 170 is provided with a power plug 171 for supplying power to the gaming machine 1 and a power switch (not shown).

  Next, control means for controlling the progress of the game will be described using the block diagram of the entire gaming machine 1 in FIG.

  The main control board 110 is a main control means for controlling the basic operation of the game, and receives various detection signals from the first start port detection switch 14a, etc., and the first special symbol display device 20 and the first big winning port opening / closing solenoid. The game is controlled by driving 16c and the like.

  The main control board 110 includes at least a one-chip microcomputer 110m including a main CPU 110a, a main ROM 110b, and a main RAM 110c, an input port for main control, and an output port (not shown).

  The main control input port includes a payout control board 130, a general winning port detection switch 12a for detecting that a game ball has entered the general winning port 12, and a game ball having entered the normal symbol gate 13. Gate detection switch 13a to detect, first start port detection switch 14a to detect that a game ball has entered the first start port 14, and second start to detect that a game ball has entered the second start port 15 The mouth detection switch 15a, the first grand prize opening detection switch 16a that detects that a game ball has entered the first grand prize opening 16, and the second that detects that a game ball has entered the second grand prize opening 17 A big prize opening detection switch 17a is connected. Various signals are input to the main control board 110 through the main control input port.

  The output port for main control includes a payout control board 130, a start port opening / closing solenoid 15c for opening / closing the pair of second start port movable pieces 15b of the second start port 15, and a first big prize opening opening / closing door 16b. The first large winning opening / closing solenoid 16c for operating the second large winning opening / closing solenoid 17c for operating the movable piece 17b for the second large winning opening, the first special symbol display device 20 for displaying special symbols, and the second special symbol. Display device 21, normal symbol display device 22 for displaying normal symbols, first special symbol hold indicator 23 and second special symbol hold indicator 24 for displaying the number of reserved symbols for special symbols, and the number of reserved balls for normal symbols The normal symbol hold display 25 and the game information output terminal board 30 for outputting an external information signal are connected. Various signals are output from the main control output port.

  The main CPU 110a reads out a program stored in the main ROM 110b based on an input signal from each detection switch or timer, performs arithmetic processing, directly controls each device or display, or determines the result of the arithmetic processing. In response, a command is transmitted to another board.

  The main CPU 110a can perform a jackpot lottery on the holding ball before the lottery processing on the holding ball and pre-acquire (pre-read) the lottery result. At this time, the pre-acquired lottery result is produced. The image is sent to the image control board 150 via the control board 120.

  The main ROM 110b of the main control board 110 stores a game control program and data and tables necessary for determining various games. For example, (1) a jackpot determination table referred to in the jackpot lottery, (2) a hit determination table referred to in the normal symbol lottery, (3) a symbol determination table for determining a special symbol stop symbol, and (4) a jackpot end Big hit game end setting data table for determining the subsequent gaming state, (5) Special electric accessory actuating mode determination table for determining the opening / closing conditions of the opening / closing doors of the first big winning opening 16 and the second big winning opening 17 , (6) a big prize opening opening determination table for specifying the opening manner of the first big winning opening 16 and the second big winning opening 17, (6) a variation pattern determining table for determining a variation pattern of special symbols, and the like. ing.

  Note that the above-described table is merely an example of characteristic tables among the tables in the present embodiment, and a number of other tables and programs (not shown) are provided for the progress of the game. ing.

  Next, details of various tables stored in the main ROM 110b of the main control board 110 will be described with reference to FIGS.

  FIG. 5 is a diagram showing an example of a determination table for performing a hit determination for each special symbol and normal symbol performed in the gaming machine according to the embodiment of the present invention.

  FIG. 5 (a-1) and FIG. 5 (a-2) are diagrams showing a jackpot determination table used for the “big winner lottery”.

  FIG. 5A-1 is a jackpot determination table (a jackpot determination table for the first special symbol display device) referred to in the first special symbol display device 20, and FIG. It is a jackpot determination table (a jackpot determination table for the second special symbol display device) referred to in the special symbol display device 21. In the tables of FIG. 5 (a-1) and FIG. 5 (a-2), although the winning probabilities for small hits are different, the jackpot probabilities are the same.

  Specifically, the big hit determination table is for determining “big hit”, “small hit”, or “losing” based on the current probability gaming state and the acquired random numbers for determining special symbols.

  For example, according to the jackpot determination table for the first special symbol display device shown in FIG. 5 (a-1), in the low probability gaming state, all the special symbol determinations “7” and “8” are performed. On the other hand, when the random number value is determined to be a jackpot, all the 20 special symbol determination random numbers “7” to “26” are determined to be a jackpot when the gaming state is a high probability game state.

  Further, according to the jackpot determination table for the first special symbol display device shown in FIG. 5 (a-1), the special symbol determination for either the low probability gaming state or the high probability gaming state. When the random number values are all four special symbol determination random values of “50”, “100”, “150”, and “200”, it is determined as “small hit”. Although not shown, when the random number is other than the special symbol determination random number shown above, it is determined as “lost”.

  Accordingly, since the random number range of the special symbol determination random number value is “0” to “598”, the probability of being determined as “big hit” in the low-probability gaming state is “1 / 299.5” and high The probability of being determined as “big hit” in the probability gaming state is “1 / 29.9”, which is approximately 10 times.

  Further, in the first special symbol display device 20, the probability of being determined as “small hit” is “1 / 149.75” regardless of whether the gaming state is the low probability gaming state or the high probability gaming state.

  Next, FIG. 5B is a diagram showing a hit determination table used for “ordinary symbol lottery”.

  Specifically, the winning determination table is for determining “winning” or “losing” based on the presence / absence of the short-time gaming state and the acquired random number for normal symbol determination.

  For example, according to the hit determination table shown in FIG. 5B, in the non-short-time gaming state, one normal symbol determination random value of “0” is determined to be a win, while in the short-time gaming state. In some cases, it is determined that all 65535 normal symbol determining random numbers from “0” to “65534” are hits. Although not shown, if the random number is other than the normal symbol determining random number shown above, it is determined as “lost”.

  Accordingly, since the random number range of the normal symbol determination random number value is “0” to “65535”, the probability of being determined as “winning” in the non-time saving gaming state is “1/65536”, and the time saving gaming state The probability of being determined as “winning” at the time of is “65535/65536”.

  FIG. 6 is a diagram showing a symbol determination table for determining a special symbol stop symbol.

  FIG. 6A is a symbol determination table that is referred to in order to determine a stop symbol at the time of a big hit, and FIG. 6B is a symbol that is referred to in order to determine a stop symbol at the time of a big hit. FIG. 6C is a symbol determination table that is referred to in order to determine a symbol to be stopped when a loss occurs.

  Specifically, according to the symbol determination table shown in FIG. 6, a special ball display device type (a type of a start opening in which a game ball has won) and a game ball at the first start port 14 or the second start port 15. The special symbol type (stop symbol data) is determined based on the jackpot symbol random number value or the small bonus symbol random number value acquired when the ball is entered.

  For example, the first special symbol display device 20 refers to the symbol determination table shown in FIG. 6A in the case of “big hit”, and if the acquired big hit symbol random number value is “55”, the stopped symbol data As “03” (special symbol 3 (first probability variation 3)).

  Further, in the first special symbol display device 20, when “small hit”, the symbol determination table shown in FIG. 6B is referred to, and if the acquired random number value for small hit symbol is “50”, it is stopped. The symbol data is determined as “08” (special symbol B (small hit B)).

  In the case of “losing”, the symbol determination table shown in FIG. 6C is referred to, and “00” (special symbol 0 (losing)) is determined as stop symbol data. That is, in the case of “losing”, any random number value is determined as stop symbol data of “00”.

  Then, at the time of starting the change of the special symbol, an effect designating command is generated as special symbol information based on the determined special symbol type (stop symbol data). Here, the production symbol designation command is composed of data of “2 bytes” as a unit command, and includes “1 byte” of MODE data for identifying the control command and the contents of the control command to be executed. It consists of “1 byte” worth of DATA data. The same applies to a variation pattern designation command described later.

  As will be described later, the game state after the jackpot game (see FIG. 7) and the type of jackpot game (see FIG. 8) are determined by the type of special symbol (stop symbol data). It can be said that the type determines the gaming state after the jackpot game ends and the type of jackpot game.

  FIG. 7 is a jackpot game end setting data table for determining the gaming state after the jackpot game ends.

  Based on the special symbol type (stop symbol data) and the state stored in the game state buffer, the high probability game flag setting, the number of high probability games (X ), A short-time game flag, and a short-time count (J) are set.

  Here, the “gaming state buffer” is information indicating the gaming state at the time of winning the big hit. The gaming state includes a combination of a short-time gaming state (or a non-short-time gaming state) and a high probability gaming state (or low probability gaming state).

  Specifically, if the gaming state buffer is “00H”, it indicates the gaming state information of the low-probability gaming state and the non-short-time gaming state in which both the short-time gaming flag and the high-probability gaming flag are not set. If the gaming state buffer is “01H”, the short-time gaming flag is not set, but the high-probability gaming flag indicates gaming state information of the high-probability gaming state and the non-short-time gaming state that are set. If the gaming state buffer is “02H”, it indicates gaming state information of a low-probability gaming state and a short-time gaming state in which the short-time gaming flag is set but the high-probability gaming flag is not set. If the game state buffer is “03H”, it indicates the game state information of the high-probability gaming state and the short-time gaming state in which both the short-time gaming flag and the high-probability gaming flag are set.

  In the jackpot game end setting data table shown in FIG. 7, even if the type of the same special symbol, the setting of the short-time game flag and the number of short-time games (J) are made different based on the information stored in the game state buffer. Is possible.

  Specifically, when the type of the special symbol is special symbol 3 (corresponding to stop symbol data 03, first probability variation jackpot “3”), regarding the high probability game flag and the high probability game number (X), Regardless of the information stored in the state buffer, the high probability game flag is set after the jackpot game ends, and the high probability game count (X) is set to “10000 times”.

  On the other hand, regarding the short-time game flag and the short-time number of times (J), if information (“00H” or “01H”) indicating a game state in which the short-time game flag is not set is stored in the game state buffer, Does not set the short-time game flag, and sets the short-time number (J) to “0”. On the other hand, if information (“02H” or “03H”) indicating the gaming state in which the short-time gaming flag is set is stored in the gaming state buffer, the short-time gaming flag is set after the big hit game is finished. , The number of time reduction (J) is set to “10000 times”.

  Thereby, the number of time reductions (J) can be changed according to the gaming state at the time of winning the jackpot, and the player can be interested in the gaming state at the time of winning the jackpot.

  FIG. 8 is a special electric accessory actuating mode determination table for determining the special winning opening opening mode determining table.

  With reference to the special electric accessory operating mode determination table shown in FIG. 8, the special winning opening opening mode determination table is determined based on the type of special symbol (stop symbol data).

  As will be described later, since the jackpot game is executed based on the jackpot opening mode determination table, it can be said that the jackpot opening mode determination table indicates the type of jackpot game.

  Further, the special electric accessory actuating mode determination table shown in FIG. 8 is characterized in that, in the second special symbol display device 21 that is actuated when a game ball enters the second starting port 15, the “short hit table” is used. "Is not determined.

  This is because, in the non-short-time gaming state, almost no gaming ball enters the second starting port 15, but “short hit” is determined when a gaming ball enters the second starting port 15. This is because even if the short-time gaming state is provided, the player's willingness to play may be reduced.

  In the present embodiment, the second special symbol display device 21 is configured not to determine the “short hit table”. Of course, the second special symbol display device 21 also determines the “short hit table”. You may comprise. However, in the case of determining the “short hit table” in the second special symbol display device 21, compared with the first special symbol display device 20 that is activated when a game ball enters the first start port 14, By configuring the “short hit table” to be difficult to determine for the reasons described above, it is possible to prevent a decrease in game motivation.

  FIG. 9 is a diagram showing a configuration of the big prize opening opening mode determination table determined in FIG. 8, and the first big winning hole opening / closing door 16b or the second big winning hole is used according to the big winning hole opening mode determination table. The opening / closing conditions of the movable piece 17b are determined.

  FIG. 9A shows a big winning opening opening determination table group for jackpots that is referred to in the jackpot game, and is composed of a long winning table, a short winning table, and an advanced winning table.

  FIG. 9B shows a big winning opening releasing mode determination table group for small hits determined at the small hit game.

  Then, a long hit game is executed based on the long hit table, a short hit game is executed based on the short hit table, a development game as described later is executed based on the developed hit table, The small hit game is executed based on the winning opening opening mode determination table.

  In the big winning opening opening determination table for jackpot shown in FIG. 9 (a), the type of the big winning opening to be opened (the first big winning opening 16 or the second big winning opening 17) and the one big win game The maximum number of round games (R), the specified number indicating the maximum number of winnings in the big winning opening in one round, the start interval time from the start of the big hit game to the execution of the first round game, and in each round game Maximum number of times of opening of the grand prize opening (K), opening time of the big winning opening for one opening of each round game, and closing time of the big winning opening for one opening of each round game And the closing interval time of the big prize opening from the end of one round game to the execution of the next round game, and the end interval time from the end of the last round game to the end of the jackpot game Are 憶.

  On the other hand, in the large winning opening opening determination table for small hits shown in FIG. 9B, the type of the large winning opening to be opened (the first large winning opening 16 or the second large winning opening 17), The maximum number of times of opening (K) in a single small hit game, a specified number indicating the maximum number of winning points in a single winning game, and the first large winning opening is opened from the start of the small hit game Until the end of the small hit game from the end of the closing time of the last prize winning opening and the closing time of the last prize winning opening The interval time is stored.

  Here, according to the long winning table of the big winning prize opening opening determination table for jackpot shown in FIG. 9A, the first big winning opening opening / closing door 16b is operated, and the first winning prize opening / closing door 16b is located on the right side of the game area 6. The grand prize winning opening 16 can be opened up to a maximum of “approximately 29 seconds” per round.

  However, when the specified number (9) of game balls have won the first grand prize opening 16 before the opening time has passed “approximately 29 seconds”, the operation of the first grand prize opening opening / closing door 16b is terminated. The game for one round will end.

Here, the short win table of the big winning prize opening manner determination table for jackpots shown in FIG. 9A and the big winning opening release mode determination table for small hits shown in FIG. 9B are the maximum number of round games ( R), the maximum number of times of opening (K), the closing interval time, and the closing time of the big winning opening at each opening number, there are data differences, but the same second big winning opening 17 performs the same opening / closing operation (second large) The winning opening 17 repeats “opening for 0.052 seconds” and closing for “2.0 seconds” for “15 times”), and the player is “short win game” or “small hit game” from the appearance. Cannot be determined.

  Thereby, it is possible to cause the player to guess whether the game is “short hit game” or “small hit game”.

  In this embodiment, the opening time in the “short hit game” and the opening time in the “small hit game” are set to the same opening time (“0.052 seconds”), and the closing time in the “short hit game” An example is shown in which the closing time in the “small hit game” is set to the same closing time (“2 seconds”).

  Of course, the present invention is not limited to this, and a configuration in which a time difference that the player cannot discriminate between “short win game” and “small hit game” may be provided.

  In addition, the per-development table of the big winning prize opening mode determination table for jackpot shown in FIG. 9A is also the above-described short winning game and small winning game until the third big winning opening is opened (K = 3). The second grand prize opening 17 performs the same opening / closing operation (the second big prize opening 17 repeats an opening time of “0.052 seconds” and a closing time of “2.0 seconds”), and the player looks Therefore, it is not possible to determine whether the game is “game per development, game per short, or game per short”.

  However, from the opening of the fourth grand prize opening (maximum number of round games (R) = "2", maximum number of big winning openings (K) = "1"), the opening of the big prize opening for games per development The time becomes longer ("approximately 29 seconds"), and the game per development can be discriminated from the short win game and the small hit game.

  For this reason, a game that first causes the player to recognize that the game is a short hit game or a small hit game, and then causes the player to recognize that the game ball is a jackpot game that can be acquired (this game is referred to as “game per development”). It can be performed.

  In this embodiment, until the opening of the big prize opening where the game per development becomes indistinguishable from the short hit game and the small hit game, the opening time of the big prize opening of the game per development is reduced to the short win game and the small hit game. The opening time is set to the same opening time ("0.052 seconds") and the closing time of the big winning opening for games per development is the closing time of the big winning opening for short win games and small hit games And the same closing time ("2 seconds"). However, even if the game is not set at the same time, a difference in time in which the player cannot determine whether the game per development, the game per short hit, or the game per small hit may be provided.

  In addition, the short opening time (“0.052 seconds”) of “short win game” and “small hit game” and the short opening time (“0.052 seconds”) of the first half of “game per development” are as described above. Thus, even if the movable piece 17b for the second big prize opening is actuated, it is necessary to win the second big prize opening 17 because it is shorter than the time for which one game ball is fired ("approximately 0.6 seconds"). Is difficult.

  For this reason, it can be said that the opening mode of “short hit game” and “small hit game” and the opening mode of the first half of “game per development” are “unfavorable opening mode” for the player.

  On the other hand, the long release time of “game per long” (“approximately 29 seconds”) and the long release time of the latter half of “game per development” (“approximately 29 seconds”) are the time (one game ball is fired) ( It is longer than “approximately 0.6 seconds”), and can be said to be an “advantageous release mode” for the player.

  Further, according to the jackpot big winning opening opening determination table shown in FIG. 9A, the maximum number of round games (R) at the time of all jackpots regardless of the long win game, the short win game, or the development game. ) Is set to the same number of times. For this reason, there is no need to provide a display device for identifying the number of round games as in the prior art.

  FIG. 10 is a diagram showing a variation pattern determination table for determining a variation pattern of special symbols as will be described later.

  Specifically, according to the special symbol variation pattern determination table shown in FIG. 10, the special symbol display device that operates (the type of the starting opening that the game ball won), the jackpot determination result, the special symbol to stop, and the short-time gaming state Based on the presence / absence, the number of special symbol hold (U1 or U2), the reach determination random number value, and the special symbol variation random value, the variation pattern of the special symbol is determined.

  Then, based on the determined special symbol variation pattern, the special symbol variation time is determined, and the special symbol variation pattern designation command for transmitting the special symbol information to the effect control board 120 is specified. An example of this variation pattern designation command is shown in FIG.

  Therefore, it can be said that the “special symbol variation pattern” defines at least the jackpot determination result and the special symbol variation time. In addition, since a reach is always performed when a big hit or a small hit, the reach determination random number value is not referred to when a big hit or a small win. The reach determination random number value and the special figure variation random value are set to 100 random numbers (0 to 99).

  Here, the special symbol variation pattern designation command is composed of “1 byte” of MODE data for identifying the command classification and “1 byte” of DATA data indicating the content (function) of the command. Yes.

  When the MODE data is “E6H”, a special symbol variation pattern designation command (of the first special symbol display device 20) corresponding to the winning of the game ball at the first start port 14 is shown. "E7H" indicates a special symbol variation pattern designation command corresponding to the winning of a game ball in the second start port 15 (second special symbol display device 21).

  Further, the special symbol variation pattern determination table shown in FIG. 10 is set so that the variation time of the special symbol is shortened when the jackpot determination result is lost and the game is in the short-time gaming state. For example, when the jackpot determination result is a loss and the number of held balls is “2”, if the game is in the short-time game state, the variation time is “3000 ms” with a probability of “95%” based on the reach determination random value. Pattern “9” (shortening variation) is determined. On the other hand, when in the non-time saving gaming state, a variation pattern in which the variation time exceeds “3000 ms” is determined.

  In this manner, the variation time is set to be short when the time-saving gaming state is entered.

  The table as described above is stored in the main ROM 110b of the main control board 110.

  Subsequently, the main RAM 110c of the main control board 110 functions as a data work area during the arithmetic processing of the main CPU 110a and has a plurality of storage areas.

  As an example of the storage area at this time, for example, in the main RAM 110c, the normal symbol hold number (G) storage area, the normal symbol hold storage area, the normal symbol data storage area, the first special symbol hold number (U1) storage area, Second special symbol holding number (U2) storage area, first special symbol random value storage area, second special symbol random value storage area, round game number (R) storage area, number of times released (K) storage area, first large Number of balls (C) storage area, game state storage area (high probability game flag storage area and time-short game flag storage area), high probability game number (X) counter of the winning opening 16 and the second grand prize opening 17 Various timer counters are provided, such as a short time (J) counter, a game state buffer, a stop symbol data storage area, a transmission data storage area for effects, a special symbol time counter, and a special game timer counter. That. Note that the above-described storage area is merely an example, and many other storage areas are provided.

  The game information output terminal board 30 is a board for outputting an external information signal generated in the main control board 110 to a hall computer or the like of the game shop. The game information output terminal board 30 is connected to the main control board 110 by wiring, and is provided with a connector for connecting external information to a hall computer or the like of a game store.

  The power supply board 170 includes a backup power supply made of a capacitor, supplies a power supply voltage to the gaming machine 1, and monitors a power supply voltage supplied to the gaming machine 1, and when the power supply voltage becomes a predetermined value or less, An interruption detection signal is output to the main control board 110. More specifically, when the power interruption detection signal becomes high level, the main CPU 110a enters an operable state, and when the power interruption detection signal becomes low level, the main CPU 110a enters an operation stop state. The backup power source is not limited to a capacitor, and may be a battery, for example, or a capacitor and a battery may be used in combination.

  The effect control board 120 mainly controls each effect such as during a game or standby.

  The effect control board 120 includes a sub CPU 120a, a sub ROM 120b, and a sub RAM 120c, and is connected to the main control board 110 so as to be communicable in one direction from the main control board 110 to the effect control board 120. .

  The sub CPU 120a reads out a program stored in the sub ROM 120b based on a command transmitted from the main control board 110 or an input signal from the effect button detection switch 35a, the cross key detection switch 36a, and the timer, and performs arithmetic processing. And corresponding data (such as an effect pattern designation command to be described later) is transmitted to the lamp control board 140 or the image control board 150 based on this processing.

  The sub RAM 120c functions as a data work area during the arithmetic processing of the sub CPU 120a.

  For example, when the sub CPU 120a in the effect control board 120 receives the fluctuation pattern designation command indicating the fluctuation pattern of the special symbol from the main control board 110, the contents of the received fluctuation pattern designation command are analyzed and the first liquid crystal display device 31 is analyzed. The voice output device 32, the effect drive device 33, the effect illumination device 34, and data for causing the second liquid crystal display device 37 to execute a predetermined effect (such as an effect pattern designation command to be described later) are specified. Then, the specified data (effect pattern designation command or the like) is transmitted to the image control board 150 or the lamp control board 140.

  FIG. 11 shows an example of a table used when an effect pattern designation command is specified based on the variation pattern designation command at this time.

  The sub ROM 120b of the effect control board 120 stores a program for effect control, data necessary for determining various games, and a table.

  For example, an effect pattern determination table for determining an effect pattern based on a variation pattern designation command received from the main control board 110, an effect symbol determination table for determining a combination of effect symbols 38 to be stopped and displayed, etc. are stored in the sub ROM 120b. It is remembered.

  In the production pattern determination table at this time, after the jackpot lottery is in the reach state, and the reach performance in the reach state suggests that the jackpot lottery result is “losing”, the revival and the jackpot lottery result is “ In addition to storing the effect pattern (revival jackpot effect pattern) for effecting “big hit”, the effect pattern for effecting switching the game state (game mode) is stored. Note that the above-described table is merely an example of characteristic tables among the tables in the present embodiment, and a number of other tables and programs (not shown) are provided for the progress of the game. ing.

  The effect control board 120 creates an effect pattern designation command using an effect pattern determination table as shown in FIG. 11 and sends it to the lamp control board 140 and the image control board 150.

  The sub RAM 120c of the effect control board 120 functions as a data work area when the sub CPU 120a performs arithmetic processing, and has a plurality of storage areas.

  The sub RAM 120c is provided with a game state storage area, an effect mode storage area, an effect pattern storage area, an effect symbol storage area, and the like. Note that the above-described storage area is merely an example, and many other storage areas are provided.

  FIG. 11 is a diagram showing an effect pattern determination table for determining a variation mode of the effect symbol 38 displayed on the first liquid crystal display device 31 and the second liquid crystal display device 37.

  FIG. 11B shows an effect mode in which the effect control board 120 shifts by receiving a notification of measuring a predetermined time from the image control board 150 and ends when it receives a notice that a certain time has elapsed from that time. It is a table showing a variation effect pattern and an effect pattern designation command determined in “specific effect mode”).

  On the other hand, FIG. 11A shows the change effect pattern and the effect pattern designation command determined in a state (“non-specific effect mode”) other than the state shifted to the specific effect mode shown in FIG. It is a table to show.

  The variation pattern designation command shown in FIGS. 11A and 11B is information received from the main control board 110, and the production random number 1 (0 to 99) is a random number generator (FIG. 11). The sub CPU 120a determines a variation effect pattern (and an effect pattern designation command in the variation effect pattern) based on such information.

  In FIG. 11, even when the sub CPU 120a receives the variation pattern designation command of the same special symbol, the variation control pattern can be determined based on the random number value 1 for the effect. The number of special pattern variation pattern designation commands stored in the main control board 110 is reduced compared to the variation effect pattern stored in 120.

  As a result, the storage capacity of the main control board 110 can be reduced, and a variety of effects can be achieved.

  The “variation effect pattern” refers to the effect contents (first liquid crystal display device 31, sound output device 32, effect drive device 33, effect illumination device 34, second liquid crystal display device 37) performed during the change of the special symbol. ) In a specific production mode. For example, in the first liquid crystal display device 31 and the second liquid crystal display device 37, the display mode of the background, the display mode of the character, and the variation mode of the production symbol 38 are determined by this variation effect pattern.

  In addition, the “reach” in the present embodiment refers to a state in which a part of the combination of the effect symbols 38 that informs the transition to the special game is stopped and the other effect symbols 38 are performing the variable display. . For example, when a combination of three effect symbols 38 of “777” is set as a combination of the effect symbols 38 informing that a transition to a jackpot game is made, the two effect symbols 38 are stopped and displayed at “7”. The state in which the remaining effect symbols 38 are variably displayed is called “reach”.

  In this way, when the sub CPU 120a determines the variation effect pattern based on the variation pattern designation command and the effect random number 1, the sub CPU 120a specifies the effect pattern designation command corresponding to the variation effect pattern and performs image control. This is transmitted to the liquid crystal control CPU 150a of the substrate 150.

  Specifically, in the effect pattern designation command, “1 command” is composed of 2 bytes of data, and “1 byte” of MODE data for identifying the control command classification and the control command to be executed. It consists of “1 byte” of DATA data indicating the contents.

  In addition, the effect pattern designation command corresponding to the variable effect pattern shown in FIG. 11A is the case of the “non-specific effect mode”, and the change based on the special symbol change pattern in the first special symbol display device 20. “MODE” is set to “A1H” for the effect pattern, and “MODE” is set to “B1H” for the change effect pattern based on the change pattern of the special symbol in the second special symbol display device 21. “DATA” is set according to the identification number of the variation effect pattern.

  In addition, as the effect pattern designation command corresponding to the change effect pattern shown in FIG. 11B, it is the case of “specific effect mode”, and the change effect based on the change pattern of the special symbol in the first special symbol display device 20. In the case of a pattern, “MODE” is set as “Z1H”. Furthermore, in the case of a variation effect pattern based on the variation pattern of the special symbol in the second special symbol display device 21, “MODE” is set as “Z2H”. “DATA” is set in accordance with the identification number of the effect pattern.

  Although illustration is omitted, in addition to the effect pattern specifying command corresponding to the variable effect pattern, the MODE setting value is changed, and “effect pattern specifying command corresponding to the demo effect pattern (MODE = 01H)”, "Effect pattern designation command corresponding to hit start effect pattern (MODE = 0H)", "Effect pattern designation command corresponding to jackpot effect pattern (MODE = 03H)", "Effect pattern designation command corresponding to hit end effect pattern ( MODE = 04H) ”and the like, and the sub CPU 120a transmits the various effect pattern designation commands to the image control board 150.

  Subsequently, the payout control board 130 shown in FIG. 4 performs payout control of the game ball.

  The payout control board 130 includes a one-chip microcomputer including a payout CPU, a payout ROM, and a payout RAM (not shown), and is connected to the main control board 110 so as to be capable of bidirectional communication.

  The payout CPU reads out the program stored in the payout ROM based on the input signals from the payout ball count detection switch 132, the door opening switch 133, and the timer for detecting whether or not the game ball has been paid out, and performs arithmetic processing. At the same time, based on the processing, the corresponding data is transmitted to the main control board 110.

  Further, a payout motor 131 of a payout device for paying out a predetermined number of game balls from the game ball storage unit is connected to the output side of the payout control board 130. The payout CPU reads out a predetermined program from the payout ROM based on the payout number designation command transmitted from the main control board 110, performs arithmetic processing, and controls the payout motor 131 of the payout device to give a predetermined game ball. Pay out.

  At this time, the payout RAM functions as a data work area during the calculation processing of the payout CPU.

  The lamp control board 140 controls the lighting of the effect lighting device 34 provided on the game board 2 and controls the driving of the motor for changing the light irradiation direction. Further, energization control is performed on a drive source such as a solenoid or a motor that operates the decoration device 33a. The lamp control board 140 is connected to the effect control board 120 and performs the above-described controls based on various commands transmitted from the effect control board 120.

  The image control board 150 is connected to the first liquid crystal display device 31, the audio output device 32, and the second liquid crystal display device 37, and the first liquid crystal display is based on various commands transmitted from the effect control board 120. Image display control in the device 31 and the second liquid crystal display device 37 and audio output control in the audio output device 32 are performed.

  This image control board 150 is used to control the display of the effect image displayed on the first liquid crystal display device 31 and the second liquid crystal display device 37, a liquid crystal control CPU 150a, a liquid crystal control RAM 150b, a liquid crystal control ROM 150c, a CGROM 151, a crystal oscillator. 152, a VRAM 153, an RTC device 154, an image control unit (VDP (Video Display Processor) 2000) (hereinafter referred to as “VDP2000”), and a sound control circuit 3000 that performs control to output sound information from the sound output device 32. Yes.

  The liquid crystal control CPU 150a creates a display list, which will be described later, based on the “effect pattern designation command” received from the effect control board 120, and transmits the display list to the VDP 2000 to thereby store the image data stored in the CGROM 151. An instruction to display on the first liquid crystal display device 31 and / or the second liquid crystal display device 37 is given.

  The image control board 150 has two asynchronous counters (also referred to as “counter”, “counter”, and “counter”).

  One counter is also referred to as a first counter 150d ("first counter controller" or "frame counter controller") that counts a first counter value (hereinafter referred to as "frame counter value") used for production. In the following, it is referred to as “frame counter 150d”, and the other counting device has a second counter value (hereinafter referred to as “RTC counter”) at a counting interval different from the counting interval (counting width) counted by the frame counter 150d. RTC device 154 (also referred to as “second counting device 154”).

  The frame counter 150d is provided in the liquid crystal control CPU 150a. The RTC device 154 includes an image control board 150, and the RTC device 154 and the liquid crystal control CPU 150a are connected via a bus. As an example of the communication form between the RTC device 154 and the liquid crystal control CPU 150a at this time, there is serial communication such as SPI (Serial Peripheral Interface).

  Of course, this configuration is an example, and the frame counter 150d may be connected to the liquid crystal control CPU 150a, or the RTC device 154 may be included in the liquid crystal control CPU 150a.

  Further, the RTC device 154 may be provided not in the image control board 150 but in the effect control board 120. In this case, as will be described later, effect time information based on the RTC counter value is not stored in the liquid crystal control RAM 150b of the effect control CPU 150a in the image control board 150, but is stored in the sub RAM 120c of the effect control board 120.

  At this time, the frame counter 150d receives the power supply from the power supply board 170, which will be described later, and counts the frame counter value at the effect processing timing of the production. When the power supply from the power supply board 170 is stopped, Stop counting the frame counter value. When the supply of power by the power supply board 170 is resumed, the frame counter 150d initializes the frame counter value registered in the register and resumes counting.

  On the other hand, the RTC device 154 includes an internal power source such as a battery or a capacitor. Unlike the frame counter 150d, the RTC counter 154 uses the internal power source even when the power supply by the power supply board 170 is stopped. Continue to count values.

  That is, the frame counter 150d executes or stops the frame counter value counting process according to the power supply state of the power supply board 170, but the RTC device 154 directly determines how the power supply state of the power supply board 170 is. It shows that the counting process of the RTC counter value is performed regardless of the actual state.

  The frame counter 150d included in the liquid crystal control CPU 150a receives a predetermined interrupt timing (when receiving an effect processing timing notification signal described later) from the VDP 2000 based on the V blank interrupt signal generated by the crystal oscillator 152. Count the frame counter value.

  That is, every time a V blank interrupt signal is generated, the “effect processing timing notification signal” is notified from the VDP 2000, so that the frame counter 150d counts the frame counter value and a predetermined number of V blank interrupt signals are received. The frame counter value may be counted by receiving an “effect processing timing notification signal” notified by the VDP 2000 when it occurs.

  The RTC device 154 is an RTC (Real Time Clock) that counts an RTC counter value based on an oscillation frequency (for example, 32768 Hz) by an oscillator (also referred to as a “crystal resonator”) that is a high-frequency module. The RTC counter value is stored in an RTC counter value register (hereinafter also referred to as “time information storage unit”).

  The information stored in the RTC counter value register is time information that is an RTC counter value. The RTC counter value register is configured by a detailed register for each time configuration information (hour, minute, second, etc.) constituting time information. By using a crystal vibrator for the RTC device 154, it is possible to count the RTC counter value with higher accuracy than the frame counter 150d.

  In the example shown above, the RTC counter value counted by the RTC device 154 is used as time information. However, the present invention is not limited to this, and the RTC device 154 counts the RTC counter value indicating a predetermined time interval. The time information may be set, and as a result, the time information may be timed. For this reason, the RTC device 154 is also referred to as a “time control unit”.

  At this time, the frame counter 150d of the liquid crystal control CPU 150a and the RTC device 154 can communicate with each other, and the liquid crystal control CPU 150a (more specifically, the frame counter 150d) transmits time information that is an RTC counter value to the RTC device 154. Input of time information which is an RTC counter value output by the RTC device 154 is received.

  Then, the liquid crystal control CPU 150a (more specifically, the frame counter 150d) uses the received time information as game designation time information (hereinafter also referred to as “effect time information” or simply “time information”). It memorize | stores in liquid crystal control RAM150b.

  When the liquid crystal control CPU 150a inputs information to and from the RTC device 154, it outputs a CE signal (chip enable signal) that makes the use of time information valid (active state) to the RTC device 154. To do.

  On the other hand, the RTC device 154 receives the CE signal from the liquid crystal control CPU 150a, and sets it to a state (active state) in which use of time information counted by the RTC device 154 is enabled.

  At this time, in the RTC device 154, the time information is updated using the frequency divided based on the oscillation frequency (“32768 Hz” in the above example) that is the original oscillation oscillated by the oscillator. When a CE signal is received from the liquid crystal control CPU 150a in a predetermined time zone (“divided delay time” to be described later) in the time information update process, the timing for changing to the active state is delayed based on the CE signal. A timing control process is performed.

  The RTC device 154 outputs the time information to the liquid crystal control CPU 150a in response to the input / output request of the time information from the liquid crystal control CPU 150a at the timing changed by the timing control process.

  The RTC counter value counted by the RTC device 154 is set to “acting time information” by the frame counter 150d as a host in order to prevent the staging time information from being registered and becoming indefinite when the frame counter 150d is not intended. It is necessary to manage as.

  Therefore, the RTC device 154 does not output the RTC counter value to the frame counter 150d, but the frame counter 150d reads the RTC counter value counted by the RTC device 154 and stores it as effect time information.

  The frame counter 150d that has read the RTC counter value in this way updates “effect time information” stored in the liquid crystal control RAM 150b described later with the read RTC counter value.

  The effect time information is information used in the effect control process performed by the process in the liquid crystal control CPU 150a and the effect control board 120.

  Each time the frame counter 150d updates the effect time information stored in the liquid crystal control RAM 150b, the liquid crystal control CPU 150a is associated with the time information in which the effect time information is associated with the information related to the specific effect stored in the liquid crystal control ROM 150c. Judgment is made.

  By determining that the effect time information has become time information associated with information related to the specific effect, the liquid crystal control CPU 150a sets a specific effect mode in which the specific effect is performed in the liquid crystal control RAM 150b. Furthermore, the liquid crystal control CPU 150a notifies the effect control board 120 that the specific effect mode has been entered.

  As described above, when the effect time information based on the RTC counter value is stored in the sub RAM 120c of the effect control board 120, the effect control CPU 120a reads the effect time information from the sub RAM 120c and performs processing. .

  The time information associated with the specific effect at this time is stored in the liquid crystal control ROM 150c, and information related to the effect content of the specific effect performed by timing the time information is associated.

  In the effect control board 120, when the liquid crystal control CPU 150a notifies that the specific effect mode is set, mode flag information related to the specific effect mode is set and stored in the sub-RAM 120c.

  In the effect control board 120, the mode flag information related to the specific effect mode is set in the sub RAM 120c, so that the table different from the table for determining the variable effect pattern in a state where the mode flag information related to the specific effect mode is not set. Is used to determine the variation production pattern.

  That is, in the state where the information regarding the specific effect mode is not set in the sub RAM 120c, the effect pattern designation command to be output to the image control board 150 is determined using the variation effect pattern determination table shown in FIG. On the other hand, when the mode flag information related to the specific effect mode is set in the sub-RAM 120c, it is output to the image control board 150 using the variation effect pattern determination table (for the specific effect mode) shown in FIG. Determine the production pattern designation command.

  The specific effect stored in the liquid crystal control ROM 150c at this time is, for example, an effect of performing a music performance by a character, and is an effect different from an effect in a privilege lottery game performed using a game ball.

  The specific effect at this time is not performed in conjunction with the effect in the privilege lottery game performed using the game ball, and is an effect not related to the lottery result of the privilege lottery game.

  However, it is possible to use a common content (theme) for the effect in the lottery game of the privilege and the specific effect, and in this case, it is possible to provide a different type of interest than the effect in the lottery game of the privilege. The production in the lottery game can be further enhanced.

  The liquid crystal control CPU 150a that has received the effect pattern designation command in the specific effect mode from the effect control board 120 in a state in which the performance time information becomes time information associated with the specific effect and the music performance is performed as the specific effect. An effect image as shown in FIG. 40 is displayed.

  The effect image shown in FIG. 40 displays a music performance effect image based on a music performance at the upper part of the image display area, and an effect image based on the effect pattern designation command in the specific effect mode from the effect control board 120 (shown in FIG. 40). In the example, the dot variation display image) is displayed at the bottom of the image display area.

  The display form of the effect image at this time differs depending on the variation state of the symbols in the game and the timing when the specific effect mode is set.

  When the liquid crystal control CPU 150a of the image control board 150 receives an effect pattern designation command determined from the effect control board 120 using the variation effect pattern determination table (for the specific effect mode) shown in FIG. A display list is created based on the command and the display list is sent to VDP2000.

  As the time information stored in the liquid crystal control RAM 150b, for example, the state of the effect mode when 12 times are stored is shown in FIG. That is, the “production time information” updated by the frame counter 150d becomes these pieces of time information, whereby the specific production in the specific production mode is performed.

  In the example shown in FIG. 38A, the liquid crystal control RAM 150b has “10:29”, “11:29”, “12:29”, “13:29”, “14:29”. , “15:29”, “16:29”, “17:29”, “18:29”, “19:29”, “20:29”, “21:29” An example in which 12 pieces of time information are stored is shown.

  In addition, the time information is not stored in the liquid crystal control RAM 150b, but the effect interval time information and the initial effect time information (in the above example, “10” in the interval of switching to the specific effect mode (music park mode, performance announcement mode) It is also possible to store “29 hours”) in the liquid crystal control RAM 150b.

  As shown in FIG. 38 (b), the specific effect at this time is “standby effect (“ pre-specific effect ”” or “ Performing performance announcements ”. Then, when the standby effect ends (one minute has passed since the specific effect mode has been reached), the “music performance effect” is performed as the music performance mode in the specific effect mode.

  The music performance effect at this time is an effect of performing a music performance performed using a character as described above, and the dance video data and sound data of the character are notified.

  In the example shown in FIG. 38B, after the standby effect for 60 seconds is completed, the music performance effect for 300 seconds is continuously performed. The standby effect at this time is, for example, an effect of displaying an image for counting down the remaining time until the music performance effect is performed.

  The specific effect image (effect image and music based on the standby effect) displayed in the specific effect after the liquid crystal control CPU 150a notifies the effect control board 120 that the specific effect mode has been reached until the specific effect mode ends. FIG. 40 shows an example in which an effect image based on the performance effect) and an effect image displayed based on the effect pattern designation command sent from the effect control board 120 in the specific effect mode are displayed.

  The display form shown in FIG. 40 at this time is determined according to the production state (whether it is in the specific production mode or whether it is in the performance announcement mode or the music performance mode in the specific production mode). Then, display control for displaying in the determined display form is performed.

  The liquid crystal control CPU 150 a further instructs the sound control circuit 3000 to output predetermined sound data to the sound output device 32 based on the effect pattern designation command received from the effect control board 120.

  The liquid crystal control RAM 150b is built in the liquid crystal control CPU 150a, functions as a data work area when the liquid crystal control CPU 150a performs arithmetic processing, and temporarily stores data read from the liquid crystal control ROM 150c.

  Information stored in the liquid crystal control RAM 150b at this time includes “effect time information” used for executing a specific effect performed by measuring a predetermined time.

  The liquid crystal control ROM 150c is configured by a mask ROM or the like, and includes a control processing program of the liquid crystal control CPU 150a, a display list generation program for generating a display list, an animation pattern for displaying an animation of an effect pattern, an animation The scene information, the specific effect information related to the specific effect, and the like are stored.

  This animation pattern is referred to when displaying the animation of the production pattern, and stores the combination of animation scene information included in the production pattern, the display order of each animation scene information, and the like. In the animation scene information, a wait frame (display time), target data (sprite identification number, transfer source address, etc.), parameters (sprite display position, transfer destination address, etc.), drawing method, and effect image are displayed. Information such as information specifying a display device is stored.

  An example of this animation information is shown in FIG. 13 and will be described below.

  Further, the specific effect information stored in the liquid crystal control ROM 150c includes time information of a specific effect mode in which the specific effect is performed and information on the specific effect (movie data including video data, sound data, etc.) that is performed by becoming the time information. Further, a configuration in which “standby production time information (date, time information)” of the standby production (prior specific production) in the specific production and “music performance production time information (date, time information)” of the music performance production are associated with each other. It may be.

  In the liquid crystal control CPU 150a, the frame counter 150d uses the “effect state information” used when determining the display mode when displaying the effect image on the first liquid crystal display device 31 and the second liquid crystal display device 37 on the image control board 150. The time information in the RTC counter value read from the RTC device 154 is used for determination, and the effect state information is stored in the liquid crystal control RAM 150b.

  The production state information at this time is the standby flag information indicating that the time is in the standby production state until the time is measured by the music performance production time information after counting the time by the standby production time information, and the time by the music performance production time information. It is composed of music performance effect flag information indicating that the music performance effect is in a state from when the music performance effect is finished until the end time at which the music performance effect ends is counted.

  That is, when the standby performance time information is timed, the liquid crystal control CPU 150a sets the standby flag information indicating the standby performance state to “valid (ON)”, and in this state, when the music performance performance time information is timed, the music performance is performed. The musical performance performance flag information indicating the performance state is set to “valid (ON)”.

  Thereby, when the standby flag information is “valid (ON)” or when the music performance effect flag information is “valid (ON)”, the image control board 150 is set to “specific effect mode”. It shows that.

  At this time, when at least one of the standby flag information and the music performance effect flag information is “valid (ON)”, that is, in the “specific effect mode”, as described above, FIG. In place of the variation effect pattern determination table as shown in FIG. 11A, an effect pattern designation command is sent to the image control board 150 using the change effect pattern determination table in the specific effect mode as shown in FIG. Output.

  Further, the liquid crystal control CPU 150a sets all the flag information (“standby flag information” and “music performance effect flag information”) to “invalid (OFF)” by measuring the end time of the specific effect (initial setting). To do. Thereby, the liquid crystal control CPU 150a notifies the effect control board 120 of “non-specific effect mode” that is an effect mode other than the “specific effect mode” as effect state information.

  Thereby, the effect control board 120 receives and stores the effect state information (non-specific effect mode) in the image control board 150.

  At this time, instead of the variation effect pattern determination table for the specific effect mode as shown in FIG. 11B, the image control board 150 is used with the change effect pattern determination table as shown in FIG. A production pattern designation command is output.

  The general-purpose board 39 is provided between the image control board 150 and the first liquid crystal display device 31 and the second liquid crystal display device 37, and converts the image data into a predetermined image format and outputs it when displaying the image data. have.

  The general-purpose board 39 has a bridge function for converting to an image format corresponding to the performance of the first liquid crystal display device 31 and the second liquid crystal display device 37 for displaying image data. For example, SXGA (1280 dots × 1080) Dot) 19-inch main liquid crystal connected as the first liquid crystal display device 31, and XGA (1024 dots × 768 dots) 17-inch main liquid crystal connected as the first liquid crystal display device 31. Absorb differences.

  Subsequently, the CGROM 151 is composed of a flash memory, an EEPROM, an EPROM, a mask ROM, and the like, and compresses image data (sprite, movie), etc. composed of a collection of pixel information in a predetermined range of pixels (for example, 32 pixels × 32 pixels). And remember. The pixel information is composed of color number information for designating a color number for each pixel and an α value indicating the transparency of the image.

  The CGROM 151 is read out in units of image data by the VDP 2000, and image processing is performed in units of image data of this frame.

  Further, the CGROM 151 stores palette data in which color number information for designating color numbers and display color information for actually displaying colors are associated with each other without being compressed.

  Note that the CGROM 151 may have a configuration in which only a part of the image data is compressed without being compressed. As a movie compression method, various known compression methods such as MPEG4 can be used.

  The crystal oscillator 152 outputs a pulse signal (V blank interrupt signal) to the VDP 2000 approximately every 16.6 milliseconds. The VDP 2000 divides this pulse signal to control the system clock. A synchronization signal or the like for synchronizing with the liquid crystal display device 31 or the second liquid crystal display device 37 is generated.

  The VRAM 153 is composed of an SRAM that can write or read image data at high speed. The VRAM 153 is configured by a memory map as shown in FIG.

  FIG. 12 is an example of a configuration diagram illustrating a configuration of a frame buffer used in the image control board 150 of the gaming machine according to the embodiment of the present invention.

  FIG. 12A shows a case where image data is displayed using either the first liquid crystal display device 31 or the second liquid crystal display device 37, and in particular, only the first liquid crystal display device 31 has the image control board 150. In other words, the second liquid crystal is not a configuration in which the first liquid crystal display device 31 and the second liquid crystal display device 37 are connected as shown in FIG. It is a memory map in the structure when not having the display device 37.

  The memory map shown in FIG. 12A includes an image data development area 153b consisting of arbitrary areas, a display list storage area 153a, a main liquid crystal first frame buffer area 153c, a main liquid crystal second frame buffer area 153d, and other areas. It is configured.

  The image data development area 153b is an area for storing image data expanded by an expansion circuit (described later) included in the VDP 2000. The display list storage area 153a temporarily stores the display list output from the liquid crystal control CPU 150a. This is the area to be stored in

  The main liquid crystal first frame buffer area 153c and the main liquid crystal second frame buffer area 153d display effect images to be displayed on the first liquid crystal display device 31 based on the display list stored in the display list storage area 153a. This is a work area for drawing.

  Incidentally, pallet data etc. are memorize | stored in other area | regions, for example.

  The two frame buffers, the first liquid crystal frame buffer area 153c and the main liquid crystal second frame buffer area 153d, are divided into a "drawing frame buffer" and a "display frame buffer" each time drawing is started. It switches alternately. That is, when one frame buffer functions as a drawing frame buffer, the other frame buffer functions as a display frame buffer.

  FIG. 12B shows a case where the image data received from the image control board 150 is displayed on both the first liquid crystal display device 31 and the second liquid crystal display device 37, that is, as shown in FIG. As shown, the memory map in the configuration in which the first liquid crystal display device 31 and the second liquid crystal display device 37 are connected.

  12B, similarly to the memory map shown in FIG. 12A, the image data development area 153b, the display list storage area 153a, the main liquid crystal first frame buffer area 153c, and the main liquid crystal A second frame buffer area 153d and other areas are provided, and a sub-liquid crystal first frame buffer 153e and a sub-liquid crystal second frame buffer 153f are further provided.

  The image data development area 153b, the display list storage area 153a, the main liquid crystal first frame buffer area 153c, the main liquid crystal second frame buffer area 153d, and the other areas are the same as described above. The frame buffer 153e and the second sub-liquid crystal frame buffer 153f are work areas for drawing effect images to be displayed on the second liquid crystal display device 37 based on the display list stored in the display list storage area 153a.

  The two frame buffers, the first sub-liquid crystal frame buffer 153e and the sub-liquid crystal second frame buffer 153f, alternate between a “drawing frame buffer” and a “display frame buffer” every time drawing is started. It will be switched. That is, when one frame buffer functions as a drawing frame buffer, the other frame buffer functions as a display frame buffer.

  In addition to the above, the first liquid crystal display device 31 as shown in FIG. 12B may be configured without the second liquid crystal display device 37, that is, with only the first liquid crystal display device 31. It is also possible to use a memory map having a frame buffer of the second liquid crystal display device 37.

  In this case, the frame buffers of the sub-liquid crystal first frame buffer 153e and the sub-liquid crystal second frame buffer 153f are not used as work areas.

  Subsequently, the VDP 2000 is a so-called image processor. Based on an instruction from the liquid crystal control CPU 150a, for the first liquid crystal display device 31, a main liquid crystal first frame buffer area 153c and a main liquid crystal second frame buffer area 153d For the second liquid crystal display device 37, the image data is read from the “display frame buffer” in the frame buffer of either the sub-liquid crystal first frame buffer 153e or the sub-liquid crystal second frame buffer 153f.

  Based on the read image data, a video signal (LVDS signal, RGB signal, etc.) is generated and output to the first liquid crystal display device 31 and / or the second liquid crystal display device 37 for display.

  The VDP 2000 includes a control register (not shown), a CG bus I / F, a CPU I / F, a clock generation circuit, an expansion circuit, a drawing circuit, a display circuit, and a memory controller, which are connected by a bus.

  The control register is a register for the VDP 2000 to control drawing and display, and drawing control and display control are performed by writing and reading data to and from the control register. The liquid crystal control CPU 150a can write and read data to and from the control register via the CPU I / F.

  This control register is a "system control register" that performs basic settings necessary for the operation of the VDP2000, a "data transfer register" that performs settings necessary for data transfer, and a setting for controlling drawing "Drawing register" for performing the settings, "Bus interface register" for performing settings necessary for bus access, "Decompression register" for performing settings necessary for decompressing compressed images, and settings for controlling display There are six types of registers, “display registers”.

  The CG bus I / F is an interface circuit for communication with the CGROM 151, and image data from the CGROM 151 is input to the VDP 2000 via the CG bus I / F.

  The CPU I / F is an interface circuit for communication with the liquid crystal control CPU 150a. The liquid crystal control CPU 150a outputs a display list to the VDP 2000, accesses a control register, and accesses the VDP 2000 via the CPU I / F. Various interrupt signals from are input to the liquid crystal control CPU 150a.

  The data transfer circuit performs data transfer between various devices. Specifically, data transfer between the liquid crystal control CPU 150a and the VRAM 153, data transfer between the CGROM 151 and the VRAM 153, and data transfer between various storage areas (including the frame buffer) of the VRAM 153 are performed.

  The clock generation circuit receives a pulse signal (V blank interrupt signal) from the crystal oscillator 152 and generates a system clock that determines the operation processing speed of the VDP2000. Also, a synchronization signal generation clock is generated, and the synchronization signal is output to the first liquid crystal display device 31 via the display circuit.

  The decompression circuit is a circuit for decompressing the image data compressed in the CGROM 151, and stores the decompressed image data in the image data development area 153b.

  The drawing circuit is a circuit that performs sequence control based on a display list composed of drawing control commands.

  The display circuit includes a main display liquid crystal first frame buffer region 153c, a main liquid crystal second frame buffer region 153d, a sub liquid crystal first frame buffer 153e, and a sub liquid crystal second frame buffer 153f in the VRAM 153. From the image data (digital signal) stored in the frame buffer functioning as a “frame buffer”, a video signal indicating the color data of the image is generated as a video signal.

  The display circuit is a circuit that outputs the generated video signal to the first liquid crystal display device 31 and the second liquid crystal display device 37. Further, the display circuit also outputs a synchronizing signal (vertical synchronizing signal, horizontal synchronizing signal, etc.) for synchronizing with the first liquid crystal display device 31, and synchronizing signal (for synchronizing with the second liquid crystal display device 37). Vertical sync signals, horizontal sync signals, etc.) are also output.

  When there is an instruction to switch the frame buffer from the liquid crystal control CPU 150a, the memory controller performs control to switch roles between the “drawing frame buffer” and the “display frame buffer”.

  The sound control circuit 3000 is provided with an audio ROM (not shown) in which a large number of audio data is stored. The sound control circuit 3000 is based on an audio output instruction command transmitted from the effect control board 120. While reading a predetermined program, the audio output control in the audio output device 32 is performed.

  FIG. 13 is a diagram showing animation information used on the image control board 150 of the gaming machine according to the embodiment of the present invention.

  The animation pattern shown in FIG. 13 (a) includes the timing of displaying the effect image in addition to the object that is the configuration information constituting the effect image displayed on the first liquid crystal display device 31 and the second liquid crystal display device 37. This is information specifying a scene as a scene, and is image forming information for forming an effect image to be displayed at the time of effect.

  A group (hereinafter also referred to as “animation group”) is formed by bundling one or a plurality of the animation patterns. For example, in FIG. 13A, a background group for displaying a background animation, a notice A notice group A for displaying the animation of the character used for A, a notice group B for displaying the animation of the character used for notice B, a reach group for displaying the animation of the reach character, and an animation of the big hit effect are displayed. The effect symbol group for displaying the animation of the big hit effect group for the effect symbol 38 is shown.

  Of course, these are merely examples of groups, and many other groups are provided.

  This animation group is stored in the liquid crystal control ROM 150c.

  The liquid crystal control CPU 150a receives the effect pattern designation command from the sub CPU 120a in the effect control board 120, determines one or more animation groups to be executed based on the effect pattern designation command, and determines the animation pattern from each animation group. To decide.

  13 (b) to 13 (d) and 13 (e), when the effect pattern designation command “A1H07H” is received among the effect pattern designation commands designated in the effect pattern determination table shown in FIG. An example of the determined animation pattern is shown in FIG.

  This effect pattern designation command (A1H07H) is a command for instructing to perform a normal variation effect with a variation effect pattern of “variation effect pattern 7” as shown in the variation pattern designation command table of FIG. It is an animation group to which the constituent elements used when performing the normal variation effect belong, and specifies at least one of the animation groups separated for each role used for the variation effect.

  That is, the liquid crystal control ROM 150c stores an animation group correspondence table (not shown) in which an effect pattern designation command and an animation group used for the effect pattern of the effect pattern designation command are associated with each other. The animation group to be used for the production pattern designation command is determined using this animation group correspondence table.

  For example, when receiving the effect pattern designation command (A1H07H) corresponding to the variable effect pattern “7”, the liquid crystal control CPU 150a determines four groups of “background group, notice A group, notice B group, effect symbol group”. The animation pattern can be determined from each of these anime groups.

  As an example, “animation pattern 1” is determined from the background group, “anime pattern 11” is determined from the notice A group, “anime pattern 21” is determined from the notice B group, and “anime pattern 501” is determined from the directing design group. To decide.

  As shown in FIGS. 13 (b) to 13 (d) and 13 (e), the animation pattern includes a combination of animation scene information, a display order of each animation scene information, information specifying a display device to be displayed, and the like. Is remembered.

  For example, in the animation pattern of the effect symbol group shown in FIG. 13E, “sub liquid crystal (second liquid crystal display device 37)” is designated in the information designating the display device to be displayed. The scene 501 is executed, the animation scene 511 is executed second after the animation scene 501, and the effect image of the animation pattern is displayed on the sub liquid crystal (second liquid crystal display device 37).

  The liquid crystal control RAM 150 b has a “scene switching counter” that counts and updates every frame, and this “scene switching counter” counts 540 while the first animation scene 501 is being executed. As a result, the animation scene is switched to the second animation scene 511.

When “60” (for 60 frames) is counted by the “scene switching counter” while the second animation scene 511 is being executed, the animation scene of the animation pattern of the effect symbol group ends.

  Note that “one frame” is the update timing of the display device (update timing of the vertical synchronization signal). For example, when the first liquid crystal display device 31 displays 60 frames per second, “1/60”. One frame is updated every second (about 16.6 ms).

  In the above example, one frame is updated every "1/60 seconds (about 16.6 ms)". However, the present invention is not limited to this, and "1/30 seconds (about 33. The configuration may be such that one frame is updated every 3 ms). In this case, the display device displays 30 frames per second.

  Each animation scene stores animation scene information. As animation information, a weight frame (display time) updated for each frame, target data (sprite identification number, transfer source address, etc.), parameters, and the like. (Sprite display position, transfer destination address, etc.), a drawing method, information for designating a display device for displaying the effect image, and the like are stored.

  For example, in the animation scene shown in FIG. 13 (e), first, the first symbol, the second symbol, the third symbol, and the fourth symbol are given coordinates (the first symbol is coordinates (x30, y30), the second symbol. Is displayed at coordinates (x40, y40), the third symbol at coordinates (x50, y50), and the fourth symbol at coordinates (x60, y60) for 20 frames (approximately 0.33 seconds).

  Then, the first symbol, the second symbol, the third symbol, and the fourth symbol are different coordinates (the first symbol is coordinates (x31, y31), the second symbol is coordinates (x41, y41), the third symbol is coordinates ( x51, y51), the 4th symbol continues to be displayed for 15 frames (about 0.25 seconds) at coordinates (x61, y61)).

  Similarly, when the first symbol, the second symbol, the third symbol, and the fourth symbol continue to be displayed at the designated coordinates for the predetermined frame, the first symbol, the second symbol, the third symbol, The animation is such that the symbol and the fourth symbol are moved and displayed.

  In addition, in each of the “background group, notice A group, notice B group” animation patterns shown in FIGS. 13B to 13D, “main liquid crystal (first liquid crystal display) in the information designating the display device to be displayed. Device 31) "is designated, animation scene 1 is executed for" 600 "frames in the background group as shown in FIG. 13 (b), and animation-scene 0 is shown in FIG. 13 (c) in the notice A group. After executing “120” frame, the animation scene 11 is executed for “180” frame. In the notice B group, as shown in FIG. 13D, after the animation scene 0 is executed for “180” frame, the animation scene 21 is “ The 240 "frame is executed, and the effect image of the animation pattern is displayed on the main liquid crystal (first liquid crystal display device 31).

  As described above, as shown in FIG. 13B to FIG. 13D, “animation pattern 1 of the background group, animation pattern 11 from the notice A group, animation pattern 21 from the notice B group, and Are determined and the animations of these animation patterns are executed in parallel in time series, whereby an effect image based on the animation pattern is displayed on the main liquid crystal (first liquid crystal display device 31). As shown in FIG. 13 (e), the animation pattern “animation pattern 501 from the production pattern group” is determined, and the animation pattern is executed to execute the animation pattern on the sub liquid crystal (second liquid crystal display device 37). An effect image based on is displayed.

  As a result, images of BG1 (mountains) and BG2 (clouds) continue to be displayed in the display area of the first liquid crystal display device 31 from the start to the end of the animation pattern, and 2 seconds from the start of the animation pattern. An image that performs animation for displaying the notice of character A after (120 frames) is displayed for 3 seconds (180 frames), and 4 images that perform animation for displaying the notice of character B after 3 seconds (180 frames) from the start of the animation pattern. Seconds (240 frames) are displayed.

  These images are displayed in an overlapping manner in the display area of the first liquid crystal display device 31, and the first drawn image is overwritten by an image drawn later and cannot be visually recognized as an image. Become.

  Furthermore, in the display area of the second liquid crystal display device 37, an image for performing the animation of the normal variation display of the effect symbol is performed for 9 seconds (540 frames), and then temporarily stopped for 1 second (60 frames) (stop time). The image that performs the animation is displayed. In addition, although the example which displays only an effect design is shown on the 2nd liquid crystal display device 37, it does not limit to this, For example, the animation pattern 1 which consists of the background group displayed in the 1st liquid crystal display device 31, and an effect The animation pattern 501 may be displayed in parallel in time series from the symbol group.

  FIG. 14 is an example of a display list composed of a group of drawing control commands, and shows an example of a display list for each display device to be displayed.

  FIG. 14A is an example of a first display list that is image forming information for forming an effect image to be displayed on the first liquid crystal display device 31, and FIG. 14B is a diagram illustrating the second liquid crystal display device 37. It is an example of the 2nd display list which is the image formation information for forming the production image displayed in.

  When the liquid crystal control CPU 150a determines the animation pattern based on the animation information as shown in FIG. 13 described above, every predetermined frame (1) displayed on each of the first liquid crystal display device 31 and the second liquid crystal display device 37. A display list is generated for each frame). That is, a display list is generated for each unit frame according to the number of display devices.

  The liquid crystal control CPU 150a outputs each display list generated in this way to the VDP 2000.

  Here, the display list generation method is such that the liquid crystal control CPU 150a changes the contents of the animation scene at the current number of frames based on the “frame counter” indicating the current frame and the determined animation pattern (animation scene). The display list for the current number of frames is generated by generating the drawing control command according to the priority (drawing order) of each animation group.

  Below, the example of the display list which comprises the effect image displayed in the 1st liquid crystal display device 31 is shown.

  In FIG. 14A, as the priority order of the animation group shown in FIG. 13A, the background group is associated with the lowest “priority 9” data, and the notice A group has “priority order 8”. ”Data,“ priority 7 ”data is associated with the notice B group, and… (omitted)…. The highest priority data is associated with the jackpot presentation group It is assumed that

  Further, in FIG. 14B, as the priority order of the animation group shown in FIG. 13A, data of “priority order 2” having a low priority order is associated with the background group, It is assumed that “priority 1” data having a high priority is associated. In the example shown in FIG. 14B, in the above case, the animation pattern 1 consisting of the background group and the animation pattern 501 from the effect design group are displayed on the second liquid crystal display device 37 in chronological order in parallel. An example of a display list is shown. Of course, when only the animation pattern 1 composed of the background group is displayed, the display list designating only the animation scene 501 of the effect design group, that is, the “background group” in the animation group column of FIG. The display list does not include the specified record.

  In FIG. 14 (a), as shown in FIGS. 13 (b) to 13 (d), the background group anime pattern 1, the notice A group from the anime pattern 11, and the notice B group It is assumed that a plurality of anime patterns with the anime pattern 21 have been determined. In FIG. 14B, as shown in FIG. 13E above, the anime pattern 1 of the background group and the animation pattern from the effect design group are displayed. Assume that a plurality of animation patterns 501 are determined.

  Next, as a display list corresponding to the effect image displayed on the first liquid crystal display device 31, the animation in the current frame counter (current number of frames) is selected from the animation pattern 1 of the lowest priority animation group (background group). Drawing control commands are generated sequentially according to the contents of the scene, and when drawing control commands are generated up to the highest priority anime group (big hit effect group) among the determined anime groups, drawing ends at the end. A display list as shown in FIG. 14A is completed by generating a command.

  Next, as a display list corresponding to the effect image displayed on the second liquid crystal display device 37, the animation pattern 1 of the animation group (background group) with the lower priority and the animation scene in the current frame counter (current number of frames). When the drawing control command for the animation group with higher priority (direction design group) is generated among the determined anime groups, the drawing end command is finally sent. The display list as shown in FIG. 14B is completed by generating.

  The display lists as shown in FIGS. 14A and 14B are generated with reference to necessary data by the liquid crystal control CPU 150a.

  In this way, the liquid crystal control CPU 150a outputs to the VDP 2000 the display lists (first display list and second display list) for each display device in which the drawing control command group is grouped for each predetermined frame (one frame). The drawing circuit constituting the VDP 2000 performs a drawing process for drawing the effect image for each display list, and displays the effect image subjected to the drawing process on the corresponding display device (the first liquid crystal display device 31 or the second liquid crystal display device 37). To do.

  Subsequently, various processes performed in the gaming machine according to the embodiment of the present invention will be described with reference to all 10 diagrams from FIG. 15 to FIG. 24.

  FIG. 15 is an example of a flowchart showing a detailed flow of the main process performed on the main control board 110 of the gaming machine in the embodiment of the present invention.

  When power is supplied from the power supply board 170, a system reset occurs in the main CPU 110a, and the main CPU 110a performs the following main processing.

  First, the main CPU 110a performs initialization processing (S1501). In this initialization process, the main CPU 110a reads a startup program from the main ROM 110b in response to power-on, and performs a process of initializing flags and the like stored in the main RAM 110c.

  Subsequently, the main CPU 110a performs an effect random number update process for updating the reach determination random number value and the special figure variation random value for determining the variation mode (variation time) of the special symbol (S1502).

  Then, the main CPU 110a updates the special symbol determination initial random number value, the big hit symbol initial random value, the small hit symbol initial random number value, and the normal symbol determination initial random value (S1503).

  When such a process is performed, it is determined whether or not a power-off process for shutting off the power is performed (S1504), and until the power-off process is performed (NO in S1504), an interrupt process is performed to produce an effect. The random number value update process (S1502) and subsequent steps are repeated. If the power interruption process is performed (YES in S1504), the process is terminated.

  FIG. 16 is an example of a flowchart showing a detailed flow of the timer interrupt process performed on the main control board 110 of the gaming machine according to the embodiment of the present invention.

  A clock pulse is generated every predetermined period (4 milliseconds) by the reset clock pulse generation circuit provided on the main control board 110, thereby executing a timer interrupt process described below.

  First, the main CPU 110a saves information stored in the register of the main CPU 110a to the stack area (S1601).

  The main CPU 110a has various timers such as a special symbol time counter update process, a special game timer counter update process such as a special electric accessory release time, a normal symbol time counter update process, and a general electric release time counter update process. A time control process for updating the counter is performed. Specifically, a process of subtracting 1 from the special symbol time counter, the special game timer counter, the normal symbol time counter, and the general electricity open time counter is performed (S1602).

  The main CPU 110a performs random number update processing for the special symbol determination random number value, the big hit symbol random number value, the small hit symbol random number value, and the normal symbol determination random number value (S1603).

  Specifically, each random number value and random number counter are incremented (unit number addition) and updated. When the added random number counter exceeds the maximum value of the random number range (when the random number counter makes one round), the random number counter is returned to “0 (zero)” and the initial random number “0 (zero) at that time” ”To update each random value.

  Subsequently, as in S1503, the main CPU 110a updates the initial random number value for updating the initial random number value for special symbol determination, the initial random number value for big hit symbol, the initial random number value for small hit symbol, and the initial random number value for normal symbol determination. Processing is performed (S1604).

  The main CPU 110a performs input control processing (S1605).

  In this input control process, the main CPU 110a includes the general winning opening detecting switch 12a, the first large winning opening detecting switch 16a, the second large winning opening detecting switch 17a, the first starting opening detecting switch 14a, and the second starting opening detecting switch 15a. Then, it is determined whether or not there is an input to each switch of the gate detection switch 13a.

  Specifically, various detection signals from the general winning opening detecting switch 12a, the first big winning opening detecting switch 16a, the second large winning opening detecting switch 17a, the first starting opening detecting switch 14a, and the second starting opening detecting switch 15a. Is inputted, predetermined data is added to the prize ball counter used for the prize ball provided for each prize opening and updated.

  Furthermore, when a detection signal is input from the first start port detection switch 14a, if the data set in the first special symbol hold number (U1) storage area is less than 4, the first special symbol hold number ( U1) Add 1 to the storage area to obtain special symbol determination random number value, jackpot symbol random number value, small hit symbol random number value, reach determination random value, and special symbol variation random value The random number value is stored in a predetermined storage unit (0th storage unit to 4th storage unit) in the first special symbol random value storage area.

  Similarly, when a detection signal is input from the second start port detection switch 15a, if the data set in the second special symbol hold number (U2) storage area is less than 4, the second special symbol hold number (U2) 1 is added to the storage area, and a special symbol determination random number value, a big hit symbol random number value, a small hit symbol random number value, a reach determination random number value, and a special symbol variation random value are acquired. Various random numbers are stored in a predetermined storage unit (0th storage unit to 4th storage unit) in the second special symbol random number value storage area.

  When a detection signal is input from the gate detection switch 13a, if the data set in the normal symbol hold number (G) storage area is less than 4, the normal symbol hold number (G) storage area is set to 1. It adds, acquires the random number value for normal symbol determination, and memorize | stores the acquired random number value for normal symbol determination in the predetermined memory | storage part (0th memory | storage part-4th memory | storage part) in a normal symbol holding | maintenance storage area.

  Further, when a detection signal is input from the first grand prize opening detection switch 16a or the second big prize opening detection switch 17a, the number of game balls won in the first big prize opening 16 or the second big prize opening 17 is counted. 1 is added to the number of entries (C) storage area for the big winning opening to update.

  Next, the main CPU 110a performs special figure special electric power control processing for controlling the jackpot lottery, the special electric accessory, and the gaming state (S1606). Subsequently, the main CPU 110a performs a general-purpose normal power control process for controlling the normal symbol lottery and the normal electric accessory (S1607).

  Specifically, it is first determined whether or not 1 or more data is set in the normal symbol hold count (G) storage area, and 1 or more data must be set in the normal symbol hold count (G) storage area. If this is the case, the current ordinary power transmission control process is terminated.

  If 1 or more data is set in the normal symbol holding number (G) storage area, after subtracting 1 from the value stored in the normal symbol holding number (G) storage area, the data is in the normal symbol holding storage area. The normal symbol determination random numbers stored in the first storage unit to the fourth storage unit are shifted to the previous storage unit. At this time, the normal symbol determination random value already written in the 0th storage unit is overwritten and erased.

  Then, a process of determining whether or not the normal symbol determination random number value stored in the 0th storage unit of the normal symbol hold storage area is a random value corresponding to “win” is performed. Thereafter, the normal symbol display device 22 displays the fluctuation of the normal symbol. When the fluctuation time of the normal symbol elapses, the normal symbol corresponding to the result of the normal symbol lottery is stopped and displayed. If the random number for normal symbol determination referred to is “winning”, the start opening / closing solenoid 15c is driven to control the second start opening 15 to the second mode for a predetermined opening time.

  Here, in the non-short-time gaming state, the variation time of the normal symbol is set to 29 seconds, and if it is “winning”, the second start port 15 is controlled to the second mode for 0.2 seconds. On the other hand, in the short-time gaming state, the normal symbol variation time is set to 0.2 seconds, and if it is “winning”, the second start port 15 is controlled to the second mode for 3.5 seconds. .

  Then, the main CPU 110a performs a payout control process (S1608).

  In this payout control process, the main CPU 110a refers to each prize ball counter, generates payout number designation commands corresponding to various winning ports, and transmits the generated payout number designation commands to the payout control board 130. To do.

  The main CPU 110a includes external information data, start opening / closing solenoid data, first big prize opening / closing solenoid data, second big prize opening / closing solenoid data, special symbol display device data, normal symbol display device data, and memory number designation command data. A creation process is performed (S1609).

  The main CPU 110a performs output control processing. In this processing, port output processing is performed to output the signals of the external information data, the start opening / closing solenoid data, the first big prize opening / closing solenoid data, and the second big prize opening / closing solenoid data created in S600 (S1610).

  Further, the special symbol display device data and the normal symbol display device data created in S600 are used to turn on the LEDs of the first special symbol display device 20, the second special symbol display device 21 and the normal symbol display device 22. Display device output processing is performed.

  Further, command transmission processing for transmitting the command set in the effect transmission data storage area of the main RAM 110c to the effect control board 120 is also performed.

  The main CPU 110a restores the information saved in S1601 to the register of the main CPU 110a (S1611).

  FIG. 17 is an example of a flowchart showing a detailed flow of the special figure special power control process performed on the main control board 110 of the gaming machine in the embodiment of the present invention.

  First, the value of the special figure special processing data is loaded (S1701), and the branch address is referenced from the loaded special figure special processing data (S1702).

  At this time, if the special symbol special electricity processing data is “0 (zero)”, the special symbol memory determination processing is performed (S1703). If the special symbol special electricity processing data is “1”, the special symbol variation processing is performed. (S1704), and if the special figure special electricity processing data is "2", special symbol stop processing is carried out (S1705).

  If the special figure special power processing data is “3”, the big hit game processing is performed (S1706), and if the special figure special electric processing data is “4”, the big hit game end processing is performed (S1707). If the process data is “5”, a small hit game process is performed (S1708).

  This “special drawing special electricity processing data” is set as necessary in each subroutine of the special figure special electricity control processing, so that the subroutine necessary for the game is appropriately processed.

  As the special symbol memory determination process at this time, the main CPU 110a performs a jackpot determination process, a special symbol determination process for determining a special symbol to be stopped and displayed, a variation time determination process for determining a variation time of the special symbol, and the like. The detailed flow of this special symbol memory determination process will be described with reference to FIG.

  FIG. 18 is an example of a flowchart showing a detailed flow of the special symbol memory determination process performed on the main control board 110 of the gaming machine in the embodiment of the present invention.

  First, the main CPU 110a determines whether or not one or more data is set in the first special symbol hold count (U1) storage area or the second special symbol hold count (U2) storage area (S1801).

  If one or more data is not set in any storage area of the first special symbol hold number (U1) storage area or the second special symbol hold number (U2) storage area (NO in S1801), the special figure is stored. The special symbol variation process of this time is terminated while the special electric processing data is kept at “0 (zero)”.

  On the other hand, if one or more data is set in the first special symbol hold count (U1) storage area or the second special symbol hold count (U2) storage area (YES in S1801), the main CPU 110a performs the jackpot determination process. This is performed (S1802).

  Specifically, when one or more data is set in the second special symbol hold count (U2) storage area, 1 is calculated from the value stored in the second special symbol hold count (U2) storage area. After the subtraction, the various random numbers stored in the first to fourth storage units in the second special symbol random number storage area are shifted to the previous storage unit. At this time, various random values already written in the 0th storage unit are overwritten and deleted. Whether the special symbol determination random number value stored in the 0th storage unit of the second special symbol random value storage area is a random value corresponding to “big hit” or a random value corresponding to “small hit” Judgment is made.

  In addition, when one or more data is not set in the second special symbol hold number (U2) storage area and one or more data is set in the first special symbol hold number (U1) storage area, Various random numbers stored in the first to fourth storage units in the first special symbol random number storage area after subtracting 1 from the value stored in the first special symbol hold number (U1) storage area Is shifted to the previous storage unit. Also at this time, various random numbers already written in the 0th storage section are overwritten and deleted. Whether the special symbol determination random number value stored in the 0th storage unit of the first special symbol random value storage area is a random value corresponding to “big hit” or a random value corresponding to “small hit” Judgment is made.

  In the present embodiment, the random number value stored in the second special symbol random value storage area is shifted (digested) with priority over the first special symbol random value storage area.

  Without being limited thereto, the first special symbol storage area or the second special symbol storage area may be shifted in the order of winning in the start opening, or the first special symbol storage area may be shifted to the second special symbol storage area. The shift may be performed with priority over.

  Next, the main CPU 110a performs a special symbol determination process for determining the type of special symbol to be stopped (S1803).

  In this special symbol determination process, if it is determined as “big hit” in the jackpot determination process (S1802), the jackpot symbol random number value stored in the 0th storage unit of the first special symbol random number value storage area is set. The jackpot symbol is determined based on this.

  Also, in the big hit determination process (S1802), if it is determined as “small hit”, the small hit symbol is stored based on the small bonus symbol random number stored in the 0th storage unit of the first special symbol random value storage area. The winning symbol is determined.

  Further, in the big hit determination process (S1802), when it is determined “lost”, a lost symbol is determined.

  Stop symbol data corresponding to the special symbol determined as described above is stored in the stop symbol data storage area.

  Next, the main CPU 110a performs special symbol variation time determination processing (S1804).

  Specifically, the variation pattern of the special symbol is determined based on the reach determination random number value and the special diagram variation random value stored in the 0th storage unit of the first special symbol random value storage area. Thereafter, the variation time of the special symbol corresponding to the determined variation pattern of the special symbol is determined. Then, a process of setting a counter corresponding to the determined variation time of the special symbol in the special symbol time counter is performed.

  The main CPU 110a sets variation display data for causing the first special symbol display device 20 or the second special symbol display device 21 to perform variation display of the special symbol (LED blinking) in a predetermined processing area.

  As a result, when variable display data is set in a predetermined processing area, LED lighting or extinguishing data is appropriately created by the above processing, and the created data is output, whereby the first special symbol display The variable display of the device 20 or the second special symbol display device 21 is performed.

  Furthermore, when the special symbol variation display is started (S1805), the main CPU 110a changes the special symbol variation pattern designation command (the first special symbol variation pattern designation command or the first special symbol variation pattern designation command) corresponding to the determined special symbol variation pattern. The second special symbol variation pattern designation command) is set in the effect transmission data storage area of the main RAM 110c.

  The main CPU 110a sets “Special Figure Special Electric Processing Data = 0” to “Special Special Electric Processing Data = 1” (S1806), prepares for the special symbol variation processing subroutine, and ends the special symbol memory determination processing. To do.

  FIG. 19 is an example of a flowchart showing a detailed flow of the main process performed on the effect control board 120 of the gaming machine in the embodiment of the present invention.

  First, the sub CPU 120a performs initialization processing (S1901).

  In this initialization process, the sub CPU 120a reads a main processing program from the sub ROM 120b and initializes and sets a flag and the like stored in the sub RAM 120c in response to power-on.

  Next, the sub CPU 120a performs an effect random number update process (S1902).

  In this effect random number update process, the sub CPU 120a updates the random numbers (the effect random number value 1, the effect random number value 2, the effect design determining random value, the effect mode determining random value, etc.) stored in the sub RAM 120c. Process.

  Subsequently, it is determined whether a power interruption process for shutting off the power is performed (S1903). Until the power interruption process is performed (NO in S1903), the effect random number update process is performed until a predetermined interrupt process is performed. Repeat. If the power interruption process is performed (YES in S1903), the process ends.

  FIG. 20 is an example of a flowchart showing a detailed flow of the timer interrupt process performed on the effect control board 120 of the gaming machine in the embodiment of the present invention.

  Although not shown in the figure, a clock pulse is generated every predetermined period (2 milliseconds) by a reset clock pulse generation circuit provided on the effect control board 120, a timer interrupt processing program is read, and the timer of the effect control board is read. Interrupt processing is executed.

  First, the sub CPU 120a saves the information stored in the register of the sub CPU 120a in the stack area (S2001), and updates various timer counters used in the effect control board 120 (S2002).

  Next, the sub CPU 120a performs command analysis processing (S2003).

  In this command analysis processing, the sub CPU 120a performs processing for analyzing a command stored in the reception buffer of the sub RAM 120c. Specific description of the command analysis processing will be described later with reference to FIGS. 21 and 22. When the effect control board 120 receives a command transmitted from the main control board 110, a command reception interrupt process of the effect control board 120 (not shown) occurs, and the received command is stored in the reception buffer. Thereafter, the received command is analyzed.

  The sub CPU 120a checks the signals of the effect button detection switch 35a and the cross key detection switch 36a, performs effect input control processing related to the effect button 35 (S2004), and receives various commands set in the transmission buffer of the sub RAM 120c. Data output processing to be transmitted to the lamp control board 140 and the image control board 150 is performed (S2005).

  Then, the sub CPU 120a restores the information saved in S1810 to the register of the sub CPU 120a (S2006).

  FIG. 21 is an example of a flowchart showing a detailed flow of a command analysis process performed on the effect control board 120 of the gaming machine in the embodiment of the present invention. FIG. 22 is a continuation of the command analysis process shown in FIG. It is a flowchart which shows.

  The sub CPU 120a confirms whether or not the command is received in the reception buffer, and confirms whether or not the command is received (S2101).

  If there is no command in the reception buffer (NO in S2101), the sub CPU 120a ends the command analysis process. If there is a command in the reception buffer (YES in S2101), it is subsequently confirmed whether or not the command stored in the reception buffer is a demo designation command (S2102).

  If the command stored in the reception buffer is a demonstration designation command (YES in S2102), the sub CPU 120a performs a demonstration effect pattern determination process for determining a demonstration effect pattern (S2103).

  Specifically, the demonstration effect pattern is determined, the determined demonstration effect pattern is set in the effect pattern storage area, and information on the determined demonstration effect pattern is transmitted to the image control board 150 and the lamp control board 140. An effect pattern designation command based on the demo effect pattern is set in the transmission buffer of the sub-RAM 120c.

  If the command stored in the reception buffer is not a demo designation command (NO in S2102), then the sub CPU 120a checks whether the command stored in the reception buffer is a special symbol storage designation command. (S2104).

  If the command stored in the reception buffer is a special symbol memory designation command (YES in S2104), the special symbol memory designation command is analyzed and displayed on the first liquid crystal display device 31 and / or the second liquid crystal display device 37. A special symbol memory number determination process for determining the number of special figure reservation images to be displayed and transmitting a special figure display number designation command corresponding to the determined display number of special figure reservation images to the image control board 150 and the lamp control board 140 (S2105).

  If the command stored in the reception buffer is not a special symbol storage designation command (NO in S2104), the sub CPU 120a then determines whether or not the command stored in the reception buffer is an effect symbol designation command. Confirmation is made (S2106).

  If the command stored in the reception buffer is an effect designating command (YES in S2106), the sub CPU 120a determines the first liquid crystal display device 31 and / or the second liquid crystal based on the content of the received effect designating command. An effect symbol determination process for determining an effect symbol 38 to be stopped and displayed on the display device 37 is performed (S2107).

  Specifically, the effect symbol determination process analyzes the effect symbol designation command, determines the effect symbol data constituting the combination of the effect symbols 38 according to the presence or absence of the jackpot and the type of jackpot, and the determined effect In addition to setting the symbol data in the effect symbol storage area and transmitting the effect symbol data to the image control board 150 and the lamp control board 140, a stop symbol designating command indicating the effect symbol data is set in the transmission buffer of the sub RAM 120c. .

  At this time, the sub CPU 120a further acquires one random number value from the effect mode determination random value updated as shown above, and based on the acquired effect mode determination random value and the received effect designating command. Then, an effect mode determination process for determining one effect mode from a plurality of effect modes (for example, a normal effect mode and a chance effect mode) is performed (S2108). Further, the determined effect mode is set in the effect mode storage area.

  If the command stored in the reception buffer is not an effect designating command (NO in S2106), the sub CPU 120a checks whether or not the command stored in the receiving buffer is a variation pattern specifying command (S2109). ).

  If the command stored in the reception buffer is a variation pattern designation command (YES in S2109), the sub CPU 120a acquires one random value from the updated effect random value 1, and the acquired effect random value 1. Based on the received variation pattern designation command and the effect mode set in the effect mode storage area, a variation effect pattern determination process for determining one variation effect pattern from a plurality of variation effect patterns is performed (S2110). .

  Thereafter, based on the effect pattern, the first liquid crystal display device 31, the audio output device 32, the decoration device 33a, the effect lighting device 34, and the second liquid crystal display device 37 are controlled. Note that the variation mode of the effect design 38 is determined based on the variation effect pattern determined here.

  If the command stored in the reception buffer is not a variation pattern designation command (NO in S2109), the sub CPU 120a checks whether or not the command stored in the reception buffer is a symbol determination command (S2111). .

  If the command stored in the reception buffer is a symbol determination command (YES in S2111), the sub CPU 120a transmits a stop designation command for stopping and displaying the effect symbol to stop the effect symbol 38 to be transmitted to the sub RAM 120c. An effect symbol stop display process to be set in the buffer is performed (S2112).

  If the command stored in the reception buffer is not a symbol determination command (NO in S2111), the sub CPU 120a determines whether or not the command stored in the reception buffer is a gaming state designation command (S2113). .

  If the command stored in the reception buffer is a gaming state designation command (YES in S2113), the sub CPU 120a stores data indicating the gaming state based on the received gaming state designation command in the gaming state storage area in the sub RAM 120c. Set (S2114).

  If the command stored in the reception buffer is not a gaming state designation command (NO in S2113), the sub CPU 120a checks whether or not the command stored in the reception buffer is an opening command (S2115).

  If the command stored in the reception buffer is an opening command (YES in S2115), the sub CPU 120a performs a hit start effect pattern determination process for determining a hit start effect pattern (S2116).

  Specifically, the hit start effect pattern is determined based on the opening command, the determined hit start effect pattern is set in the effect pattern storage area, and information on the determined hit start effect pattern is controlled by the image control board 150 and the lamp control. In order to transmit to the board 140, an effect pattern designation command based on the determined hit start effect pattern is set in the transmission buffer of the sub RAM 120c.

  If the command stored in the reception buffer is not an opening command (NO in S2115), the sub CPU 120a determines that the command stored in the reception buffer is the first grand prize winning port 16 and / or the second major winning prize port 17. It is confirmed whether or not it is a special winning opening opening designation command for instructing opening (S2117).

  If the command stored in the reception buffer is a big winning opening opening designation command (YES in S2117), the sub CPU 120a performs a jackpot effect pattern determination process for determining a jackpot effect pattern (S2118).

  Specifically, the jackpot effect pattern is determined based on the big prize opening opening designation command, the determined jackpot effect pattern is set in the effect pattern storage area, and information on the determined jackpot effect pattern is stored in the image control board 150 and the lamp. In order to transmit to the control board 140, an effect pattern designation command based on the determined jackpot effect pattern is set in the transmission buffer of the sub RAM 120c.

  If the command stored in the reception buffer is not a special winning opening opening designation command (NO in S2117), the sub CPU 120a checks whether or not the command stored in the reception buffer is an ending command (S2119). ).

  If the command stored in the reception buffer is an ending command (YES in S2119), the sub CPU 120a performs a hit end effect pattern determination process for determining a hit end effect pattern (S2120).

  Specifically, the winning end effect pattern is determined based on the ending command, the determined winning end effect pattern is set in the effect pattern storage area, and information on the determined hit end effect pattern is controlled by the image control board 150 and the lamp control. In order to transmit to the board 140, an effect pattern designation command based on the determined hit end effect pattern is set in the transmission buffer of the sub-RAM 120c.

  If it is not any command (NO in S2119), the command analysis process is terminated by terminating the present process.

  Next, FIG. 23 is a flowchart showing a detailed flow of a main process performed in the image control board 150 of the gaming machine according to the embodiment of the present invention.

  When power is supplied from the power supply board 170, a system reset occurs in the liquid crystal control CPU 150a, and the liquid crystal control CPU 150a performs main processing as described below.

  The liquid crystal control CPU 150a performs an initialization process (S2301).

  In this initialization process, the liquid crystal control CPU 150a reads the main processing program from the liquid crystal control ROM 150c and instructs the initial settings of the various modules of the liquid crystal control CPU 150a and the VDP 2000 when the power is turned on.

  Here, the liquid crystal control CPU 150a, as an instruction for initial setting of the VDP 2000, (1) instructs the display circuit constituting the VDP 2000 to create and output a video signal, and therefore instructs the display of the video signal (display). (“1” is set to 0 bit of the register), or (2) image data that is frequently used in the decompression circuit constituting the VDP2000 (image data such as production symbol 38) is decompressed to the image data development area 153b of the VRAM 153. In order to set the initial value data in the expansion register, or (3) the initial value image data (such as a character image “power-on”) is drawn in the drawing circuit constituting the VDP 2000. Output value display list.

  Subsequently, the liquid crystal control CPU 150a performs a drawing execution start process (S2302).

  In this drawing execution start process, drawing execution start data is set in the drawing register in order to instruct VDP 2000 to execute drawing on the display list that has already been output.

  That is, at the start of power-on, execution of drawing on the initial value display list output at step (S2301) is instructed, and at normal routine processing, execution of drawing on the display list output at S2050 described later is instructed. It will be.

  Next, the liquid crystal control CPU 150a performs effect pattern designation command analysis processing for analyzing the effect pattern designation command (command stored in the reception buffer of the liquid crystal control RAM 150b) transmitted from the effect control board 120 (S2303).

  When the image control board 150 receives a command transmitted from the effect control board 120, a command reception interrupt process of the image control board 150 (not shown) occurs, and the received command is stored in the reception buffer. Thereafter, the received command is analyzed.

  The effect pattern designation command analysis process confirms whether or not an effect pattern designation command is stored in the reception buffer. If the effect pattern designation command is not stored in the reception buffer, the process is continued. If the effect pattern designation command is stored in the reception buffer, a process of reading a new effect pattern designation command is performed. Based on the read effect pattern designation command, one or more animation groups to be executed are determined, and an animation pattern is determined from each animation group.

  When the animation pattern is determined, the read effect pattern designation command is deleted from the transmission buffer.

  Next, the liquid crystal control CPU 150a performs animation control processing (S2304).

  In this animation control process, based on the above-described “scene switching counter”, “weight frame”, “frame counter” to be updated, and the animation pattern determined by the process as described above, Update the scene address.

  Thereby, the liquid crystal control CPU 150a determines the display list from the display information (sprite identification number, display position, etc.) of one frame of the animation scene at the updated address according to the priority order (drawing order) of the animation group to which the animation scene belongs. When the generation of the display list is completed, the display list is output to the VDP 2000 (S2305). The display list output here is stored in the display list storage area 153a of the VRAM 153 via the CPU I / F 2030 in the VDP 2000.

  Then, the liquid crystal control CPU 150a determines whether or not the FB switching flag = 01 (S2306).

  Here, as will be described later with reference to FIG. 24B, the FB switching flag indicates that if the previous display list has been drawn in the V blank interrupt every 1/60 seconds (about 16.6 ms). , FB switching flag = 01. That is, it is determined whether or not the previous drawing has been completed.

  If the FB switching flag is “01” (YES in S2306), the liquid crystal control CPU 150a sets the FB switching flag to “00” (S2307) (turns off the FB switching flag) and ends the process.

  On the other hand, if the FB switching flag is “00” (NO in S2306), the process waits until the FB switching flag becomes “01”.

  Next, FIG. 24 is a flowchart showing a detailed flow of an interrupt process performed on the image control board 150 of the gaming machine according to the embodiment of the present invention.

  In the interrupt processing of the image control board 150, a drawing end interrupt process performed by inputting a drawing end interrupt signal, a V blank interrupt process performed by inputting a V blank interrupt signal, and a command are received. And at least a command reception interrupt process performed.

  Note that the drawing end interrupt process and the V blank interrupt process will be described with reference to FIG. 24, but the command reception interrupt process has been described above, and is not shown.

  FIG. 24A is a flowchart showing a detailed flow of a drawing end interrupt process performed on the image control board 150 of the gaming machine according to the embodiment of the present invention.

  When the drawing of a predetermined unit frame (one frame) is completed, the VDP 2000 outputs a drawing end interrupt signal to the liquid crystal control CPU 150a.

  When the liquid crystal control CPU 150a receives a drawing end interrupt signal from the VDP 2000, the liquid crystal control CPU 150a executes a drawing end interrupt process.

  In the drawing end interrupt process, the liquid crystal control CPU 150a sets the drawing end flag = 01 (turns on the drawing end flag), and ends the current drawing end interrupt process (S2401). That is, the drawing end flag is turned on every time drawing ends.

  FIG. 24B is a flowchart showing a detailed flow of the V blank interrupt process performed on the image control board 150 of the gaming machine according to the embodiment of the present invention.

  The crystal oscillator 152 constituting the image control board 150 generates a V blank interrupt signal (vertical synchronization signal) having a pulse waveform every 1/60 seconds (about 16.6 ms), and this V blank interrupt signal is generated. The detected VDP 2000 outputs an “effect processing timing notification signal” based on the V blank interrupt signal to the liquid crystal control CPU 150a at a predetermined timing.

  Thereby, the liquid crystal control CPU 150a receives an “effect process timing notification signal” based on the V blank interrupt signal from the VDP 2000, and performs an interrupt process to perform an effect by receiving the effect process timing notification signal. The effect process is performed at the interrupt timing by the interrupt process.

  The predetermined timing at which the VDP 2000 outputs the “production process timing notification signal” to the liquid crystal control CPU 150a is determined based on the generated V blank interrupt signal.

  As an interrupt process performed by the image control board 150, first, the liquid crystal control CPU 150a performs a process of updating various counters of “scene switching counter”, “wait frame”, and “frame counter” from existing values by a unit quantity ( S2402).

  Subsequently, when the liquid crystal control CPU 150a performs processing for updating these various counters, it determines whether or not “01” is set in the “drawing end flag” (S2403). This “drawing end flag” is flag information for determining whether or not the rendering process of the effect image in the immediately preceding frame has ended.

  If the liquid crystal control CPU 150a determines that the “drawing end flag” is “01” (YES in step S2403), that is, determines that drawing of the effect image in the frame has ended, the “drawing end flag” "00" is set to "" (S2404).

  On the other hand, if “01” is not set in the “drawing end flag” (NO in S2402), that is, if it is determined that drawing of the effect image in the frame has not ended, the current V blank assignment Finish the process. Even if an effect processing timing notification signal based on the V blank interrupt signal is received from the VDP 2000, the subsequent interrupt processing is not performed unless the effect image drawing processing in the immediately preceding frame is completed in the liquid crystal control CPU 150a. It is shown that.

  Then, the rendering of the effect image in the immediately preceding frame has been completed, and when “00” is set in the “rendering end flag” (S2404), the liquid crystal control CPU 150a continues to the memory controller configuring the VDP2000. Then, together with an instruction to switch between “display frame buffer” and “drawing frame buffer”, an “effect processing timing notification signal” is output (S2405).

  This “effect process timing notification signal” is a signal for notifying the effect process timing in the liquid crystal control CPU 150a.

  Then, the liquid crystal control CPU 150a sets “01” in the “FB switching flag” (turns on the FB switching flag) (S2406), cancels the standby state, and ends the V blank interrupt processing.

  Thus, the liquid crystal control CPU 150a instructs the VDP2000 memory controller to generate an effect image in units of frames corresponding to the effect pattern designation command received from the effect control board 120 in the drawing frame buffer after switching.

  As a result, the VDP 2000 reads the image information constituting the effect image stored in the CGROM 151 and stores the effect image composed of the frames in the drawing frame buffer on the VRAM 153.

  In addition to this, in the VDP 2000, even if the V blank interrupt signal generated by the crystal oscillator 152 is detected, when the V blank interrupt signal is detected immediately before, an effect processing timing notification signal is notified to the liquid crystal control CPU 150a. If the V blank interrupt signal is present, the effect processing timing notification signal is not notified. Conversely, when the V blank interrupt signal is detected immediately before, the effect processing timing notification is sent to the liquid crystal control CPU 150a. When the signal is not notified, the presentation process timing notification signal may be notified in the case of the V blank interrupt signal.

  This is because, for example, when the V blank interrupt signal is detected in VDP2000, the interruption flag is “valid (ON)”, so that the effect processing timing notification signal is notified to the liquid crystal control CPU 150a, and then the interruption Set the flag from “valid (ON)” to “invalid (OFF)”. Subsequently, when the next V blank interrupt signal is received, since the interrupt flag is set to “invalid (OFF)”, the interrupt flag is not notified to the liquid crystal control CPU 150a without notifying the liquid crystal control CPU 150a. Is set to “valid (ON)”, an effect processing timing notification signal can be notified every other time (at intervals).

  FIG. 25 is a block diagram showing a detailed configuration of the RTC device constituting the gaming machine in the embodiment of the present invention.

  The RTC device 154 shown in FIG. 25 is the RTC device 154 included in the image control board 150 constituting the gaming machine shown in FIG. As shown in FIG. 4, the RTC device 154 is connected to the liquid crystal control CPU 150a in a state where mutual communication is possible. As an example of the connection form at this time, there is a synchronous serial communication form such as SPI (Serial Peripheral Interface).

  This RTC device 154 is based on a frequency (hereinafter referred to as “oscillation frequency”) oscillated by a built-in oscillator or connected by a bus line (hereinafter referred to as “oscillation frequency”). It is a device for updating (referred to as “time information”).

  As this oscillator, a high-precision crystal resonator can be used.

  The game designation time information at this time is time information used for a specific effect or the like in a game designated in advance. By updating this time information, it is shown that the specific effect is activated when the game specified time specified in advance is reached.

  As shown in FIG. 25, the RTC device 154 includes an I / F circuit 154a including a CE signal transmission / reception unit 154b and a data communication unit 154c, an oscillator 154d, a frequency division control unit 154e, a CE signal reception state determination unit 154f, a time An information update hold control unit 154g, a time information update processing unit 154h, a storage control unit 154i, a time information storage unit 154j, and a timing control processing unit 154k are provided.

  The CE signal transmission / reception unit 154b included in the I / F circuit 154a that is an interface with the liquid crystal control CPU 150a is an interface that receives an input of a CE (chip enable) signal output from the liquid crystal control CPU 150a connected to the RTC device 154. This CE signal indicates that the liquid crystal control CPU 150a has selected the RTC device 154 as a device, and the CE signal is in an active state (CE = “H” (High)) and selected. As a result, input / output of information (time information) between the RTC device 154 and the liquid crystal control CPU 150a becomes effective.

  That is, the case where the CE signal is in an active state indicates a state in which the liquid crystal control CPU 150a can use (validate) the time information updated by the RTC device 154.

  This indicates that when the CE signal is in an active state, the RTC device 154 may accept an input / output request for time information by the liquid crystal control CPU 150a. Of course, the RTC device 154 updates the time information regardless of whether the CE signal is in an active state or an inactive state.

  The data communication unit 154c is a data communication interface for inputting / outputting time information to / from the liquid crystal control CPU 150a. In the example shown in FIG. 25, the RTC device 154 and the liquid crystal control CPU 150a are connected by serial communication. Is shown.

  As serial communication at this time, there is an SPI communication form as described above, and communication is performed with a configuration in which at least a clock signal line, a data input signal line, and a data output signal line are connected. Of course, in addition to these signal lines, there are provided signal lines and the like for connecting devices having a master-slave relationship (not shown).

  A clock signal line indicated by “CLK” in FIG. 25 is a clock signal used for data input / output (transmission / reception), and information (in the above example, time information in synchronization with the rising edge of the clock signal). ) Is input / output.

  In addition, a data input signal line illustrated as “DI” in FIG. 25 is a signal line through which information is input from the liquid crystal control CPU 150 a to the RTC device 154. Furthermore, the data output signal line indicated as “DO” in FIG. 25 is a signal line through which information is input from the RTC device 154 to the liquid crystal control CPU 150a.

  The data communication unit 154c, which is an interface for inputting and outputting information through such a signal line, is connected to the storage control unit 154i. This storage control unit 154i is also called a memory controller, reads out the time information stored in the time information storage unit 154j constituted by a register and the like, and when the CE signal is in an active state, the data communication unit 154c Communication with the liquid crystal control CPU 150a via the input / output of time information.

  Subsequently, when the CE signal transmission / reception unit 154b receives an input of the CE signal from the liquid crystal control CPU 150a, the CE signal transmission / reception unit 154b notifies the CE signal reception state determination unit 154f of the reception of the CE signal. The CE signal reception state determination unit 154f determines the reception state of the CE signal. When the CE signal is notified from the CE signal transmission / reception unit 154b, the CE signal reception state determination unit 154f determines and manages the CE signal as an active state. If not notified, it is determined to be inactive and managed.

  The CE signal reception state determination unit 154f receives an input of a frequency division frequency obtained by dividing the oscillation frequency oscillated in the oscillator 154d in the frequency division control unit 154e, and is in a state where it is managed as an active state at this time, or It is determined whether it is in a state managed as an inactive state.

  As described above, the oscillator 154d can be configured by a crystal resonator and oscillates at an oscillation frequency serving as a source oscillation. For example, the oscillator 154d oscillates at an oscillation frequency of 32768 Hz (Hertz). In this embodiment, a configuration using the oscillator 154d as an oscillator different from the crystal oscillator 152 is shown. However, the present invention is not limited to this, and the configuration using the crystal oscillator 152 without newly providing the oscillator 154d. May be.

  Further, based on the oscillation frequency oscillated in the oscillator 154d, the frequency division control unit 154e generates one or a plurality of frequency division frequencies by dividing the frequency by a designated division ratio designated in advance. That is, the frequency division control unit 154e generates a frequency division frequency for the designated frequency division ratio by multiplying the oscillation frequency by the reciprocal of the designated frequency division ratio.

  For example, when the oscillation frequency of the original oscillation oscillated from the oscillator 154d is “32768 Hz” in the example shown above and “2” is designated as the designated division ratio, the oscillation frequency of the designated division ratio is specified. A frequency division frequency of “16384 Hz” multiplied by the reciprocal is generated.

  Subsequently, the frequency division control unit 154e generates a new frequency division by further dividing the generated frequency division (frequency division of “16384 Hz” in the above example) based on the specified frequency division ratio. It will be. In this example, a frequency division frequency of “8192 Hz” is newly generated by dividing the frequency division frequency of “16384 Hz” based on the specified frequency division ratio “2”.

  In this way, the frequency division control unit 154e generates one or a plurality of frequency division frequencies based on the oscillation frequency, and a new frequency division frequency is generated based on the generated frequency division frequency. There is also. In this case, the frequency dividing frequency that is a source for generating a new frequency dividing frequency is referred to as “parent frequency dividing frequency” or “generator frequency dividing frequency”. On the other hand, a frequency division frequency newly generated based on this “parent frequency division (source frequency division frequency)” is referred to as “child frequency division frequency” or “generation frequency division frequency”.

  In the above example, “16384 Hz” corresponds to “parent frequency division”, and “8192 Hz” divided from this “parent frequency division” corresponds to “child frequency division”.

  The frequency division control unit 154e generates a plurality of frequency division frequencies based on the designated frequency division ratio up to a unit frequency division frequency that is a minimum unit designated in advance.

  As described above, when the oscillation frequency of “32768 Hz” is oscillated by the oscillator 154d and the unit frequency division is set to “1 Hz”, the frequency division control unit 154e adds the total frequency including the unit frequency division frequency. 15 frequency division frequencies will be generated. The number of frequency division frequencies generated corresponds to a “power value (power value)” when the oscillation frequency serving as the original oscillation is expressed by a power (power) of a specified frequency division ratio.

  The frequency division control unit 154e is a frequency used for internal control in the liquid crystal control CPU 150a, and is a frequency dividing frequency used for determining the processing timing of the effect (also referred to as effect timing). And a “unit frequency division frequency” (also referred to as “second frequency division frequency”) that is a frequency division frequency used for updating time information. It becomes.

  In this example, “production timing determination frequency division frequency” is shown as an example of “first frequency division frequency”, and “unit frequency division frequency” is shown as an example of “second frequency division frequency”. However, the present invention is not limited to this, and the first frequency division frequency and the second frequency division frequency may be any one of the frequency division frequencies generated by the frequency division control unit 154e.

  At this time, in the CE signal reception state determination unit 154f, from the timing at which the production timing determination frequency is divided (measurement of the cycle), after that timing, the unit division frequency becomes the cycle (measurement of the cycle). It is detected that the divided delay time which is the period until the timing is reached.

  That is, it indicates that the timing that is the period of the production timing determination division frequency (measures the period) is the start timing of the division delay time, and similarly the period of the unit division frequency (measures the period). It shows that the timing is the end timing of the divided delay time.

  The production timing determination division frequency is, for example, “4096 Hz”, and the unit division frequency is, for example, “1 Hz (Hertz)”. In this case, the time information is updated by “1 second” at the timing of the unit period (one period) of the unit frequency division frequency.

  When the CE signal reception state determination unit 154f detects the frequency division delay time, it is managed as an active state because the CE signal is notified from the CE signal transmission / reception unit 154b, or the CE signal is not notified. Judgment processing is performed as to whether or not the inactive state is managed.

  The processing performed according to the determination result of this determination processing is different, and the time information is updated after the processing.

  Below, each processing according to three judgment results is explained.

  First, as a first determination result, it is determined by this determination process that the CE signal is not notified continuously within the division delay time and is managed as an inactive state. In other words, when the RTC device 154 indicates that there is no possibility that the time information input / output processing is performed from the liquid crystal control CPU 150a, the CE signal reception state determination unit 154f performs the time information update processing unit 154h. To update the time information.

  The time information update processing unit 154h uses the storage control unit 154i to store the time information stored in the time information storage unit 154j at the timing when the period of the unit frequency division is measured by the generation processing by the frequency division control unit 154e. And updates and stores only the unit time specified in advance.

  The updated time information updated by this update process is overwritten on the already stored time information and stored in the time information storage unit 154j.

  The unit time at this time is the minimum unit time to be managed as time information. When the unit time is managed in seconds, the time information update processing unit 154h sets time information with “1 second” as the minimum unit. Update. That is, the time information is updated every 1 second.

  Next, as a second determination result, when the CE signal is notified at the start timing of the divided delay time by the determination process performed in the CE signal reception state determination unit 154f, the active state is managed. When making a determination, that is, when the RTC device 154 indicates a state in which input / output of time information may be performed from the liquid crystal control CPU 150a, the CE signal reception state determination unit 154f performs time information update suspension control. An update hold instruction for temporarily holding the time information update process is given to the unit 154g.

  In the above, the processing in the CE signal reception state determination unit 154f when the CE signal is notified at the start timing of the division delay time and managed as the active state is shown. The case where the CE signal is notified at the start timing of ”means that the frequency division delay time continues to be active and the active state at the start timing of the frequency division delay time. This includes the case of inactive state at the end timing. That is, the determination is based on the start timing of the divided delay time, and does not ask the subsequent state (active state, inactive state).

  When the time information update hold control unit 154g receives an update hold instruction from the CE signal reception state determination unit 154f, the time information update hold control unit 154g performs update hold processing for holding the update of the time information until the timing when the active state is changed to the inactive state. This update hold process is also referred to as an access hold process because update (access) of time information is held (held).

  In addition, the timing at which the access hold state is canceled in the access hold process, and the timing at which the active state is managed as the inactive state, as described above, means that use of time information is effective in the liquid crystal control CPU 150a or the like. The timing when the state is not performed is shown.

  By this access hold processing, it is possible to avoid overlap of the timing of updating the time information and the input / output timing of the time information, and time information is timed more accurately (stable timekeeping operation is performed). Is possible.

  The time information update hold control unit 154g in the state in which the access hold processing is performed is notified that the CE signal is in an inactive state via the CE signal reception state determination unit 154f, that is, the time information update The access hold state is canceled by notifying that the use is valid. Then, the time information update suspension control unit 154g instructs the time information update processing unit 154h to update the time information.

  The time information update processing unit 154h updates the time information stored in the time information storage unit 154j for a unit time specified in advance via the storage control unit 154i. The updated time information is overwritten on the existing time information and stored in the time information storage unit 154j.

  As a third determination result, the determination process performed in the CE signal reception state determination unit 154f is within the divided delay time, but the CE signal is not notified at the start timing of the divided delay time, When it is determined that the use of time information is not valid, but the CE signal is notified at the end timing of the divided delay time, that is, the use of time information is valid The CE signal reception state determination unit 154f accepts the CE signal within the frequency division delay time and changes to the state in which the use of the time information is enabled, the timing control processing unit 154k and the time information update processing unit 154h. Notify each.

  The timing control processing unit 154k receives the CE signal from the CE signal reception state determination unit 154f within the frequency division delay time, thereby notifying that the state (active state or inactive state) has been changed. Process.

  The timing control processing performed by the timing control processing unit 154k controls the state change timing for changing from the inactive state where the use of time information is not valid to the active state where the use of time information is valid. It is processing.

  More specifically, in this timing control process, the RTC device 154 receives the CE signal within the division delay time and newly sets the timing at which the RTC device 154 enters the active state at a time other than the division delay time. In this timing, it is assumed that the inactive state where the use of time information is not valid is changed to the active state where the use of time information is valid. Thereby, the input / output processing of the time information from the liquid crystal control CPU 150a is performed after the change to the active state.

  Therefore, the time information update processing unit 154h recognizes that the CE signal has been received and has entered the active state at the state change timing after setting, which is set by performing timing control by the timing control processing unit 154k.

  That is, since the time information update processing unit 154h recognizes that the CE signal is not received and is in an inactive state within the frequency division delay time, the CE signal reception state determination unit 154f performs the frequency division delay. The time information is updated at the timing when the period of the unit frequency is measured, which is the end timing of time.

  The state change timing after setting set by the timing control processing shown above is determined based on the period of the production timing determination divided frequency that is the divided frequency generated by dividing by the dividing control unit 154e. In addition to the timing, the timing is determined based on the period of the oscillation frequency oscillated by the oscillator 154d.

  The timing based on the period of the production timing determination division frequency is after the timing when the period of the unit division frequency, which is the end timing of the division delay time, is measured. The timing which becomes a period is shown.

  The timing based on the period of the oscillation frequency is after the timing of measuring the period of the unit frequency division, which is the end timing of the frequency division delay time, and first becomes the half period of the oscillation frequency that is the original oscillation. Timing is shown.

  As described above, the timing control processing unit 154k has a frequency division delay time from the timing at which the frequency division control unit 154e measures the cycle of the production timing determination frequency to the timing at which the unit frequency is measured. When the CE signal for changing the state to the active state in which the use of the time information is valid is received, the timing control for delaying the state change timing to a time other than the divided delay time is performed.

  As a result, the RTC device 154 avoids the state change from the inactive state to the active state upon receipt of the CE signal from the liquid crystal control CPU 150a at the timing when the time information update processing unit 154h updates the time information. Thus, stable time information can be updated.

  The RTC device 154 updates the time information according to the three determination results as described above.

  In the example shown above, the state change from the inactive state to the active state by receiving the CE signal at the timing when the period of the production timing determination frequency division is measured and the timing when the period of the unit frequency division is measured. However, the present invention is not limited to this, and the following configuration may be used.

  In other words, the division delay time from the timing at which the period of the production timing determination division frequency is measured to the timing at which the period of the unit division frequency is measured is always the timing regardless of the above determination. It may be configured to delay the state change timing to a time other than the division delay time by performing the control process.

  As an example of this configuration, a delay control device 155 as shown in FIG. 36 can be provided between the RTC device 154 and the liquid crystal control CPU 150a.

  A detailed description of the configuration shown in FIG. 36 will be given later.

  26 to 29 are timing charts in the time information update process performed in the gaming machine according to the embodiment of the present invention.

  FIG. 26 and FIG. 27 show an enlarged timing chart in which a part of the time portion is enlarged together with a timing chart in the time information update process.

  FIG. 26A, FIG. 26B, FIG. 27A, and FIG. 27B show the pulse waveform at the oscillation frequency of “32768 Hz” oscillated from the oscillator 154d, and “32768 Hz” of this oscillation frequency. Of the divided frequencies generated by dividing, the pulse waveforms of “4096 Hz”,..., “4 Hz”, “2 Hz”, and “1 Hz” are shown.

  Furthermore, in FIG. 26A, FIG. 26B, FIG. 27A, and FIG. 27B, the RTC device 154 receives the CE signal pulse waveform received from the liquid crystal control CPU 150a, and this CE signal. The pulse waveform of the CE status verification pulse used to set an access hold identification flag, which will be described later according to the state, the pulse waveform of the access hold identification flag in which the hold time for temporarily holding the update of the time information is set, and the time information A pulse waveform of a time update timing signal (also referred to as “carry signal”) in which update timing is set and time information to be set are shown.

  First, FIG. 26 corresponds to the first determination result shown above, and the time from the timing at which the period of the production timing determination division frequency is measured to the timing at which the period of the unit division frequency is measured. An example is shown in which the inactive state continues without receiving the CE signal for the circumferential delay time. That is, it is an example in the case where it is determined that the inactive state is present at both the timing at which the period of the production timing determination frequency division is measured and the timing at which the period of the unit frequency division is measured.

  FIG. 26B shows a timing chart in which the timing at which the time information is updated by expanding one period of the unit frequency division frequency.

  In FIG. 26B, the timing at which the period of the production timing determination frequency division is measured is “timing A”, and the timing at which the period of the unit frequency division is measured is “timing B”. From this, the time interval from the timing A to the timing B indicates the frequency division delay time. In addition, after becoming one cycle of the unit frequency division frequency, first, a timing that becomes a half cycle of the production timing determination frequency division frequency is set as “timing C”.

  In FIG. 26B, since the inactive state continues for the frequency division delay time, the timing B, which is the timing of one cycle of the unit frequency divided as the end time of the frequency division delay time. In this case, an example in which time information is updated for unit time is shown. In addition, although time information is updated at timing B, for convenience, an example in which time information is updated until timing C is shown.

  Next, FIG. 27 corresponds to the second determination result shown above, from the timing at which the period of the production timing determination division frequency is measured to the timing at which the period of the unit division frequency is measured. An example is shown in which the division delay time continues and remains in the active state. That is, it is an example in the case where it is determined that the active state is in both the timing at which the period of the production timing determination frequency division is measured and the timing at which the period of the unit frequency division is measured.

  FIG. 27B shows a timing chart in which the timing at which the time information is updated by expanding one period of the unit frequency division frequency is the same as FIG. 26B.

  In FIG. 27 (b), as in FIG. 26 (b), the timing at which the period of the production timing determination frequency division is measured is “timing A”, and the timing at which the period of the unit frequency division is measured is “timing B”. Then, after one cycle of the unit frequency is obtained, the timing that becomes the half cycle of the effect timing determination frequency is first set as “timing C”.

  Further, in FIG. 27 (b), in addition to these, at timing A, since the CE signal is in an active state, the access hold identification flag is enabled (flgMskSec = “H”). The timing at which the active hold identification flag activated at the timing A is canceled (flgMskSec = “L”) at the timing when the state is changed from the active state to the inactive state is “timing D”.

  In FIG. 27 (b), at timing A, the access hold identification flag is validated (flgMskSec = “H”) and the update of the time information is suspended because it is in the active state by receiving the CE signal. The update of the held time information is changed from the active state to the inactive state by receiving the CE signal, and the activated access hold identification flag is released (flgMskSec = “L”). ) Is performed at the timing D.

  FIG. 27 shows an example in which the frequency division delay time from the timing at which the period of the production timing determination frequency division is measured to the time at which the period of the unit frequency division is measured is continuously active. However, in addition to being in the active state (CE = “H”) at the timing A when the period of the production timing determination frequency division is measured, the inactive state (CE) at the timing B when the period of the unit frequency division is measured. = “L”), the same processing is performed.

  It should be noted that, as described above, “in the active state (CE =“ H ”) at the timing A when the period of the production timing determination frequency division is measured, but in the inactive state at the timing B when the period of the unit frequency division is measured. In the case (changed to CE = “L”), the access hold identification flag is set at timing A.

  Then, the access hold identification flag set in this way is canceled at the time “timing C”, and the time update is performed at the time “timing C”.

  In other words, regardless of the state of the timing B at which the period of the unit frequency division is measured, if at least the CE signal is received at the time of the timing A at which the period of the production timing determination frequency division is measured, The time information is updated by temporarily holding as shown in FIG.

  FIG. 28 and FIG. 29 correspond to the third determination result shown above, and are the timing at which the period of the unit frequency division is measured from the timing at which the period of the effect timing determination frequency division is measured. 10 is a timing chart in the case where the timing change process is performed by changing the state from the inactive state to the active state by receiving the CE signal by the time before.

  28 and 29, timing A, timing B, timing C, and timing D are provided as in FIG.

  In FIG. 28, the timing control processing unit 154k shown in FIG. 25 performs the timing control process, so that CE is measured from the timing at which the period of the production timing determination divided frequency is measured to the timing at which the period of the unit divided frequency is measured. This is an example in which the state change timing for changing the state from the inactive state to the active state by receiving a signal is set to a timing determined based on the period of the production timing determination frequency division frequency.

  In FIG. 28, the state change timing for changing the state from the inactive state to the active state by receiving the CE signal from the timing at which the production timing determination divided frequency is generated to the timing at which the unit divided frequency is generated. Shows an example in which, after the timing at which the unit divided frequency, which is the end timing of the divided delay time, is generated, is set to a timing that is a half cycle of the production timing determination divided frequency first.

  FIG. 28 shows a timing chart of the CEq signal in which timing is set by performing timing control processing on the CE signal received from the liquid crystal control CPU 150a.

  That is, in the RTC device 154, time information input / output processing is performed at a timing based on the CEq signal newly set for the CE signal received from the liquid crystal control CPU 150a.

  FIG. 28 shows an example in which the active state is set at a timing corresponding to a half cycle of the effect timing determination frequency division frequency. This active state is the timing D that is set to the inactive state by the CE signal received from the liquid crystal control CPU 150a. It will continue until.

  From this, when the timing control processing unit 154k performs the timing control processing, the start timing for making the use of the time information valid becomes one period of the unit frequency division frequency, and then the production timing determination frequency division is first performed. Timing C is a half cycle of the frequency.

  The time information continues until the timing D is changed from the active state to the inactive state by the CE signal after the use is made effective at the timing C, and the timing D is made effective. This is the end timing of the time information.

  Therefore, the RTC device 154 generates the CEq signal set to the active state from the timing C to the timing D.

  At this time, since the state change timing to the active state is changed to the timing C, the RTC device 154 (more specifically, the time information update processing unit 154h), when measuring the period of the unit frequency division, Since it is recognized that the use (input / output) of information is not valid, the carry signal at the timing B when the unit frequency division frequency is obtained, as in the state shown in FIG. Is activated (clkSec = "H"), and the time information is updated.

  As shown in FIG. 28, the timing of receiving the CE signal by the timing control process and delaying the timing of the active state to the timing at which the period of the production timing determination frequency division is measured is sufficient for the frequency division delay time. Therefore, the input of time information and the update of time information can be separated, and the time information can be updated stably.

  Note that a delay time (also referred to as “first delay time”) until a timing that is a half cycle of the effect timing determination divided frequency is stored in the time information storage unit 154j, and the liquid crystal control CPU 150a is transmitted via the data communication unit 154c. Then, the storage control unit 154i may read out the delay time and the data communication unit 154c may return the delay time to the requesting liquid crystal control CPU 150a.

  Subsequently, FIG. 29 is a timing at which the period of the unit frequency division is measured from the timing at which the period of the production timing determination frequency division is measured by the timing control processing unit 154k illustrated in FIG. 25 performing the timing control process. This is an example in which the state change timing for changing the state from the inactive state to the active state by receiving the CE signal is set to a timing determined based on the period of the transmission frequency of the original oscillation.

  In FIG. 29, the state is changed from the inactive state to the active state by receiving the CE signal from the timing at which the period of the production timing determination division frequency is measured to the time at which the period of the unit frequency division is measured. The change timing is the timing after the timing at which the unit divided frequency, which is the end timing of the divided delay time, is generated, and the timing at which the half cycle of the oscillation frequency that is the original oscillation is first shown.

  FIG. 29 also shows a timing chart of a CEq signal in which timing is set by performing timing control processing on the CE signal received from the liquid crystal control CPU 150a.

  FIG. 29 shows an example in which the active state is set at a timing corresponding to a half cycle of the oscillation frequency, and this active state is continued until the timing D is set to the inactive state by the CE signal received from the liquid crystal control CPU 150a. It becomes.

  From this, by performing the timing control process, the start timing for making the use of the time information effective becomes one cycle of the unit frequency and then first becomes a half cycle of the oscillation frequency that is the original oscillation. The timing is “timing E”.

  The time information continues until the timing D is changed from the active state to the inactive state by the CE signal after the use is made effective at the timing E, and the timing D is made effective. This is the end timing of the time information.

  Therefore, the RTC device 154 generates the CEq signal set to the active state from the timing E to the timing D.

  At this time, since the state change timing to the active state is changed to the timing E, the RTC device 154 (more specifically, the time information update processing unit 154h) detects the time when measuring the period of the unit frequency division frequency. Since it is recognized that the use (input / output) of information is not valid, the carry signal at the timing B when the unit frequency division frequency is obtained, as in the state shown in FIG. Is activated (clkSec = "H"), and the time information is updated.

  As shown in FIG. 29, by delaying the timing of receiving the CE signal and making it active by the timing control processing until the timing at which the oscillation frequency is generated, the delay is delayed for a long time. Therefore, the time information can be reliably updated.

  In addition, as shown in FIG. 29, when it is decided to delay until the timing that becomes the half cycle of the oscillation frequency, when it is decided to delay until the timing that becomes the half cycle of the production timing determination divided frequency shown in FIG. In comparison, the period in which the use (input / output) of the time information is prohibited is shortened from the timing when the use of the time information by the CE signal received from the liquid crystal control CPU 150a is validated.

  Note that a delay time (also referred to as “second delay time”) until the timing at which the oscillation frequency becomes a half cycle is stored in the time information storage unit 154j, and the delay time is transmitted from the liquid crystal control CPU 150a via the data communication unit 154c. When the acquisition request is made, the storage control unit 154i may read the delay time, and the data communication unit 154c may return the delay time to the requesting liquid crystal control CPU 150a.

  FIG. 30 is a flowchart showing a detailed flow of main processing performed in the RTC device of the gaming machine according to the embodiment of the present invention.

  In FIG. 30, the RTC device 154 generates one or a plurality of divided frequencies by dividing the oscillation frequency oscillated by the oscillator by a “designated division ratio” designated in advance (S3001). By this frequency division frequency generation processing, the production timing determination frequency used for production and the unit frequency used for updating the unit time are produced.

  When one or a plurality of frequency division frequencies are generated in this way, the RTC device 154 determines the production timing determination frequency division of the first frequency division frequency that is designated in advance as a frequency used for production from the generated frequency division frequency. A frequency is specified (S3002). In the example shown above, the frequency division frequency of “4096 Hz” is set as the production timing determination frequency division frequency.

  Similarly, the RTC device 154 specifies a unit frequency division frequency of the second frequency division frequency that is designated in advance as a frequency used for production from the generated frequency division frequency (S3003). In the example shown above, the frequency division frequency of “1 Hz” is set as the unit frequency division.

  Subsequently, the RTC device 154 starts from the timing at which the specified production timing determination frequency is divided (measures the cycle), and after that timing, similarly to the cycle of the specified unit frequency (period). The frequency division delay time, which is a period until the timing is measured, is detected, and at the start timing of the frequency division delay time, the CE signal is activated and is in an active state, and processing for input / output of time information is performed. It is determined whether or not it is in a valid state (S3004).

  First, when it is determined by this determination process that the process for inputting / outputting time information is valid at the start timing of the division delay time (YES in S3004), the RTC device 154 determines the time information used for the game. Is temporarily suspended by setting an access hold identification flag (S3005).

  In other words, when it is determined that the processing for inputting / outputting time information is valid by receiving the CE signal, the RTC device 154 may make an input / output request for time information from the liquid crystal control CPU 150a. At the same time, since the division delay time is detected, the time information is updated at the end timing of the division delay time.

  Therefore, when these timings overlap, stable operation of time information update and time information input / output processing may be hindered. For this reason, the RTC device 154 temporarily holds the update of the time information used for the game by setting the access hold identification flag.

  In this way, in the temporarily suspended state, the RTC device 154 subsequently determines whether or not the active state has been canceled and the state has been changed to the inactive state (S3006).

  Until this determination process determines that the active state has been released and the state has been changed to the inactive state (NO in S3006), the standby state is set, and the active state is released and the state is changed to the inactive state. If it is determined that it has been lost (YES in S3006), the RTC device 154 updates the temporarily held time information (S3007).

  Next, in the determination process (S3004), at the start timing of the frequency division delay time, the CE signal is validated and is in an active state, and the process for inputting / outputting time information is valid. If it is not determined at the start timing of the frequency division delay time that the process for inputting / outputting time information is valid (NO in S3004), the RTC device 154 continues the detected frequency division delay time continuously. By receiving the CE signal, it is determined whether the use of time information is not enabled (S3008).

  If it is determined that the use of the time information is not activated (YES in S3008), the RTC device 154 updates the time information at the timing of measuring the unit period of the unit divided frequency (S3009).

  In this case, since the use of the time information is not validated, the RTC device 154 does not accept the input / output request of the time information from the liquid crystal control CPU 150a within the division delay time. Therefore, the RTC device 154 updates the time information.

  Next, in the determination process (S3008), whether or not the use of time information is not enabled by receiving the CE signal continuously for the detected divided delay time, the end timing of the divided delay time If the RTC device 154 determines that the use of time information is enabled (NO in S3008), the RTC device 154 changes the state from the state where the CE signal is not enabled to the enabled state. A timing control process for controlling the state change timing is performed (S3010).

  A detailed flow of the timing control process is shown in FIGS. 31 to 33 and will be described later.

  Then, the RTC device 154 that has performed the timing control process updates the time information at the timing of measuring the unit period of the unit frequency division frequency (S3009).

  In this case, the timing change process sets the state change timing of the state change from the state where the CE signal is not enabled to the enabled state to a time other than the division delay time. In addition, the RTC device 154 does not accept an input / output request for time information from the liquid crystal control CPU 150a, and the time information can be updated stably.

  FIG. 31 is a flowchart showing a detailed flow of timing control processing constituting main processing performed in the RTC device 154 shown in FIG.

  In FIG. 31, the RTC device 154 determines that the CE signal is enabled and in an active state at the start timing of the division delay time, and that processing for inputting and outputting time information is enabled. Thus, the process is started when it is determined that the use of time information is enabled at the end timing of the frequency division delay time.

  First, in the RTC device 154, input / output of time information from an inactive state in which input / output of time information is not enabled by receiving a CE signal at a predetermined timing based on a cycle of a specified frequency specified in advance. A state change timing for changing the state to the activated active state is set (S3101). The detailed flow of this setting process is shown in FIGS.

  The designated frequency designated in advance at this time is either the production timing determination divided frequency or the unit divided frequency shown above, and the use of any one of these divided frequencies is registered as setting information. Then, the state change timing is set using the frequency dividing frequency registered as the setting information.

  In addition to this, the designated frequency may be designated in association with a processing element (processing means) that realizes timing control processing in the RTC device 154. The processing element at this time is a type of software and hardware when the timing control process is realized by software such as a program and when it is realized using hardware such as an IC circuit.

  As described above, when the state change timing is set, the RTC device 154 sets the timing at which the input / output of time information is enabled by the CE signal to the state change release timing that makes the state inactive. (S3102).

  FIG. 32 is an example of a flowchart showing a detailed flow of the state change timing setting process shown in FIG.

  The process for setting the state change timing in FIG. 32 is a process for changing to the state change timing shown in the time chart shown in FIG.

  In this process, after the start timing of the frequency division delay time, the production timing determination frequency division first specifies the timing for measuring the half cycle (S3201). Then, the specified timing is set as a state change timing for changing the state to an active state that enables processing in input / output of time information (S3202).

  FIG. 33 is another example of a flowchart showing a detailed flow of the state change timing setting process shown in FIG.

  The process for setting the state change timing in FIG. 33 is a process for changing to the state change timing shown in the time chart shown in FIG.

  In this process, after the start timing of the frequency division delay time, the timing at which the oscillation frequency as the original oscillation first measures a half cycle is specified (S3301). Then, the specified timing is set as a state change timing for changing the state to an active state that enables processing in input / output of time information (S3202).

  FIG. 34 is a flowchart showing a detailed flow of time information output processing performed by the RTC device 154 included in the gaming machine according to the embodiment of the present invention.

  In FIG. 34, the RTC device 154 determines whether or not an access request for time information has been made from the liquid crystal control CPU 150a (S3401). This is processing for determining whether or not an access request for time information is made from the liquid crystal control CPU 150a via the data input signal line in the data communication unit 154c in the block configuration diagram of the RTC device 154 shown in FIG.

  Until the access request is made (NO in S3401), the RTC device 154 is in a standby state, and when determining that the access request has been made (YES in S3401), the RTC device 154 continues to produce the effect timing determination frequency division frequency (first frequency division). It is determined whether or not (frequency) is enabled (S3402).

  If it is not determined that the production timing determination frequency division frequency (first frequency division frequency) is enabled (NO in S3402), the RTC device 154 subsequently enables the CE state verification pulse (S3403), and the oscillator The system waits for one period (unit period) at the oscillation frequency to be oscillated (S3404). If it is determined that the production timing determination frequency division frequency (first frequency division frequency) is activated (YES in S3402), the process waits until it is determined that it is not activated.

  By this standby processing, the timing of time update can be surely shifted from the frequency division delay time shown above, and normal operation can be ensured at a high level.

  Subsequently, when waiting for a time corresponding to one cycle at the oscillation frequency, the RTC device 154 outputs time information to the liquid crystal control CPU 150a (S3405), and determines whether or not the access request is completed (S3406).

  FIG. 35 is a block diagram showing a detailed configuration of the liquid crystal control CPU 150a included in the gaming machine according to the embodiment of the present invention.

  35, the liquid crystal control CPU 150a includes a liquid crystal control unit 160, a CE signal output unit 161, a timing adjustment unit 162, a storage unit 163, and a data input / output control unit 164.

  Also by applying this configuration to the liquid crystal control CPU 150a, the RTC device 154 can receive the CE signal from the liquid crystal control CPU 150a during the frequency division delay time and avoid updating the time information.

  In other words, in order to avoid the time information update performed by the RTC device 154 receiving the CE signal from the liquid crystal control CPU 150a during the division delay time, the timing control process performed by the RTC device 154 described above is exclusive. This shows that it is possible to perform processing with the configuration shown in FIG.

  The liquid crystal control unit 160 is a main control process in the liquid crystal control CPU 150a and creates a display list based on the “effect pattern designation command” received from the effect control board 120 as described above, and this display list is displayed as VDP2000. Display control processing for displaying the image data stored in the CGROM 151 on the first liquid crystal display device 31 and / or the second liquid crystal display device 37.

  The CE signal output unit 161 generates a CE signal (chip enable signal) when inputting / outputting time information timed by the RTC device 154. This CE signal is a signal (validation signal) that activates (sets to an active state) to select the RTC device 154, and the CE signal output unit 161 converts the CE signal into the RTC Output to the device 154.

  When the timing adjustment unit 162 is notified that the CE signal is output from the CE signal output unit 161 (after the oscillation timing of the signal in which the use of the game specified time information is enabled), the data input / output The control unit 164 performs processing for adjusting the output timing of data output to the RTC device 154 (a clock signal used for serial communication and a signal input to the RTC device 154).

  The timing adjustment unit 162 adjusts the output timing based on the delay time stored in the storage unit 163 after the CE signal output unit 161 outputs the CE signal to the RTC device 154.

  The delay time stored in the storage unit 163 at this time is, for example, the following information.

  As a first example of this delay time, the same information as the delay time (first delay time or second delay time) stored in the time information storage unit 154j of the RTC device 154 is used.

  Further, as a second example, it is a time required for a unit period of a frequency division frequency used for specifying an oscillation frequency or a frequency division delay time oscillated from an oscillator of the RTC device 154. In the second example, a time calculated by adding the time of the pulse width of the CE signal may be used.

  The data input / output control unit 164 transmits time information request information to the RTC device 154 based on the time information acquisition request from the liquid crystal control unit 160. In the example shown in FIG. 35, since the connection form in the serial communication is shown, the data input / output control unit 164 sends the time information request information to the data input signal in synchronization with the rising timing of the clock signal indicated by CLK. The data is transmitted to the RTC device 154 using a line (DI).

  The data input / output control unit 164 receives time information output from the RTC device 154 using a data output signal line (DO), and responds to the liquid crystal control unit 160 with the time information.

  Accordingly, the liquid crystal control unit 160 performs control processing for displaying image data using the received time information.

  In the above example, the data input / output control unit 164 receives time information from the RTC device 154 by using the data output signal line (DO). However, in addition to this, the data output signal line (DO) ) To receive delay time information from the RTC device 154.

  When the delay time information is received from the RTC device 154, the data input / output control unit 164 stores the delay time information in the storage unit 163.

  The timing adjustment unit 162 performs a process of adjusting the output timing using the delay time stored by the data input / output control unit 164.

  FIG. 36 is a configuration block diagram of timing control processing performed in the gaming machine according to the embodiment of the present invention.

  FIG. 36 shows a liquid crystal control CPU 150a, an RTC device 154, and a delay control device 155. The delay control device 155 includes a flip-flop circuit and the like, and is output from the liquid crystal control CPU 150a. After the received CE signal is received and subjected to delay control processing, a CEq signal corresponding to the CE signal is output from the “Q (queue)” terminal to the RTC device 154 as a CE signal.

  That is, the delay control device 155 delays the CE signal reception timing in the RTC device 154 by a predetermined time from the timing at which the CE signal is output from the liquid crystal control CPU 150a and the RTC device 154 receives the CE signal. Process.

  More specifically, the delay control device 155 receives the CE signal output from the liquid crystal control CPU 150a at the D terminal shown in FIG. 36, and receives this CE signal at the “/ CLR (clear bar)” terminal to receive the D signal. Clear (cancel) the signal input from the terminal.

  Subsequently, the delay control device 155 receives an output signal having the same frequency as the oscillation frequency (32768 Hz) from the RTC device 154 at the “CLK” terminal. This output signal is a signal having the same phase as the frequency (32768 Hz) of the internal signal. That is, the output signal and the internal signal are in a synchronized state. Note that a signal line is not connected to the “/ PRE (prebar)” terminal and the “/ Q (cuber)” terminal that give initial signal values.

  Upon receiving such a signal, the delay control device 155 latches the CE signal at the rising timing in the pulse waveform of the output signal. Then, the delay control device 155 inputs the CEq signal, which is an output signal after latching, to the RTC device 154 as a CE signal.

  In other words, the delay control device 155 synchronizes the input timing of the CEq signal to the RTC device 154 using the output signal input from the RTC device 154, and sends the input signal as the CE signal to the RTC device 154. Will be entered.

  As a result, the output timing at which the CE signal is output from the liquid crystal control CPU 150a is delayed by a time corresponding to one cycle or half of the pulse waveform of the output signal.

  The rise at this time indicates a state in which the value in the pulse waveform has reached the specified upper limit value instantaneously, and accordingly, the rise timing indicates the timing at which the value reaches the upper limit value. The term “fall” refers to a state in which the value in the pulse waveform has instantaneously reached the designated lower limit value, and the term “fall timing” refers to the timing at which this value has reached this lower limit value.

  FIG. 37 is a flowchart showing a detailed flow of processing performed in the delay control device 155 shown in FIG.

  In FIG. 37, the delay control device 155 detects this when receiving an input of an output signal output from the RTC device 154 and having the same frequency as the internal signal (S3701).

  Subsequently, the delay control device 155 latches the CE signal at the rising timing in the pulse waveform of the detected output signal (S3702). As described above, this latch process is a process in which the delay control device 155 synchronizes the input timing of the CEq signal to the RTC device 154 using the output signal input from the RTC device 154.

  Then, the delay control device 155 outputs the CEq signal delayed by one cycle or half cycle by latch processing to the RTC device 154 as a CE signal (S3703).

  FIG. 39 is a diagram illustrating an example of a timing chart describing the relationship between the specific effect mode and the symbol variation.

  The symbol variation at this time indicates that the effect symbol used in the jackpot lottery process is in a state where it has fluctuated (lottery process state).

  First, the case where the symbol variation starts during the normal game effect mode and the symbol variation ends during the performance announcement mode will be described.

  FIG. 39 (a) shows an example of effect display when the symbol variation starts during the normal game effect mode and the symbol variation ends during the performance announcement mode.

  As shown in FIG. 39 (a), the liquid crystal control CPU 150a of the gaming machine performs symbol variation display by starting symbol variation during the normal game effect mode.

  In the normal symbol variation display, the liquid crystal control CPU 150a displays, for example, a variation display of the effect symbol 38, an effect display screen for variation, and the like. And liquid crystal control CPU150a continues the effect display in the symbol change until then even if it becomes the start time of performance announcement mode during normal symbol change.

  Also, the liquid crystal control CPU 150a notifies the performance control board 120 that the performance notification mode has been entered when the start time of the performance notification mode is reached. The performance control board 120 changes the performance display after the next change to the performance display in the performance notification mode in the specific performance mode by the notification in the performance notification mode. Here, the performance announcement mode effect display in the specific effect mode is an effect by the variation effect pattern determined by the variation effect pattern determination table for the specific effect mode.

  Next, the liquid crystal control CPU 150a divides the display screen area into an upper large screen area and a lower small screen area when the symbol variation ends during the performance announcement mode and the next symbol variation starts.

  The liquid crystal control CPU 150a displays the variation image by the variation effect pattern for the lower small screen area selected on the effect control board 120 in the lower small screen area. Further, the liquid crystal control CPU 150a displays a notification screen indicating that the music performance mode is about to start in the upper large screen area. For example, as shown in FIG. 39 (a), the notification screen displays the name of the music performed in the music performance mode, the countdown of the time until the music performance mode is started, and the like.

  Further, the liquid crystal control CPU 150a displays the time for which the counter is down on the notification screen based on the presentation time information stored in the liquid crystal control RAM 150b.

  Next, the liquid crystal control CPU 150a displays live video, video video, promotional video, etc. in the music performance mode in the upper large screen area when the symbol change does not end during the performance announcement mode and the start time of the music performance mode is reached. To do. Further, the liquid crystal control CPU 150a continuously displays the display screen showing the symbol variation in the lower small screen region only by the variation display of the effect symbol 38 or the like.

  Further, when the start time of the music performance mode is reached, the liquid crystal control CPU 150a notifies the effect control board 120 that the start time of the music performance mode has been reached. The effect control board 120 changes the effect display after the next change to the effect display for the music performance mode in response to the start notification of the music performance mode.

  Here, the effect display for the music performance mode is the same as the effect display in the performance notification mode. In this embodiment, the effect display for the music performance mode and the effect display for the performance announcement mode are the same, but the effect display for the music performance mode and the effect display of the performance announcement mode , May be different.

  Furthermore, when the end time of the music performance mode, that is, the end time of the specific effect mode is reached, the liquid crystal control CPU 150a notifies the effect control board 120 that the end time of the specific effect mode is reached. The effect control board 120 changes the effect display after the next change to the effect display for the normal game effect mode in response to the end notification of the specific effect mode.

  Next, a case where the symbol variation starts during the normal game performance mode, continues through the performance notification mode, and continues to the music performance mode will be described.

  FIG. 39B shows an effect display example in the case where the symbol variation starts during the normal game performance mode, and the symbol variation continues through the performance notification mode until the music performance mode.

  As shown in FIG. 39 (b), the liquid crystal control CPU 150a of the gaming machine 1 displays the symbol variation display in the same manner as in FIG. 39 (a) when the symbol variation is started during the normal game effect mode. Do. And even if it becomes the start time of performance notification mode during normal symbol fluctuation, liquid crystal control CPU150a continues the effect display in the symbol fluctuation until then.

  In addition, when the start time of the performance notification mode is reached, the liquid crystal control CPU 150a notifies the effect control board 120 that the start time of the performance notification mode has been reached, as described above. The production control board 120 changes the production display after the next change to the production display for the performance announcement mode (specific production mode) by the start notification of the performance announcement mode. However, in this example, the next change is not started during the performance notification mode, and the music performance mode is entered.

  Next, the liquid crystal control CPU 150a, when the symbol variation does not end during the performance announcement mode and the start time of the music performance mode comes, the display screen area is divided into a full-screen large screen area and a small window reduction screen (so-called “so-called window reduction screen”). , Wipe screen) and area. The liquid crystal control CPU 150a displays the symbol variation continuously on the entire large screen area. Further, the liquid crystal control CPU 150a displays a live video, a video video, a promotion video, etc. in the music performance mode in the small window reduction screen area.

  Furthermore, when the start time of the music performance mode is reached, the liquid crystal control CPU 150a notifies the effect control board 120 that the start time of the music performance mode has been reached, as described above. The effect control board 120 changes the effect display after the next change to the effect display for the music performance mode (specific effect mode) in response to the start notification of the music performance mode.

  Next, the liquid crystal control CPU 150a, when the symbol variation ends during the music performance mode and starts the next symbol variation, the display screen area is divided from the entire large screen area and the small window reduced screen area, Change to splitting the upper large screen area and lower small screen area. The liquid crystal control CPU 150a displays a display screen showing the next symbol variation in the lower small screen area. In addition, the liquid crystal control CPU 150a displays live video, video video, promotion video, etc. in the music performance mode in the upper large screen area.

  Furthermore, when the end time of the music performance mode, that is, the end time of the specific effect mode is reached, the liquid crystal control CPU 150a notifies the effect control board 120 that the end time of the specific effect mode is reached. The effect control board 120 changes the effect display after the next change to the effect display for the normal game effect mode in response to the end notification of the specific effect mode.

  Next, the symbol variation starts during the normal game production mode, continues through the performance announcement mode, and continues until the music performance mode. However, the symbol variation may be performed in multiple productions (for example, reach production, advanced reach production, special reach). A case will be described in which there is an effect boundary during design variation. In FIG. 39 (c), the symbol variation starts during the normal game performance mode, and the symbol variation continues through the performance notification mode and continues to the music performance mode. However, a boundary of performance occurs in the performance notification mode. In this case, an effect display example is shown.

  As shown in FIG. 39 (c), the liquid crystal control CPU 150a of the gaming machine 1 is the same as in FIG. 39 (a) and FIG. 39 (b) when the symbol change is started during the normal game effect mode. Next, the symbol variation display is performed.

  And even if it becomes the start time of performance notification mode during normal symbol fluctuation, liquid crystal control CPU150a continues the effect display in the symbol fluctuation until then.

  In addition, when the start time of the performance notification mode is reached, the liquid crystal control CPU 150a notifies the effect control board 120 that the start time of the performance notification mode has been reached, as described above. The production control board 120 changes the production display after the next change to the production display for the performance announcement mode (specific production mode) by the start notification of the performance announcement mode. However, in this example, the next change is not started during the performance notification mode, and the effect display is not changed by the effect control board 120.

  Next, the liquid crystal control CPU 150a divides the display screen area into an entire large screen area and a small window reduction screen area when there is a production boundary in the symbol variation during the performance announcement mode. The liquid crystal control CPU 150a displays the symbol variation continuously on the entire large screen area. In addition, the liquid crystal control CPU 150a displays a notification screen that the music performance mode is about to start in the small window reduction screen area.

  Next, the liquid crystal control CPU 150a continues the split display of the entire large screen area and the small window reduced screen area when the symbol variation does not end during the performance announcement mode and the start time of the music performance mode is reached. . Then, the liquid crystal control CPU 150a displays the symbol variation continuously on the entire large screen area. Further, the liquid crystal control CPU 150a displays a live video, a video video, a promotion video, etc. in the music performance mode in the small window reduction screen area. Therefore, the music performance is displayed in a reduced size.

  Furthermore, when the start time of the music performance mode is reached, the liquid crystal control CPU 150a notifies the effect control board 120 that the start time of the music performance mode has been reached, as described above. The effect control board 120 changes the effect display after the next change to the effect display for the music performance mode (specific effect mode) in response to the start notification of the music performance mode.

  Next, the liquid crystal control CPU 150a, when the symbol variation ends during the music performance mode and starts the next symbol variation, the display screen area is divided from the entire large screen area and the small window reduced screen area, Change to splitting the upper large screen area and lower small screen area.

  The liquid crystal control CPU 150a displays a display screen showing the next symbol variation in the lower small screen area. In addition, the liquid crystal control CPU 150a displays live video, video video, promotion video, etc. in the music performance mode in the upper large screen area.

  Furthermore, when the end time of the music performance mode, that is, the end time of the specific effect mode is reached, the liquid crystal control CPU 150a notifies the effect control board 120 that the end time of the specific effect mode is reached. The effect control board 120 changes the effect display after the next change to the effect display for the normal game effect mode in response to the end notification of the specific effect mode.

  Next, a case will be described in which the performance notification mode is entered in the state where the symbol variation is not in the normal game performance mode, the symbol variation occurs during the performance notification mode, and the program performance mode continues.

  FIG. 39 (d) shows an example of an effect display in the case where the performance change mode is entered while the design variation is not in the normal game performance mode, and the design variation occurs during the performance notification mode and continues until the music performance mode. Indicates.

  As shown in FIG. 39 (d), the liquid crystal control CPU 150a of the gaming machine 1 has the display screen area as the upper large screen area and the lower large screen area when there is no symbol variation display and the start time of the performance announcement mode is reached. Divide into small screen area.

  The liquid crystal control CPU 150a displays a notification screen that the music performance mode is about to start in the upper large screen area. Similarly to the above, the liquid crystal control CPU 150a displays the time to count down on the notification screen based on the presentation time information stored in the liquid crystal control RAM 150b.

  In addition, the liquid crystal control CPU 150a displays the effect symbol 38 stopped and displayed in the previous variation display in the lower small screen area. At this time, the effect design 38 displayed in the lower small screen area is displayed as a simplified dot display image or the like.

  In addition, when the start time of the performance notification mode is reached, the liquid crystal control CPU 150a notifies the effect control board 120 that the start time of the performance notification mode has been reached, as described above. The production control board 120 changes the production display after the next change to the production display for the performance announcement mode (specific production mode) by the start notification of the performance announcement mode.

  Next, the liquid crystal control CPU 150a continues the divided display of the upper large screen area and the lower small screen area when the symbol variation occurs during the performance announcement mode. The liquid crystal control CPU 150a displays a display screen showing the symbol variation in the lower small screen area.

  In addition, the liquid crystal control CPU 150a continuously displays a notification screen that the music performance mode is about to start in the upper large screen area. Also at this time, similarly to the above, the liquid crystal control CPU 150a displays the time for counting down on the notification screen based on the effect time information stored in the liquid crystal control RAM 150b.

  Next, the liquid crystal control CPU 150a continues the split display of the upper large screen area and the lower small screen area when the symbol variation does not end during the performance announcement mode and the start time of the music performance mode is reached. The liquid crystal control CPU 150a continues the symbol variation display in the lower small screen area. In addition, the liquid crystal control CPU 150a displays live video, video video, promotion video, etc. in the music performance mode in the upper large screen area.

  Furthermore, when the start time of the music performance mode is reached, the liquid crystal control CPU 150a notifies the effect control board 120 that the start time of the music performance mode has been reached, as described above. The effect control board 120 changes the effect display after the next change to the effect display for the music performance mode (specific effect mode) in response to the start notification of the music performance mode.

  Furthermore, when the end time of the music performance mode, that is, the end time of the specific effect mode is reached, the liquid crystal control CPU 150a notifies the effect control board 120 that the end time of the specific effect mode is reached. The effect control board 120 changes the effect display after the next change to the effect display for the normal game effect mode in response to the end notification of the specific effect mode.

  As described above, the gaming machine 1 enters the music performance mode at the predetermined time based on the presentation time information stored in the liquid crystal control RAM 150b, and displays live video, video video, promotional video, and the like.

  FIG. 41 shows a state in which a plurality of gaming machines are arranged in a single horizontal row across the passage.

  By adopting the configuration as described above, the same specific effects (standby effect (performance announcement effect), music performance effect) are performed at the same time when the gaming machines enter the specific effect mode substantially simultaneously. That is, the same video is displayed and the same sound data is notified.

  Thereby, it is felt that each gaming machine is performing a specific effect in conjunction with each other, and an effect with a sense of unity is possible.

  The embodiment described above is one embodiment of the present invention, and is not limited to these examples, and can be implemented with appropriate modifications within a range not changing the gist thereof.

1 gaming machine 150 image control board 150a liquid crystal control CPU
150b Liquid crystal control RAM
150c LCD control ROM
150d first counter (frame counter)
151 CGROM
152 Crystal Oscillator 153 VRAM
154 Second counting device (RTC device)
154a I / F circuit 154b CE signal transmission / reception unit 154c Data communication unit 154d Oscillator 154e Frequency division control unit 154f CE signal reception state determination unit 154g Time information update hold control unit 154h Time information update processing unit 154i Storage control unit 154j Time information storage unit 154k timing control processor

Claims (3)

A time control unit that performs time control of game designated time information used in the game;
A display control unit that performs display control of an effect image used for the effect in the game using the game designation time information time-controlled by the time control unit, and
The timing control unit is
A frequency dividing frequency generating means for generating a frequency divided by dividing the oscillation frequency by oscillating an oscillation frequency used for updating the game designation time information related to the game by an oscillator;
The first divided frequency out of the divided frequencies divided by the divided frequency generation means and the first divided frequency after the first divided frequency is generated are different from the first divided frequency. From a state where the use of the game designated time information is not validated to a state where the use of the game designated time information is validated at a time other than the frequency division delay time until the second divided frequency is generated. State change timing setting means for setting the state change timing to be changed, and
The display control unit
Based on the oscillation frequency or the division frequency that specifies the division delay time used for setting the state change timing by the state change timing setting means, the input / output of game designation time information time-controlled by the time-control unit A gaming machine comprising timing adjustment means for adjusting timing. The timing adjusting means includes
The timing for reading out the game designation time information is adjusted after the time required for the unit period of the oscillation frequency oscillated by the oscillator has elapsed from the oscillation timing of the signal in which use of the game designation time information is enabled. Item 1. The gaming machine according to Item 1. The timing adjusting means includes
3. The read timing of the game specified time information is adjusted after elapse of a time obtained by adding a cycle time of a signal that makes the use of the game specified time information valid to a unit cycle time of the oscillation frequency. The gaming machine described.

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