JP2014107769A - Sub-ranging a/d converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To implement higher precision and higher speed without adding to circuit scale and current consumption.SOLUTION: A sub-ranging A/D converter includes: a voltage-current converter array 400 for generating currents sized and polarized in accordance with differential voltages between an input voltage and reference voltages used in a flash type upper bit deciding A/D converter for deciding upper M bits; a current switch array 500 for selectively additively outputting the output currents of two or more voltage-current converters of the voltage-current converter array in accordance with a combination of output values of a plurality of voltage comparators used in the upper bit deciding A/D converter; and a lower bit deciding A/D converter 700 for receiving the addition current of the current switch array to generate a code of lower L bits.

Description

  The present invention relates to a sub-ranging A / D converter that achieves higher accuracy and higher speed without increasing circuit scale and current consumption.

  In order to achieve high-speed A / D conversion, an A / D converter having a configuration as shown in FIG. 16 generally called a flash type is often used. This is because when an N-bit output digital signal is obtained, the voltage comparator array 20 composed of a plurality of voltage comparators arranged in parallel is moved simultaneously, and the input voltage Vin input to the input terminal 1 and the voltage terminal By comparing simultaneously a plurality of reference voltages generated by the resistor array 10 connected between the voltage Vref + of 2 and the voltage Vref− of the voltage terminal 3, which reference voltage is near the input voltage Vin. Information is obtained and input to the encoder 30 for determination and converted into an N-bit digital signal.

  However, since this flash type configuration is difficult to achieve highly accurate A / D conversion, when it is made highly accurate, a sub-ranging type A / D converter as shown in FIG. Used. This is the first flash A / D converter (resistor array 10A, voltage comparator array 20A, M-bit digital signal) having the same configuration as in FIG. It is determined by the upper bit encoder 30A). Then, a lower L-bit digital signal is generated by the second flash A / D converter.

  In the second flash type A / D converter, one divided resistor group 10B1 in the resistor array 10B is selected by the voltage selector 40 in accordance with the upper M-bit digital signal, and generated by the selected divided resistor array 10B1. Each sub-reference voltage and the input voltage Vin captured by the sampling hold circuit 50 are compared by each voltage comparator of the voltage comparator array 20B, and the comparison result is captured by the lower bit encoder 30B. A bit digital signal is generated.

  According to this, for example, in order to produce an A / D converter having a resolution of 12 bits, it is only necessary to prepare two flash A / D converters having a resolution of 6 bits. It is possible to dramatically reduce the number of vessels.

  However, this sub-ranging A / D converter selects one divided resistor array 10B1 from the resistor array 10B in the second flash A / D converter, and each voltage comparator of the voltage comparator array 20B. It takes time to apply a reference voltage to the circuit, and speeding up is difficult.

  In order to solve this problem, there is a prior patent such as Patent Document 1. This is because the reference voltage applied to the voltage comparator array 20B of the second flash type A / D converter is precharged to a voltage close to that in advance, thereby reducing the time required for the reference voltage to settle. It is to reduce.

  Further, as another method of the sub-ranging A / D converter, a configuration as described in Non-Patent Document 1 has been proposed. This is to select one of the voltage amplifiers having different input offsets according to the determined upper bit, and to generate the input voltage of the second A / D converter that determines the lower bit. is there. In this case, there is no need to distribute the reference voltage to the second A / D converter for determining the lower bits, which is required in the conventional sub-ranging type. There is no need to arrange the vast number of reference voltages required for the sub-ranging type and the large resistor array to generate them. The present invention is based on the technology of Non-Patent Document 1 and proposes further improvements.

JP 2009-182513 A

P. Low “A Fully Differential, Vretically Structured and Compensated Subranging A / D-Converter” IMTC'94 May 10-12, Hamamatsu, pp890-893

The problems of the prior art introduced above will be explained one by one below. First, in the flash type A / D converter as shown in FIG. 16, for example, in order to make an A / D converter with a resolution of 8 bits, 2 ⁸ −1 (= 255) different reference voltages and It is necessary to prepare 255 voltage comparators corresponding thereto. When the resolution is further increased, the number of necessary voltage comparators increases exponentially. For this reason, it is very difficult to achieve high accuracy under the demand for limited circuit scale and power consumption. Further, in order to achieve high accuracy, it is necessary to make the input conversion offset allowed for the voltage comparator very small, so that high accuracy is further difficult from this aspect.

  Further, in the conventional sub-ranging type A / D converter as shown in FIG. 17, the second flash type A / D converter for determining the lower bits differs depending on the determined upper bits. It is necessary to apply a reference voltage every sampling period. For this reason, considering the settling time of the reference voltage, there is a problem that the sampling period cannot be shortened and it is difficult to increase the speed.

  Although Patent Document 1 is a technique that satisfies the above two requirements of high accuracy and high speed at the same time, the precharge of the reference voltage applied to the second flash A / D converter for determining the lower bits is performed. Therefore, additional circuit components such as a track hold circuit are required. Even if the reference voltage is precharged, the settling time constant of the reference voltage itself is not shortened, so that the A / D converter cannot be operated at a higher speed than the time constant of the reference voltage generation unit.

  The configuration described in Non-Patent Document 1 as another sub-ranging type method is that the window amplifiers in Fig. 1 in the document drive an A / D converter for determining the lower bits of the subsequent stage at high speed. Driving force is necessary to In addition, only a very small input offset error is allowed in order to accurately determine the lowest bit of the lower bit.

  That is, for example, when it is desired to achieve a resolution of 12 bits in total of the upper 6 bits and the lower 6 bits, 64 window amplifiers are required, and the size of each window amplifier depends on the relationship between the driving power and the input offset accuracy. , Become very big. For this reason, it is quite difficult to achieve a circuit scale and power consumption that are permitted as a system-on-chip IP core.

  An object of the present invention is to provide a sub-ranging A / D converter that can achieve higher accuracy and higher speed without increasing the circuit scale and current consumption.

In order to achieve the above object, the invention according to claim 1 is directed to a first reference voltage generation circuit that generates a plurality of different first reference voltages that are separated by the same voltage difference, and the first reference voltage generation. A voltage comparator array comprising a plurality of voltage comparators for comparing the plurality of individual first reference voltages generated by the circuit and an input voltage; and an output value of the plurality of voltage comparators is fetched to determine the number of bits. A high-order bit determination A / D converter comprising a high-order bit encoder for generating a high-order bit code of M (M is an integer of 2 or more), a plurality of different second reference voltages spaced apart by the same voltage difference A second reference voltage generation circuit for generating a plurality of second reference voltages generated from the second reference voltage generation circuit and the input voltage and a magnitude corresponding to the difference voltage Generate multiple currents of polarity A voltage-current converter array composed of voltage-current converters and an output current of two or more voltage-current converters of the plurality of voltage-current converters are selected according to a combination of output values of the plurality of voltage comparators. A low-order bit analog signal generation circuit including a current addition circuit that adds and outputs the low-order bit analog signal generation circuit generated by the low-order bit analog signal generation circuit. Is an A / D converter for determining a lower bit that generates a code of lower bits of 2).
According to a second aspect of the present invention, in the subranging A / D converter according to the first aspect, between the individual output sides of the plurality of voltage-current converters and the input side of the current adder circuit, Or inserted between the output side of the current adder circuit and the input side of the A / D converter for lower bit determination, and the input current is supplied to the first holding means and the first When the current is input to the first holding means, the current is output from the second holding means, and when the current is input to the second holding means, the second holding means alternately holds the second holding means. And a current sample and hold circuit for outputting a current from one holding means.
According to a third aspect of the present invention, in the subranging A / D converter according to the first or second aspect, the second reference voltage generation circuit is provided in common or independently with the first reference voltage generation circuit. And a sub-reference voltage generation unit for generating K sub-reference voltages obtained by dividing each voltage of the second reference voltage into K pieces (K is a positive integer equal to or greater than 2), The device is composed of K sub-voltage / current converters to which the sub-reference voltage is input and whose outputs are commonly connected.
According to a fourth aspect of the present invention, in the subranging A / D converter according to the first, second, or third aspect, the number of the two or more voltage-current converters selected so that the output current is added is externally set. A setting circuit for setting is provided.
According to a fifth aspect of the present invention, in the subranging A / D converter according to the first, second, third, or fourth aspect, the A / D converter for lower bit determination is redundant with respect to the number of bits L. A bit is set.

  According to the present invention, a plurality of voltage-current converters are arranged, and from among the plurality of voltage-current converters, two or more voltage-current converters that drive the A / D converter for determining a lower bit are selected, Since the output currents are summed to drive the A / D converter for lower bit determination, the speed can be increased. Further, since the output currents of two or more voltage-current converters are added, the offsets of the individual voltage-current converters can be averaged, and high accuracy can be effectively achieved. In addition, by expanding the allowable input voltage range of the voltage-current converter, in principle, the output current of a considerable number of voltage-current converters can be merged to drive the A / D converter for lower bit determination. High speed and high accuracy can be achieved. In addition, a plurality of voltage-current converters are inevitably provided for constructing a sub-ranging A / D converter, and in a circuit that has to be newly added for higher accuracy. Absent. Therefore, an increase in area due to an increase in voltage-current converters does not occur.

It is a block diagram for explaining the principle of the sub-ranging A / D converter of the present invention. It is a block diagram for explaining the principle of the sub-ranging A / D converter of the present invention that handles differential input signals. It is a block diagram of the sub-ranging type A / D converter of the 1st example of the present invention. It is explanatory drawing of the voltage generation for the low-order bits of the subranging type A / D converter of FIG. It is a block diagram of the subranging type A / D converter of the 2nd example of the present invention. FIG. 6 is an explanatory diagram of voltage generation for lower bits of the sub-ranging A / D converter of FIG. 5. FIG. 6 is an explanatory diagram of voltage generation for lower bits of the sub-ranging A / D converter of FIG. 5. It is explanatory drawing of a voltage-current converter. It is explanatory drawing of the voltage-current converter which extended the differential input voltage range. It is explanatory drawing of the voltage-current converter which further extended the differential input voltage range. It is a circuit diagram of the voltage-current converter which connected the preamplifier in the front | former stage. It is a circuit diagram of the voltage-current converter which enabled the output common current to be 0. It is a circuit diagram of the voltage-current converter which added the offset adjustment function. It is. It is a circuit diagram of a current sample and hold circuit. It is a circuit diagram of a switch selection signal generation circuit. It is a block diagram of a conventional flash type A / D converter. It is a block diagram of a conventional sub-ranging A / D converter.

  The present invention provides a plurality of voltage currents having the same transconductance, in which an input voltage and a different reference voltage are connected to a generation circuit portion of an analog signal for lower bits input to an A / D converter for lower bit determination. Arrange the transducers in an array. Then, according to the combination of the output values of the individual voltage comparators in the voltage comparator array, the output currents of two or more voltage-current converters of the plurality of voltage-current converters are selected and added, and this is subordinated The analog signal for bits is input to the A / D converter for lower bit determination. As a result, more accurate and faster A / D conversion is achieved without increasing the circuit scale and current consumption.

  Thus, by using the output currents of two or more voltage-current converters for driving the A / D converters for determining the lower bits at the same time, the lower-order bits among the currents consumed by all the voltage-current converters It is possible to increase the rate of current consumption actually used to drive the decision A / D converter. That is, the A / D converter for lower bit determination can be driven at higher speed.

  Also, by adding the output currents of two or more voltage-current converters, the input conversion offset of each voltage-current converter can be effectively averaged, and the input offset accuracy required for each voltage-current converter Can be loosened.

  Also, when configuring one voltage-current converter by combining a plurality of sub-voltage-current converters, the number is set according to the application, and the transconductance is made constant over a wide input voltage range, More voltage-current converters can be connected to the A / D converter for lower bit determination at the same time, and higher speed and higher accuracy can be realized for the same power consumption and circuit scale.

<Principle of the present invention>
FIG. 1 shows the configuration of the sub-ranging A / D converter of the present invention. In FIG. 1, 100 is a resistor array composed of a plurality of resistors for generating 2 ^M −1 (M is the number of upper bits) reference voltage, and 200 is a different reference generated by the resistor array 100. A voltage comparator array composed of 2 ^M −1 voltage comparators for comparing the voltage with the input voltage Vin of the input terminal 1, 300 receives the output value of the voltage comparator array 200, and receives an upper M-bit digital signal Is a high-order bit encoder that generates The resistor array 100 is connected between the high voltage terminal 2 and the low voltage terminal 3, and generates a voltage obtained by equally dividing the voltage between the terminals 2 and 3 into 2 ^M −1 as a reference voltage. A generation circuit is configured. The above resistor array 100, voltage comparator array 200, and upper bit encoder 300 constitute a flash type upper bit determining A / D converter.

400 is a voltage-current converter array composed of 2 ^M −1 voltage-current converters, and 500 is a 2 ^M that extracts two or more output currents of the output currents of the individual voltage-current converters of the voltage-current converter array 400. Reference numeral 600 denotes a current sample / hold circuit that holds a current value output from the current switch array 500. The resistor array 100, the voltage / current converter array 400, the current switch array 500, and the current sample / hold circuit 600 described above constitute a lower bit analog signal generation circuit. Reference numeral 700 denotes an A / D converter for lower bit determination that generates a lower M-bit digital signal from the current value output from the current sample hold circuit 600. The individual voltage-current converters of the voltage-current converter array 400 have the same transconductance, and the magnitude and polarity according to the voltage difference between the input voltage Vin of the input terminal 1 and the reference voltage generated by the resistor array 100. Current is output. The current switch array 500 turns on two or more current switches by a switch selection signal S1 generated by the higher-order bit determination encoder 300 according to the combination of the output values of the individual voltage comparators of the voltage comparator array 200. A current adder circuit is configured to act to turn off the remaining current switches.

  The upper M-bit code includes a first voltage comparator corresponding to the highest reference voltage whose output in the voltage comparator array 200 indicates “1” and a reference voltage of only one stage from the first voltage comparator. It is determined by the array arrangement position of the second high voltage comparator (the output of this voltage comparator indicates “0”).

  The switch selection signal S1 includes two current switch arrays 500 so that the output currents of the adjacent first and second voltage / current converters corresponding to the first and second voltage comparators are selectively added. Turn on the current switch and turn off the others. The output current of the first voltage-current converter corresponding to the first voltage comparator is a positive current, and the output current of the second voltage-current converter corresponding to the second voltage comparator is a negative current. When both currents are added, a current indicating a level corresponding to the input voltage Vin can be obtained between the reference voltage corresponding to the first voltage comparator and the reference voltage corresponding to the second voltage comparator. Therefore, if the current value at this level is held by the sample hold circuit 600 and then A / D converted by the A / D converter 700 for lower bit determination, the lower L bits can be determined.

  The current sample and hold circuit 600 is inserted between the output side of the current switch array 500 and the input side of the A / D converter 700 for determining the lower bit, but the individual outputs of the plurality of voltage current converters. May be inserted individually between the input side of the current switch array 500 and the input side of the current switch array 500.

  The sub-ranging A / D converter shown in FIG. 1 can be configured as a differential type as shown in FIG. 2 when the differential input voltages Vin + and Vin− are input. A is assigned to each code on the non-inversion side, and B is assigned to each code on the inversion side. S1A is a non-inverting switch selection signal, and S1B is an inverting switch selection signal. The arithmetic unit 800 generates a digital signal of N (= M + L) bits. Here, the resistance arrays 100A and 100B may be shared.

<First embodiment>
FIG. 3 shows a sub-ranging A / D converter according to the first embodiment of the present invention. Here, it is assumed that the number of upper bits is 6, the number of lower bits is 4, and a resolution of 10 bits is achieved as a whole. FIGS. 4A to 4C show that the first to 31st voltage comparators 20001 to 20001 among the flash type A / D converters for determining the upper bits by inputting the input voltage Vin to the input terminal 1. In this example, the output of 20031 is “1” and the outputs of the 32nd to 63rd voltage comparators 20032 to 20063 are “0”. In this case, the output current of the 31st voltage-current converter 40031 and the output current of the 32nd voltage-current converter 40032 are selected by turning on the switches 50031, 50032 of the current switch array 500 by the switch selection signal S1. Are added and held by the current sample and hold circuit 600 and then input to the A / D converter 700 for determining the lower bits. It is assumed that the A / D converter 700 for determining the lower bits digitizes the width of 160 mV from 520 mV to 680 mV with 4 bits (1 step is 10 mV and 16 steps). As will be described later, the lower voltage range (520 mV to 680 mV) is convenient and does not indicate an actual voltage value.

  Here, as shown in FIGS. 4A and 4B, a voltage value example of the 31st reference voltage Vref31 = 595 mV, the 32nd reference voltage Vref32 = 605 mV, and the input voltage Vin = 602.5 mV is assumed. It is assumed that the transconductance Gm = 40 mA / V of the 31st and 32nd voltage / current converters 40031 and 40032 is common. In this case, the output current of the 31st voltage-current converter 40031 is a positive current of 300 μA [= (602.5 mV−595 mV) × 40 mA / V], and the 32nd voltage-current converter 40032 is 100 μA [= ( 602.5 mV−605 mV) × 40 mA / V].

  When the output currents of the voltage-to-current converters 40031 and 40032 are added, the current becomes 200 μA (= 300 μA-100 μA), and this current is connected to the common voltage (= 600 mV), which is an average voltage of 520 mV to 680 mV, as described above. 200 Ω), the input voltage of the lower bit determining A / D converter 700 is 640 mV (= 600 mV + 200 Ω × 200 μA). This can be regarded as a voltage amplifier having a gain of 16 times effectively by combining the parallel two voltage-current converters 40031 and 40032 and the resistor R4.

  FIG. 4 (c) shows the state of this voltage amplification in detail. The voltage range from the 31st reference voltage Vref31 = 595 mV to the 32nd reference voltage Vref32 = 605 mV is expanded by the voltage / current converters 40031 and 40032. That is, rather than sensing the range of the potential difference of 10 mV from 595 mV to 605 mV with the A / D converter 700 for determining the lower bits, the common voltage of 600 mV is left as it is and linearly multiplied by 8 times. That is, as a whole, it is magnified 16 times and apparently projected into a voltage range from 520 mV to 680 mV, and this is input to the A / D converter 700 for lower bit determination, whereby the lower bit code is specified. The input voltage value 602.5 mV is specified.

  In Non-Patent Document 1, only one of a plurality of provided Window Amplifiers is selected according to the output of Comparators Decoding-logic. This is equivalent to selecting and operating only one of the voltage-current converters 40031 and 40032 in this embodiment. In this case, for example, when the input voltage Vin changes in the range from 595 mV to 605 mV, the output current of the voltage-current converter 40031 changes in the range of 0 to 400 μA. The output current of the voltage-current converter 40032 varies in the range of −400 μA to 0 μA. That is, regardless of which of the voltage / current converters 40031 and 40032 is selected, the width of the change in the output current is 400 μA.

  On the other hand, when both the voltage-current converters 40031 and 40032 are operated as in this embodiment, the total output current changes in the range of −400 μA to 400 μA, and only one of them is operated. The change width is obtained at 800 μA which is doubled. As a result, it is possible to reduce the time required for generating the input voltage of the A / D converter 700 for determining the lower bit by causing the output current to flow through the resistor R4 and to increase the speed.

  Further, by adding the outputs of two or more voltage-current converters, the input offset voltages of the individual voltage-current converters are averaged and the accuracy is improved.

  Here, the voltage-current converters 40031 and 40032 that are operated simultaneously are provided to configure the sub-ranging A / D converter, and are not added to increase the current supply capability. That is, in Non-Patent Document 1, only one of a plurality of voltage-current converters is selected and operated. In the present invention, two or more voltage-current converters are similarly provided. Select and operate simultaneously. Therefore, in the sub-ranging A / D converter of the present invention, it is possible to realize a higher speed without increasing the circuit scale and area as compared with Non-Patent Document 1.

  As described above, by operating both of the voltage-current converters 40031 and 40032, the actual operation with respect to the current consumption when the whole of the plurality of voltage-current converters provided in the voltage-current converter array 400 is operated. The ratio with respect to the current consumption by the negative current converter is increased. Thus, it can be considered that high speed is realized.

  FIG. 4C shows an example in which the input voltage Vin is between the 31st reference voltage Vref31 = 595 mV and the 32nd reference voltage Vref32 = 605 mV. In this case, the average voltage of the two reference voltages is 600 mV. Further, the common voltage of the A / D converter 700 for lower bit determination is also 600 mV, which matches the average voltage of the two reference voltages. However, the average voltage of the two reference voltages changes according to the input voltage. Therefore, in general, the average voltage of the two reference voltages does not match the common voltage of the A / D converter 700 for determining the lower bit.

  Further, by increasing the number of voltage-current converters to be operated simultaneously to 3 or more, higher speed and higher accuracy can be achieved. However, increasing the number of voltage-current converters that are operated simultaneously increases the current consumption. Therefore, it is preferable to select an appropriate number of simultaneous operations in accordance with required speed and accuracy and allowable current consumption.

  Further, in order to increase the accuracy by increasing the number of voltage-current converters that are operated simultaneously, it is necessary to widen the input voltage range in which each voltage-current converter has a certain transconductance. As a result, the transconductance decreases, and it may be difficult to obtain the effect of increasing the operation speed. In consideration of this point, it is preferable to select an appropriate number of simultaneous operations.

  As a specific form of use, the sub-ranging A / D converter of the present invention is prepared as a system-on-chip IP core, and according to product specifications (allowable power consumption and required conversion speed). By setting the number of voltage-current converters to be selected at the same time, it becomes unnecessary to redesign the A / D converter for each product.

  In addition, there is provided a setting circuit for externally setting the number of voltage-current converters that operate the integrated circuit including the sub-ranging A / D converter of the present invention at the same time by an external signal (or a setting value stored in a register). The user can set the number of simultaneous operations according to the required specifications, or can set the number of simultaneous operations according to the operating environment (noise level, power supply voltage, etc.).

<Second embodiment>
As described above, when the 31st and 32nd current / voltage converters 30031 and 30032 are selected by the switch selection signal S1, the reference voltages are Vref31 = 595 mV and Vref32 = 605 mV, respectively. When the input voltage Vin = 592.5 mV, in this embodiment, the reference voltages should be Vref30 = 585 mV and Vref31 = 595 mV, respectively. However, the upper A / D converter selects a range in which the reference voltage is different from the range in which the input voltage is sandwiched due to the influence of actual circuit characteristics fluctuations such as the characteristics of the resistance elements and fluctuations in the voltage comparator array. There is a case. For example, the situation is such that Vref31 = 595 mV and Vref32 = 605 mV are selected one higher. At this time, since the input voltage is out of the range of the reference voltages Vref31 and Vref32, the A / D converter 700 for determining the lower bits cannot perform A / D conversion correctly.

  Therefore, as a countermeasure against this, as shown in FIG. 5, the lower bit determining A / D converter 700 is replaced with a 5-bit lower bit determining A / D converter 700A with redundant bits in the number of bits. Overlapping with the input voltage range that can be handled by the higher-order bit determination.

  Thus, even though the input voltage Vin = 592.5 mV is not between the 31st reference voltage Vref31 = 595 mV and the 32nd reference voltage Vref32 = 605 mV, the current switch array 500 allows the 31st voltage-current conversion. When the unit 40031 and the 32nd voltage-current converter 40032 have been selected, it will be confirmed that they can be output without problems by providing redundant bits.

  In this case, if the reference voltage Vref31 and Vref32 are divided into 5 bits (32 steps) including 1 bit of extension, the minimum voltage is 440 mV and the maximum voltage is 760 mV, the intermediate voltage is also 600 mV. It is. At this time, as shown in FIG. 6A, the output current of the 31st voltage-current converter 40031 becomes a negative current of 100 μA [= (592.5 mV−595 mV) × 40 mA / V], and the 32nd Since the voltage-current converter 40032 has a negative current of 500 μA [= (592.5 mV−605 mV) × 40 mA / V], the current flowing through the resistor R4 is 600 μA in the reverse direction. Therefore, the input voltage of the A / D converter 700A for lower bit determination is 480 mV (= 600 mV−200Ω × 600 μA).

  As can be seen from FIG. 6B, the voltage received by the lower bit determining A / D converter 700A due to the bit extension of the lower bit determining A / D converter 700A is the lower bit determining A / D. The converter 700A is handled correctly without saturating.

  As described above, the input voltage Vin falls within the input range of the A / D converter 700A for lower-order bit determination. In order to briefly explain how to decode this, the same input voltage Vin is used. Two cases assuming = 592.5 mV are compared in FIG. 6B and FIG. FIG. 7A illustrates which voltage-current converter output current should be used for A / D conversion when the input voltage Vin = 592.5 mV is used. Since the input voltage Vin = 592.5 mV, the voltage-current converters to be originally selected are 40030 and 40031, and the reference voltages thereof are two, Vref30 = 585 mV and Vref31 = 595 mV, respectively.

  6B and 7A have the same input voltage Vin = 592.5 mV, the same A / D conversion result must be obtained. For this purpose, the state saved by the input range redundancy of the A / D converter 700A for lower bit determination in FIG. 6B is replaced with the normal state shown in FIG. 7A (without redundancy). It can be seen that it should be translated into FIG. 7B shows how to translate the state of FIG. 6B into FIG. 7A by paying attention to the difference between FIG. 6B and FIG. 7A.

  Here, the output code of the A / D converter 700A for determining the lower bits is incremented by 160 mV, which is exactly one reference voltage range, and the reference voltage of the two voltage-current converters used instead is only 10 mV. When lowered, it can be understood that FIG. 6B is converted to FIG. 7B. In an actual circuit, one bit of the expanded most significant bit overlaps with the least significant bit of the upper bit. After outputting the lower 5 bits, the lower most significant bit and the least significant bit of the upper A / D conversion output may be added (or subtracted) and output, and a circuit similar to the adder (or subtractor) 900 is provided. No special circuit is required. For example, the output code of the A / D converter 700A for determining the lower bits is set to “00000” to “01000” between 520 mV and 680 mV, “−01000” to “00000” from 440 mV to 520 mV, and 680 mV to 760 mV. If “01000” to “11000” are set, the lower 6 bits of “0” are supplemented to the upper 6 bits, and the lower 5 bits are added. In this way, even in the case where the input range of the A / D converter 700A for lower bit determination is made redundant, digital code calculation using a normal digital code calculation method without redundancy becomes possible.

<About voltage-current converter>
FIG. 8A shows the simplest voltage-current converter 410 composed of a pair of differential circuits composed of NMOS transistors M1 to M3. FIG. 8B shows the voltage-current conversion characteristic of the voltage-current converter 410, and FIG. 8C shows the transconductance characteristic of the voltage-current converter 410.

  By the way, in general CMOS technology, the allowable differential input voltage range for allowing the transconductance Gm of the voltage / current circuit 410 to be constant within 1% is often less than 10 mV.

  In the sub-ranging A / D converter of the present invention, two or more voltage-current converters are operated according to the input voltage Vin, the output currents are added, and the A / D conversion for lower bit determination The input voltage of the generator 700 is generated. Accordingly, in order to accurately generate the input voltage of the A / D converter 700 for lower bit determination that accurately reflects the voltage of the input voltage Vin, two or more voltage-current converters operating simultaneously are assumed. It is necessary to have substantially the same and constant transconductance over the entire range of input voltage Vin to be applied.

  For example, in the case of the first embodiment, each voltage-to-current converter needs to have a substantially constant transconductance in the input voltage range of ± 10 mV, that is, twice the width of the reference voltage interval. is there. When three or more voltage-current converters are operated simultaneously, it is necessary to have substantially the same transconductance in an input voltage range that is several times as wide as the reference voltage interval that is operated simultaneously. In the case of the second embodiment, it is necessary to have a substantially constant transconductance in the input voltage range which is 30 mV, that is, in the input voltage range wider than the case of the first embodiment by the reference voltage interval.

  When operating an odd number (for example, 3) of voltage / current converters simultaneously, in order to make the input voltage range the same between the + side and the − side, the reference voltage of the voltage / current converter must It is appropriate to set it at the center between the reference voltages used by the A / D converter for determination.

  Therefore, a voltage-current converter 420 configured by connecting two pairs of differential circuits composed of NMOS transistors M11 to M18 in parallel as shown in FIG. This voltage-to-current converter 420 includes a first transistor M11 (small size) having a gate connected to a non-inverting input terminal, transistors M12 and M13 (large size) having a gate connected to an inverting input terminal, and a current source transistor M17. A differential circuit and a second differential circuit comprising a transistor M14 (small size) having a gate connected to an inverting input terminal, transistors M15 and M16 (large size) having a gate connected to a non-inverting input terminal, and a current source transistor M18 The output terminals of the first and second differential circuits are connected in parallel. In this way, by intentionally unbalancing the transistor size of the differential circuit between the two pairs of differential circuits and providing an input offset, as shown in FIG. The flat area can be expanded to extend the allowable differential input voltage range. FIG. 9B shows voltage-current conversion characteristics of the voltage-current converter 420.

  FIG. 10A shows a configuration for further expanding the differential allowable input voltage range. One voltage-current converter 430 is divided into K small-sized sub-voltage / current converters 4301 to 430K, and the average values of the sub-reference voltages VrefA1 to VrefAK given to the respective sub-voltage / current converters 4301 to 430K are By setting the sub reference voltages VrefA1 to VrefAK to be equal to the original reference voltage VrefA, a constant transconductance can be achieved in a wider differential input voltage range. FIG. 10B shows the transconductance characteristic of the voltage-current converter 430. This is an example when K = 4.

  Further, when actually designing the voltage-current converter, since it is desired to increase the value of the transconductance Gm as much as possible, it may be possible to newly install a voltage amplifier in the first stage. For example, as shown in FIG. 11, a design example in which a preamplifier 440 including NMOS transistors M21 to M28 and load resistors R1 and R2 is arranged in the previous stage of the voltage-current converter 420 can be considered. 12 shows a design example of the voltage / current converter 450 in which the current sources I1 and I2 having the same current value are connected to the load side of the voltage / current converter 420 of FIG. Is a design example of the voltage-current converter 460 to which the voltage-current converter 450 is improved so that the two current sources I1, I2 can be controlled by the offset correction signal S2 and an offset adjustment function for offset cancellation is added. It is.

<Current sample hold circuit>
FIG. 14A shows a basic configuration of the current sample and hold circuit 600. The current sample and hold circuit 600 includes a first NMOS transistor M31 having a gate and a drain connected in common, a drain connected to the gate of the transistor M31 selectively by a switch 610, and holding an input current as a voltage in a gate capacitor. , NMOS transistors M32 and M33 as second current holding means, and a switch 620 for extracting one drain current of the transistors M32 and M33. The switches 610 and 620 are switched in every phase of the clock CLK in reverse phase, and the output current obtained by sampling the input current every cycle is switched each time.

  FIG. 14B shows a specific circuit of the current sample and hold circuit 600. The switch 610 includes analog switches 611 and 612, and the switch 620 includes analog switches 621 and 622. The analog switch 631 functions as a band compensating MOS resistor. The analog switches 641 and 642 are for charge injection compensation that absorbs gate charges when the switch 610 is OFF. Each analog switch 611, 612, 621, 622, 641, 642 is turned ON / OFF by the clock CLK and the inverted clock CLKB.

  For example, during the period when the clock CLK is H, the first input voltage Vin is input to the A / D converter for determining the upper bit, and the output current of the voltage / current converter is the transistor M33 which is the second current holding means. Hold on. Next, during the period when the inverted clock CLKB becomes H, a current is taken out from the drain of the transistor M33, is passed through the resistor R4 (see FIG. 4B) and converted into a voltage, and the A / D converter 700 for lower bit determination To enter.

  At the same time, the second input voltage Vin is input to the upper bit determining A / D converter. As a result, A / D conversion can be performed at a sample rate twice as high as the clock frequency. Note that the sample-and-hold operation can be performed with a higher-speed clock CLK by performing the sample-and-hold operation in a current state before the voltage-current converter outputs the current through the resistor and converts the voltage into a voltage.

<Switch selection signal generation circuit>
FIG. 15 shows a switch selection signal generation circuit 310 that generates the switch selection signal S1. Reference numeral 311 denotes a two-input AND gate that inverts one input and takes a logical sum, 312 denotes a two-input AND gate, and 313 denotes a two-input OR gate. In this example, as in the case shown in FIG. 10, four sub-voltage / current converters are selected in order to achieve a constant transconductance in a wide differential input voltage range. That is, four current switches that are “1” (= ON) are always selected. For example, in the circuit of FIG. 15, when the -1st to 36th voltage comparator outputs are "1" and the 37th to 65th voltage comparator outputs are "0", the -1st to 34th currents. The switches and the 39th to 68th current switches are “0”, and the four current switches from the 35th to the 38th are “1”. In this way, the circuit is such that the change position from “1” to “0” (current switches 36 and 37) and the current switches above and below (current switches 35 and 38) are set to “1”.

  However, in FIG. 15, the current switches that are selected and turned on are not necessarily adjacent to each other. As a selection method, the input received by the higher-order encoder 300 that determines the lower bit as much as possible is a value close to “0”, that is, the output that is the target for the output of the voltage-current converter of the lower-bit analog signal generation circuit An algorithm is suitable so that a nearby switch is turned on, so that it is near the boundary between “1” and “0” of the output of the voltage comparator. In this sense, the current switch that is selected and turned on is not necessarily adjacent. It does n’t fit.

  The boundary between the region where the voltage comparator output is continuous at “0” and the region where the voltage comparator output is continuous at “1” is usually one place. However, as shown in FIG. 15, although the 34th voltage comparator output is “1” and the 35th voltage comparator output is “0”, the characteristics of the resistance elements and the voltage There may be a case in which “1” is output instead of “0” at the 36th voltage comparator output due to the influence of actual circuit characteristics such as variations in the performance of a device such as a comparator array. The case where there are a plurality of boundaries between the region where the voltage comparator output is “0” and the region where the output is “1” is called “bubble”, and even under such circumstances, the current switch It is required to make a selection without problems.

  In FIG. 15, it can be confirmed that the following procedure is satisfied for the selection of the current switch even when a bubble occurs. One is that the number of current switches that are “1” (= ON) is four, and the other is that the center position of the four current switches that are selected as “1” is the bubble generation point (35 Between the th and th 36th current switches).

  In FIG. 15, the four positions of the current switch selected as “1” are not continuous under the generation of the bubble, but of course, the four voltage-current converters to be selected are continuous even when the bubble is generated. Such a combinational circuit may be assembled. Although the number of current switches simultaneously selected is four in this example, eight or other larger numbers can be designated depending on the allowable input differential voltage range of the voltage-current converter.

  The important condition for the switch selection signal generation circuit 310 is that the number of selected current switches is plural, and the center position of the selected current switch is the region where the voltage comparator output is “0” and “1”. To be near the boundary of the region.

  Also, the following two pieces of information are required when generating the lower bit code. One is the output of the switch selection signal generation circuit 310 (information on which current switch is selected), and the other is the A / D converter 700 of the lower-order bit of the second stage by the selected voltage-current converter. Is the output. It should be noted here that the output of the higher-order bit determination encoder 300 is not necessarily required. It is only necessary to have information on how many current switches are turned on.

100, 100A, 100B: Resistor array 200, 200A, 200B: Voltage comparator array 300, 300A, 300B: High-order bit encoder, 310: Switch selection signal generation circuit 400, 400A, 400B: Voltage-current converter array, 410, 420, 430, 450, 460: Voltage current converter, 440: Preamplifier 500, 500A, 500B: Current switch array 600: Current sample hold circuit, 610, 620: Switch 700, 700A: A / D converter for lower bit determination 800: Calculator 900: Adder

Claims (5)

A first reference voltage generation circuit that generates a plurality of different first reference voltages spaced apart by the same voltage difference; and the plurality of individual first reference voltages generated by the first reference voltage generation circuit; A voltage comparator array comprising a plurality of voltage comparators for comparing the input voltage and the output value of the plurality of voltage comparators are fetched to generate an upper bit code having M bits (M is an integer of 2 or more). An upper bit determining A / D converter comprising:
A second reference voltage generation circuit for generating a plurality of different second reference voltages spaced apart by the same voltage difference; a plurality of individual second reference voltages generated from the second reference voltage generation circuit; A voltage-current converter array comprising a plurality of voltage-current converters for comparing the input voltage and generating a current of magnitude and polarity according to the difference voltage, and two or more voltages of the plurality of voltage-current converters A current addition circuit for selecting and adding the output current of the current converter according to the combination of the output values of the plurality of voltage comparators and outputting the selected signal, a low-order bit analog signal generation circuit,
A lower bit determination A / D that inputs the lower bit analog signal generated by the lower bit analog signal generation circuit and generates a lower bit code having a bit number L (L is an integer of 2 or more). converter,
A sub-ranging A / D converter characterized by comprising: The subranging A / D converter according to claim 1,
Individually inserted between each output side of the plurality of voltage-current converters and an input side of the current addition circuit, or an input side of the output side of the current addition circuit and the A / D converter for determining the lower bit When the input current is input to the first holding means, the input current is alternately held by the first holding means and the second holding means every predetermined clock period. Subranging comprising a current sample and hold circuit that outputs current from the second holding means and outputs current from the first holding means when current is input to the second holding means Type A / D converter. The sub-ranging A / D converter according to claim 1 or 2,
The second reference voltage generation circuit is provided in common or independently with the first reference voltage generation circuit, and each of the second reference voltage is K pieces (K is a positive integer of 2 or more). A sub-reference voltage generation unit that generates K sub-reference voltages divided into
The voltage-current converter is composed of K sub-voltage current converters to which the sub-reference voltage is input and outputs are commonly connected.
A sub-ranging A / D converter characterized by the above. The sub-ranging A / D converter according to claim 1, 2, or 3,
A sub-ranging A / D converter comprising a setting circuit for externally setting the number of the two or more voltage-current converters selected to be added with an output current. The sub-ranging A / D converter according to claim 1, 2, 3, or 4,
In the sub-ranging A / D converter, the A / D converter for lower bit determination has redundant bits set for the number of bits L.

Images