JP2014103447A - Interface circuit and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption.SOLUTION: A voltage generation circuit 32 controls a voltage value of a driving voltage VD1 supplied to an input/output circuit 31 on the basis of a power-down signal PDN and a standby signal STBY. The driving voltage VD1 is supplied to an external device 20 via an external terminal P11. An input/output circuit 51 of the external device 20 operates on the basis of the driving voltage VD1. A selection circuit 13 selects an output signal R1a of an input buffer 42 without a Schmitt characteristic or an output signal R1b of an input buffer 43 with a Schmitt characteristic on the basis of the standby signal STBY, and outputs reception data RD1 depending on the selected signal R1a or signal R1b.

Description

  The present invention relates to an interface circuit and a semiconductor device.

  Conventionally, an electronic apparatus has a plurality of semiconductor devices (semiconductor chips) connected to each other. Each semiconductor device includes an interface circuit for communicating with the connected semiconductor device (see, for example, Patent Documents 1 and 2).

International Publication No. 2002/45268 JP 2011-41109 A

  Electronic devices are required to reduce power consumption. For this reason, the interface circuit of the semiconductor device included in the electronic device is similarly required to reduce power consumption.

  According to one aspect of the present invention, an external device is connected to an external terminal, and is an interface circuit for exchanging signals with the external device, wherein a first reception signal corresponding to a voltage level of the external terminal is received. An input circuit including an input buffer for outputting; a Schmitt circuit for outputting a second received signal corresponding to a voltage level of the external terminal; and the input circuit according to a control signal for controlling an operating state of the input circuit. And a voltage generation circuit that outputs a driving voltage having a first voltage value or a second voltage value lower than the second voltage value to the external device, and the first reception signal according to the control signal, Or a selection circuit that selects and outputs the second reception signal.

  According to one aspect of the present invention, power consumption can be reduced.

1 is a schematic diagram of a system. FIG. 3 is a circuit diagram of an interface circuit according to the first embodiment. It is a wave form diagram which shows operation | movement of an interface circuit. It is a wave form diagram which shows operation | movement of an interface circuit. It is a circuit diagram of the interface circuit of 2nd Embodiment. It is a wave form diagram which shows operation | movement of an interface circuit. It is a circuit diagram of the interface circuit of 3rd Embodiment. It is a wave form diagram which shows operation | movement of an interface circuit. It is a circuit diagram of the interface circuit of 4th Embodiment. It is a wave form diagram which shows operation | movement of an interface circuit. FIG. 10 is a circuit diagram of an interface circuit according to a fifth embodiment. It is a wave form diagram which shows operation | movement of an interface circuit. It is a circuit diagram of the interface circuit of 6th Embodiment. It is a wave form diagram which shows operation | movement of an interface circuit. It is a circuit diagram of the interface circuit of 7th Embodiment. It is a wave form diagram which shows operation | movement of an interface circuit.

(First embodiment)
The first embodiment will be described below.
As shown in FIG. 1, the system includes a system device 10 and an external device 20 connected to the system device 10. The system apparatus 10 and the external apparatus 20 are, for example, semiconductor devices (devices). The system device 10 has external terminals P10 to P13. The external device 20 has external terminals P21 to P23. The external terminal P10 of the system apparatus 10 is connected to a power supply wiring for supplying the external power supply voltage VDE. The external terminals P11, P12, and P13 of the system apparatus 10 are connected to the external terminals P21, P22, and P23 of the external apparatus 20, respectively. The external terminals P13 and P23 are grounded.

  The system apparatus 10 includes an internal circuit 11 and an interface circuit (denoted as “I / F”) 12. The external device 20 includes an internal circuit 21 and an interface circuit (denoted as “I / F”) 22. The internal circuit 11 outputs a control signal and transmission data to the interface circuit 12. Further, the internal circuit 11 receives reception data output from the interface circuit 12.

  The interface circuit 12 generates a drive voltage based on the external power supply voltage VDE supplied from the outside of the system apparatus 10 via the external terminal P10. The interface circuit 12 controls the voltage value of the drive voltage in response to the control signal. The input / output circuit included in the interface circuit 12 operates according to the drive voltage. Further, the interface circuit 12 outputs the generated drive voltage VD1 to the outside of the system apparatus 10 via the external terminal P11. The drive voltage VD1 is supplied to the interface circuit 22 via the external terminal P21 of the external device 20 connected to the external terminal P11. The input / output circuit included in the interface circuit 22 operates according to the drive voltage VD1.

  The interface circuit 12 outputs a transmission signal corresponding to the transmission data supplied from the internal circuit 11. The transmission signal is supplied to the interface circuit 22 of the external device 20 via the external terminal P12 of the system device 10 and the external terminal P22 of the external device 20. The interface circuit 22 outputs received data corresponding to the received signal. Similarly, the interface circuit 22 of the external device 20 outputs a transmission signal corresponding to the transmission data supplied from the internal circuit 21. The transmission signal is supplied to the interface circuit 12 of the system apparatus 10 via the external terminal P22 of the external apparatus 20 and the external terminal P12 of the system apparatus 10. The interface circuit 12 outputs received data corresponding to the received signal.

  The internal circuit 11 of the system apparatus 10 operates with a power supply voltage supplied from the outside of the system apparatus 10 via a power supply terminal (not shown) or a drive voltage generated based on the power supply voltage. Similarly, the internal circuit 21 of the external device 20 operates with a power supply voltage supplied from the outside of the external device 20 via a power supply terminal (not shown) or a drive voltage generated based on the power supply voltage.

  As shown in FIG. 2, the system apparatus 10 includes an interface circuit 12 and a selection circuit 13. The interface circuit 12 includes an input / output circuit 31 and a voltage generation circuit 32.

  The input / output circuit 31 includes an output buffer 41 and input buffers 42 and 43. The high potential side power supply terminal of the output buffer 41 is connected to a wiring (hereinafter referred to as power supply wiring VD1) for transmitting a drive voltage VD1 generated by the voltage generation circuit 32 described later. Is connected to the external terminal P13. The external terminal P13 is grounded. Therefore, the low potential side power supply terminal of the output buffer 41 is at the ground level (0 volts (V)). Similarly, the high potential side power supply terminals of the input buffers 42 and 43 are connected to the power supply wiring VD1, and the low potential side power supply terminal is connected to the external terminal P13.

  Transmission data TD1 is supplied to the input terminal of the output buffer 41 from the internal circuit 11 shown in FIG. 1, and the output terminal of the output buffer 41 is connected to the external terminal P12. The output buffer 41 outputs a signal corresponding to the transmission data TD1. The input terminal of the input buffer 42 is connected to the external terminal P12. The output terminal of the input buffer 42 is connected to the selection circuit 13. The input buffer 42 outputs a signal R1a corresponding to the level of the external terminal P12. Similarly, the input terminal of the input buffer 43 is connected to the external terminal P12. The output terminal of the input buffer 43 is connected to the selection circuit 13. The input buffer 43 outputs a signal R1b corresponding to the level of the external terminal P12.

  The input buffer 43 is a buffer circuit having a Schmitt characteristic. Hereinafter, the input buffer 43 may be referred to as a Schmitt circuit 43. On the other hand, the input buffer 42 is a buffer circuit having no Schmitt characteristic. For example, the input buffer 42 uses the intermediate voltage level between the voltage level of the high potential side power supply terminal and the voltage level of the low potential side power supply terminal as the threshold voltage. That is, the input buffer 42 has input characteristics corresponding to one threshold voltage. This input buffer 42 has a faster response characteristic than the Schmitt circuit 43. The Schmitt circuit 43 is more resistant to noise mixed in the input signal than the input buffer 42.

  The voltage generation circuit 32 is supplied with a power down signal PDN and a standby signal STBY from the internal circuit 11 shown in FIG. The voltage generation circuit 32 generates a drive voltage VD1 based on the external power supply voltage VDE. Then, the voltage generation circuit 32 controls the voltage value of the drive voltage VD1 based on the power down signal PDN and the standby signal STBY.

  For example, the voltage generation circuit 32 generates the drive voltage VD1 having the voltage value V2 in response to the L level (low potential power supply voltage) power down signal PDN and the standby signal STBY. The voltage value V2 is set to a standard (Typical) operating voltage value of the output buffer 41 and the input buffers 42 and 42 included in the input / output circuit 31, and is, for example, 3.3 volts [V]. The drive voltage VD1 having the voltage value V2 is an example of the operating voltage.

  The voltage generation circuit 32 generates the drive voltage VD1 having the voltage value V1 in response to the standby signal STBY at the H level (high potential power supply voltage) and the power down signal PDN at the L level. The voltage value V1 corresponds to the minimum voltage in the common operating voltage range of the output buffer 41 and the input buffers 42 and 43 included in the interface circuit 12 and the output buffer 61 and the input buffer 62 included in the interface circuit 22. For example, it is 1 volt [V]. The drive voltage VD1 having the voltage value V1 is an example of a standby voltage.

  Then, the voltage generation circuit 32 generates the drive voltage VD1 having the voltage value V0 in response to the H level power down signal PDN. The voltage value V0 is set equal to the voltage level of the low potential side power supply terminal so as to stop the operation of the input / output circuit 31, and is 0 volt [V], for example. The drive voltage VD1 having the voltage value V0 is an example of a stop voltage.

  For example, the voltage generation circuit 32 includes a first voltage generation unit that generates a voltage having a voltage value V2 and a second voltage generation unit that generates a voltage having a voltage value V1. Then, based on the standby signal STBY and the power down signal PDN, the drive voltage VD1 of the voltage value V2 or the voltage value V1 is obtained by activating or deactivating the first voltage generation unit and the second voltage generation unit. Generate. Then, based on the standby signal STBY and the power-down signal PDN, the output terminal is connected to, for example, a power supply wiring having a ground potential, thereby generating the drive voltage VD1 having the voltage value V0.

  The selection circuit 13 is supplied with the output signal R1a of the input buffer 42 and the output signal R1b of the input buffer 43. The selection circuit 13 is supplied with a standby signal STBY. The selection circuit 13 selects one of the output signals R1a and R1b according to the standby signal STBY, and outputs received data RD1 according to the selected signal (for example, equal to the level of the selected signal). For example, the selection circuit 13 selects the output signal R1a of the input buffer 42 in response to the L level standby signal STBY, and outputs the reception data RD1 corresponding to the selected signal R1a. On the other hand, the selection circuit 13 selects the output signal R1b of the input buffer 43 in response to the standby signal STBY at H level, and outputs the reception data RD1 corresponding to the selected signal R1b. The standby signal STBY is an example of a control signal.

  As described above, the voltage generation circuit 32 outputs an operating voltage when the standby signal STBY is at the L level, and outputs a standby voltage when the standby signal STBY is at the H level. Therefore, the selection circuit 13 outputs the reception data RD1 corresponding to the output signal R1a of the input buffer 42 when the input / output circuit 31 operates at the operating voltage. When the input / output circuit 31 operates at the standby voltage, the selection circuit 13 outputs the reception data RD1 corresponding to the output signal R1b of the input buffer 43 (Schmitt circuit 42).

  The interface circuit 22 of the external device 20 has an input / output circuit 51, and the input / output circuit 51 includes an output buffer 61 and an input buffer 62. Similar to the input buffer 42 included in the interface circuit 12 of the system apparatus 10, the input buffer 62 is a buffer circuit having no Schmitt characteristic.

  The high potential side power supply terminal of the output buffer 61 and the high potential side power supply terminal of the input buffer 62 are connected to the external terminal P <b> 21 of the external device 20. The external terminal P21 is connected to the external terminal P11 of the system apparatus 10. Therefore, the drive voltage VD1 generated by the voltage generation circuit 32 is supplied to the high potential side power supply terminals of the output buffer 61 and the input buffer 62. The low potential side power supply terminal of the output buffer 61 and the low potential side power supply terminal of the input buffer 62 are connected to the external terminal P23, and this external terminal P23 is grounded. The output buffer 61 and the input buffer 62 operate with the drive voltage VD1 supplied from the interface circuit 12 of the system apparatus 10.

  Transmission data TD2 is supplied to the input terminal of the output buffer 61 from the internal circuit 21 shown in FIG. 1, and the output terminal of the output buffer 61 is connected to the external terminal P22. The output buffer 61 outputs a signal corresponding to the transmission data TD2. The input terminal of the input buffer 62 is connected to the external terminal P22. The input buffer 62 outputs received data RD2 corresponding to the level of the external terminal P22. The reception data RD2 is supplied to the internal circuit 21 shown in FIG.

Next, the operation will be described.
As shown in FIG. 3, when the standby signal STBY is at L level, the drive voltage VD1 is a voltage value V2.

  The selection circuit 13 shown in FIG. 2 selects the output signal R1a of the input buffer 42 in response to the standby signal STBY at the L level, and outputs the reception data RD1 corresponding to the signal R1a. Therefore, the input / output circuit 31 and the selection circuit 13 shown in FIG. 2 operate as a circuit without a Schmitt function. Further, the input / output circuit 31 operates at a standard speed (response speed with respect to the input signal) based on the drive voltage VD1 having the voltage value V2. This enables high-speed data transfer between the system device 10 and the external device 20.

  When the standby signal STBY rises from the L level to the H level (time T1), the voltage value of the drive voltage VD1 changes from the voltage value V2 to the voltage value V1. The selection circuit 13 shown in FIG. 2 selects the output signal R1b of the input buffer 43 in response to the H level standby signal STBY and outputs the reception data RD1 corresponding to the signal R1b. Accordingly, the input / output circuit 31 and the selection circuit 13 illustrated in FIG. 2 operate as a circuit having a Schmitt function.

  The voltage value V1 is lower than the voltage value V2 that is the operating voltage. Therefore, the current consumption in the input / output circuit 31 is reduced as compared with the driving voltage VD1 having the voltage value V2. Similarly, current consumption in the input / output circuit 51 of the external device 20 is reduced.

  In semiconductor devices, miniaturization of MOS transistors included in the interface circuits 12 and 22 is being promoted for high integration. As a transistor is miniaturized, the off-leakage current in the transistor tends to increase. Therefore, current consumption in the interface circuit when no signal is transferred increases as the transistors included in the interface circuit are miniaturized.

  On the other hand, in the present embodiment, in the standby state, the drive voltage VD1 of the interface circuits 12 and 22 is changed to a voltage value V1 lower than the voltage value V2 that is the operating voltage. Therefore, the off-leakage current of the transistors included in the interface circuits 12 and 22 is smaller than that when the drive voltage VD1 having the voltage value V2 is supplied to the interface circuits 12 and 22. The drive voltage VD1 supplied to the input / output circuits 31 and 51 is a voltage value V1 lower than the voltage value V2 supplied for normal operation. For this reason, the power consumption of the input / output circuit 31 is reduced by the product of the voltage value of the drive voltage VD1 and the current flowing between the power supply lines, that is, between the power supply terminals of the output buffer 41 and the input buffers 42 and 43. Similarly, the power consumption of the input / output circuit 51 is reduced by the product of the voltage value of the drive voltage VD1 and the current flowing between the power supply lines, that is, between the power supply terminals of the output buffer 61 and the input buffer 62.

  The voltage value V1, which is a standby voltage, corresponds to the lowest value of the common operating voltage range of the output buffer 41 and the input buffers 42 and 43 included in the interface circuit 12 and the output buffer 61 and the input buffer 62 included in the interface circuit 22. Is set. Accordingly, the internal circuit 11 shown in FIG. 1 can perform low-speed communication with the internal circuit 21 via the interface circuits 12 and 22. For this reason, for example, the operation mode of the internal circuits 11 and 21 can be changed, and information on state transition (state transition) can be exchanged.

  The input / output circuit 31 and the selection circuit 13 illustrated in FIG. 2 operate as a circuit having a Schmitt function. Therefore, the input / output circuit 31 has higher resistance to external noise than when the Schmitt function is not provided. That is, propagation of external noise to the internal circuit 11 (see FIG. 1) can be reduced, and malfunction of the internal circuit 11 can be reduced.

  Next, when the standby signal STBY falls from the H level to the L level (time T2), the voltage value of the drive voltage VD1 increases from the voltage value V1 to the voltage value V2. The selection circuit 13 shown in FIG. 2 selects the output signal R1a of the input buffer 42 in response to the standby signal STBY at L level, and outputs the reception data RD1 corresponding to the signal R1a. Therefore, the input / output circuit 31 and the selection circuit 13 shown in FIG. 2 operate as a circuit without a Schmitt function.

  As shown in the upper part of FIG. 4, when the drive voltage VD1 reaches the voltage value V2 (operating voltage) (time T3), the interface circuits 12 and 22 shown in FIG. 2 communicate based on the drive voltage VD1 of the voltage value V2 ( High-speed communication).

  The waveform of the comparative example is shown in the lower part of FIG. Thus, when the drive voltage VD1 is lowered to the voltage value V0 (0 volts), the drive voltage VD1 becomes the voltage value V2 at time T4. This time T4 is later than the time T3 (shown in the upper part of FIG. 4) when the drive voltage VD1 of the voltage value V1 is raised to become the voltage value V2. When the drive voltage VD1 is lowered to the voltage value V0 (0 volt), it is necessary to perform the device initialization sequence after the drive voltage VD1 rises to the voltage value V2. The initialization sequence of the device includes setting of signal levels that are not held by the decrease of the drive voltage VD1. For example, in the flip-flop circuit, after the drive voltage VD1 is supplied, the output signal level is indefinite (H level or L level). For this reason, it is necessary to supply a signal to the set terminal or reset terminal of the flip-flop circuit to set the output signal level to a desired level (H level or L level). After performing such an initialization sequence, communication is started (for example, time T5).

  On the other hand, in the case of the present embodiment, the drive voltage VD1 having the voltage value V1 is supplied to the interface circuits 12 and 22. Thus, for example, the flip-flop circuit holds the output signal level by the drive voltage VD1 having the voltage value V1. For this reason, a device initialization sequence is not required. Therefore, communication is possible at time T3 when the drive voltage VD1 reaches the voltage value V2. This enables high-speed communication in a short time after the standby state is canceled by the standby signal STBY.

As described above, according to the present embodiment, the following effects can be obtained.
(1-1) The voltage generation circuit 32 controls the voltage value of the drive voltage VD1 supplied to the input / output circuit 31 based on the power-down signal PDN and the standby signal STBY. The drive voltage VD1 is supplied to the external device 20 via the external terminal P11. The input / output circuit 51 of the external device 20 operates based on the drive voltage VD1. The voltage value V1 of the drive voltage VD1 is lower than the voltage value V2 that is the operating voltage. Therefore, the current consumption in the input / output circuit 31 in the standby state can be reduced as compared with the driving voltage VD1 having the voltage value V2. Similarly, current consumption in the input / output circuit 51 of the external device 20 in the standby state can be reduced.

  (1-2) The selection circuit 13 selects the output signal R1b of the input buffer 43 in response to the H level standby signal STBY and outputs the reception data RD1 corresponding to the signal R1b. Therefore, the input / output circuit 31 and the selection circuit 13 operate as a circuit having a Schmitt function. The voltage value V1, which is a standby voltage, corresponds to the lowest value of the common operating voltage range of the output buffer 41 and the input buffers 42 and 43 included in the interface circuit 12 and the output buffer 61 and the input buffer 62 included in the interface circuit 22. Is set. Therefore, the internal circuit 11 can perform low-speed communication with the internal circuit 21 via the interface circuits 12 and 22. For this reason, for example, the operation mode of the internal circuits 11 and 21 can be changed, and information on state transition (state transition) can be exchanged.

  (1-3) The input / output circuit 31 and the selection circuit 13 operate as a circuit having a Schmitt function. Therefore, the input / output circuit 31 has higher resistance to external noise than when the Schmitt function is not provided. That is, propagation of external noise to the internal circuit 11 can be reduced, and malfunction of the internal circuit 11 can be reduced.

  (1-4) In the standby state, the drive voltage VD1 having the voltage value V1 is supplied to the interface circuits 12 and 22. Therefore, for example, since the level of the flip-flop circuit is held, the device initialization sequence is unnecessary. Therefore, communication is possible at time T3 when the drive voltage VD1 reaches the voltage value V2. As a result, the time from when the standby state is canceled by the standby signal STBY until communication becomes possible (time required for return) can be shortened compared to when the communication is stopped.

(Second Embodiment)
Next, a second embodiment will be described.
In addition, the same code | symbol is attached | subjected about the same member as said embodiment, and all or one part of the description is abbreviate | omitted.

  As shown in FIG. 5, this system includes a system device 10a and an external device 20 that are connected to each other. The system device 10 a includes an interface circuit 12 a and a selection circuit 13. The interface circuit 12a includes an input / output circuit 31 and a voltage generation circuit 32a. Although omitted in FIG. 5, the system device 10a has an internal circuit 11 (see FIG. 1), and the external device 20 has an internal circuit 21 (see FIG. 1). The internal circuits 11 and 21 are the same in other embodiments described later.

  The voltage generation circuit 32a outputs a first level (eg, H level) stability signal Ss when the drive voltage VD1 is stable at the operating voltage (voltage value V2). The voltage generation circuit 32a is different from the first level when the drive voltage VD1 is not stable or when the difference between the voltage value of the drive voltage VD1 and the operating voltage (voltage value V2) is equal to or greater than a predetermined value. A stable signal Ss of the second level (for example, L level) is output.

  The selection circuit 13 selects either the output signal R1a of the input buffer 42 or the output signal R1b of the input buffer 43 in response to the stability signal Ss output from the voltage generation circuit 32a, The reception data RD1 having the same level is output. For example, the selection circuit 13 selects the output signal R1a of the input buffer 42 in response to the H level stable signal Ss, and outputs the reception data RD1 corresponding to the selected signal R1a. On the other hand, the selection circuit 13 selects the output signal R1b of the input buffer 43 in response to the L level stable signal Ss, and outputs the reception data RD1 corresponding to the selected signal R1b.

Next, the operation will be described.
As shown in FIG. 6, when the standby signal STBY is at the L level, the drive voltage VD1 is the voltage value V2, and the stable signal Ss is at the H level. Accordingly, the selection circuit 13 shown in FIG. 5 selects the output signal R1a of the input buffer 42 in response to the H level stable signal Ss and outputs the reception data RD1 corresponding to the signal R1a. Therefore, the input / output circuit 31 and the selection circuit 13 illustrated in FIG. 5 operate as a circuit without a Schmitt function.

  When the standby signal STBY rises from the L level to the H level (time T1), the voltage value of the drive voltage VD1 changes from the voltage value V2 to the voltage value V1, and the L level stable signal Ss is output. The selection circuit 13 shown in FIG. 5 selects the output signal R1b of the input buffer 43 in response to the L level stable signal Ss, and outputs the reception data RD1 corresponding to the signal R1b. Therefore, the input / output circuit 31 and the selection circuit 13 illustrated in FIG. 5 operate as a circuit having a Schmitt function.

  Next, when the standby signal STBY falls from the H level to the L level (time T2), the voltage value of the drive voltage VD1 increases from the voltage value V1 to the voltage value V2. When the drive voltage VD1 becomes stable at the voltage value V2 (time T3), an H level stability signal Ss is output. The selection circuit 13 shown in FIG. 5 selects the output signal R1a of the input buffer 42 in response to the H level stable signal Ss, and outputs the reception data RD1 corresponding to the signal R1a. Therefore, the input / output circuit 31 and the selection circuit 13 shown in FIG. 5 operate as a circuit without a Schmitt function.

  The rate at which the drive voltage VD1 changes (the amount of change in unit time) depends on the supply capability of the voltage generation circuit 32a shown in FIG. 5 and the magnitude of the load (the parasitic resistance and the parasitic capacitance of the power supply wiring that supplies the drive voltage VD1). The number of elements that supply the drive voltage VD1 is affected. That is, the length of the period during which the drive voltage VD1 changes (the period from time T2 to time T3 in FIG. 6) changes according to the supply capability of the voltage generation circuit 32a and the size of the load.

  The threshold value of the input buffer 42 shown in FIG. 5 is, for example, 1/2 of the drive voltage VD1 (1/2, but when the voltage at the low potential side power supply terminal is 0 volt). Accordingly, when the voltage value of the drive voltage VD1 is low (close to the voltage value V1), the level of the output signal may change in response to noise mixed in the input signal. Such a change in signal level causes a malfunction in the internal circuit 11 (see FIG. 1).

  On the other hand, in the present embodiment, based on the fact that the drive voltage VD1 is stabilized at the voltage value V2 (H level stable signal Ss), the input buffer 43 having the Schmitt function is changed to the input buffer 42 having no Schmitt function. Switch. That is, after the input buffer 42 without the Schmitt function operates stably, the Schmitt function is changed from “present” to “not present” in the input / output circuit 31. As a result, noise immunity is increased during a period in which the voltage value of the drive voltage VD1 is changed from the voltage value V1 to the voltage value V2 (period from time T2 to time T3 in FIG. 6), and malfunction of the internal circuit 11 is suppressed.

As described above, according to the present embodiment, the following effects can be obtained.
(2-1) The voltage generation circuit 32a outputs the first level (H level) stability signal Ss when the drive voltage VD1 is stable at the operating voltage (voltage value V2), and the drive voltage VD1 is stable. When not, or when the difference between the voltage value of the drive voltage VD1 and the operating voltage (voltage value V2) is greater than or equal to a predetermined value, the second level (L level) stability signal Ss is output. The selection circuit 13 selects either the output signal R1a of the input buffer 42 or the output signal R1b of the input buffer 43 in response to the stability signal Ss output from the voltage generation circuit 32a, The reception data RD1 having the same level is output. Therefore, the input / output circuit 31 and the selection circuit 13 operate as a circuit having a Schmitt function when the drive voltage VD1 is not stable. Therefore, malfunctions when the drive voltage VD1 is not stable can be suppressed.

  (2-2) The time required for the drive voltage VD1 of the voltage value V1 to rise to the voltage value V2 and stabilize varies depending on the supply capability of the voltage generation circuit 32a and the size of the load. Therefore, the input / output circuit 31 and the selection circuit 13 can be operated as a circuit without a Schmitt function after the drive voltage VD1 is stabilized in accordance with the supply capacity and the load size.

(Third embodiment)
Next, a third embodiment will be described.
In addition, the same code | symbol is attached | subjected about the same member as said embodiment, and all or one part of the description is abbreviate | omitted.

  As shown in FIG. 7, the system includes a system device 10b and an external device 20 that are connected to each other. The system apparatus 10 b includes an interface circuit 12, a selection circuit 13, and a signal transition detection circuit (TD: TransientDetector) 14. The interface circuit 12 includes an input / output circuit 31 and a voltage generation circuit 32.

  The standby signal STBY is supplied to the signal transition detection circuit 14. The output signal R1b of the input buffer 43 is supplied to the signal transition detection circuit 14. The signal transition detection circuit 14 generates a detection signal Sk based on the standby signal STBY and the output signal R1b of the input buffer 43. For example, the signal transition detection circuit 14 resets the detection signal Sk in response to the standby signal STBY at the H level (for example, sets to the L level). When the standby signal STBY is at the L level, the signal transition detection circuit 14 sets the detection signal Sk when detecting the level transition of the output signal R1b of the input buffer 43, that is, outputs the detection signal Sk at the H level.

  In response to the detection signal Sk output from the signal transition detection circuit 14, the selection circuit 13 selects either the output signal R1a of the input buffer 42 or the output signal R1b of the input buffer 43, and the selected signal The reception data RD1 having a level equal to is output. For example, the selection circuit 13 selects the output signal R1a of the input buffer 42 in response to the H level detection signal Sk, and outputs the reception data RD1 corresponding to the selected signal R1a. On the other hand, the selection circuit 13 selects the output signal R1b of the input buffer 43 in response to the L level detection signal Sk, and outputs the reception data RD1 corresponding to the selected signal R1b.

Next, the operation will be described.
As shown in FIG. 8, when the standby signal STBY rises from the L level to the H level (time T1), the voltage value of the drive voltage VD1 changes from the voltage value V2 to the voltage value V1. Further, the detection signal Sk is reset to the L level by the standby signal STBY at the H level.

  Next, when the standby signal STBY falls from the H level to the L level (time T2), the voltage value of the drive voltage VD1 increases from the voltage value V1 to the voltage value V2. The driving voltage VD1 becomes stable at the voltage value V2.

  When the level of the external terminal P12 changes (time T3), the level of the output signal R1b of the input buffer 43 shown in FIG. 7 changes. The level change of the output signal R1b is detected by the signal transition detection circuit 14, and the H level detection signal Sk is output. The selection circuit 13 shown in FIG. 7 selects the output signal R1a of the input buffer 42 in response to the detection signal Sk at the H level, and outputs the reception data RD1 according to the signal R1a. Therefore, the input / output circuit 31 and the selection circuit 13 shown in FIG. 7 operate as a circuit without a Schmitt function.

  The level change at the external terminal P12 is caused by a signal output from the external device 20, for example. The internal circuit 21 (see FIG. 1) of the external device 20 outputs a signal for the system device 10b, for example, a request signal for requesting a predetermined process, from the external terminal P22. Thus, in a system in which data communication between the system device 10b and the external device 20 is started using the signal output from the external device 20 as a trigger, it is possible to improve resistance to external noise.

  The level change at the external terminal P12 is also caused by a signal transmitted from the system device 10b to the external device 20. For example, the system device 10b transmits a high-speed data to the external device 20 after outputting a signal indicating the start of communication. The level of the external terminal P12 changes based on the signal indicating the start of communication, and the Schmitt function is switched according to this level change. Therefore, it is possible to easily start high-speed communication by changing the state of the input / output circuit 31 with a signal indicating the start of communication (from the presence of Schmitt to the absence of Schmitt).

As described above, according to the present embodiment, the following effects can be obtained.
(3-1) The signal transition detection circuit 14 detects the transition of the reception signal R1b output from the input buffer 43 and sets the detection signal Sk. The selection circuit 13 selects one of the output signal R1a of the input buffer 42 and the output signal R1b of the input buffer 43 according to the detection signal Sk, and outputs the reception data RD1 having the same level as the selected signal. .

  The level change of the reception signal R1b is caused by a level change at the external terminal P12, for example, a signal output from the external device 20. Therefore, in a system in which data communication between the system device 10b and the external device 20 is started using a signal output from the external device 20 as a trigger, it is possible to improve resistance to external noise.

(Fourth embodiment)
Next, a fourth embodiment will be described.
In addition, the same code | symbol is attached | subjected about the same member as said embodiment, and all or one part of the description is abbreviate | omitted.

  As shown in FIG. 9, the system includes a system device 10c and an external device 20 that are connected to each other. The system device 10c includes an interface circuit 12c, a selection circuit 13, and a signal transition detection circuit 14. The interface circuit 12c includes an input / output circuit 31 and a voltage generation circuit 32c.

  The signal transition detection circuit 14 generates a detection signal Sk based on the standby signal STBY and the output signal R1b of the input buffer 43. The signal transition detection circuit 14 resets the detection signal Sk in response to the standby signal STBY at the H level (for example, at the L level). When the standby signal STBY is at the L level, the signal transition detection circuit 14 detects the level transition of the output signal R1b of the input buffer 43 and outputs the H level detection signal Sk.

  The voltage generation circuit 32c controls the voltage value of the drive voltage VD1 in response to the power down signal PDN and the detection signal Sk. For example, the voltage generation circuit 32c generates the drive voltage VD1 having the voltage value V2 in response to the detection signal Sk at the H level and the power down signal PDN at the L level. The voltage generation circuit 32c generates the drive voltage VD1 having the voltage value V1 in response to the L level detection signal Sk and the L level power down signal PDN. Then, the voltage generation circuit 32c generates the drive voltage VD1 having the voltage value V0 in response to the H level power down signal PDN.

Next, the operation will be described.
As shown in FIG. 10, when the standby signal STBY rises from the L level to the H level (time T1), the detection signal Sk is reset to the L level. With this L level detection signal Sk, the voltage value of the drive voltage VD1 changes from the voltage value V2 to the voltage value V1.

  The voltage generation circuit 32c shown in FIG. 9 generates the drive voltage VD1 having the voltage value V1 in response to the L level detection signal Sk (L level power down signal PDN). Therefore, as shown in FIG. 10, the voltage value of the drive voltage VD1 can be changed by the pulsed standby signal STBY.

  Next, when the level of the external terminal P12 changes (time T2), the level of the output signal R1b of the input buffer 43 shown in FIG. 9 changes. The level change of the output signal R1b is detected by the signal transition detection circuit 14, and the H level detection signal Sk is output. The selection circuit 13 shown in FIG. 9 selects the output signal R1a of the input buffer 42 in response to the H level detection signal Sk, and outputs the reception data RD1 corresponding to the signal R1a. Therefore, the input / output circuit 31 and the selection circuit 13 illustrated in FIG. 9 operate as a circuit without a Schmitt function.

As described above, according to the present embodiment, the following effects can be obtained.
(4-1) The signal transition detection circuit 14 resets the detection signal Sk in response to the H level standby signal STBY, detects the level transition of the output signal R1b of the input buffer 43, and sets the detection signal Sk. The voltage generation circuit 32c controls the voltage value of the drive voltage VD1 in response to the power down signal PDN and the detection signal Sk. Therefore, the voltage value of the drive voltage VD1 can be changed by the pulsed standby signal STBY. Since it is not necessary to maintain the standby signal STBY at the H level, it is not necessary to measure the timing for releasing the standby state of the input / output circuit 31, and the processing of the internal circuit 11 can be reduced.

(Fifth embodiment)
Next, a fifth embodiment will be described.
In addition, the same code | symbol is attached | subjected about the same member as said embodiment, and all or one part of the description is abbreviate | omitted.

  As shown in FIG. 11, this system includes a system device 10 and an external device 20a connected to each other. The external device 20a has an interface circuit 22a and a selection circuit 23. The interface circuit 22a includes an input / output circuit 51a and a voltage monitoring circuit 52. The input / output circuit 51 a includes an output buffer 61 and input buffers 62 and 63.

  The input terminal of the input buffer 62 is connected to the external terminal P22. An output terminal of the input buffer 62 is connected to the selection circuit 23. The input buffer 62 outputs a signal R2a corresponding to the level of the external terminal P22. Similarly, the input terminal of the input buffer 63 is connected to the external terminal P22. An output terminal of the input buffer 63 is connected to the selection circuit 23. The input buffer 63 outputs a signal R2b corresponding to the level of the external terminal P22.

  Similar to the input buffer 43 included in the interface circuit 12 of the system apparatus 10, the input buffer 63 is a buffer circuit having Schmitt characteristics. Similarly to the input buffer 42, the input buffer 62 is a buffer circuit having no Schmitt characteristic. For example, the input buffer 62 uses the intermediate voltage level between the voltage level of the high potential side power supply terminal and the voltage level of the low potential side power supply terminal as the threshold voltage. That is, the input buffer 62 has input characteristics corresponding to one threshold voltage. This input buffer 62 has a faster response characteristic than the Schmitt circuit 63. The Schmitt circuit 63 is more resistant to noise mixed in the input signal than the input buffer 62.

  The voltage monitoring circuit 52 is supplied with a drive voltage VD1 which is an operating voltage of the output buffer 61 and the input buffers 62 and 63 included in the input / output circuit 51a. The voltage monitoring circuit 52 monitors the voltage value of the drive voltage VD1, and outputs a control signal ST2 corresponding to the monitoring result. For example, the voltage monitoring circuit 52 compares the voltage value of the drive voltage VD1 with a predetermined threshold value Vt2. The threshold value Vt2 is set to a value between the voltage value V1 and the voltage value V2. The voltage monitoring circuit 52 outputs the control signal ST2 at the L level when the voltage value of the drive voltage VD1 is equal to or higher than the threshold value Vt2, and the H level when the voltage value of the drive voltage VD1 is lower than the threshold value Vt2. The control signal ST2 is output. The control signal ST2 is supplied to the selection circuit 23.

  The selection circuit 23 selects one of the output signal R2a of the input buffer 62 and the output signal R2b of the input buffer 63 in accordance with the control signal ST2, and according to the selected signal (for example, the level of the selected signal Equal to), receive data RD2 is output. For example, the selection circuit 23 selects the output signal R2a of the input buffer 62 in response to the L level control signal ST2, and outputs the reception data RD2 corresponding to the selected signal R2a. On the other hand, the selection circuit 23 selects the output signal R2b of the input buffer 63 in response to the H level control signal ST2, and outputs the reception data RD2 corresponding to the selected signal R2b.

Next, the operation will be described.
As shown in FIG. 12, when the standby signal STBY is at L level, the drive voltage VD1 is a voltage value V2. Accordingly, the output signal R1a of the input buffer 42 shown in FIG. 11 is selected according to the standby signal STBY at the L level. Accordingly, the input / output circuit 31 and the selection circuit 13 illustrated in FIG. 11 operate as a circuit without a Schmitt function. On the other hand, in the interface circuit 22a shown in FIG. 11, since the voltage value of the drive voltage VD1 is higher than the threshold value Vt2, the L level control signal ST2 is output. Accordingly, the output signal R2a of the input buffer 62 shown in FIG. 11 is selected in accordance with the L level control signal ST2. Therefore, the input / output circuit 51a and the selection circuit 23 illustrated in FIG. 11 operate as a circuit without a Schmitt function.

  Next, when the standby signal STBY rises from the L level to the H level (time T1), the voltage value of the drive voltage VD1 changes from the voltage value V2 to the voltage value V1. Then, the output signal R1b of the input buffer 43 shown in FIG. 11 is selected in accordance with the H level standby signal STBY. Therefore, the input / output circuit 31 and the selection circuit 13 illustrated in FIG. 11 operate as a circuit having a Schmitt function.

  When the voltage value of drive voltage VD1 falls below threshold value Vt2, H-level control signal ST2 is output. Accordingly, the output signal R2b of the input buffer 63 shown in FIG. 11 is selected in accordance with the H level control signal ST2. Therefore, the input / output circuit 51a and the selection circuit 23 illustrated in FIG. 11 operate as a circuit having a Schmitt function.

  Next, when the standby signal STBY falls from the H level to the L level (time T2), the output signal R1a of the input buffer 42 shown in FIG. 11 is selected according to the standby signal STBY at the L level. Therefore, the input / output circuit 31 and the selection circuit 13 illustrated in FIG. 11 operate as a circuit without a Schmitt function. On the other hand, in the interface circuit 22a shown in FIG. 11, when the voltage value of the drive voltage VD1 becomes higher than the threshold value Vt2, the L level control signal ST2 is output. Accordingly, the output signal R2a of the input buffer 62 shown in FIG. 11 is selected in accordance with the L level control signal ST2. Therefore, the input / output circuit 51a and the selection circuit 23 illustrated in FIG. 11 operate as a circuit without a Schmitt function.

As described above, according to the present embodiment, the following effects can be obtained.
(5-1) The voltage monitoring circuit 52 included in the interface circuit 22a of the external device 20a monitors the voltage value of the drive voltage VD1, and outputs a control signal ST2 corresponding to the monitoring result. The selection circuit 23 selects one of the output signal R2a of the input buffer 62 and the output signal R2b of the input buffer 63 in accordance with the control signal ST2, and according to the selected signal (for example, the level of the selected signal Equal to), receive data RD2 is output.

  Accordingly, the input / output circuit 51a changes the presence or absence of the Schmitt function according to the voltage value of the drive voltage VD1 supplied from the voltage generation circuit 32 of the system device 10. As described above, the system device 10 controls the operation state (standby state) of the external device 20a and the presence or absence of the Schmitt characteristic. And in the system apparatus 10 and the external apparatus 20a, the tolerance with respect to the noise mixed in the signal in the external terminals P12 and P22 can be improved.

  (5-2) The voltage monitoring circuit 52 outputs an L level control signal ST2 when the voltage value of the drive voltage VD1 becomes higher than the threshold value Vt2. That is, the control signal ST2 is maintained at the H level until the voltage value of the drive voltage VD1 becomes higher than the threshold value Vt2. As described above, by canceling the Schmitt function after the drive voltage VD1 becomes higher than the threshold value Vt2, malfunction when the drive voltage VD1 is low can be suppressed.

(Sixth embodiment)
Next, a sixth embodiment will be described.
In addition, the same code | symbol is attached | subjected about the same member as said embodiment, and all or one part of the description is abbreviate | omitted.

  As shown in FIG. 13, this system has a system device 10b and an external device 20b connected to each other. The external device 20b includes an interface circuit 22a, a selection circuit 23, and a signal transition detection circuit 24. The interface circuit 22a includes an input / output circuit 51a and a voltage monitoring circuit 52.

  The control signal ST2 output from the voltage monitoring circuit 52 is supplied to the signal transition detection circuit 24. The signal transition detection circuit 24 is supplied with the output signal R2b of the input buffer 63. The signal transition detection circuit 24 generates a detection signal Sk2 based on the control signal ST2 and the output signal R2b. For example, the signal transition detection circuit 24 resets the detection signal Sk2 in response to the H level control signal ST2. When the control signal ST2 is at L level, the signal transition detection circuit 24 sets the detection signal Sk2 when detecting the level transition of the output signal R2b of the input buffer 63, that is, outputs the detection signal Sk2 at H level.

  In response to the detection signal Sk2 output from the signal transition detection circuit 24, the selection circuit 23 selects one of the output signal R2a of the input buffer 62 and the output signal R2b of the input buffer 63, and the selected signal The reception data RD2 having a level equal to is output. For example, the selection circuit 23 selects the output signal R2a of the input buffer 62 in response to the H level detection signal Sk2, and outputs the reception data RD2 corresponding to the selected signal R2a. On the other hand, the selection circuit 23 selects the output signal R2b of the input buffer 63 in response to the L level detection signal Sk2, and outputs the reception data RD2 corresponding to the selected signal R2b.

Next, the operation will be described.
As shown in FIG. 14, when the standby signal STBY is at L level, the drive voltage VD1 is a voltage value V2. Therefore, the output signal R1a of the input buffer 42 shown in FIG. 13 is selected in accordance with the L level standby signal STBY. For this reason, the input / output circuit 31 and the selection circuit 13 shown in FIG. 13 operate as a circuit without a Schmitt function. On the other hand, in the interface circuit 22a shown in FIG. 13, since the voltage value of the drive voltage VD1 is higher than the threshold value Vt2, the L level control signal ST2 is output. Accordingly, the output signal R2a of the input buffer 62 shown in FIG. 13 is selected in accordance with the L level control signal ST2. For this reason, the input / output circuit 51a and the selection circuit 23 shown in FIG. 13 operate as a circuit without a Schmitt function.

  Next, when the standby signal STBY rises from the L level to the H level (time T1), the output signal R1b of the input buffer 43 shown in FIG. 13 is selected according to the standby signal STBY at the H level. For this reason, the input / output circuit 31 and the selection circuit 13 illustrated in FIG. 13 operate as a circuit having a Schmitt function.

  When the voltage value of drive voltage VD1 falls below threshold value Vt2, control signal ST2 becomes H level. Therefore, the output signal R2b of the input buffer 63 shown in FIG. 13 is selected in accordance with the H level control signal ST2. For this reason, the input / output circuit 51a and the selection circuit 23 illustrated in FIG. 13 operate as a circuit having a Schmitt function.

  Next, when the standby signal STBY falls from the H level to the L level (time T2), the voltage value of the drive voltage VD1 increases from the voltage value V1 to the voltage value V2. When the voltage value of the drive voltage VD1 becomes equal to or higher than the threshold value Vt2, the control signal ST2 becomes L level. Eventually, the drive voltage VD1 is stabilized at the voltage value V2.

  Next, in the system apparatus 10b, when the level of the external terminal P12 changes (time T3) by transmission from the system apparatus 10b to the external apparatus 20b or transmission from the external apparatus 20b to the system apparatus 10b, the input shown in FIG. The level of the output signal R1b of the buffer 43 changes. The level change of the output signal R1b is detected by the signal transition detection circuit 14, and the H level detection signal Sk is output. The selection circuit 13 shown in FIG. 13 selects the output signal R1a of the input buffer 42 in response to the H level detection signal Sk, and outputs the reception data RD1 corresponding to the signal R1a. Therefore, the input / output circuit 31 and the selection circuit 13 illustrated in FIG. 13 operate as a circuit without a Schmitt function.

  Similarly, in the external device 20b, when the level of the external terminal P22 changes, the level of the output signal R2b of the input buffer 63 shown in FIG. 13 changes. The level change of the output signal R2b is detected by the signal transition detection circuit 24, and an H level detection signal Sk2 is output. The selection circuit 23 shown in FIG. 13 selects the output signal R2a of the input buffer 62 in response to the H level detection signal Sk2, and outputs the reception data RD2 corresponding to the signal R2a. Therefore, the input / output circuit 51a and the selection circuit 23 illustrated in FIG. 13 operate as a circuit without a Schmitt function.

As described above, according to the present embodiment, the following effects can be obtained.
(6-1) The voltage monitoring circuit 52 included in the interface circuit 22a of the external device 20b monitors the voltage value of the drive voltage VD1, and outputs a control signal ST2 according to the monitoring result. The signal transition detection circuit 24 resets the detection signal Sk2 in response to the H level control signal ST2. The signal transition detection circuit 24 sets the detection signal Sk2 when detecting the level transition of the output signal R2b of the input buffer 63 when the control signal ST2 is at the L level. The selection circuit 23 selects the output signal R2a of the input buffer 62 in response to the set detection signal Sk2, and selects the output signal R2b of the input buffer 63 in response to the reset detection signal Sk2.

  Therefore, the input / output circuit 51a enables the Schmitt function when the drive voltage VD1 supplied from the voltage generation circuit 32 of the system apparatus 10b changes to the voltage value V1. The input / output circuit 51a eliminates the Schmitt function according to the change in the reception signal R2b based on the change in the signal level of the external terminal P22. The signal level of the external terminal P22 varies depending on signal transmission from the external device 20b to the system device 10b, for example, a request signal. In this manner, the Schmitt function can be eliminated, that is, the Schmitt function can be canceled by the signal from the external device 20b to the system device 10b.

  (6-2) The voltage monitoring circuit 52 outputs an L level control signal ST2 when the voltage value of the drive voltage VD1 becomes higher than the threshold value Vt2. That is, the control signal ST2 is maintained at the H level until the voltage value of the drive voltage VD1 becomes higher than the threshold value Vt2. The signal transition detection circuit 24 outputs a detection signal Sk2 corresponding to the transition of the reception signal R2b when the control signal ST2 is at the L level.

  Therefore, after the voltage value of the drive voltage VD1 becomes higher than the threshold value Vt2, the Schmitt function is controlled according to the transition of the reception signal R2b, that is, the Schmitt function is released. As described above, by canceling the Schmitt function after the drive voltage VD1 becomes higher than the threshold value Vt2, malfunction when the drive voltage VD1 is low can be suppressed.

(Seventh embodiment)
Next, a seventh embodiment will be described.
In addition, the same code | symbol is attached | subjected about the same member as said embodiment, and all or one part of the description is abbreviate | omitted.

  As shown in FIG. 15, this system includes a system device 10c and an external device 20c connected to each other. The external device 20c includes an interface circuit 22c, a selection circuit 23, and a signal transition detection circuit 24. The interface circuit 22 c includes an input / output circuit 51 a and a command decode circuit 53.

The internal circuit 11 of the system device 10c transmits a predetermined control command (input Schmitt control command) to the external device 20c.
The command decode circuit 53 is supplied with the output signal R2a of the input buffer 62 included in the input / output circuit 51a. The command decode circuit 53 monitors the output signal R2a. The command decode circuit 53 determines whether or not the control command generated by decoding the bit string of the output signal R2a is a predetermined control command (input Schmitt control command). When the command decode circuit 53 receives a predetermined control command (input Schmitt control command), the command decode circuit 53 outputs a pulsed command reception signal SD. The command reception signal SD is supplied to the signal transition detection circuit 24.

  The signal transition detection circuit 24 generates a detection signal Sk2 based on the command reception signal SD and the output signal R2b. For example, the signal transition detection circuit 24 resets the detection signal Sk2 in response to the H level command reception signal SD. The signal transition detection circuit 24 outputs an H level detection signal Sk2 when detecting a level transition of the output signal R2b of the input buffer 63 when the command reception signal SD is at the L level. In response to the detection signal Sk2 output from the signal transition detection circuit 24, the selection circuit 23 selects one of the output signal R2a of the input buffer 62 and the output signal R2b of the input buffer 63, and the selected signal The reception data RD2 having a level equal to is output.

Next, the operation will be described.
As shown in FIG. 16, the terminal level of the external terminal P12 of the system apparatus 10c and the terminal level of the external terminal P22 of the external apparatus 20c are changed by signals transmitted from the system apparatus 10c to the external apparatus 20c. When a predetermined control command is received by the command decode circuit 53 shown in FIG. 15, an H level command reception signal SD is output. The detection signal Sk2 becomes L level by this H level command reception signal SD. The selection circuit 23 shown in FIG. 13 selects the output signal R2b of the input buffer 63 in response to the L level detection signal Sk2, and outputs the reception data RD2 corresponding to the signal R2b. Therefore, the input / output circuit 51a and the selection circuit 23 illustrated in FIG. 13 operate as a circuit having a Schmitt function.

  Next, when the standby signal STBY rises from the L level to the H level (time T1), the detection signal Sk is reset to the L level. With this L level detection signal Sk, the voltage value of the drive voltage VD1 changes from the voltage value V2 to the voltage value V1. The voltage generation circuit 32c shown in FIG. 15 generates the drive voltage VD1 having the voltage value V1 in response to the L level detection signal Sk (L level power down signal PDN). Therefore, as shown in FIG. 16, the voltage value of the drive voltage VD1 can be changed by the pulsed standby signal STBY.

  Next, in the system device 10c, when the level of the external terminal P12 changes (time T2), the level of the output signal R1b of the input buffer 43 shown in FIG. 15 changes. The level change of the output signal R1b is detected by the signal transition detection circuit 14, and the H level detection signal Sk is output. The selection circuit 13 shown in FIG. 15 selects the output signal R1a of the input buffer 42 in response to the H level detection signal Sk and outputs the reception data RD1 corresponding to the signal R1a. Therefore, the input / output circuit 31 and the selection circuit 13 shown in FIG. 15 operate as a circuit without a Schmitt function.

  Similarly, in the external device 20c, when the level of the external terminal P22 changes, the level of the output signal R2b of the input buffer 63 shown in FIG. 15 changes. The level change of the output signal R2b is detected by the signal transition detection circuit 24, and an H level detection signal Sk2 is output. The selection circuit 23 shown in FIG. 15 selects the output signal R2a of the input buffer 62 in response to the H level detection signal Sk2, and outputs the reception data RD2 corresponding to the signal R2a. Therefore, the input / output circuit 51a and the selection circuit 23 shown in FIG. 15 operate as a circuit without a Schmitt function.

As described above, according to the present embodiment, the following effects can be obtained.
(7-1) The command decode circuit 53 included in the interface circuit 22c of the external device 20c decodes the control command according to the level of the reception signal R2a output from the input buffer 62. When the command decode circuit 53 receives a predetermined control command (input Schmitt control command), the command decode circuit 53 outputs a pulsed command reception signal SD. The signal transition detection circuit 24 resets the detection signal Sk2 in response to the H level command reception signal SD. The selection circuit 23 selects the reception signal R2b output from the input buffer 63 according to the reset detection signal Sk2. Therefore, the Schmitt function of the interface circuit 22c of the external device 20c can be changed to be present by a predetermined control command supplied from the system device 10c to the external device 20c. Thereby, the tolerance with respect to an external noise can be improved.

  (7-2) The signal transition detection circuit 24 sets the detection signal Sk2 when detecting the level transition of the output signal R2b of the input buffer 63 when the control signal ST2 is at L level. The selection circuit 23 selects the output signal R2a of the input buffer 62 in response to the set detection signal Sk2. The input / output circuit 51a eliminates the Schmitt function according to the change in the reception signal R2b based on the change in the signal level of the external terminal P22. The signal level of the external terminal P22 changes depending on transmission of a signal from the system apparatus 10c to the external apparatus 20c or transmission of a signal from the external apparatus 20c to the system apparatus 10c. As described above, the Schmitt function can be eliminated, that is, the Schmitt function can be canceled by communication between the system device 10c and the external device 20c.

In addition, you may implement each said embodiment in the following aspects.
In each of the above embodiments, the internal circuit 11 (see FIG. 1) of the system device 10 may be operated by the external power supply voltage VDE or a drive voltage generated based on the external power supply voltage VDE. The internal circuit 21 of the external device 20 may be operated by a drive voltage supplied from the system device 10.

  In each of the above embodiments, the combination of system devices and external devices connected to each other can be changed as appropriate. For example, the external device 20a shown in FIG. 11, the external device 20b shown in FIG. 13, or the external device 20c shown in FIG. 15 may be connected to the system device 10a shown in FIG. Further, the external device 20a shown in FIG. 11 or the external device 20c shown in FIG. 15 may be connected to the system device 10b shown in FIG. Similarly, the external device 20a shown in FIG. 11 or the external device 20b shown in FIG. 13 may be connected to the system device 10c shown in FIG.

  The above embodiments may be embodied in a system device including a plurality of interface circuits. Further, the present invention may be embodied in a system device including an interface circuit that controls the drive voltage and an interface circuit that does not control the drive voltage.

  In each of the above embodiments, the selection circuit 13 may be included in each interface circuit 12, 12a, 12c. The selection circuit 13 and the signal transition detection circuit 14 may be included in each interface circuit 12, 12a, 12c. Similarly, the selection circuit 23 may be included in each interface circuit 22, 22a, 22c. The selection circuit 23 and the signal transition detection circuit 24 may be included in each interface circuit 22, 22a, 22c.

  In each of the above embodiments, the interface circuit 12, 12a, or 12c may include an output circuit including the output buffer 41 and an input circuit including the input buffers 42 and 43. Similarly, interface circuits 22, 22 a and 22 c having an output circuit including the output buffer 61 and an input circuit including the input buffers 62 and 63 may be used.

10 System equipment (semiconductor equipment)
13 Selection Circuit 20 External Device (Semiconductor Device)
31 I / O circuit (input circuit)
32 Voltage generation circuit 42 Input buffer 43 Input buffer (Schmitt circuit)
P12 External terminal R1a First received signal R1b Second received signal STBY Standby signal (control signal)
VD1 drive voltage V2 first voltage value V1 second voltage value

Claims (10)

An external circuit is connected to an external terminal, and is an interface circuit for exchanging signals with the external device,
An input circuit including an input buffer that outputs a first reception signal according to the voltage level of the external terminal, and a Schmitt circuit that outputs a second reception signal according to the voltage level of the external terminal;
A voltage for outputting a drive voltage having a first voltage value or a second voltage value lower than the first voltage value to the input circuit and the external device in accordance with a control signal for controlling an operation state of the input circuit. A generation circuit;
A selection circuit that selects and outputs the first reception signal or the second reception signal according to the control signal;
An interface circuit comprising: A signal transition detection circuit that detects a transition of the second received signal and generates a detection signal;
The selection circuit selects the first reception signal or the second reception signal based on the detection signal;
The interface circuit according to claim 1. The control signal includes a standby signal for switching the input circuit to an operating state or a standby state,
The signal transition detection circuit resets the detection signal based on the standby signal, sets the detection signal according to the transition of the second reception signal,
The selection circuit selects the second reception signal according to the reset detection signal, and selects the first reception signal according to the set detection signal;
The interface circuit according to claim 2. The voltage generation circuit changes a voltage value of the drive voltage according to the detection signal;
The interface circuit according to claim 2 or 3, wherein Transmission data to the external device is input, an output terminal is connected to the external terminal, and an output buffer to which the driving voltage is supplied is provided.
The interface circuit according to claim 1, wherein: The voltage generation circuit outputs a stability signal indicating whether the driving voltage is stable at the first voltage value;
The selection circuit selects the first reception signal when the drive voltage is stable, and selects the second reception signal when the drive voltage is not stable, according to the stability signal. To do,
The interface circuit according to claim 1. An interface circuit in which a system device is connected to an external terminal, and an input / output circuit that operates based on a drive voltage supplied from the system device transmits and receives signals to and from the system device via the external terminal,
The input / output circuit is
An output buffer to which transmission data is supplied and whose output terminal is connected to the external terminal;
A first input buffer for outputting a first reception signal corresponding to the signal level of the external terminal;
A second input buffer having a Schmitt characteristic and outputting a second received signal according to the voltage level of the external terminal;
Including
The interface circuit further includes
A voltage monitoring circuit that generates a control signal by comparing a voltage value of the driving voltage with a threshold value;
A selection circuit that selects and outputs the first reception signal or the second reception signal based on the control signal;
An interface circuit comprising: An interface circuit in which a system device is connected to an external terminal, and an input / output circuit that operates based on a drive voltage supplied from the system device exchanges signals with the system device via the external terminal,
The input / output circuit is
An output buffer to which transmission data is supplied and whose output terminal is connected to the external terminal;
An input buffer for outputting a first reception signal corresponding to the signal level of the external terminal;
A Schmitt circuit that outputs a second received signal in accordance with the voltage level of the external terminal;
Including
The interface circuit further includes
A signal transition detection circuit for detecting a transition of the second received signal and outputting a detection signal;
A selection circuit that selects and outputs the first reception signal or the second reception signal based on the detection signal;
An interface circuit comprising: A voltage monitoring circuit for generating a control signal by comparing a voltage value of the driving voltage with a threshold value;
9. The interface circuit according to claim 8, wherein the signal transition detection circuit resets a detection signal based on the control signal. A command decoding circuit for receiving a control command based on the first reception signal and outputting a command reception signal;
9. The interface circuit according to claim 8, wherein the signal transition detection circuit resets the detection signal based on the command reception signal.