JP2014093619A - Clock parallel type serializer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable the signal type of a signal outputted from each channel to be easily changed, and to restrain a noise component from getting mixed in a data signal.SOLUTION: A clock parallel type serializer circuit 1 comprises: a PLL unit 20 for generating a multiply-by-1 first clock signal 104 on the basis of an inputted reference clock 103 and a second clock signal 105 derived by multiplying the reference clock 103 by a prescribed factor; a plurality of data/clock shared channel units 10 for generating, on the basis of an inputted data/clock selection signal 102, either 1-bit serial data converted from inputted multiple-bit parallel data or a clock signal for synchronizing a receiving circuit side and outputting the generated data or signal as a signal 107; and a load pulse generation unit 30 for generating, on the basis of the second clock signal 105, a load pulse signal 106 for determining output timing for a signal outputted from the plurality of data/clock shared channel units 10.

Description

  The present invention relates to a clock parallel serializer circuit, and more particularly to a circuit capable of selectively outputting either serial data or a clock.

  In recent years, due to the improvement in system performance, the transfer rate required for transferring data between devices and between boards has increased, and for that purpose, it is necessary to widen the bandwidth required for data transfer. In order to widen the band, a method of increasing the number of signal lines used when transferring data can be considered, but increasing the number of signal lines means increasing the number of pins of LSI (Large Scale Integration), Increasing the number of LSI pins may increase the area of the LSI, increase the number of wires on the substrate, and increase the manufacturing cost associated therewith.

  In addition, when the signal changes, there is a risk that noise may occur, and when the number of signal lines is increased, the noise generation factor increases. If changed, there is a problem that it is disadvantageous in terms of noise countermeasures.

  Therefore, recently, in order to solve such a problem, a method is generally used in which parallel data composed of a plurality of signals is converted into serial data bundled into one signal and transmitted. Thereby, compared with the case where parallel data is transmitted as it is, generation | occurrence | production of noise can be suppressed.

  In the method of converting parallel data into serial data and transmitting the serial data transmitted from the transmission side to the reception side, a clock signal as a timing signal is required to return the original parallel data on the reception side. Become.

  As a transmission method of such a clock signal, a method of transmitting a clock signal using a signal line different from a signal line for transmitting serial data, and a method of transmitting a clock signal superimposed on serial data Is used. A circuit that transmits serial data and a clock signal using the former method is generally called a clock parallel serializer circuit.

JP 2002-321407 A

  By the way, a conventional clock parallel serializer circuit includes a data channel for transmitting a data signal and a clock channel for transmitting a clock signal. These channels are usually fixed in position when designing the circuit board, and in order to minimize the delay difference between each data signal and the clock signal, the channels are designed to have equal length wiring. There is a problem that a wiring in which a clock line for transmission straddles a data line for transmitting a data signal may occur, and the base design becomes complicated.

  Further, in order to change the position of the clock channel, it is necessary to be able to output both the data signal and the clock signal in one channel. As described above, as a method for enabling both the data signal and the clock signal to be output, for example, the serial data output from the serializer unit and the clock generated by the PLL or the like at the subsequent stage of the serializer unit provided in the data channel. A method of providing a selector circuit for selecting and outputting one of the signals is used.

  However, in this case, since the signals having different phases of the data signal and the clock signal are input to the selector circuit, a noise component due to the clock signal is mixed into the data signal when operated as a data channel. In particular, when transmitting data signals at high speed, there is a problem that a small amount of noise may have a large effect.

  Accordingly, the present invention has been made in view of the above-described problems in the prior art, and can easily change the signal type of the data signal and the clock signal output from each channel, and the clock for the data signal can be changed. An object of the present invention is to provide a clock parallel type serializer circuit capable of suppressing mixing of noise components caused by signals.

  In order to achieve the above object, the present invention converts a plurality of externally input parallel data into 1-bit serial data and generates a clock signal for synchronizing the receiving circuit side as a transmission destination, A clock parallel serializer circuit for outputting the serial data and the clock signal, wherein the reference clock signal is multiplied by 1 based on a reference clock signal input from the outside, and the reference clock A PLL unit that generates a second clock signal having a predetermined multiplication of the signal, a plurality of channel units that generate either the serial data or the clock signal based on a selection signal input from the outside, and the second unit A load path that determines the output timing of signals output from the plurality of channel units based on the clock signal of Characterized in that it comprises a load pulse generator for generating a scan signal.

  According to the present invention, in each channel unit, parallel data input from the outside is converted into serial data based on the selection signal, and a clock signal is generated based on the first and second clock signals. Each channel unit can selectively output both parallel data and a clock signal, and the signal type of the signal output from each channel unit can be easily changed.

  In the clock parallel serializer circuit, the channel unit includes a clock generation signal output unit that outputs a multi-bit clock generation signal for generating the clock signal, and the parallel data and the selection signal based on the selection signal. A selector unit that selects one of the clock generation signals; a phase synchronization circuit unit that synchronizes the phase of the output signal from the selector unit with the phase of the first clock signal based on the first clock signal; And a serializer unit that converts an output signal from the phase synchronization circuit unit into either the serial data or the clock signal based on the second clock signal and the load pulse signal. Thereby, the change from the conventional circuit can be performed easily.

  In the clock parallel serializer circuit, the clock generation signal may be a fixed value, and the number of bits may be the same as the number of bits of the parallel data. As described above, since signals other than parallel data input to the selector unit are fixed values, noise components mixed in the parallel data can be suppressed.

  In the clock parallel serializer circuit, the number of multiplications of the second clock signal may be the same as the number of bits of the parallel data.

  As described above, according to the present invention, the signal types of the data signal and the clock signal output from each channel can be easily changed, and mixing of noise components caused by the clock signal with respect to the data signal is suppressed. It becomes possible.

1 is a block diagram showing an embodiment of a clock parallel serializer circuit according to the present invention. It is a block diagram which shows an example of a structure of a data / clock shared channel part. It is a time chart for demonstrating the case where a data / clock shared channel part operate | moves as a data channel. It is a time chart for demonstrating the case where a data / clock shared channel part operate | moves as a clock channel.

  Next, an embodiment for carrying out the present invention will be described in detail with reference to the drawings.

  FIG. 1 shows an embodiment of a clock parallel serializer circuit according to the present invention. The clock parallel serializer circuit 1 includes a plurality of data / clock shared channel units 10, 10,. Phase Locked Loop) unit 20, load pulse generation unit 30, and a plurality of differential output buffer units 40, 40,. In this example, four data / clock shared channel units 10A to 10D are used as the data / clock shared channel unit 10, and four differential output buffer units 40A to 40D are used as the differential output buffer unit 40. .

  The data / clock shared channel unit 10A is a circuit that operates as one of a data channel that outputs a data signal and a clock channel that outputs a clock signal. The data / clock shared channel unit 10A generates a signal 107A based on various types of input signals. Generate and output. Parallel data 101A, a data / clock selection signal 102A, a first clock signal 104, a second clock signal 105, and a load pulse signal 106 are input to the data / clock shared channel unit 10A.

  The parallel data 101A is a data signal of a plurality of bits (for example, n bits (n is an integer)) supplied from the outside. The data / clock selection signal 102A is a binary signal supplied from the outside, and determines the operation of the data / clock shared channel unit 10A according to the signal state (signal value).

  The first clock signal 104 is a clock signal that is supplied from a PLL unit 20 described later and has a predetermined frequency. The second clock signal 105 is a clock signal supplied from the PLL unit 20 and multiplied by n with respect to the first clock signal 104.

  The load pulse signal 106 is a signal for determining the output timing of the signal 107A supplied from the load pulse generation unit 30 described later and output from the data / clock shared channel unit 10A.

The data / clock shared channel unit 10A operates as a data channel when the data / clock selection signal 102A is in a predetermined state (for example, the value is “0”), and the input parallel data 101A is converted into serial data 107A ₁ . Converted and output as a signal 107A.

On the other hand, when the data / clock selection signal 102A is in another state (for example, the value is “1”), the data / clock shared channel unit 10A operates as a clock channel, and the receiving circuit side that is the transmission destination is the transmission side. and it outputs the clock signal 107A ₂ for synchronizing with a signal 107A.

  Similar to the data / clock shared channel unit 10A, the data / clock shared channel units 10B to 10D are circuits that operate as one of the data channel and the clock channel. Based on various input signals, the data / clock shared channel units 10B to 10D 107D is generated and output. The data / clock shared channel sections 10B to 10D include parallel data 101B to 101D, data / clock selection signals 102B to 102D, a first clock signal 104, a second clock signal 105, and a load pulse signal 106. Is input to each circuit.

In the data / clock shared channel units 10B to 10D, as in the data / clock shared channel unit 10A, the data / clock selection signals 102B to 102D input to the respective circuits are in a predetermined state (for example, the value is “0”). In this case, it operates as a data channel, converts the input parallel data 101B to 101D into serial data 107B _{1 to} 107D ₁ and outputs them as signals 107B to 107D.

On the other hand, when the data / clock selection signals 102B to 102D are in other states (for example, the value is “1”), the data / clock shared channel units 10B to 10D operate as clock channels, and the clock signals 107B _{2 to} 107D. ₂ is output as signals 107B to 107D.

  Since the data / clock shared channel units 10A to 10D have the same configuration, in the following description, the data / clock shared channel unit 10 will be described as “data / clock shared channel unit 10” unless it is necessary to distinguish between them.

  The PLL unit 20 generates a first clock signal 104 multiplied by 1 with respect to the reference clock 103 and a second clock signal 105 multiplied by n based on the reference clock 103 input from the outside. The generated first clock signal 104 is supplied to each data / clock shared channel unit 10, and the second clock signal 105 is supplied to each data / clock shared channel unit 10 and the load pulse generating unit 30.

  Here, the multiplication number n of the second clock signal 105 is determined by the bit number n of the parallel data 101. For example, when the parallel data 101 is 7 bits, the second clock signal 105 is 7 of the reference clock 103. This is a multiplied clock signal.

The load pulse generator 30 generates a load pulse signal 106 that is synchronized with the second clock signal 105 supplied from the PLL unit 20. The generated load pulse signal 106 is supplied to each data / clock shared channel unit 10, and when parallel data 101 input to the data / clock shared channel unit 10 is converted into serial data 107A _{1 to} 107D ₁ and outputted. And the timing for generating and outputting the clock signals 107A _{2 to} 107D ₂ are determined.

  The differential output buffer unit 40A uses a differential transmission technique such as LVDS (Low Voltage Differential Signaling) to transmit the signal 107A supplied from the data / clock shared channel unit 10A to each pair of signal lines. The differential signals 108A and 109A having opposite phases are output.

  Similarly to the differential output buffer unit 40A, the differential output buffer units 40B to 40D convert the signals 107B to 107D supplied from the data / clock shared channel units 10B to 10D to the differential signals 108B and 109B to the differential signal 108D. And 109D.

  Next, the configuration of the data / clock shared channel unit 10 will be described with reference to FIG. As shown in FIG. 2, the data / clock shared channel unit 10 includes a selector unit 11, a clock generation signal output unit 12, a phase synchronization circuit unit 13, and a serializer unit 14.

  The selector unit 11 receives the parallel data 101 and a clock generation signal 201 supplied from a clock generation signal output unit 12 to be described later, and selects one of the input signals based on the state (value) of the data / clock selection signal 102. Is output as a signal 202. For example, when the data / clock selection signal 102 is in a predetermined state (for example, the value is “0”), the selector unit 11 selects the parallel data 101 and outputs it as the signal 202, and the data / clock selection signal 102 is When it is in another state (for example, the value is “1”), the clock generation signal 201 is selected and output as the signal 202.

  The clock generation signal output unit 12 outputs a clock generation signal 201 for generating a clock signal output when the data / clock shared channel unit 10 operates as a clock channel. The clock generation signal 201 is a multi-bit signal and has the same number as the number of bits of the parallel data 101. Each bit of the clock generation signal 201 outputs a fixed value. This fixed value is set in advance, and what value of the clock generation signal 201 is output from the clock generation signal output unit 12 can be arbitrarily changed.

  The phase synchronization circuit unit 13 receives the signal 202 selected by the selector unit 11 and the first clock signal 104 output from the PLL unit 20, and synchronizes the phase of the signal 202 with the phase of the first clock signal 104. The signal 202 is output as the signal 203.

  The serializer unit 14 receives the signal 203 output from the phase synchronization circuit unit 13, the second clock signal 105 output from the PLL unit 20, and the load pulse signal 106 output from the load pulse generation unit 30. Based on the clock signal 105 and the load pulse signal 106, the signal 203 is converted into a 1-bit serial signal that is phase-synchronized with the second clock signal 105 and output as a signal 107.

  Next, the operation of the data / clock shared channel section 10 in the clock parallel serializer circuit 1 having the above configuration will be described. As described above, since the data / clock shared channel unit 10 operates as one of the data channel and the clock channel, in the following description, the data / clock shared channel unit 10 operates as a data channel and as a clock channel. Will be described in order.

  In the following example, the number of bits of the parallel data 101 is 7 bits, and the data / clock shared channel unit 10 operates as a data channel when the value of the data / clock selection signal 102 is “0”. In the case of “1”, description will be made assuming that it operates as a clock channel.

  First, the case where the data / clock shared channel unit 10 operates as a data channel will be described with reference to the time chart shown in FIG.

  When the data / clock selection signal 102 having a value of “0” is input to the data / clock shared channel unit 10, the data / clock shared channel unit 10 operates as a data channel. Based on the state (value) of the supplied data / clock selection signal 102, the selector unit 11 of the unit 10 includes the input parallel data 101 and the clock generation signal 201 supplied from the clock generation signal output unit 12. The parallel data 101 is selected and output as a signal 202. The output signal 202 is supplied to the phase synchronization circuit unit 13.

  On the other hand, the PLL unit 20 generates a first clock signal 104 and a second clock signal 105 based on the input reference clock 103. The load pulse generator 30 generates a load pulse signal 106 based on the second clock signal 105 supplied from the PLL unit 20.

  Next, the phase synchronization circuit unit 13 receives the signal 202 output from the selector unit 11 and the first clock signal 104 generated by the PLL unit 20, and phase-shifts the signal 202 to the first clock signal 104. Synchronize and output as signal 203. The output signal 203 is supplied to the serializer unit 14.

  The serializer unit 14 receives the signal 203 output from the phase synchronization circuit unit 13, the second clock signal 105 generated by the PLL unit 20, and the load pulse signal 106 generated by the load pulse generation unit 30. Based on the second clock signal 105 and the load pulse signal 106, the signal 203 is phase-synchronized with the second clock signal 105 and output as a signal 107 which is 1-bit serial data.

  Here, the timing for converting the parallel data 101 input to the data / clock shared channel unit 10 into 1-bit serial data is determined by the states of the second clock signal 105 and the load pulse signal 106. Specifically, for example, the serializer unit 14 converts the signal 203 into 1-bit serial data at the timing when the value of the load pulse signal 106 is “1” and the second clock signal 105 rises.

  Next, the case where the data / clock shared channel unit 10 operates as a clock channel will be described with reference to the time chart shown in FIG. In the following description, it is assumed that the clock generation signal output unit 12 of the data / clock shared channel unit 10 outputs a fixed value 7-bit clock generation signal 201 shown in FIG.

  When the data / clock selection signal 102 having a value “1” is input to the data / clock shared channel unit 10, the data / clock shared channel unit 10 operates as a clock channel. Based on the state (value) of the supplied data / clock selection signal 102, the clock generation signal 201 is selected from the input parallel data 101 and the clock generation signal 201 supplied from the clock generation signal output unit 12. And output as a signal 202. The output signal 202 is supplied to the phase synchronization circuit unit 13.

  Next, the phase synchronization circuit unit 13 receives the signal 202 output from the selector unit 11 and the first clock signal 104 generated by the PLL unit 20, and phase-shifts the signal 202 to the first clock signal 104. Synchronize and output as signal 203. The output signal 203 is supplied to the serializer unit 14. The signal 203 is the same signal as the clock generation signal 201 because the state (value) of the clock generation signal 201 output from the clock generation signal output unit 12 does not change.

  The serializer unit 14 receives the signal 203 output from the phase synchronization circuit unit 13, the second clock signal 105 generated by the PLL unit 20, and the load pulse signal 106 generated by the load pulse generation unit 30. Based on the second clock signal 105 and the load pulse signal 106, the signal 203 is phase-synchronized with the second clock signal 105 and output as a signal 107 which is 1-bit serial data.

  Here, the timing at which the parallel data 101 input to the data / clock shared channel unit 10 is converted into 1-bit serial data is the same as that when the data / clock shared channel unit 10 operates as a data channel. For example, the serializer unit 14 sets the signal 203 to 1 at the timing when the value of the load pulse signal 106 is “1” and the second clock signal 105 rises. Convert to bit serial data.

  Therefore, when the data / clock shared channel unit 10 operates as a clock channel, the data / clock shared channel unit 10 outputs a clock signal having the same frequency as that of the reference clock 103.

  Thus, when the data / clock shared channel unit 10 operates as a data channel, the data / clock shared channel unit 10 can appropriately convert the input parallel data 101 into serial data. When the data / clock shared channel unit 10 operates as a clock channel, the data / clock shared channel unit 10 has the same frequency as the reference clock 103 based on the clock generation signal 201 generated by the clock generation signal output unit 12. The clock signal can be output.

  Therefore, any one of the plurality of data / clock shared channel units 10 can be operated as a clock channel, and the other channels can be operated as data channels.

  As described above, according to the present embodiment, since the operation of the data / clock shared channel section can be changed according to the state of the data / clock selection signal, the signal type output from each channel in accordance with the infrastructure design Can be easily changed.

  In addition, since the generation signal for generating the clock signal is input to the selector section provided in the data / clock shared channel section instead of the clock signal itself, the data / clock shared channel section operates as a data channel. In this case, noise components caused by the clock signal are not mixed with the input data, and noise generation can be suppressed.

  Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments of the present invention, and various modifications and applications are possible without departing from the scope of the present invention. It is. For example, the present invention is not limited to a case where any one of a plurality of data / clock shared channel units is operated as a clock channel, and two or more channel units are operated as a clock channel and applied to a so-called dual link technique. It is also possible to do.

  The dual link is a technique mainly used in the field of image processing. For example, all channels are divided into two links (one link is a combination of one clock and a plurality of data), and data is transmitted to each link. By transmitting alternately, the transmission band can be widened.

  Also, for example, when operating a plurality of channel units as clock channels, each channel unit has a clock generation signal transmission unit, so that clock signals having different phases and frequencies can be transmitted in each clock channel. .

DESCRIPTION OF SYMBOLS 1 Clock parallel type serializer circuit 10 (10A, 10B, 10C, 10D) Data / clock shared channel part 11 Selector part 12 Clock generation signal output part 13 Phase synchronization circuit part 14 Serializer part 20 PLL part 30 Load pulse generation part 40 (40A, 40B, 40C, 40D) Differential output buffer 101 (101A, 101B, 101C, 101D) Parallel data 102 (102A, 102B, 102C, 102D) Data / clock selection signal 103 Reference clock 104 First clock signal 105 the second clock signal 106 load pulse signal 107 (107A, 107B, 107C, 107D) signal _{107A 1, 107B 1, 107C 1} , 107D 1 serial data _{107A 2, 107B 2, 107C 2} , 107D 2 Lock signal 108 (108A, 108B, 108C, 108D) the differential signal 109 (109A, 109B, 109C, 109D) the differential signal 201 clock generating signal 202 signal 203 signal

Claims (4)

A clock that converts externally input multi-bit parallel data into 1-bit serial data, generates a clock signal for synchronizing the receiving circuit as a transmission destination, and outputs the serial data and the clock signal A parallel running serializer circuit,
A PLL unit that generates a first clock signal that is multiplied by 1 of the reference clock signal and a second clock signal that is a predetermined multiplication of the reference clock signal based on a reference clock signal input from the outside;
Based on a selection signal input from the outside, a plurality of channel units that generate either the serial data or the clock signal;
A clock parallel serializer circuit, comprising: a load pulse generation unit that generates a load pulse signal that determines an output timing of signals output from the plurality of channel units based on the second clock signal. The channel portion is
A clock generation signal output unit that outputs a clock generation signal of a plurality of bits for generating the clock signal;
A selector unit that selects either the parallel data or the clock generation signal based on the selection signal;
A phase synchronization circuit unit that synchronizes the phase of the output signal from the selector unit with the phase of the first clock signal based on the first clock signal;
2. A serializer unit that converts an output signal from the phase synchronization circuit unit into either the serial data or the clock signal based on the second clock signal and the load pulse signal. The clock parallel serializer circuit described in 1.   The clock parallel serializer circuit according to claim 1, wherein the clock generation signal has a fixed value and the number of bits is the same as the number of bits of the parallel data.   4. The clock parallel serializer circuit according to claim 1, wherein the number of multiplications of the second clock signal is the same as the number of bits of the parallel data. 5.

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