JP2014086351A - Monitoring device of power storage module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a monitoring device of a power storage module which specifies timing error between the measurement timing and the acquisition timing of cell voltage of each power storage cell constituting a power storage module such as a battery pack.SOLUTION: A cell voltage measurement circuit 7 and a timing correction circuit 9 measure the terminal voltage value EC1 or EM1 of a capacitor C which changed depending on a common time constant, and a CPU 5 acquires the terminal voltage value. Based on the terminal voltage value and the time constant, the CPU 5 calculates the measurement timing of cell voltage value VC of the cell voltage measurement circuit 7, and the measurement timing of module voltage value Vm of the timing correction circuit 9. Consequently, the CPU 5 can specify the timing error of acquisition timing for acquiring the cell voltage value VC and module voltage value Vm.

Description

  The present invention relates to a technique for monitoring the voltage of a power storage module.

  For example, module batteries (assembled batteries) in which a plurality of secondary batteries (unit cells) are connected in series are used in hybrid vehicles and electric vehicles. The assembled battery or the single battery is managed by, for example, a voltage detection device, and the voltage detection device detects the voltage of the assembled battery or the single battery. 2. Description of the Related Art Conventionally, a circuit for detecting the voltage of an assembled battery or a single battery is provided, and there is a voltage detection device that performs failure diagnosis of the detection circuit (Patent Document 1). In this voltage detection device, a differential amplifier is connected in parallel for each cell, the cell voltage is measured by the differential amplifier, and the voltage of the assembled battery is measured by the total voltage detection circuit. And by comparing the total voltage of the cell voltage and the voltage (total voltage) of the battery pack, or by comparing the average voltage of the battery voltage (total voltage) and the cell voltage, Performs fault diagnosis of amplifiers and total voltage detection circuits.

JP 2003-134675 A

  By the way, in order to obtain the voltage of each single cell constituting the assembled battery, it is preferable to detect the voltage of each battery at the same time. However, in the above prior art, it is not considered that the timing for detecting the voltage of each battery is shifted. When the cell voltage fluctuates due to a change in ripple voltage or load current, etc. The voltage cannot be calculated correctly.

  In the present specification, a storage module such as an assembled battery is configured in a configuration using a voltage measurement circuit that sequentially selects each of a plurality of input terminals connected to each unit cell of the assembled battery and measures the voltage of each unit cell. Disclosed is a technique capable of specifying a timing error between the timing at which the cell voltage of each storage cell is measured and the timing at which it is acquired.

  A monitoring device for a power storage module in which a plurality of power storage cells disclosed in the present specification are connected in series has a plurality of input terminals to which the power storage cells are connected, and a cell measurement circuit that measures the power storage cells; A time constant circuit having a circuit element having a time constant and generating a reference value that changes according to the time constant; and a control unit, wherein the control unit is configured to change the cell during the fluctuation of the reference value. Obtained by the time constant circuit during a first acquisition process in which a measurement circuit measures the reference value via the input terminal and acquires the reference value as a first reference value and the reference value fluctuates. Based on the second acquisition process for acquiring the reference value as a second reference value, the first reference value, the second reference value, and the time constant, the measurement timing of the cell of the cell measurement circuit, The control unit It has a configuration for executing a timing error specifying process for specifying a timing error between the acquisition timing acquired a value.

  In the monitoring device of the power storage module, the control unit, based on the change amount acquisition process for acquiring the change amount of the reference value within a reference time during the change of the reference value, the reference time and the change amount, And a time constant specifying process for specifying a time constant of the time constant circuit, wherein the timing error specifying process specifies the timing error based on the time constant specified in the time constant specifying process. May be.

  The power storage module monitoring apparatus includes a module measurement circuit that measures the power storage module, and the control unit causes the cell measurement circuit to measure each power storage cell, and a measured value of each power storage cell. Module acquisition processing for acquiring the measurement value of the module by the module measurement circuit at a timing shifted by a time corresponding to the timing error with respect to the acquisition timing.

  The power storage module monitoring apparatus may execute an abnormality determination process for determining a detection abnormality of the power storage module based on the measurement value of the module and the measurement value of the cell.

  In the storage module monitoring apparatus, the cell measurement circuit may include a count circuit that counts time, and according to the count circuit, the measurement timing of the storage cell and the storage module may be matched.

  The technology disclosed in this specification is realized in various modes such as a failure diagnosis device, a failure diagnosis method, a computer program for realizing the functions of these devices or methods, and a recording medium on which the computer program is recorded. can do.

  According to the invention disclosed in this specification, the monitoring device of the storage module identifies a timing error between the timing at which the cell voltage of each storage cell constituting the storage module such as an assembled battery is measured and the acquisition timing. can do.

The block diagram which shows the structure of the battery module which concerns on one Embodiment. Graph showing difference between module voltage measurement timing and cell voltage measurement timing Flow chart of acquisition timing error detection processing Graph showing time variation of capacitor terminal voltage Flow chart of acquisition timing error correction processing

(Outline of the embodiment)

  The power storage module monitoring apparatus according to the present embodiment causes the cell measurement circuit to measure the reference value via the input terminal during the fluctuation of the reference value that changes according to the time constant, and uses the reference value as the first reference value. And the reference value is acquired as the second reference value without going through the cell measurement circuit. Here, the first reference value and the second reference value are reference values that change according to a common time constant. Therefore, the timing error between the measurement timing of the cell measurement circuit and the acquisition timing at which the control unit acquires the measurement value of the cell is specified based on the first reference value, the second reference value, and the time constant. Can do.

  According to the monitoring device of the power storage module, the change amount of the reference value within the reference time is acquired during the change of the reference value, and the time constant is specified based on the reference time and the change amount. And the monitoring apparatus of an electrical storage module specifies a timing error based on the specified time constant. Thereby, when the time constant changes due to a temperature change or the like, the timing error can be specified with higher accuracy than in the configuration in which the time constant is a fixed value.

  According to this storage module monitoring device, the cell measurement circuit measures each storage cell, acquires the measurement value, and is shifted by a time corresponding to the timing error with respect to the acquisition timing of the measurement value of each storage cell. At the timing, the module measurement value by the module measurement circuit is acquired. Thereby, it can suppress that the measurement timing of a cell and a module shifts | deviates.

  According to the monitoring device for the power storage module, the detection abnormality of the power storage module is determined based on the measured value of the module and the measured value of the cell. Thereby, it can suppress that the precision which can perform abnormality determination falls.

  According to this storage module monitoring apparatus, the cell measurement circuit has a count circuit for counting time, and the measurement timings of the storage cell and the storage module are matched according to the count circuit. Thereby, the error specifying process is facilitated, and the burden on the control unit can be reduced.

(Electric configuration of battery pack)
A battery module 1 according to an embodiment will be described with reference to FIGS. 1 to 5. The battery module 1 is an example of a power storage device. The battery module 1 is mounted on, for example, an electric vehicle or a hybrid vehicle (hereinafter simply referred to as an automobile), and supplies power to a power source that is operated by electrical energy under the control of an electronic control unit (hereinafter referred to as ECU) (not shown). It is supplied or charged with electric power from the power source.

  As shown in FIG. 1, the battery module 1 includes a control device 2, an assembled battery 3, and a battery voltage measurement unit 4.

  The control device 2 includes a central processing unit (hereinafter referred to as CPU) 5 and a memory 6. The memory 6 stores various programs for controlling the operation of the battery voltage measuring unit 4. The CPU 5 controls each unit according to the program read from the memory 6. The CPU 5 is an example of a control unit.

  The assembled battery 3 is an example of a power storage module, and is an assembled battery in which, for example, four first cells C1 to fourth cells C4 are connected in series. The assembled battery 3 may have a configuration in which two, three, or five or more cells are connected in series. Moreover, each cell C1-C4 is an example of an electrical storage cell, for example, is secondary batteries, such as a lithium ion battery. However, each of the cells C1 to C4 is not limited to a single battery, and may be a power storage element, and may be a capacitor.

  The battery voltage measurement unit 4 includes a cell voltage measurement circuit 7, a module voltage measurement circuit 8, and a timing correction circuit 9. The cell voltage measurement circuit 7, the module voltage measurement circuit 8, and the timing correction circuit 9 are disposed on a common substrate, for example. The control device 2 and the battery voltage measurement unit 4 are collectively referred to as a cell sensor (hereinafter referred to as CS). The battery voltage measurement unit 4 is an example of a monitoring device.

  The cell voltage measurement circuit 7 measures the voltage values VC1 to VC4 of the cells C1 to C4. The cell voltage measurement circuit 7 includes a multiplexer (hereinafter referred to as MUX) 10 and an A / D converter (hereinafter referred to as ADC) 1. The MUX 10 has a plurality of terminals, for example, six terminals from the first terminal to the sixth terminal. Among them, the first to fourth terminals are connected to the positive side of each of the cells C1 to C4, and the cell voltage measuring circuit 7 is a voltage value VC1 of each of the cells C1 to C4 from the first to fourth terminals of the MUX 10. Measure VC4.

  The cell voltage measurement circuit 7 is an example of a cell measurement circuit, and the voltage values VC1 to VC4 of the cells C1 to C4 are examples of cell measurement values. Further, the cell voltage measurement circuit 7 measuring the voltage values VC1 to VC4 of the cells C1 to C4 is an example of a cell acquisition process.

  Specifically, the cell voltage measurement circuit 7 receives from the CPU 5 a signal for specifying the terminals from the first terminal to the sixth terminal and a trigger signal for acquiring the voltage at the first terminal to the sixth terminal. Then, the cell voltage measurement circuit 7 receives the trigger signal and starts measuring the voltage.

  The cell voltage measurement circuit 7 first measures the voltage value VC1 of the cell C1 with the MUX 10. The MUX 10 includes a timer 11 that counts time, and after starting the measurement of the voltage, the MUX 10 automatically switches the target of the cell for measuring the voltage sequentially based on the timing TZ according to the count time of the timer 11. Then, the cell voltage measurement circuit 7 measures the cell voltage value VC1 of the cell C1.

  Next, the same processing as that of the cell C1 described above is also performed in the cell C2. The cell voltage measurement circuit 7 executes the above-described processing also in the cells C3 and C4. The timer 11 is an example of a count circuit.

  The ADC 1 converts an analog signal having a voltage value measured by the cell voltage measurement circuit 7 using the MUX 10 into a digital signal and stores the digital signal in the register 12. Then, when an instruction to acquire the voltage value VC1 of the cell C1 is transmitted from the CPU 5, the register 12 immediately gives the digital value to the CPU 5 as an output signal.

  Further, since the timing TZ of the timer is determined by the specification of the MUX 10, the timer timing TZ cannot be changed from an external device such as the CPU 5. Therefore, the acquisition timing TD at which the CPU 5 issues an instruction to acquire the voltages of the cells C1 to C4 may not match the measurement timing TB at which the cell voltage measurement circuit 7 measures the voltage of the measurement target cell.

  The module voltage measurement circuit 8 measures the voltage of the assembled battery 3. The module voltage measurement circuit 8 includes resistors R1 and R2 and ADC2. The voltage of the assembled battery 3 is divided by resistors R1 and R2. When a voltage acquisition instruction is transmitted from the CPU 5, the module voltage measurement circuit 8 measures a module voltage value Vm that is a voltage value of the assembled battery 3. Then, the module voltage measuring circuit 8 gives the divided voltage value VBm to the ADC 2 as an analog signal.

  The ADC 2 converts the given voltage value VBm into a digital value. Then, when an acquisition instruction for the module voltage value Vm is transmitted from the CPU 5, the ADC 2 immediately gives the digital value to the CPU 5 as an output signal. The module voltage measurement circuit 8 is an example of a module measurement circuit, and the module voltage value Vm is an example of a module measurement value. Further, the module voltage measurement circuit 8 measuring the module voltage value Vm is an example of a module acquisition process.

  Therefore, when the acquisition instruction of the module voltage value Vm is transmitted from the CPU 5, the module voltage measurement circuit 8 measures the module voltage value Vm and gives the digital value to the CPU 5 as an output signal.

  That is, the difference between the acquisition timing TE at which the CPU 5 instructs to acquire the module voltage value Vm and the measurement timing TF at which the module voltage measurement circuit 8 measures the module voltage value Vm is so small that it can be ignored. Since the CPU 5 can change the timing TE, the timing TD and the timing TE can be set to the same timing.

  The timing correction circuit 9 detects the difference between the voltage measurement timing TB measured by the cell voltage measurement circuit 7 using the MUX 10 and the voltage measurement timing TH measured by the timing correction circuit 9 using the ADC 3 (described later).

  The timing correction circuit 9 includes a constant voltage source Vref, switches SW1 and SW2, a resistor R3, a capacitor C, and an ADC3. The constant voltage source Vref is, for example, a voltage regulator. The switches SW1 and SW2 may be semiconductor switches such as MOSFETs (MOS field effect transistors) or mechanical switches such as mechanical relays. The capacitor C is, for example, a film capacitor. The switch SW1, the resistor R3, and the capacitor C are connected in series from the constant voltage source Vref to the ground. The constant voltage source Vref, the switch SW1, the switch SW2, the resistor R3, and the capacitor C are examples of a time constant circuit.

  The CPU 5 gives a close command signal (also referred to as a close command signal or an ON command signal; hereinafter, unified by the close command signal) to SW1, and sets SW1 to the closed state. The CPU 5 gives the cell voltage measuring circuit 7 a signal for specifying the terminals from the first terminal to the sixth terminal and a trigger signal for acquiring the voltage at the first terminal to the sixth terminal.

  Then, the cell voltage measurement circuit 7 starts measuring the voltage with the MUX 10. The 5th and 6th terminals of the MUX 10 are connected to the capacitor C. This is because the CPU 5 measures the switching time delay when the MUX 10 switches the measurement terminal from the fifth terminal to the sixth terminal.

  The cell voltage measurement circuit 7 measures the terminal voltage value VK of the capacitor C at the 5th and 6th terminals of the MUX, and supplies the terminal voltage value VK to the ADC 1. Note that the cell voltage measurement circuit 7 measuring the terminal voltage value VK of the capacitor C is an example of a first acquisition process, and the terminal voltage value VK of the capacitor C is an example of a first reference value.

  On the other hand, when the acquisition instruction of the terminal voltage value VK of the capacitor C is transmitted from the CPU 5, the timing correction circuit 9 measures the terminal voltage value VK, converts the terminal voltage value VK into a digital value by the ADC 3, and the digital value To the CPU 5 as an output signal.

  That is, the difference between the acquisition timing TG at which the CPU 5 issues an instruction to acquire the terminal voltage value VK of the capacitor C and the measurement timing TH at which the timing correction circuit 9 measures the terminal voltage value VK of the capacitor C is so small that it can be ignored. .

  Since the CPU 5 can change the timing TG, the timing TG, the timing TD, and the timing TE can be set to the same timing. Moreover, the timing correction circuit 9 measuring the terminal voltage value VK of the capacitor C is an example of a second acquisition process, and the terminal voltage value VK of the capacitor C is an example of a second reference value.

  Further, the CPU 5 normally gives a close command signal to SW2, and sets SW2 to a closed state. Thereby, the terminal voltage value VK of the capacitor C is set to 0V. At the start of charging of the capacitor C, the CPU 5 gives an open command signal (also referred to as an open command signal or an off command signal, hereinafter unified by the open command signal) to SW2, and sets SW2 to an open state.

(CS failure detection function)
The CS is equipped with a function for detecting its own failure such as overvoltage or overheating, and when the failure is detected, the failure information is transmitted to the ECU of the vehicle. As the failure diagnosis method, for example, the cell voltage value VC obtained by summing the voltage values VC1 to VC4 of the cells C1 to C4 of the assembled battery 3 is compared with the module voltage value Vm, and the difference becomes a certain level or more. There is a way to make it sometimes out of order.

  And when ECU of a vehicle receives failure information from CS, it performs fail safe control which stops charging / discharging of the assembled battery 3, or stops operation | movement of a vehicle safely. However, if the failure detection function of the CS malfunctions, there arises a problem that the fail-safe function works even though the CS is normal.

(Difference in timing between cell voltage measurement and module voltage measurement)
For example, FIG. 1 does not have the timing correction circuit 9, the cell voltage measurement circuit 7 measures the voltage values VC1 to VC4 of the cells C1 to C4, and the module voltage measurement circuit 8 measures the module voltage value Vm. It is set as the structure only to do.

  In this case, when the cell voltage fluctuates, the cell voltage value VC may not match the module voltage value Vm. The acquisition timing TE at which the CPU 5 issues an instruction to acquire the module voltage value Vm may not coincide with the measurement timing TB at which the cell voltage measurement circuit 7 measures the cell voltage, and the cell voltage value VC and the module voltage value may be different. This is because the Vm acquisition timing is different.

  Further, as described above, the timing TZ is determined by the specification of the MUX 10, and the specification has a large difference between the maximum value and the minimum value of the timing TZ due to individual differences of the MUX 10 and fluctuations due to the environmental temperature. Further, the time from when the ADC 1 receives the voltage values VC1 to VC4 of the cells C1 to C4 from the MUX 10 to convert them into digital values also varies depending on the temperature state of the ADC1.

  For this reason, it is difficult to absorb the timing difference due to the specifications of the MUX 10 and ADC 1 by calibration at the time of shipment. Therefore, it is difficult to match the measurement timing TB when the cell voltage measurement circuit 7 measures the cell voltage with the measurement timing TE when the module voltage measurement circuit 8 measures the module voltage.

  When there is no change in the voltage values VC1 to VC4 of the cells C1 to C4, there is no problem if the CPU 5 does not match the acquisition timing of the cell voltage value VC and the module voltage value Vm. If the voltage values VC1 to VC4 of the cells C1 to C4 fluctuate due to ripples or load fluctuations of the load devices, the cell voltage value VC and the module voltage value Vm are obtained due to the difference in both timings. There will be a difference.

  For example, as shown in FIG. 2, it is assumed that the voltage values VC1 to VC4 of the cells C1 to C4 are fluctuated by noise such as ripple from 4,1V to 4.2V. The cell voltage measurement circuit 7 measures the voltage value VC1 of the cell C1 after TCA elapses from the start of the measurement process, and thereafter measures the voltage values VC2, VC3, VC4 of the cells C2, C3, C4 at TCB intervals.

  On the other hand, the module voltage measurement circuit 8 measures the module voltage value Vm after the TMA elapses from the start of the measurement process, and thereafter measures the voltage of the assembled battery 3 at the TMB interval. In FIG. 2, the module voltage measurement circuit 8 measures the module voltage value Vm, and the value obtained by dividing the voltage by 4 (= 4.2 V) of the number of cells (module voltage measurement) for easy understanding. The values measured by the circuit 8 are described.

  Then, the CPU 5 compares the cell voltage value VC with the module voltage value Vm. In the above case, the cell voltage value VC is 16.4V, but the module voltage value Vm is 16.8V. In other words, since the difference between the two voltages is 0.4 V, the CS erroneously detects an abnormality even though it does not fail.

  Therefore, if the voltage values VC1 to VC4 of the cells C1 to C4 vary, the CS failure detection function malfunctions, so the CPU 5 matches the acquisition timings of the cell voltage value VC and the module voltage value Vm. There is a need. Note that the CPU 5 comparing the cell voltage value VC with the module voltage value Vm is an example of an abnormality determination process.

(Detection of timing difference by timing correction circuit)
The CPU 5 detects the difference between the timing for acquiring the module voltage value Vm measured by the module voltage measuring circuit 8 and the timing for acquiring the voltage values VC1 to VC4 of the cells C1 to C4 measured by the cell voltage measuring circuit 7. The acquisition timing error detection process is started.

  Specifically, as shown in FIGS. 3 and 4, the CPU 5 gives an open command to SW2 and gives a close command to SW1 (S11). CPU5 acquires the terminal voltage value EC1 of the capacitor | condenser C which the cell voltage measurement circuit 7 measured by the 5th terminal of MUX10 after TCZ1 progress after giving a close command to SW1 (S12). Next, the CPU 5 obtains the terminal voltage value EM1 of the capacitor C measured by the timing correction circuit 9 after TMZ1 has elapsed since the close command was given to SW1 (S13).

Note that the values of the capacitor C and the resistor R may vary depending on the temperature environment, and the CPU 5 cannot adjust the timing even if correction is performed in this state. Therefore, for example, the CPU 5 calculates the value of CR from the time TMZ1 and the terminal voltage value EM1 of the corresponding capacitor C using the following formula 1.
<Formula 1>
CR = −t × LN (1-Et / E0)
In Equation 1, t corresponds to TMZ1, Et corresponds to the terminal voltage value EM1 of the capacitor C, and E0 corresponds to Vref. If this CR is used, it is possible to cope with fluctuations in the values of the capacitor C and the resistance R due to fluctuations in the temperature environment. Note that the CPU 5 calculates the CR value as an example of a time constant specifying process.

  Next, the CPU 5 obtains the terminal voltage value ECC of the capacitor C measured by the cell voltage measurement circuit 7 at the sixth terminal of the MUX 10 after TCZC has elapsed since the close command was given to the SW 1 (S14). Then, the CPU 5 obtains the terminal voltage value EMM of the capacitor C measured by the timing correction circuit 9 after TMZM elapses after giving the close command to SW1 (S15).

  Since the capacitor C is connected in series with the resistor R1, the terminal voltage value VK of the capacitor C monotonously increases with time at a certain time constant (FIG. 4). Further, the CPU 5 acquires the terminal voltage value EC1, the terminal voltage value ECC, the terminal voltage value EM1, and the terminal voltage value EMM at different times.

  For this reason, each terminal voltage value becomes a different value. The time constant varies depending on the values of the resistor R and the capacitor C. The acquisition of the terminal voltage value EC1, the terminal voltage value ECC, the terminal voltage value EM1, and the terminal voltage value EMM by the CPU 5 is an example of a change amount acquisition process.

The CPU 5 calculates a time TC1 when the cell voltage measurement circuit 7 measures the terminal voltage value EC1 from the terminal voltage value EC1. Specifically, the CPU 5 calculates the time TC1 using the following formula 2 (S16).
<Formula 2>
t = −C × R × LN (1-Et / E0)
In Equation 2, t corresponds to TC1, Et corresponds to EC1, and E0 corresponds to Vref.

  Similarly, the CPU 5 calculates the time TM1 when the timing correction circuit 9 measures the terminal voltage value EM1 from the terminal voltage value EM1. Specifically, the CPU 5 calculates the time TM1 by the above equation 2. In Equation 2, t corresponds to TM1, Et corresponds to EM1, and E0 corresponds to Vref.

  Then, the CPU 5 calculates the time TCC when the cell voltage measurement circuit 7 measures the terminal voltage value ECC from the terminal voltage value ECC, using Equation 2. The CPU 5 calculates the time TMM for which the timing correction circuit 9 measures the terminal voltage value EMM from the terminal voltage value EMM from Equation 2 (S17 to S19). The order of processing from S16 to S19 does not matter.

  The CPU 5 calculates the difference between the timing for acquiring the terminal voltage of the capacitor C measured by the timing correction circuit 9 and the timing for acquiring the terminal voltage of the capacitor C measured by the cell voltage measurement circuit 7 (S20). Specifically, first, the CPU 5 calculates ΔT1 (= TM1−TC1) from the time TC1 and the time TM1, and calculates the time difference in the start state in which the CPU 5 starts the acquisition timing error detection process.

  Next, the CPU 5 calculates ΔTCM (= TMM−TCC) from the time TCC and the time TMM, and calculates the time difference after the start state. Then, the CPU 5 stores ΔT1 and ΔTCM in the memory 6 (S21), and ends the acquisition timing error detection process. Note that ΔT1 and ΔTCM are examples of timing errors, and the process in which the CPU 5 calculates ΔT1 and ΔTCM is an example of a timing error specifying process.

(Detection of timing difference by timing correction circuit)
The CPU 5 executes an acquisition timing error correction process based on ΔT1 and ΔTCM stored in the memory 6. The CPU 5 can execute the acquisition timing error correction process based on the above ΔT1 and ΔTCM because the CPU 5 gives an acquisition timing TG for instructing acquisition of the terminal voltage value VK of the capacitor C, and the CPU 5 gives an instruction for acquiring the module voltage value Vm. This is because the CPU 5 can make the acquisition timing TE to be the same.

  As shown in FIG. 5, the CPU 5 first corrects the acquisition timing error of the voltage values VC1 to VC4 and the acquisition timing of the module voltage value Vm at the start of acquiring the voltage values VC1 to VC4 of the cells C1 to C4. Therefore, the CPU 5 determines whether or not the acquisition of the voltage value VC1 is started (S31).

  If the CPU 5 determines that it is time to start acquiring the voltage value VC1 (S31: YES), the CPU 5 makes an acquisition request for the module voltage value Vm at the acquisition timing corrected by ΔT1 (S32). Then, the CPU 5 stores the module voltage value Vm in the memory 6 (S33).

  When the CPU 5 determines that the acquisition of the voltage values VC2 to VC4 is not the start of acquisition of the voltage value VC1 (S31: NO), the CPU 5 acquires the module voltage value Vm at the acquisition timing corrected by ΔTCM. A request is made (S35). Then, the CPU 5 stores the module voltage value Vm in the memory 6 (S36).

  The CPU 5 continues the processes of S35 and S36 until it is determined that the acquisition of the voltage values VC1 to VC4 is finished (S37: NO). When the CPU 5 determines that the acquisition of the voltage values VC1 to VC4 has ended (S37: YES), the CPU 5 calculates the sum of the module voltage values Vm stored in the memory 6 (S38), and calculates the average value of the module voltage values Vm. (S39), and the acquisition timing error correction process is terminated.

(Effect of this embodiment)
According to this embodiment, the cell voltage measurement circuit 7 and the timing correction circuit 9 measure the terminal voltage values EC1 and EM1 and the like of the capacitor C that change according to the common time constant, and the CPU 5 determines the terminal voltage value. get. The CPU 5 calculates the measurement timing of the cell voltage value VC of the cell voltage measurement circuit 7 and the measurement timing of the module voltage value Vm of the timing correction circuit 9 based on the terminal voltage value and the time constant. Thereby, the CPU 5 can specify the timing error of the acquisition timing for acquiring the cell voltage value VC and the module voltage value Vm.

<Other embodiments>
The technology disclosed in the present specification is not limited to the embodiments described with reference to the above description and drawings, and includes, for example, the following various aspects.

  In the above embodiment, the CPU 5 calculates ΔT1 and ΔTCM and corrects the time. In other words, the CPU 5 measures the voltage of the assembled battery 3 at a measurement timing such that ΔT1 and ΔTCM are zero. However, the present invention is not limited to this, and the CPU 5 may have a sufficiently small value close to zero, even if ΔT1 and ΔTCM are not completely zero.

  In the above embodiment, the capacitor C is charged, and the terminal voltage value VK of the capacitor C is monotonously increased with time at a certain time constant (FIG. 4). However, the present invention is not limited to this, and the capacitor C may be discharged so that the terminal voltage value VK of the capacitor C decreases monotonously with time with a certain time constant.

  In the above embodiment, the RC circuit has a time constant from the resistor R3 and the capacitor C. However, the present invention is not limited to this, and a configuration having a time constant in the LR circuit from a coil and a resistor may be used, or a configuration having a time constant in an LRC circuit from a coil, a resistor and a capacitor may be used.

  In the above embodiment, the timer 11 is used as an example of the count circuit. However, the configuration is not limited to this, and the count circuit may be automatically switched by a timer IC, a microcomputer, an RC circuit that does not use a clock, or the like.

  In the above embodiment, the fifth and sixth terminals of the MUX 10 are connected to the capacitor C. However, the present invention is not limited to this, and the MUX 10 does not separately prepare a terminal for connecting to the capacitor C. For example, a switching switch is provided at any one of the first terminal to the fourth terminal, and the cell voltage is measured by switching the switch. For example, the voltage of the capacitor C may be measured.

  In the above-described embodiment, the CPU 5 has a configuration in which CR is obtained by Equation 1 using the terminal voltage value EMZ1 of the capacitor C at the time TM1. However, the present invention is not limited to this, and the CPU 5 may be configured to obtain CR based on the terminal voltage value of the capacitor C not only at the time TMZ <b> 1 but also at a certain appropriate time. Further, either the configuration for obtaining CR based on the terminal voltage value of the capacitor C measured by the timing correction circuit 9 or the configuration for obtaining CR based on the terminal voltage value of the capacitor C measured by the cell voltage measurement circuit 7 may be used. .

2: control device, 3: assembled battery, 5: CPU, 6: memory

Claims (6)

A monitoring device for a storage module in which a plurality of storage cells are connected in series,
A plurality of input terminals to which each of the storage cells is connected, and a cell measurement circuit for measuring the storage cells;
A time constant circuit having a circuit element having a time constant, and generating a reference value that changes according to the time constant;
A control unit,
The controller is
A first acquisition process for causing the cell measurement circuit to measure the reference value via the input terminal during the fluctuation of the reference value, and acquiring the reference value as a first reference value;
A second acquisition process for acquiring the reference value obtained by the time constant circuit as a second reference value during the fluctuation of the reference value;
Based on the first reference value, the second reference value, and the time constant, between the measurement timing of the cell of the cell measurement circuit and the acquisition timing at which the control unit acquires the measurement value of the cell. A power storage module monitoring apparatus, comprising: a timing error specifying process for specifying a timing error. It is the monitoring apparatus of the electrical storage module of Claim 1, Comprising:
The controller is
A change amount acquisition process for acquiring a change amount of the reference value within a reference time during the fluctuation of the reference value;
A time constant specifying process for specifying a time constant of the time constant circuit based on the reference time and the amount of change;
In the timing error specifying process, the timing error is specified based on the time constant specified in the time constant specifying process. It is the monitoring apparatus of the electrical storage module of Claim 1 or 2,
A module measuring circuit for measuring the power storage module;
The controller is
A cell acquisition process for causing the cell measurement circuit to measure each of the storage cells;
A module acquisition process for acquiring the measurement value of the module by the module measurement circuit at a timing shifted by a time corresponding to the timing error with respect to the acquisition timing of the measurement value of each storage cell. , Monitoring device for storage module. It is the monitoring apparatus of the electrical storage module of Claim 3, Comprising:
A storage module monitoring device, comprising: an abnormality determination process for determining a detection abnormality of the storage module based on the measurement value of the module and the measurement value of the cell. It is the monitoring apparatus of the electrical storage module of Claim 1, Comprising:
The cell measurement circuit includes a count circuit that counts time, and according to the count circuit, the storage module monitoring device matches the measurement timing of the storage cell and the storage module. A method of monitoring a power storage module in which a plurality of power storage cells are connected in series,
A first acquisition step of causing the cell measurement circuit to measure the reference value via the input terminal during the fluctuation of the reference value, and acquiring the reference value as a first reference value;
A second acquisition step of acquiring the reference value obtained by the time constant circuit as a second reference voltage value during the fluctuation of the reference value;
Based on the first reference value, the second reference value, and the time constant, between the measurement timing of the cell of the cell measurement circuit and the acquisition timing at which the control unit acquires the measurement value of the cell. A method for monitoring a power storage module, comprising: a timing error specifying step for specifying a timing error.

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