JP2014082520A - Semiconductor device, and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a trench structure that is capable of improving a dielectric strength voltage, and provide a method of manufacturing the semiconductor device.SOLUTION: The semiconductor device comprises: a first n-type semiconductor layer 11; a second n-type semiconductor layer 12; a p-type semiconductor layer 13; a trench 3 penetrating the p-type semiconductor layer 13 to the second n-type semiconductor layer 12; an insulator layer 5 formed in a bottom 3a and a side 3b of the trench 3 along the surface of the trench 3; a gate electrode insulated from the second n-type semiconductor layer 12 and the p-type semiconductor layer 13 by the insulation layer 5; and an n-type semiconductor region 14 formed on the p-type semiconductor layer 13 and around the trench 3. At least a part of the gate electrode is formed inside the trench 3. The manufacturing method comprises forming at least a part of the insulation layer 5 in the trench 3 by sputtering.

Description

  The present invention relates to a semiconductor device having a trench structure and a method for manufacturing the same.

  FIG. 5 shows an example of a cross section of a vertical insulated gate semiconductor device having a conventional trench structure. The semiconductor device 9A includes a first n-type semiconductor layer 911, a second n-type semiconductor layer 912, a p-type semiconductor layer 913, an n-type semiconductor region 914, a trench 93, a gate electrode 94, and a gate insulating layer 95.

  The first n-type semiconductor layer 911 is a base of the semiconductor device 9A. The second n-type semiconductor layer 912 is formed on the first n-type semiconductor layer 911. The p-type semiconductor layer 913 is formed on the second n-type semiconductor layer 912. The n-type semiconductor region 914 is formed on the p-type semiconductor layer 913.

  The trench 93 is formed so as to penetrate the p-type semiconductor layer 913 and the n-type semiconductor region 914 and reach the second n-type semiconductor layer 912. A gate electrode 94 and a gate insulating layer 95 are formed inside the trench 93. The gate insulating layer 95 insulates the gate electrode 94 from the second n-type semiconductor layer 912, the p-type semiconductor layer 913, and the n-type semiconductor region 914. The gate insulating layer 95 is formed along the inner surface of the trench 93.

  The semiconductor device 9A is manufactured using the semiconductor substrate 9A 'shown in FIG. The semiconductor substrate 9A 'includes a first n-type semiconductor layer 911, a second n-type semiconductor layer 912, a p-type semiconductor layer 913, an n-type semiconductor region 914, and a spare trench 93'.

  First, the side and bottom portions of the preliminary trench 93 'are thermally oxidized. Thereby, the gate insulating layer 95 is formed on the surface of the trench 93 shown in FIG. Then, the gate electrode 94 is formed in the recess formed by the gate insulating layer 95, and the semiconductor device 9A is completed.

  In order to improve the withstand voltage of the semiconductor device 9A, it is known to increase the thickness of the bottom 95a of the gate insulating layer 95 (see Patent Document 1). When the gate insulating layer 95 is formed by thermal oxidation, if the bottom portion 95a of the gate insulating layer 95 is thickened, the side portion 95b of the gate insulating layer 95 is also thickened at the same time. When the side portion 9b of the gate insulating layer 95 is thickened, the response of the semiconductor device 9A to the voltage applied to the gate electrode 94 is deteriorated. Therefore, increasing the thickness of the bottom portion 95a of the gate insulating layer 95 in order to improve the withstand voltage of the semiconductor device 9A is limited. As described above, when the gate insulating layer 95 is formed only by thermal oxidation, it is difficult to improve the withstand voltage of the semiconductor device 9A having a trench structure.

Japanese Patent Laid-Open No. 01-192174

  The present invention has been conceived under the circumstances described above, and an object of the present invention is to provide a semiconductor device having a trench structure capable of improving the withstand voltage and a method for manufacturing the same.

A method of manufacturing a semiconductor device provided by the first aspect of the present invention includes a first semiconductor layer having a first conductivity type, and provided on the first semiconductor layer, opposite to the first conductivity type. A second semiconductor layer having a second conductivity type; a trench penetrating the second semiconductor layer to reach the first semiconductor layer; and formed at a bottom portion and a side portion of the trench along a surface of the trench. An insulating layer, a gate electrode formed at least partially within the trench, and insulated from the first semiconductor layer and the second semiconductor layer by the insulating layer, on the second semiconductor layer, and And a semiconductor region having the first conductivity type formed around the trench, wherein at least a part of the insulating layer is formed in the trench by sputtering. Has process It is characterized in Rukoto.

  According to such a configuration, it is possible to form the insulating layer having a desired thickness at a desired position of the trench. In particular, the desired insulating layer can be formed on the bottom or side of the trench regardless of the material constituting the first semiconductor layer, the second semiconductor layer, or the semiconductor region, and the plane orientation. Thereby, the insulating layer is formed thick at the bottom of the trench, and the withstand voltage of the semiconductor device can be improved.

  In a preferred embodiment of the present invention, before the step of forming the insulating layer, the method includes a step of forming a preliminary trench whose bottom reaches the first semiconductor layer, and the step of forming the insulating layer includes: A step of thermally oxidizing the bottom and side portions of the preliminary trench to form the trench and the first insulating portion along the surface of the trench so as to cover the bottom portion of the first insulating portion. Forming a second insulating portion by sputtering, and after the step of forming the insulating layer, the gate is formed in the recess formed by the first insulating portion and the second insulating portion. The method further includes the step of forming at least a part of the electrode. According to such a configuration, when the second insulating portion is formed, the first insulating portion covers the side portion and the bottom portion of the trench. Therefore, the second insulating part can be formed by sputtering without damaging the side part or the bottom part of the trench.

  A semiconductor device provided by the second aspect of the present invention includes a first semiconductor layer having a first conductivity type, and a second semiconductor layer provided on the first semiconductor layer and opposite to the first conductivity type. A second semiconductor layer having a conductivity type, a trench penetrating the second semiconductor layer to reach the first semiconductor layer, and an insulating layer formed on the bottom and sides of the trench along the surface of the trench And a gate electrode that is insulated from the first semiconductor layer and the second semiconductor layer by the insulating layer and at least partially formed inside the trench; and on the second semiconductor layer and the trench. A semiconductor region having the first conductivity type formed around the semiconductor device, wherein the thickness of the insulating layer at the bottom of the trench is equal to the thickness of the insulating layer at the side of the trench. Bigger than that The insulating layer includes a first insulating portion formed along the inner surface of the trench, and a second insulating portion surrounded by the first insulating portion and the gate electrode. It is a feature.

  Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

  Hereinafter, preferred embodiments of the present invention will be specifically described with reference to the drawings.

  FIG. 1 shows an example of an embodiment of a semiconductor device according to the present invention. The semiconductor device A of this embodiment includes a first n-type semiconductor layer 11, a second n-type semiconductor layer 12, a p-type semiconductor layer 13, a high-concentration p-type semiconductor region 13a, an n-type semiconductor region 14, a trench 3, a gate electrode 41, A gate insulating layer 5, a source electrode 42, a drain electrode 43, and an interlayer insulating film 6 are provided.

The first n-type semiconductor layer 11 is a substrate made of a material obtained by adding high-concentration impurities to silicon carbide, and serves as a base for the semiconductor device A. The second n-type semiconductor layer 12 is formed on the first n-type semiconductor layer 11. The second n-type semiconductor layer 12 is made of a material obtained by adding a low concentration impurity to silicon carbide. The size of the second n-type semiconductor layer 12 in the depth direction x is about 10 μm. The p-type semiconductor layer 13 is formed on the second n-type semiconductor layer 12. The size of the p-type semiconductor layer 13 in the depth direction x is about 0.7 μm. The n-type semiconductor region 14 is formed on the p-type semiconductor layer 13. The size of the n-type semiconductor region 14 in the depth direction x is about 0.3 μm. The high concentration p-type semiconductor region 13 a is formed on the p-type semiconductor layer 13.

  The trench 3 is formed so as to penetrate the p-type semiconductor layer 13 and the n-type semiconductor region 14 and reach the second n-type semiconductor layer 12. The size of the trench 3 in the depth direction x is greater than or equal to the size of the p-type semiconductor layer 13 in the depth direction x. In the present embodiment, the bottom 3a of the trench 3 is located at an intermediate portion of the second n-type semiconductor layer 12 in the depth direction x.

  A gate electrode 41 and a gate insulating layer 5 are formed inside the trench 3. The gate insulating layer 5 insulates the gate electrode 41 from the second n-type semiconductor layer 12, the p-type semiconductor layer 13, and the n-type semiconductor region 14. The gate insulating layer 5 includes a first insulating part 51 and a second insulating part 52. The first insulating portion 51 is formed on the bottom 3 a and the side 3 b of the trench 3 along the inner surface of the trench 3. In the present embodiment, the first insulating portion 51 is made of silicon dioxide. The second insulating part 52 is surrounded by the first insulating part 51 and the gate electrode 41. The second insulating part 52 is made of, for example, silicon dioxide or alumina.

  The size L1 in the width direction y of the side portion of the gate insulating layer 5 is, for example, 0.1 μm. On the other hand, the size L2 of the bottom of the gate insulating layer 5 is, for example, 4 μm. Here, the size L1 is smaller than the size L2. Further, the size L3 of the bottom portion of the first insulating portion 51 is, for example, 0.05 μm. The size L4 of the bottom portion of the second insulating portion 52 is, for example, 3.95 μm.

  The source electrode 42 is made of, for example, Al and is in contact with the n-type semiconductor region 14 and the high-concentration p-type semiconductor region 13a. The drain electrode 43 is also made of, for example, Al and is in contact with the first n-type semiconductor layer 11. The drain electrode 43 is formed on the side where the second n-type semiconductor layer 12 is formed and on the opposite side across the first n-type semiconductor layer 11. The interlayer insulating film 6 is formed so as to cover the gate electrode 41.

  Next, an example of a manufacturing method of the semiconductor device A will be described below with reference to FIGS.

  First, as shown in FIG. 2, a semiconductor substrate to be the first n-type semiconductor layer 11 is prepared. Next, an n-type semiconductor layer is formed on the surface side of the substrate by an epitaxial crystal growth method. Next, a mask having a predetermined shape is formed on the upper surface of the n-type semiconductor layer, and impurity ions (p-type) are implanted. Next, impurity ions (n-type or p-type) are similarly implanted to form the second n-type semiconductor layer 12, the p-type semiconductor layer 13, the n-type semiconductor region 14, and the high-concentration p-type semiconductor region 13a. .

  Next, the preliminary trench 3 ′ is formed so as to penetrate the n-type semiconductor region 14 and the p-type semiconductor layer 13. At this time, the bottom 3 ′ a of the preliminary trench 3 ′ reaches the second n-type semiconductor layer 12. The depth L5 of the preliminary trench 3 'is 2.0 μm, for example.

Next, the side 3′b and the bottom 3′a of the preliminary trench 3 ′ are thermally oxidized. An oxide film grows on the surface of the spare trench 3 ′ and in the second n-type semiconductor layer 12, the p-type semiconductor layer 13, and the n-type semiconductor region 14 near the surface of the spare trench 3 ′. And as shown in FIG. 3, the trench 3 and the 1st insulating part 51 are formed. The first insulating portion 51 is formed on the bottom 3 a and the side 3 b of the trench 3.

  Next, as shown in FIG. 4, the second insulating portion 52 is formed by sputtering above the bottom of the first insulating portion 51 in the drawing. An insulator is sputtered toward the trench 3 from above in the figure. Therefore, an insulating layer is also formed near the opening of the trench 3. Thereafter, the insulating layer is removed. Note that it is not always necessary to remove this insulating layer.

  Next, the gate electrode 41 is formed in the recess formed by the first insulating part 51 and the second insulating part 52. Next, an interlayer insulating film 6 made of silicon dioxide or the like is formed so as to cover the gate electrode 41 by CVD (Chemical Vapor Deposition). Finally, the source electrode 42 and the drain electrode 43 are formed. Through the above steps, the manufacture of the semiconductor device A shown in FIG. 1 is completed.

  Next, the operation of the semiconductor device and the manufacturing method thereof according to the present invention will be described.

  By forming the second insulating portion 52 by sputtering, it is possible to form the gate insulating layer 5 having a desired thickness at a desired position in the trench 3. Therefore, a desired gate insulating layer 5 can be formed at the bottom 3a of the trench regardless of the plane orientation of the silicon carbide substrate constituting the second n-type semiconductor layer 12 and the like. In particular, even if the surface of the second n-type semiconductor layer 12 or the like is a Si surface, the gate insulating layer 5 having a desired thickness can be formed on the bottom 3a of the trench 5 regardless of the plane orientation. As a result, the withstand voltage of the semiconductor device A can be improved.

  When the second insulating portion 52 is formed, the first insulating portion 51 covers the side 3b and the bottom 3a of the trench. Therefore, the second insulating portion 52 can be formed by sputtering without damaging the side 3b and the bottom 3a of the trench.

  The semiconductor device and the manufacturing method thereof according to the present invention are not limited to the above-described embodiments. The specific configuration of each part of the semiconductor device and the manufacturing method thereof according to the present invention can be varied in design in various ways.

  The material constituting the first semiconductor layer of the semiconductor device according to the present invention is not limited to silicon carbide. For example, GaN, diamond, Si, etc. may be used. In addition, the first insulating portion of the semiconductor device according to the present invention is not necessarily formed by thermal oxidation. For example, CVD may be used to form the first insulating portion. Moreover, you may form the insulating layer in the semiconductor device concerning this invention using only sputtering.

  Note that the first semiconductor layer, the second semiconductor layer, and the semiconductor region referred to in the present invention do not have to be formed in a flat plate shape as shown in the above embodiment. These may be formed along the trench referred to in the present invention.

It is principal part sectional drawing which shows an example of the semiconductor device concerning this invention. It is principal part sectional drawing which shows a one part process in the manufacturing method concerning this invention. FIG. 3 is a fragmentary cross-sectional view showing a step that follows FIG. 2. FIG. 4 is a fragmentary cross-sectional view showing a step that follows FIG. 3. It is principal part sectional drawing which shows an example of the conventional semiconductor device. It is principal part sectional drawing which shows a one part process in the manufacturing method of the conventional semiconductor device.

A semiconductor device 11 first n-type semiconductor layer 12 second n-type semiconductor layer 13 p-type semiconductor layer 13a high-concentration p-type semiconductor region 14 n-type semiconductor region 3 trench 3 ′ spare trench 3a, 3′a bottom 3b, 3′b side Part 41 gate electrode 42 source electrode 43 drain electrode 5 gate insulating layer 51 first insulating part 52 second insulating part 6 interlayer insulating film x depth direction y width direction

Claims (3)

A first semiconductor layer having a first conductivity type;
A second semiconductor layer provided on the first semiconductor layer and having a second conductivity type opposite to the first conductivity type;
A trench that penetrates through the second semiconductor layer and reaches the first semiconductor layer;
An insulating layer formed on the bottom and sides of the trench along the surface of the trench;
A gate electrode which is insulated from the first semiconductor layer and the second semiconductor layer by the insulating layer, and at least a part of which is formed inside the trench;
A semiconductor region having the first conductivity type formed on the second semiconductor layer and around the trench;
A method for manufacturing a semiconductor device comprising:
A method for manufacturing a semiconductor device, comprising the step of forming at least a part of the insulating layer in the trench by sputtering. Before the step of forming the insulating layer, the step of forming a preliminary trench whose bottom reaches the first semiconductor layer,
The step of forming the insulating layer includes thermally oxidizing the bottom and side portions of the preliminary trench to form the trench and the first insulating portion along the surface of the trench;
Forming a second insulating part by sputtering so as to cover the bottom of the first insulating part,
After the step of forming the insulating layer, the method further includes the step of forming at least a part of the gate electrode in the recess formed by the first insulating portion and the second insulating portion.
A method for manufacturing a semiconductor device according to claim 1. A first semiconductor layer having a first conductivity type;
A second semiconductor layer provided on the first semiconductor layer and having a second conductivity type opposite to the first conductivity type;
A trench that penetrates through the second semiconductor layer and reaches the first semiconductor layer;
An insulating layer formed on the bottom and sides of the trench along the surface of the trench;
A gate electrode which is insulated from the first semiconductor layer and the second semiconductor layer by the insulating layer, and at least a part of which is formed inside the trench;
A semiconductor region having the first conductivity type formed on the second semiconductor layer and around the trench;
A semiconductor device comprising:
The thickness of the insulating layer at the bottom of the trench is greater than the thickness of the insulating layer at the side of the trench;
The insulating layer includes a first insulating portion formed along the inner surface of the trench, and a second insulating portion surrounded by the first insulating portion and the gate electrode. Semiconductor device.

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