JP2014081783A - Microcontroller, handler address specification method and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a microcontroller, a handler address specification method and a program capable of arranging a handler with a high degree of freedom and at low cost, and specifying a handler address at a high speed.SOLUTION: A microcontroller 100 includes: an interruption controller 200 for, in accordance with the input of an interruption request due to a plurality of interruption factors, outputting control information preliminarily associated with the interruption factors to a CPU 300; handler storage means 401 for storing an interruption handler preliminarily associated with the control information; base address storage means 402 for storing a base address, an access time to which is shorter than that of the handler storage means 401; and a CPU 300 connected to the base address storage means 402. The CPU 300 specifies the handler address as the storage position of the handler in the handler storage means 401 on the basis of the base address and the control information.

Description

  The present invention relates to a microcontroller, a handler address specifying method, and a program, and more particularly to a technique for specifying a handler address.

  The microcontroller has a function of interrupting a program being executed and calling a pre-registered program when an error occurs in a calculation result or when a processing request is sent from a peripheral device. This is called interruption. At this time, a program that is called in accordance with the type of interrupt request and is waiting on the memory for processing and controlling the interrupt is referred to as an interrupt handler (hereinafter referred to as an interrupt handler or handler). Conventionally, a method for specifying a storage address of a handler to be executed (hereinafter referred to as a handler address) in response to an interrupt request to a microcontroller has been proposed.

  Patent Document 1 discloses a fixed vector interrupt method and a variable vector interrupt method as methods for specifying a handler address. In the fixed vector interrupt method, a plurality of handler addresses associated with a plurality of interrupt levels are stored in the register IHA. Then, according to the interrupt level of the generated interrupt request, the handler address corresponding to the interrupt level is selected from the register IHA. The fixed vector interrupt method is characterized in that the processing time is short and the contents of the register IHA can be set freely, so that the degree of freedom is high. On the other hand, the variable vector interrupt method is a method in which a vector number is fetched when an interrupt occurs, a vector table entry is calculated based on the vector number, and a handler address is specified. The variable vector interrupt method also has the advantage of a high degree of freedom.

  Patent Document 1 further discloses a configuration in which these methods can be selected in order to complement the features of the fixed vector interrupt method and the variable vector interrupt method. Specifically, for each of a plurality of interrupt levels, a method for specifying a handler address to be adopted is associated with each other in advance and stored in the register IVC, and from the register IVC according to the interrupt level of the generated interrupt request. A method for specifying a handler address corresponding to the interrupt level is selected.

Japanese Patent Laid-Open No. 06-324884

  In the device described in Patent Document 1, because of the fixed vector interrupt method, the register IHA stores all of a plurality of handler addresses corresponding to a plurality of interrupt levels. In such a configuration, the size of the register IHA increases as the types of interrupt levels increase. In general, a register used for the register IHA has a shorter access time than a general-purpose flash memory or the like, in other words, a high speed, but an area (cost) per unit bit is expensive. Therefore, there is a problem that an increase in registers causes an increase in circuit size and manufacturing cost. Therefore, a handler address specifying method capable of realizing a small size and low cost while maintaining the features of high speed and high flexibility is desired.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

According to one embodiment, the microcontroller is a microcontroller that executes an interrupt handler in response to an interrupt request from a plurality of interrupt factors,
First storage means for storing a base address used for specifying a handler address which is an address indicating a storage position of the interrupt handler; and second storage means for storing the interrupt handler;
In response to the input of the interrupt request, an interrupt controller that outputs control information associated with the interrupt factor in advance,
In response to an interrupt request output from the interrupt controller, a CPU for acquiring and executing the interrupt handler is provided.
The access time from the CPU to the first storage means is shorter than the access time from the CPU to the second storage means, and
The CPU
(A) In response to the interrupt request output from the interrupt controller, the first storage means is accessed to obtain the base address;
(B) identifying the handler address based on the acquired base address and the control information output from the interrupt controller;
(C) Based on the specified handler address, the second storage means is accessed to execute the interrupt handler.

According to another embodiment, the microcontroller is a microcontroller that executes an interrupt handler in response to an interrupt request from a plurality of interrupt factors,
In response to the input of the interrupt request, the interrupt request, the first or second control information associated in advance with the interrupt factor, and the handler address specifying method information associated in advance with the interrupt factor An interrupt controller that outputs
CPU that acquires and executes the first interrupt handler or the second interrupt handler in response to an interrupt request output from the interrupt controller;
A first base address used to specify a first handler address which is an address indicating a storage location of the first interrupt handler, and an address indicating a storage location of the second interrupt handler. First storage means for storing a second base address used to identify the two handler addresses;
A first interrupt handler storage area for storing each of the plurality of first interrupt handlers in a fixed-size individual area prepared in advance in the order specified by the first control information; A table storage area that stores a handler address table that associates the control information with the second handler address in advance, and a first interrupt handler storage area that stores the first interrupt handler. Storage means,
The access time from the CPU to the first storage means is shorter than the access time from the CPU to the second storage means, and
The CPU
(A) When the handler address specifying method information indicates a direct branch method,
(A) In response to the interrupt request output from the interrupt controller, the first storage means is accessed to obtain the first base address,
(B-2) Based on the first base address, the order specified by the first control information, and the fixed size of the individual area for storing each of the interrupt handlers in the first handler storage area Identifying the first handler address from
(C) accessing the second storage means based on the identified first handler address to execute the first interrupt handler;
(B) When the handler address specifying method information indicates a table reference method,
(A) In response to the interrupt request output from the interrupt controller, the first storage means is accessed to obtain the second base address;
(B-1) Refers to the handler address table based on the second base address, and the second address associated with the second control information output from the interrupt controller in the handler address table. Identify the handler address,
(C) Based on the specified second handler address, the second storage means is accessed to execute the second interrupt handler.

According to another embodiment, the handler address specifying method is performed by the CPU:
A step of inputting control information corresponding to the interrupt factor from the interrupt controller;
Obtaining a base address from the first storage means;
Identifying a handler address which is a storage location of the handler in the second storage means based on the base address and the control information,
The access time from the CPU to the first storage means is shorter than the access time from the CPU to the second storage means.

According to another embodiment, the handler address specifying method is performed by the CPU:
Inputting from the interrupt controller the first or second control information corresponding to the interrupt factor and the handler address specifying method information corresponding to the interrupt factor;
(A) When the handler address specifying method information indicates a direct branch method,
Obtaining a first base address from a first storage means;
Identifying a first handler address that is a storage location of the first handler from a first handler storage area in a second storage means based on the first base address and the first control information;
(B) When the handler address specifying method information indicates a table reference method,
Obtaining a second base address from the first storage means;
Identifying a second handler address from a handler address table based on the second base address and the second control information,
The first handler storage area is stored in an order based on the first control information in a fixed-size individual area for storing the first handler,
The first base address is an address indicating a storage position of the first handler storage area in the second storage means,
The handler address table is a table in which the second control information and the second handler address are associated with each other in advance.
The second base address is an address indicating a storage position of a handler address table in the second storage means,
The access time from the CPU to the first storage means is shorter than the access time from the CPU to the second storage means.

  According to another embodiment, the program causes a computer to execute any one of the methods described above.

  According to the present invention, it is possible to provide a microcontroller, a handler address specifying method, and a program capable of specifying a handler address at high speed while arranging handlers with high flexibility and low cost.

1 is a diagram showing a configuration of a microcontroller 100 according to a first exemplary embodiment. 1 is a diagram showing a configuration of a microcontroller 100 according to a first exemplary embodiment. It is a figure which shows the structure of the interruption controller 200 concerning Embodiment 1. FIG. FIG. 3 is a diagram showing a configuration of an interrupt control register 206 according to the first embodiment. FIG. 3 is a diagram showing a configuration of base registers 4020 and 4030 according to the first embodiment. 3 is a flowchart showing processing of the microcontroller 200 according to the first embodiment. FIG. 10 is a diagram showing an arrangement of handlers in the memory 4010 according to the first embodiment. 3 is a timing chart showing processing of the microcontroller 200 according to the first exemplary embodiment. It is a figure which shows the structure of the interrupt control register 206 concerning Embodiment 2. FIG. 10 is a flowchart showing processing of the microcontroller 200 according to the second embodiment. FIG. 10 is a diagram showing an arrangement of handlers in a memory 4010 according to the second embodiment. FIG. 10 is a diagram illustrating a configuration of an interrupt control register 206 according to the third embodiment. 10 is a flowchart showing processing of the microcontroller 200 according to the third embodiment. FIG. 10 is a diagram showing an arrangement of handlers in a memory 4010 according to the third embodiment.

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings.

<Embodiment 1>
In the present embodiment, there are two handler address specifying methods: a table reference method that is lower in cost than the above-described fixed vector allocation method, and a direct branch method that enables a faster interrupt response than the table reference method. Is disclosed.

  First, an outline of the table reference method will be described. In the table reference method, the handler address table base register (HTBASE) stores the top address of the handler address table, and the handler address table stores a plurality of handler addresses corresponding to a plurality of interrupt factors. Then, in response to the generation of the interrupt request, the CPU acquires the head address of the handler address table from the register HTBASE, and selects the handler address corresponding to the interrupt factor of the interrupt request from the handler address table.

  In the table reference method, the handler address table can be stored in a general-purpose flash memory or the like that is slower than a register but has a lower area (cost) per unit bit. Therefore, the table reference method can reduce the cost required for the register IHA in the fixed vector interrupt method described in Patent Document 1.

  With this configuration, the present embodiment realizes specification of a handler address with a small size and low cost while maintaining the features of high speed and high flexibility.

  On the other hand, there is a demand for faster interrupt responsiveness. Therefore, in this embodiment, in order to respond to this further request, the identification of the handler address by the direct branch method is also supported. According to the direct branch method, it is possible to realize an interrupt response faster than the table reference method.

  An outline of the direct branching method will be described. In the direct branch method, the handler address base register (HABASE) stores the base address. In addition, a memory (such as a general-purpose flash memory) stores a plurality of handlers corresponding to a plurality of interrupt levels (for example, priority) in order of priority starting from the base address. Here, the size of the storage area of each handler is fixed uniformly. Therefore, based on the base address and the priority, the address (handler address) of the storage area of the handler corresponding to the priority is uniquely specified. When an interrupt request is generated, the CPU acquires a base address from the register HABASE, and specifies a handler address from the base address and the priority of the interrupt request.

  The direct branch method is faster than the table reference method because it does not require a step of referring to the handler address table. However, the direct branching method has a restriction that the size of the storage area of the handler is fixed.

  The configuration of the microcontroller 100 having the above-described features will be described with reference to FIG.

  The microcontroller 100 according to the present embodiment includes at least an interrupt controller 200, a CPU 300, a handler storage unit 401, and a base address storage unit 402.

  The handler storage unit 401 is a storage unit that stores an interrupt handler as a second storage unit. The storage address of the interrupt handler in the handler storage unit 401 is called a handler address. For example, a general-purpose flash memory can be used as the handler storage unit 401.

  The base address storage unit 402 is a storage unit that stores a base address as the first storage unit. As the base address storage unit 402, for example, a register can be used. The access time from the CPU 300 to the base address storage means 402 as the first storage means is shorter than the access time from the CPU 300 to the handler storage means 401 as the second storage means. Here, the base address is a calculation reference for specifying the handler address, that is, an address used for specifying the handler address.

  The interrupt controller 200 outputs control information associated in advance for each interrupt factor to the CPU 300 in response to an input of an interrupt request by a plurality of interrupt factors.

  The CPU 300 specifies the handler address by a predetermined calculation using the control information output from the interrupt controller 200 and the base address stored in the base address storage unit 402 as parameters.

  For example, when the handler address is specified by the table reference method, the handler address can be specified by performing the following calculation.

  As a premise, the microcontroller 100 further includes a table storage unit that stores a handler address table in which control information and a handler address are associated with each other in advance. The base address indicates the storage address of the handler address table in the table storage means. At this time, the CPU 300 obtains a target handler address from the handler address table stored in the base address of the table storage means using the control information as a key. Thereafter, the CPU 300 can acquire a handler from the handler address in the handler storage unit 401 and execute an interrupt process.

  When the handler address is specified by the direct branch method, the handler address can be specified by performing the following calculation.

  As a premise, it is assumed that the handler storage unit 401 has a handler storage area in which fixed-length areas for storing handlers are stored in the order based on the control information. The base address indicates the start address of the handler storage area in the handler storage unit 401. At this time, the CPU 300 specifies the handler address based on the base address of the handler storage unit 401, the above-described fixed length, and the order rule based on the control information. Thereafter, the CPU 300 can acquire a handler from the handler address in the handler storage unit 401 and execute an interrupt process.

  In the present embodiment, in order to complement the features of each of these two handler address specifying methods, a configuration for selecting these methods according to conditions is also disclosed. As a result, it is possible to realize a handler address specifying method that has a balance between high speed and flexibility while assuming a small size and low cost.

  A configuration of the microcontroller 100 capable of selecting two handler address specifying methods will be described with reference to FIG.

  The interrupt controller 200 receives input of an interrupt request from the peripheral function 101 inside the microcontroller 100 and an interrupt request from the outside of the microcontroller 100, and outputs information necessary for interrupt processing to the CPU 300. For example, the interrupt controller 200 can select a handler address specifying method according to the interrupt factor, and output the selection result to the CPU 300 as handler address specifying method information. Some interrupt requests from the outside require the CPU 300 to inflate the airbag in response to a high speed, such as an interrupt request from the automobile collision sensor 502, Some interrupt requests from the temperature sensor 501 do not require a very fast response. In the case of an interrupt request due to an interrupt factor that requires high-speed response, such as the collision sensor 502, the direct branching method is suitable as a method for specifying a handler address. Further, in the case of an interrupt request due to an interrupt factor that does not require such a high-speed response, such as the temperature sensor 501, a table reference method that can increase the memory utilization efficiency is suitable as a method for specifying a handler address.

  A memory 4010 as the handler storage unit 401 is a flash memory as a program storage area. When the operating speed of the CPU 300 is higher than the operating speed of the memory 4010, the cache 104 is often provided between the memory 4010 and the CPU 300 in order to prevent a reduction in processing performance of the CPU 300 due to the speed difference.

  When the memory 4010 is mounted inside the microcontroller 100 as shown in FIG. 2, the interrupt handler (the interrupt handler (first interrupt handler) specified by the direct branch method) and the interrupt specified by the table reference method are used. It is preferable to store in the memory 4010 a handler address table used in the table reference method (including the interrupt handler (including the second interrupt handler)). In the present embodiment, an example in which the first interrupt handler, the second interrupt handler, and the handler address table are stored in the memory 4010 will be described. Note that the first interrupt handler, the second interrupt handler, and the handler address table are not necessarily stored in the physically same memory 4010. For example, the first interrupt handler, the second interrupt handler, and the handler address table may be distributed and stored in a plurality of physical storage devices constituting one address space. Alternatively, they can be stored in different address spaces. Specifically, either the first interrupt handler or the second interrupt handler may be stored in the memory 4010, and the other may be stored in the RAM 105, the external memory 503, or other storage means (not shown).

  CPU 300 executes a predetermined process according to a program stored in memory 4010. The CPU 300 reads out the instruction code stored in the memory 4010 via the instruction fetch unit 302 and the cache 104. When the instruction code required by the CPU 300 is already stored in the cache 104, the memory 4010 is not accessed, and the instruction code is immediately sent from the cache 104 to the instruction fetch unit 302.

  The program may be stored in the RAM 105 inside the microcontroller 100 or the external memory 503 outside the microcontroller 100. When the instruction code is stored in the RAM 105, the CPU 300 reads out the instruction code via the instruction fetch unit 302, the cache 104, the CPU bus 103, and the load / store unit 303. When an instruction code is stored in the external memory 503, the CPU 300 reads out the instruction code via the instruction fetch unit 302, the cache 104, the CPU bus 103, the external memory cache 106, and the external memory controller 107.

  When the CPU 300 receives an interrupt request from an interrupt factor for which the direct branch method is selected from the interrupt controller 200, the execution unit 301 first has a handler address base register (HABASE) 4020 as the base address storage means 402. To obtain a first base address. Then, the execution unit 301 calculates the handler address using the acquired first base address and the first control information received from the interrupt controller 200, typically the priority. The method for calculating the handler address will be described in detail later. The CPU 300 reads the instruction code of the handler from the handler address thus obtained according to the procedure described above.

When the CPU 300 receives an interrupt request from an interrupt factor for which the table reference method is selected from the interrupt controller 200, the execution unit 301 first has a handler address table base register (HTBASE) as the base address storage means 402. 4030 is accessed to obtain the second base address. The execution unit 301 stores the handler address using the acquired second base address and the second control information received from the interrupt controller 200, typically an interrupt factor identifier, for example, a factor number. Calculate the address. The storage address of the handler address will be described in detail later.
Next, the CPU 300 outputs the storage address of the handler address from the load / store unit 303 to the CPU bus 103. If the storage address of the handler address is an address in the memory 4010, the CPU 300 reads the handler address from the storage address in the memory 4010. That is, the CPU 300 reads the handler address from the memory 4010 via the load / store unit 303, the CPU bus 103, and the cache 104. When the handler address required by the CPU 300 is already stored in the cache 104, the memory 4010 is not accessed, and the handler address is sent from the cache 104 to the load / store unit 303 via the CPU bus 103 immediately. Reading the instruction code from the handler address thus obtained is performed according to the procedure described above.

  A handler address base register (HABASE) 4020 as the base address storage unit 402 is a register for setting a start address (base address) of a direct branch type handler as a first base address. A handler address table base register (HTBASE) 4030 as a second register is a register for setting a start address (base address) of a table address type handler address table as a second base address. The HABASE 4020 and the HTBASE 4030 may be provided either inside or outside the CPU 300. However, it is desirable that the HABASE 4020 and the HTBASE 4030 be provided in the vicinity of the CPU 300 so that the CPU 300 can be accessed as fast as possible, that is, with a short access time.

  By appropriately setting the base addresses stored in the HABASE 4020 and the HTBASE 4030, the first interrupt handler, the second interrupt handler, and the handler address table are stored not only in the memory 4010 but also in the microcontroller 100. It is also possible to store in the RAM 105, the external memory 503 outside the microcontroller 100, or other storage means (not shown). For example, if the handler address table is stored in the RAM 105 directly connected to the load / store unit 303, the handler address can be read at high speed, and the response performance to the interrupt request of the interrupt factor for which the table reference method is selected is improved. It is possible.

  A specific implementation example of the interrupt controller 200 will be described with reference to FIG.

  The interrupt controller 200 accepts peripheral functions inside the microcontroller 100 and inputs of interrupt requests 0 to n from outside the microcontroller 100. Interrupt requests 0 to n correspond to interrupt factors 0 to n, respectively, and are input to the request detection unit 201 through independent signal lines.

  The request detection unit 201 detects the input of the above-described interrupt request. The detection result of the interrupt request is stored in the request flag 202 for each interrupt factor 0 to n. Further, the content of the request flag 202 is sent to the request mask unit 203.

  The request mask unit 203 determines whether to mask the interrupt request according to the request masks 0 to n input from the interrupt control registers 206 provided for the interrupt factors 0 to n, that is, interrupts to the CPU 300. When it is determined whether to prohibit or permit, and when it is not masked, an interrupt request is sent to the priority determination unit 204.

  The priority determination unit 204 is based on the interrupt request input from the request mask unit 203 and the priority 0 to n set for each interrupt factor 0 to n input from the interrupt control register 206. Select the highest priority interrupt factor. The priority determination unit 204 sends the factor number and priority of the selected highest priority interrupt factor to the interrupt request generation unit 205.

  The interrupt request generation unit 205 is a handler set for each of the interrupt factor input from the interrupt control register 206 and the factor number of the highest priority interrupt factor input from the priority determination unit 204. The priority as the first control information, the second control information, which is information necessary for the CPU 300 to specify the handler address together with the interrupt request to the CPU 300 based on the address specifying method information 0 to n. The cause number and the handler address specifying method information are output. Here, the handler address specifying method information is information indicating whether a handler address should be specified by a handler address specifying method, that is, a direct branch method or a table reference method. The interrupt request generation unit 205 uses only the first control information and the handler address specifying method information when the handler address specifying method information is the direct branch method, and the second control information when the handler address specifying method information is the table reference method. Only the handler address specifying method information may be output to the CPU 300.

  When receiving an interrupt request from the interrupt controller 200, the CPU 300 notifies the interrupt controller 200 of the interrupt response and the cause number of the received interrupt request.

  An interrupt response input unit 207 in the interrupt controller 200 receives an interrupt response and a factor number notified from the CPU 300, and outputs a request flag clear signal corresponding to the factor number to the request flag 202. The interrupt factor request flag 202 corresponding to the factor number is cleared.

  The peripheral bus interface 208 receives an access request to the interrupt control register 206 from the peripheral bus, and performs control for setting a value in the interrupt control register 206 and reading a value from the interrupt control register 206.

  A specific example of the interrupt control register 206 will be described with reference to FIG.

  Interrupt control registers 206 are provided corresponding to interrupt factors 0 to n, respectively. The interrupt control register 206 is a bit (EIMK) for setting whether to mask the interrupt request from the corresponding interrupt factor, and the handler address when the CPU 300 accepts the interrupt request from the corresponding interrupt factor It includes bits (EITB) for setting specific method information and bits (EIP3-EIP0) for setting the priority of the corresponding interrupt factor.

  Specific examples of HABASE4020 and HTBASE4030 will be described with reference to FIG.

  A handler address base register (HABASE) 4020 is a register for setting a start address (base address) of a direct branch type interrupt handler. The direct branch type interrupt handler (first interrupt handler) is arranged in order of priority starting at the address set in this register.

  The handler address table base register (HTBASE) 4030 is a register for setting the start address (base address) of the handler address table of the table reference method. The table reference type handler addresses are arranged in the order of the interrupt cause factor numbers, starting with the address set in this register.

  Next, a process executed by the CPU 300 when the microcontroller 100 receives an interrupt request will be described with reference to FIG.

  S101: The CPU 300, together with the interrupt request signal from the interrupt controller 200, uses the priority as the first control information and the factor number of the interrupt as the second control information as information for specifying the handler address. Input of at least one of them and handler address specifying method information is accepted.

  At this time, the CPU 300 can output an interrupt response and the accepted interrupt cause number to the interrupt controller 200. Thereby, the interrupt controller 200 can recognize that the CPU 300 has accepted the interrupt request related to the factor number. The interrupt response input unit 207 in the interrupt controller 200 clears the interrupt factor request flag 202 corresponding to the factor number, and cancels the waiting state for accepting the interrupt request related to the factor number.

  S102: When the handler address specifying method information input from the interrupt controller 200 is information indicating the direct branch method, the CPU 300 acquires the value of the handler address base register (HABASE) 4020.

  S103: On the other hand, when the handler address specifying method information input from the interrupt controller 200 is information indicating the table reference method, the CPU 300 acquires the value of the handler address table base register (HTBASE) 4030.

S104: When the handler address specifying method information is information indicating the direct branch method, the CPU 300 executes the handler based on the priority as the first control information input in S101 and the HABASE value acquired in S102. Identify the address. Specifically, the handler address is specified by performing the calculation of Equation 1. In Equation 1, the handler size is a predetermined fixed value (for example, 16 bytes).
(Expression 1) Handler address = Base address stored in HABASE + Priority x Handler size

S105: When the handler address specifying method information is information indicating the table reference method, the CPU 300 firstly, based on the factor number as the second control information input in S101 and the value of HTBASE acquired in S103. Identify the storage address of the handler address. Specifically, the calculation of Equation 2 is performed to specify the storage address of the handler address, that is, the address of the table storing the handler address. In Equation 2, the address size is a predetermined fixed value (for example, 4 bytes).
(Equation 2) Handler address storage address = Base address stored in HTBASE + Reason number × Address size

  S106: The CPU 300 reads data from the storage address of the handler address calculated by Equation 2, and uses the read data as the handler address.

  S107: The CPU 300 branches to the handler address. That is, the instruction code of the interrupt handler stored at the handler address specified by the handler address specifying method of either the direct branch method or the table reference method is read, and processing is performed according to the instruction code.

  FIG. 7 shows an arrangement image on the address space of the interrupt handlers (first interrupt handler and second interrupt handler) in the memory 4010.

  The direct branch type interrupt handler (first interrupt handler) 602 is arranged in order of priority from the base address 601 set in the handler address base register (HABASE) 4020. The size of the storage area of each handler, that is, the handler size is fixed (for example, 16 bytes). For example, when priority levels 0 to 15 can be set, the handlers INTPR0 to INTPR15 corresponding to the priority levels 0 to 15 are stored in a 16-byte handler size area with the base address 601 as a base point. Arranged in order.

  The handler address of the table reference method is arranged in the order of the factor number from the base address 603 set in the handler address table base register (HTBASE) 4030. An area for storing these handler addresses is called a handler address table 604. The size of the storage area of each handler address, that is, the address size is fixed (for example, 4 bytes). For example, when the factor numbers 0 to n exist, the handler addresses INT0 to INTn corresponding to the factor numbers 0 to n are stored in the 4-byte address size area starting from the base address 603, respectively. Arranged in order.

  In the table reference method, the arrangement address and size of the interrupt handler (second interrupt handler) corresponding to each factor number are arbitrary (605).

  FIG. 8 shows a timing chart of signals between the interrupt controller 200 and the CPU 300 when an interrupt occurs.

  Time t2: Interrupt request 1 (req1) of interrupt factor 1 is asserted.

From time t3 to t5: req1 is asserted, and the request flag 1 is set. The interrupt controller 200 outputs an interrupt request (intreq), a factor number (intnum [N: 0]), a priority (intpri [3: 0]), and handler address specifying method information (intiteb) to the CPU 300. At this time, the set value of the interrupt control register 1 corresponding to the interrupt factor 1 is as follows, and a signal is output from the interrupt controller 200 to the CPU 300 according to this set value.
EITB = 1: Select table reference method EIP3-EIP0 = 5: Priority 5

  Note that during this period, the CPU 300 is higher than the priority level 5 as can be seen from the fact that the CPU 300 does not notify the interrupt controller 200 of the interrupt response (intake) and the cause number (intakenum [N: 0]). This interrupt is not accepted by the CPU 300 for some reason such as processing a priority interrupt.

  Time t5: The interrupt request (req3) for interrupt factor 3 is asserted.

Time t6 to t8: Request flag 3 is set in response to the assertion of req3. Since the priority of the interrupt factor 3 is higher than the priority of the interrupt factor 1, the information notified to the CPU 300 by the interrupt controller 200 is switched from the factor 1 to the factor 3. The set value of the interrupt control register 3 corresponding to the factor 3 is as follows, and a signal is output from the interrupt controller 200 to the CPU 300 according to this set value.
EITB = 0: Select a direct branching method based on priority EIP3-EIP0 = 2: Priority 2

  Time t8: The CPU 300 accepts the interrupt request for the factor 3, and notifies the interrupt controller 200 of the interrupt response (intake) and the factor number (intakenum [N: 0]).

  Time t9: The interrupt controller 200 receives an interrupt response (intake) from the CPU 300, clears the request flag 3 corresponding to the factor 3, and simultaneously withdraws the interrupt request (intreq).

  Time t10 to t12: Since the request flag 1 remains set, the interrupt controller 200 notifies the CPU 300 again of the interrupt request (intreq) and the information of the factor 1 (factor number, priority, handler address specifying method information). To do.

  In this embodiment, since the handlers and handler address tables are stored in the memory 4010 external to the interrupt controller 200, the handlers and handler address tables can be freely arranged, and the number of interrupt factors Even if this increases, a handler corresponding to an interrupt factor can be provided at low cost.

  In this embodiment, the CPU 300 can calculate the handler address or the storage address of the handler address at high speed by storing the base address in the HABASE 4020 and the HTBASE 4030 whose access time is shorter than that of the memory 4010.

<Embodiment 2>
In the direct branching method of the first embodiment, the handler address is specified based on the priority set according to the interrupt factor. Therefore, the number of interrupt handlers (first interrupt handlers) that can specify the handler address by the direct branching method is limited to the number of priorities or less. Also, when multiple interrupt sources are set to the same priority and the method for specifying the handler addresses of these multiple sources is the direct branch method, the interrupt handlers for these multiple interrupt sources are the same Therefore, it becomes necessary to perform processing for determining the interrupt factor in the interrupt handler, and the high-speed interrupt responsiveness that is an advantage of the direct branching method is impaired.

  Therefore, in the second embodiment of the present invention, the interrupt control register 206 is further provided with a bit for designating a handler number when the direct branching method is selected. Thereby, the handler address of the direct branching method can be specified independently of the priority set as the interrupt factor, and the above-described problems in the first embodiment can be solved.

  A configuration of the microcontroller 100 according to the second embodiment of the present invention will be described.

  The microcontroller 100 according to the second embodiment is characterized by the configuration of the interrupt control register 206 in the interrupt controller 200. The rest of the configuration is the same as in the first embodiment.

  The configuration of the interrupt control register 206 in this embodiment will be described with reference to FIG.

  The interrupt control register 206 is provided for each interrupt factor 0 to n. Interrupt control register 206 includes bits (HN5 to HN0) for specifying a handler number when the handler address specifying method information is set to the direct branch method. Note that the number of bits in the present embodiment is an example, and the present invention is not limited to this.

  A process executed by the CPU 300 when the microcontroller 100 according to the present embodiment receives an interrupt request will be described with reference to FIG.

  S201: The CPU 300 includes the handler number as the first control information and the interrupt factor number as the second control information as information for specifying the handler address together with the interrupt request signal from the interrupt controller 200. Input of at least one of them and handler address specifying method information is accepted.

  At this time, the CPU 300 can output an interrupt response and the accepted interrupt cause number to the interrupt controller 200.

  S102: When the handler address specifying method information input from the interrupt controller 200 is information indicating the direct branch method, the CPU 300 acquires the value of the handler address base register (HABASE) 4020.

  S103: On the other hand, when the handler address specifying method information input from the interrupt controller 200 is information indicating the table reference method, the CPU 300 acquires the value of the handler address table base register (HTBASE) 4030.

S204: When the handler address specifying method information is information indicating the direct branch method, the CPU 300 executes the handler based on the handler number as the first control information input in S201 and the value of HABASE acquired in S102. Identify the address. Specifically, the handler address is specified by performing the calculation of Equation 3.
(Expression 3) Handler address = Base address stored in HABASE + Handler number × Handler size

  S105: When the handler address specifying method information is information indicating the table reference method, the CPU 300 firstly, based on the factor number as the second control information input in S201 and the value of HTBASE acquired in S103. Identify the storage address of the handler address. Specifically, the calculation of Equation 2 is performed to specify the storage address of the handler address, that is, the address of the table storing the handler address.

  S106: The CPU 300 reads data from the storage address of the handler address calculated by Equation 2, and uses the read data as the handler address.

  S107: The CPU 300 branches to the handler address. That is, the instruction code of the interrupt handler stored at the handler address specified by the handler address specifying method of either the direct branch method or the table reference method is read, and processing is performed according to the instruction code.

  FIG. 11 shows an arrangement image on the address space of the interrupt handlers (first interrupt handler and second interrupt handler) in the present embodiment.

  Direct branch type interrupt handlers (first interrupt handlers) 606 are arranged in the order of handler numbers starting from the base address 601 set in the handler address base register (HABASE) 4020. The size of the storage area of each handler, that is, the handler size is fixed (for example, 16 bytes). For example, when 0 to 63 can be set as the handler number, the handlers INTNUM0 to INTNUM63 corresponding to the handler numbers 0 to 63 with the base address 601 as a base point are stored in a handler size area of 16 bytes respectively. Arranged in numerical order.

  The handler address of the table reference method is arranged in the order of the factor number from the base address 603 set in the handler address table base register (HTBASE) 4030. An area for storing these handler addresses is called a handler address table 604. The size of the storage area of each handler address, that is, the address size is fixed (for example, 4 bytes). For example, when the factor numbers 0 to n exist, the handler addresses INT0 to INT15 corresponding to the factor numbers 0 to n are stored in the 4-byte address size areas starting from the base address 603, respectively. Arranged in order.

  In the table reference method, the arrangement address and size of the interrupt handler (second interrupt handler) corresponding to each factor number are arbitrary (605).

  In the present embodiment, in the direct branch method, the interrupt controller 200 outputs a handler number previously associated with an interrupt factor by the interrupt control register 206 to the CPU 300, and the CPU 300 handles the handler address based on the handler number. Configured to identify. Thereby, the number of handlers can be specified without being restricted by the number of priorities. Further, it is not necessary to perform processing for determining the interrupt factor in the handler.

<Embodiment 3>
In the first and second embodiments, a direct branch method is assigned for interrupt factors that require a high-speed interrupt response, and a table reference method is assigned for interrupt factors that do not require a high-speed interrupt response. And free and efficient use of memory.

  However, there may be a case where only the direct branching method can be used as a method for specifying the handler address due to some constraints. The third embodiment of the present invention relates to a microcontroller 100 that can use a memory freely and efficiently even in such a case.

  A configuration of the microcontroller 100 according to the third embodiment of the present invention will be described.

  The microcontroller 100 according to the third embodiment is characterized by the configuration of the interrupt control register 206 in the interrupt controller 200 and the arrangement method of the interrupt handlers in the memory 4010. The rest of the configuration is the same as in the first and second embodiments.

  The configuration of the interrupt control register 206 in this embodiment will be described with reference to FIG.

  The interrupt control register 206 is provided for each interrupt factor 0 to n. Interrupt control register 206 includes bits (HN5-HN0) for specifying a handler number. Note that the number of bits in the present embodiment is an example, and the present invention is not limited to this. In this embodiment, among the interrupt factors 0 to n, the handler numbers of interrupt factors x1 to xn that do not require a high-speed interrupt response are all set to a common number, for example, 63. As a result, when the CPU 300 receives an interrupt request from the interrupt factors x1 to xn, the CPU 300 branches to the interrupt handler with the handler number 63.

  A process executed by the CPU 300 when the microcontroller 100 according to the present embodiment receives an interrupt request will be described with reference to FIG.

  S301: CPU 300 accepts an input of a handler number as first control information as information for specifying a handler address together with an interrupt request signal from interrupt controller 200.

  At this time, the CPU 300 can output an interrupt response and the accepted interrupt cause number to the interrupt controller 200.

  S102: The CPU 300 acquires the value of the handler address base register (HABASE) 4020.

  S204: The CPU 300 specifies the handler address based on the handler number as the first control information input in S301 and the HABASE value acquired in S102. Specifically, the handler address is specified by performing the calculation of Equation 3.

  S107: The CPU 300 branches to the handler address. That is, the instruction code of the interrupt handler stored at the handler address is read and processing is performed according to the instruction code.

  FIG. 14 shows an arrangement image of the interrupt handlers in the address space according to the present embodiment.

  Interrupt handlers (first interrupt handlers) 606 are arranged in the order of handler numbers from the base address 601 set in the handler address base register (HABASE) 4020. The size of the storage area of each handler, that is, the handler size is fixed (for example, 16 bytes). For example, when 0 to 63 can be set as the handler number, the handlers INTNUM0 to INTNUM63 corresponding to the handler numbers 0 to 63 with the base address 601 as a base point are stored in a handler size area of 16 bytes respectively. Arranged in numerical order.

  In the present embodiment, in the interrupt control register 206 in the interrupt controller 200, the handler numbers of interrupt factors x1 to xn that do not require a high-speed interrupt response are all set to a common number, for example, 63. . Thus, when the CPU 300 accepts an interrupt request from the interrupt factors x1 to xn, it branches to the handler INTNUM63. In the handler INTNUM63, a process for determining from which of the interrupt factors x1 to xn the interrupt request originated and branching to the handlers INTx1 to INTxn specific to the interrupt factors x1 to xn is described. . This increases the degree of freedom in the location and size of the interrupt handler (first interrupt handler) for interrupt factors x1 to xn that do not require a high-speed interrupt response, and increases the memory utilization efficiency. be able to.

  In the present embodiment, in microcontroller 100 that can only use the direct branch method, interrupt control register 206 in interrupt controller 200 assigns a common handler number to an interrupt factor that does not require a high-speed interrupt response. Then, the interrupt handler corresponding to the common handler number in the memory 4010 is caused to determine the interrupt factor of the interrupt request and perform processing to branch to another interrupt handler for each interrupt factor. As a result, with regard to an interrupt factor that does not require a high-speed interrupt response, the degree of freedom increases in the location and size of the interrupt handler, and the use efficiency of the memory can be increased.

<Embodiment 4>
The third embodiment realizes free and efficient use of the memory for an interrupt factor that does not require a high-speed interrupt response. The fourth embodiment of the present invention relates to a microcontroller 100 that can use a memory freely and efficiently for an interrupt factor that requires a high-speed interrupt response.

  A configuration of the microcontroller 100 according to the fourth embodiment of the present invention will be described.

  The microcontroller 100 of the fourth embodiment is characterized by the configuration of the interrupt control register 206 in the interrupt controller 200 and the arrangement method of the interrupt handlers in the memory 4010. The rest of the configuration is the same as in the third embodiment.

  The interrupt control register 206 in the present embodiment sets the handler number of the interrupt factor y that requires a high-speed interrupt response to an arbitrary factor number, for example, 30. At this time, if the interrupt handler corresponding to the interrupt factor y is larger than the specified handler size, the interrupt control register 206 assigns the handler number 31 consecutive to the handler number 30 to any other interrupt. Do not assign to factors.

  In addition, as shown in FIG. 14, the interrupt handler for the factor y is stored in an area obtained by connecting the area of the handler INTNUM 30 and the area of the handler INTNUM 31 in the memory 4010.

  Thereby, the freedom degree of the size of an interrupt handler can be increased without impairing high-speed interrupt response performance.

  In the present embodiment, the memory 4010 stores one interrupt handler in a continuous storage area associated with the identifiers of a plurality of interrupt handlers, and the interrupt control register 206 in the interrupt controller 200 Of the identifiers of the plurality of interrupt handlers, only the identifier of the interrupt handler associated with the top area of the continuous storage area is associated with a predetermined interrupt factor. Thereby, the freedom degree of the size of an interrupt handler can be increased without impairing high-speed interrupt response performance.

<Other embodiments>
It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention.

  For example, in the above-described embodiment, the hardware configuration has been described. However, the present invention is not limited to this, and any processing may be realized by causing a CPU (Central Processing Unit) to execute a computer program. Is possible. In this case, the computer program can be stored and provided to the computer using various types of non-transitory computer readable media. Non-transitory computer readable media include various types of tangible storage media. Examples of non-transitory computer-readable media include magnetic recording media (for example, flexible disks, magnetic tapes, hard disk drives), magneto-optical recording media (for example, magneto-optical disks), CD-ROMs (Read Only Memory), CD-Rs, CD-R / W, semiconductor memory (for example, mask ROM, PROM (Programmable ROM), EPROM (Erasable PROM), flash ROM, RAM (Random Access Memory)). The program may also be supplied to the computer by various types of transitory computer readable media. Examples of transitory computer readable media include electrical signals, optical signals, and electromagnetic waves. The temporary computer-readable medium can supply the program to the computer via a wired communication path such as an electric wire and an optical fiber, or a wireless communication path.

100 Microcontroller 101 Peripheral Function 102 Peripheral Bus 103 CPU Bus 104 Cache 105 RAM
106 External Memory Cache 107 External Memory Controller 200 Interrupt Controller 201 Request Detection Unit 202 Request Flag 203 Request Mask Unit 204 Priority Determination Unit 205 Interrupt Request Generation Unit 206 Interrupt Control Register 207 Interrupt Response Input Unit 208 Peripheral Bus Interface 300 CPU
301 execution unit 302 instruction fetch unit 303 load store unit 401 handler storage unit 402 base address storage unit 4010 memory 4020 HABASE (first base address storage unit)
4030 HTBASE (second base address storage means)
501 Temperature sensor 502 Collision sensor 503 External memory

Claims (20)

A microcontroller that executes an interrupt handler in response to an interrupt request caused by multiple interrupt factors,
First storage means for storing a base address used for specifying a handler address which is an address indicating a storage position of the interrupt handler;
Second storage means for storing the interrupt handler;
In response to the input of the interrupt request, an interrupt controller that outputs control information associated with the interrupt factor in advance,
In response to an interrupt request output from the interrupt controller, a CPU for acquiring and executing the interrupt handler is provided.
The access time from the CPU to the first storage means is shorter than the access time from the CPU to the second storage means, and
The CPU
(A) In response to the interrupt request output from the interrupt controller, the first storage means is accessed to obtain the base address;
(B) identifying the handler address based on the acquired base address and the control information output from the interrupt controller;
(C) accessing the second storage means based on the specified handler address to execute the interrupt handler;
Microcontroller. The second storage means has a table storage area for storing a handler address table in which the control information and the handler address are associated in advance.
The base address is an address indicating a storage position of the handler address table in the second storage means,
The CPU
(B-1) The handler address table is referenced based on the base address, and the handler address associated with the control information output from the interrupt controller is specified in the handler address table. Microcontroller. The second storage means has a handler storage area for storing each of the plurality of interrupt handlers in each of the fixed-size individual areas prepared in the order specified by the control information,
The base address is an address indicating a storage position of the handler storage area in the second storage means,
The CPU
(B-2) The handler address is specified based on the base address based on the order specified by the control information and a fixed size of an individual area for storing each of the interrupt handlers in the handler storage area. 1. The microcontroller according to 1. A microcontroller that executes an interrupt handler in response to an interrupt request caused by multiple interrupt factors,
In response to the input of the interrupt request, the interrupt request, the first or second control information associated in advance with the interrupt factor, and the handler address specifying method information associated in advance with the interrupt factor An interrupt controller that outputs
CPU that acquires and executes the first interrupt handler or the second interrupt handler in response to an interrupt request output from the interrupt controller;
A first base address used to specify a first handler address which is an address indicating a storage location of the first interrupt handler, and an address indicating a storage location of the second interrupt handler. First storage means for storing a second base address used to identify the two handler addresses;
A first interrupt handler storage area for storing each of the plurality of first interrupt handlers in a fixed-size individual area prepared in advance in the order specified by the first control information; A table storage area that stores a handler address table that associates the control information with the second handler address in advance, and a first interrupt handler storage area that stores the first interrupt handler. Storage means,
The access time from the CPU to the first storage means is shorter than the access time from the CPU to the second storage means, and
The CPU
(A) When the handler address specifying method information indicates a direct branch method,
(A) In response to the interrupt request output from the interrupt controller, the first storage means is accessed to obtain the first base address,
(B-2) Based on the first base address, the order specified by the first control information, and the fixed size of the individual area for storing each of the interrupt handlers in the first handler storage area Identifying the first handler address from
(C) accessing the second storage means based on the identified first handler address to execute the first interrupt handler;
(B) When the handler address specifying method information indicates a table reference method,
(A) In response to the interrupt request output from the interrupt controller, the first storage means is accessed to obtain the second base address;
(B-1) Refers to the handler address table based on the second base address, and the second address associated with the second control information output from the interrupt controller in the handler address table. Identify the handler address,
(C) accessing the second storage means based on the identified second handler address to execute the second interrupt handler;
Microcontroller. The first storage means is a register;
The microcontroller according to any one of claims 1 to 4, wherein the second storage unit is a memory having a longer access time by the CPU than the register. The microcontroller according to claim 4, wherein the table storage area, the first interrupt handler storage area, and the second interrupt handler storage area are on the same address space. The microcontroller according to any one of claims 1 to 3, wherein the control information is a priority. The microcontroller according to any one of claims 1 to 3, wherein the control information is an identifier of an interrupt factor. The microcontroller according to any one of claims 1 to 3, wherein the control information is a handler identifier. The microcontroller according to claim 4 or 6, wherein the second control information is an identifier of an interrupt factor. A common handler identifier is associated with a plurality of interrupt factors in advance,
The microcontroller according to claim 9, wherein the second storage unit stores a handler that causes the CPU to execute a process of further branching to another handler that differs for each interrupt factor in a storage area corresponding to the handler identifier. The second storage means stores one handler in a continuous storage area corresponding to a plurality of handler identifiers,
The microcontroller according to claim 9 or 11, wherein among the plurality of handler identifiers, only the identifier of the handler corresponding to the head area of the continuous storage area is associated with a predetermined interrupt factor. CPU
A step of inputting control information corresponding to the interrupt factor from the interrupt controller;
Obtaining a base address from the first storage means;
Identifying a handler address which is a storage location of the handler in the second storage means based on the base address and the control information,
The handler address specifying method, wherein an access time from the CPU to the first storage means is shorter than an access time from the CPU to the second storage means. The handler address specifying method according to claim 13, wherein the base address is an address indicating a storage position of a handler address table in which the control information and the handler address are associated in advance in the second storage unit. The second storage means has a handler storage area for storing each of the plurality of interrupt handlers in each of the fixed-size individual areas prepared in the order specified by the control information,
The handler address specifying method according to claim 13, wherein the base address is an address indicating a storage position of the handler storage area in the second storage means. CPU
Inputting from the interrupt controller the first or second control information corresponding to the interrupt factor and the handler address specifying method information corresponding to the interrupt factor;
(A) When the handler address specifying method information indicates a direct branch method,
Obtaining a first base address from a first storage means;
Identifying a first handler address that is a storage location of the first handler from a first handler storage area in a second storage means based on the first base address and the first control information;
(B) When the handler address specifying method information indicates a table reference method,
Obtaining a second base address from the first storage means;
Identifying a second handler address from a handler address table based on the second base address and the second control information,
The first handler storage area is stored in an order based on the first control information in a fixed-size individual area for storing the first handler,
The first base address is an address indicating a storage position of the first handler storage area in the second storage means,
The handler address table is a table in which the second control information and the second handler address are associated with each other in advance.
The second base address is an address indicating a storage position of a handler address table in the second storage means,
The handler address specifying method, wherein an access time from the CPU to the first storage means is shorter than an access time from the CPU to the second storage means. The first storage means is a register;
The handler address specifying method according to any one of claims 13 to 16, wherein the second storage unit is a memory having a longer access time by the CPU than the register. The first control information is a handler identifier;
A common handler identifier is associated with a plurality of interrupt factors in advance,
17. The handler address specification according to claim 16, wherein the second storage means stores a handler that causes the CPU to execute a process of further branching to another handler that differs for each interrupt factor in a storage area corresponding to the handler identifier. Method. The second storage means stores one handler in a continuous storage area corresponding to a plurality of handler identifiers,
The handler address specifying method according to claim 18, wherein, among the plurality of handler identifiers, only the identifier of the handler corresponding to the head area of the continuous storage area is associated with a predetermined interrupt factor.   A program for causing a computer to execute the method according to any one of claims 13 to 19.

Images