JP2014074605A - Hysteresis circuit and resolver/digital converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To exclude influence caused by vibration and bit skip generated in an input signal value on an output signal value in a hysteresis circuit.SOLUTION: A hysteresis circuit 30 generates an output signal corresponding to hysteresis of an input signal from an A/D conversion part 30 synchronously with a clock. The hysteresis circuit 30 calculates a difference value between an input signal value before one clock and an output signal value before one clock and generates an output signal value of a present clock in accordance with the calculated difference value. The hysteresis circuit 30 determines a value obtained by adding one bit to the output signal value before one clock as the output signal value of the present clock when the difference value is a positive threshold or more, determines a value obtained by subtracting one bit from the output signal value before one clock when the difference value is a negative threshold or less, and determines the output signal value before one clock as the output signal value of the present clock when the difference value is less than the positive threshold and greater than the negative threshold.

Description

  The present invention relates to a hysteresis circuit, and is suitably used for, for example, a resolver / digital converter that converts an electrical signal output from a resolver into a digital angle signal.

  A resolver / digital converter (hereinafter referred to as “R / D converter”) converts an electrical signal output from a resolver that detects a rotation angle of a rotating body into a digital value (see, for example, Patent Document 1). Specifically, the resolver includes a primary winding provided on the rotor and two secondary windings provided on the stator. The two secondary windings are mechanically shifted by 90 °. When a sine wave excitation signal is applied to the primary winding, a sine wave output and a cosine wave output modulated according to the rotation angle of the rotor are obtained from the two secondary windings, respectively. The R / D converter converts the sine wave output and cosine wave output of the resolver into digital values according to a predetermined sample clock.

  As such an R / D converter, Patent Document 1 discloses an A / D converter for analog / digital conversion of a sine wave output and a cosine wave output of a resolver, and a sine wave value and a cosine wave value from the A / D converter. A configuration including correction means for correcting hysteresis is disclosed. In Patent Document 1, in order to compensate for an error that occurs in an A / D conversion value due to the influence of noise or the like on the input of the A / D converter, the A / D conversion value has a hysteresis characteristic. Specifically, when the difference between the previous sample and the current A / D conversion value is within a certain value, the correction unit sets the A / D conversion value to the previous value.

JP 2004-309285 A JP-A-4-353765

  In such an R / D converter, the A / D conversion value may oscillate in synchronization with a sinusoidal excitation signal. In the R / D converter described in Patent Document 1 described above, when the A / D conversion value vibrates, if the vibration width of the A / D conversion value exceeds a certain value in the correction unit, the correction unit also detects this vibration. It cannot be compensated. Therefore, the hysteresis-corrected sine wave value and cosine wave value also vibrate.

  Further, in the above-mentioned Patent Document 1, the A / D conversion value is set to one of the value one sample before and the current A / D conversion value by the correcting means. Therefore, when the A / D conversion value causes a so-called “bit skip” in which the signal value does not change by 1 bit every sample clock due to disturbance noise or the like, the hysteresis-corrected sine wave value and cosine There arises a problem that a bit skip appears in the wave value as it is. When such a situation occurs, there is a possibility that a deviation occurs between the rotation angle of the rotor obtained from the R / D converter and the actual rotation angle. Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  A hysteresis circuit provided in the resolver / digital converter according to the embodiment includes an analog / digital conversion unit that converts an output signal of the resolver into an angle signal, and an input signal from the analog / digital conversion unit in synchronization with the clock. A hysteresis circuit that generates an output signal corresponding to the hysteresis and outputs the output signal as an angle signal. The hysteresis circuit generates a difference signal between the input signal value one clock before and the output signal value one clock before, and generates and outputs the output signal value of the current clock according to the difference value from the subtraction circuit. Output circuit. When the difference value is greater than or equal to the positive threshold value, the output circuit outputs a value obtained by adding 1 bit to the output signal value one clock before as the output signal value of the current clock, and the difference value is equal to or less than the negative threshold value. In this case, a value obtained by subtracting one bit from the output signal value one clock before is output as the output signal value of the current clock, and the difference value is less than the positive threshold value and greater than the negative threshold value. Sometimes, the output signal value one clock before is output as the output signal value of the current clock.

  According to the above-described embodiment, in the hysteresis circuit that generates the output signal value corresponding to the hysteresis of the digital input signal value, it is possible to eliminate the influence of the vibration and the bit skip generated in the input signal value.

It is a block diagram which shows the structure of the R / D converter by one embodiment. It is a figure which shows the relationship between an excitation signal and the digital value output from an A / D conversion part. It is a block diagram which shows the structure of the hysteresis circuit by one Embodiment. It is a figure which shows the relationship between the input signal value and output signal value in the hysteresis circuit by one Embodiment. It is a block diagram which shows the modification of the hysteresis circuit of FIG. It is a block diagram which shows the structure of the conventional hysteresis circuit. It is a figure which shows the relationship between the input signal value and output signal value in the conventional hysteresis circuit.

  Hereinafter, an embodiment will be described in detail with reference to the drawings. The same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

[Configuration of R / D converter]
FIG. 1 is a block diagram illustrating a configuration of an R / D converter according to an embodiment. The R / D converter according to the embodiment is applied to, for example, a motor control system as shown in FIG.

  Referring to FIG. 1, the motor control system is a system for controlling current supply to AC motor M1, and includes motor driver 1, motor control unit 2, resolver 3, R / D converter 4, and the like. Consists of

  The motor driver 1 drives the AC motor M1. The motor driver 1 drives the AC motor M1 by converting DC power from a DC power source into AC current by an inverter.

  The motor control unit 2 is configured by a microcomputer. The motor control unit 2 controls current supply from the motor driver 1 to the AC motor M1. In the energization control of the AC motor M1, the motor control unit 2 controls the current supplied to the AC motor M1 according to the rotor rotation angle θ detected by the R / D converter 4.

  The resolver 3 is a rotation angle sensor that detects the rotation angle of the AC motor M1. The resolver 3 includes a rotor, a stator, a primary winding, and two secondary windings. The rotor has an outer diameter whose gap with the inner peripheral surface of the stator changes in a sine wave shape in the circumferential direction. The primary winding is provided in the rotor and receives a sinusoidal excitation signal VEx from the R / D converter 4.

  Two secondary windings are provided on the stator. The first secondary winding is mechanically offset by 90 ° from the primary winding. The second secondary winding is further mechanically shifted by 90 ° from the first secondary winding. As shown in FIG. 2, when a sinusoidal excitation signal VEx is applied to the primary winding, the first and second secondary windings have signals V1, V2 modulated according to the rotational angle θ of the rotor. Each occurs.

  The R / D converter 4 converts the signals (analog signals) V1 and V2 output from the two secondary windings of the resolver 3 into angle signals (digital signals). The R / D converter 4 outputs the converted angle signal to the motor control unit 2. Specifically, the R / D converter 4 includes an excitation signal generator 10, an A / D (analog / digital) converter 20, and a hysteresis circuit 30.

  The excitation signal generator 10 generates an excitation signal VEx composed of the above sine wave and outputs the generated excitation signal VEx to the primary winding of the resolver 3.

  The A / D converter 20 converts the signals V1 and V2 respectively output from the two secondary windings of the resolver 3 into a digital value φ corresponding to the rotation angle θ of the rotor. The method for converting the output signals V1 and V2 of the resolver 3 into the digital value φ may be performed by using a known general technique. Therefore, further description will not be repeated here. The digital value φ is a multi-bit signal, and the number of bits varies according to the resolution of the A / D converter 20.

  FIG. 2 shows the relationship between the excitation signal VEx and the digital value φ output from the A / D converter 20. 2 corresponds to the rotation angle θ of the rotor in a state where the rotation of the rotor in AC motor M1 is stopped.

  Referring to FIG. 2, when the rotation of the rotor is stopped, the rotation angle θ of the rotor usually shows a constant value. Therefore, the digital value φ corresponding to the rotation angle θ of the rotor also shows a constant value. However, the digital value φ indicates a waveform that oscillates around the constant value. This vibration is synchronized with the vibration of the excitation signal output from the excitation signal generator 10 of the R / D converter 4. Further, the amplitude of the vibration of the digital value φ has a magnitude depending on the resolution of the A / D converter 20.

  As described above, when the digital value φ output from the A / D converter 20 vibrates in synchronization with the excitation signal, there is a shift between the rotation angle θ of the AC motor M1 detected by the resolver 3 and the actual rotation angle. It can happen. In such a situation, there is a possibility that the accuracy of the energization control of the AC motor M1 in the motor control unit 2 is lowered.

  Therefore, in the R / D converter according to the embodiment, the hysteresis circuit 30 receives the digital value from the A / D converter 20 and generates an output signal (digital value) corresponding to the hysteresis (history) of the input signal. To do. Thereby, the influence of the excitation signal is suppressed. The output signal generated by the hysteresis circuit 30 is given to the motor control unit 2 as an angle signal.

[Schematic configuration and problems of conventional hysteresis circuit]
First, a schematic configuration and problems of a conventional hysteresis circuit will be described with reference to the drawings. FIG. 6 is a block diagram showing a configuration of a conventional hysteresis circuit.

  Referring to FIG. 6, the conventional hysteresis circuit uses an output signal (digital signal) out of an A / D converter (not shown) as an input signal, and outputs a signal out_hys generated according to the hysteresis of the input signal as an output signal. To do. In the following description, the output signal out input to the hysteresis circuit is also referred to as “input signal value”, and the signal out_hys output from the hysteresis circuit is also referred to as “output signal value”.

  The conventional hysteresis circuit includes a D flip-flop 1100 and an output circuit 1000 for generating an output signal value out_hys.

  The D flip-flop 1100 is a delay flip-flop, and operates based on a clock CLK generated by a clock generation circuit (not shown). The D flip-flop 1100 takes the input signal value out in response to the rising of the clock CLK and supplies it to the output circuit 1000.

  The output circuit 1000 receives the input signal value out and the input signal value out delayed by one clock by the D flip-flop 1100 in synchronization with the clock CLK. In the following description, in order to distinguish these two input signal values, the input signal value out of the current clock is also referred to as “input signal value out”, and the input signal value out delayed by one clock is expressed as “input signal value”. Also referred to as “out_d1”. This input signal value out_d1 corresponds to the input signal value out one clock before. The output circuit 1000 generates an output signal value out_hys corresponding to the hysteresis (history) of the difference value between these two input signal values.

  Specifically, the output circuit 1000 calculates and holds a difference value (= out−out_d1) obtained by subtracting the input signal value out_d1 from the input signal value out. This difference value represents the amount of change in the input signal value out of the current clock with respect to the input signal value out one clock before. Then, the output circuit 1000 compares the difference value of the previous clock with the difference value of the current clock, and compares the comparison result with the following equation (3) to obtain the output signal value out_hys of the current clock. calculate.

  Specifically, when the difference value of 1 clock before is 1 bit and the current clock difference value is 1 bit, the output circuit 1000 adds 1 bit to the input signal value out_d1 of 1 clock before Let the value be the output signal value out_hys. Then, the output circuit 1000 outputs the generated output signal value out_hys in response to the next rising edge of the clock. That is, when the transition that the input signal value out of the current clock increases by 1 bit with respect to the input signal value out of 1 clock before occurs twice (= the input signal value out has transitioned by 2 bits in total) Sometimes) increase the output signal value out_hys by one bit.

  On the other hand, when the difference value one clock before is −1 bit and the current clock difference value is −1 bit, the output circuit 1000 subtracts 1 bit from the input signal value out_d1 one clock before. Let the value be the output signal value out_hys. Then, the output circuit 1000 outputs the generated output signal value out_hys in response to the next rising edge of the clock. That is, when the transition that the input signal value out of the current clock decreases by 1 bit with respect to the input signal value out of one clock before occurs twice (= the input signal value out is a total of −2 bits transition) The output signal value out_hys is decreased by 1 bit.

  Note that the output circuit 1000 is configured such that the difference value of the current clock becomes 1 bit after a plurality of clock periods in which the difference value becomes 0 continuously after the difference value before a plurality of clocks becomes 1 bit. That is, the output signal value out_hys is increased by 1 bit even when the input signal value out transitions a total of 2 bits across a plurality of clock periods in which the difference value is 0.

  Similarly, after the difference value for each clock becomes −1 bit, and after a plurality of clock periods in which the difference value becomes 0 continuously, the current clock difference value becomes −1 bit, that is, The output signal value out_hys is also decreased by 1 bit even when the input signal value out transits a total of −2 bits across a plurality of clock periods in which the difference value becomes 0.

  As described above, in the conventional hysteresis circuit, the transition direction of the input signal value out is determined by comparing the input signal value out of the current clock with the input signal value out of one clock before. Then, the output signal value out_hys is changed by 1 bit in the determined transition direction. FIG. 7 shows the relationship between the input signal value out and the output signal value out_hys in the conventional hysteresis circuit. Referring to FIG. 7, when the input signal value out has transitioned by 2 bits in total, it is determined that the input signal value out has shifted in the increasing direction, and 1 bit is added to the input signal value out_d1 one clock before. The value is the output signal value out_hys of the next clock. Further, when the input signal value out has transitioned by a total of −2 bits, it is determined that the input signal value out has transitioned in a decreasing direction, and a value obtained by subtracting 1 bit from the input signal value out_d1 one clock before is calculated as follows. Assume that the output signal value of the clock is out_hys.

  With such a configuration, when the input signal value out vibrates with a 2-bit vibration width, the output signal value out_hys is not affected by the vibration of the input signal value out and has a constant value (vibration). Corresponding to the signal value at the center of the width). However, when the vibration width of the input signal value out increases to 3 bits, the output signal value out_hys cannot be affected by the vibration of the input signal value out, and vibrates with a vibration width of 1 bit. That is, in the conventional hysteresis circuit, a stable output signal value out_hys can be obtained as long as the vibration width of the input signal value out is 2 bits or less. However, when the vibration width of the input signal value out exceeds 2 bits, The output signal value out_hys vibrates due to the influence of the vibration of the input signal value out.

  The output signal value out_hys is set to a value obtained by adding 1 bit to the input signal value out_d1 one clock before, or a value obtained by subtracting one bit from the input signal value out_d1 one clock before. However, when a so-called “bit skip” occurs in which the signal value does not transition by one bit every clock due to disturbance noise or the like, there arises a problem that the bit skip appears in the output signal value out_hys as it is.

  Further, since the output signal value out_hys is generated by adding / subtracting 1 bit to the input signal value out_d1 one clock before, the output signal value out_hys always has a deviation of at least 1 bit with respect to the input signal value out. . Therefore, the transition is completed without the output signal value out_hys finally matching the input signal value out.

  As will be described in detail below, the hysteresis circuit according to the embodiment is configured to obtain a stable output signal value out_hys even when vibration or bit skip occurs in the input signal value out. Further, the hysteresis circuit according to the embodiment is configured to be able to finally match the output signal value out_hys with the input signal value out.

[Configuration of Hysteresis Circuit According to One Embodiment]
FIG. 3 is a block diagram illustrating a configuration of a hysteresis circuit according to an embodiment. The hysteresis circuit 30 according to the embodiment uses an output signal out from the A / D converter 20 (FIG. 1) as an input signal, and outputs a signal out_hys generated according to the hysteresis of the input signal as an output signal. Therefore, similarly to the conventional hysteresis circuit shown in FIG. 5, the output signal out input to the hysteresis circuit 30 is also referred to as “input signal value”, and the signal out_hys output from the hysteresis circuit 30 is also referred to as “output signal value”. To do.

  Referring to FIG. 3, hysteresis circuit 30 according to one embodiment includes D flip-flops 50 and 52, a subtraction circuit 60, and an output circuit 70. The hysteresis circuit 30 further includes a classification circuit 80, a D flip-flop 54, RS flip-flops 91 to 97, an arithmetic circuit 100, a command generation circuit 110, and logical product circuits 120 and 122.

  The D flip-flop 50 operates based on a clock CLK generated by a clock generation circuit (not shown). The D flip-flop 50 takes in the input signal value out in response to the rise of the clock CLK and supplies it to the subtraction circuit 60.

  The D flip-flop 52 operates based on the clock CLK. The D flip-flop 52 takes in the output signal value out_hys in response to the rise of the clock CLK and supplies it to the subtraction circuit 60.

  In synchronization with the clock CLK, the input signal value out delayed by one clock by the D flip-flop 50 and the output signal value out_hys delayed by one clock by the D flip-flop 52 are input to the subtraction circuit 60. . In the following description, the input signal value out delayed by one clock is also referred to as “input signal value out_d”, and the output signal value out_hys delayed by one clock is also referred to as “output signal value out_hys_d”. The input signal value out_d and the output signal value out_hys_d correspond to the input signal value out and the output signal value out_hys one clock before, respectively.

  The subtraction circuit 60 calculates a difference value SUB (= out_d−out_hys_d) obtained by subtracting the output signal value out_hys_d from the input signal value out_d by the following equation (4). The subtraction circuit 60 outputs the calculation result SUB to the output circuit 70. The difference value SUB represents a difference value between the input signal value out one clock before and the output signal value out_hys one clock before.

  The output circuit 70 receives the output signal value out_hys_d from the D flip-flop 52 and receives the difference value SUB from the subtraction circuit 60. The output circuit 70 calculates the output signal value out_hys of the current clock by comparing the difference value SUB with the following equation (5).

  Specifically, the output circuit 70 presets a positive threshold value and a negative threshold value for the difference value SUB. The output circuit 70 compares the difference value SUB with the positive threshold value and the negative threshold value for each clock CLK. When the difference value SUB is equal to or greater than the positive threshold value, the output circuit 70 sets a value obtained by adding 1 bit to the output signal value out_hys_d as the output signal value out_hys of the current clock. That is, when the input signal value out becomes larger than the output signal value out_hys by a positive threshold or more, the output signal value out_hys is increased by 1 bit.

  Further, when the difference value SUB is equal to or smaller than the negative threshold value, the output circuit 70 sets a value obtained by subtracting 1 bit from the output signal value out_hys_d as the output signal value out_hys of the current clock. That is, when the input signal value out becomes smaller than the output signal value out_hys by a negative threshold or less, the output signal value out_hys is decreased by 1 bit.

  Here, the positive threshold value and the negative threshold value are set according to the vibration width of the input signal value out. Each of the positive threshold value and the negative threshold value is set to a value obtained by adding one bit to a half value of the vibration width of the input signal value out. For example, when the vibration width of the input signal value out is 6 bits, the positive threshold value is set to 4 bits and the negative threshold value is set to -4 bits.

  When the difference value SUB is 4 bits or more, the output circuit 70 sets a value obtained by adding 1 bit to the output signal value out_hys_d as the output signal value out_hys of the current clock. On the other hand, when the difference value SUB is −4 bits or less, the output circuit 70 sets the value obtained by subtracting 1 bit from the output signal value out_hys_d as the output signal value out_hys of the current clock. The output circuit 70 outputs the generated output signal value out_hys in response to the next rising edge of the clock CLK.

  When the difference value SUB is not less than −3 bits and not more than 3 bits, the output circuit 70 uses the output signal value out_hys_d as it is, except when either an addition command UP or a subtraction command DN described later is activated. The output signal value out_hys of the current clock is assumed. Thereby, the influence of the vibration of the input signal value out can be eliminated.

  Thus, the output circuit 70 increases or decreases the output signal value out_hys by 1 bit when the input signal value out increases or decreases beyond the oscillation width of the input signal value out. Therefore, when the input signal value out vibrates due to the influence of the excitation signal, the output signal value out_hys is not changed. Therefore, the output signal value out_hys is kept at a constant value without vibrating.

  On the other hand, when the input signal value out increases or decreases beyond the oscillation width of the input signal value out, the output circuit 70 adds or subtracts 1 bit to the output signal value out_hys (output signal value out_hys_d) one clock before. Thus, the output signal value out_hys always changes bit by bit. Therefore, even if a bit skip occurs in the input signal value out, the transition of the output signal value out is limited to 1 bit. As a result, it is possible to prevent bit skipping in the output signal value out_hys.

  As described above, the conventional hysteresis circuit determines the transition direction of the input signal value out, and based on the determination result, the value obtained by adding / subtracting 1 bit to the input signal value out is set as the output signal value out_hys. To do. In contrast, the hysteresis circuit according to the embodiment determines the magnitude of the transition of the input signal value out, and determines that the input signal value out has transitioned beyond the vibration width of the input signal value out. A value obtained by adding / subtracting 1 bit to / from the output signal value out_hys_d is defined as an output signal value out_hys.

  As described above, in the hysteresis circuit 30, the D flip-flop 50, the subtracting circuit 60, the output circuit 70, and the D flip-flop 52 prevent the output signal value out_hys from oscillating and skipping the bit, thereby reducing the output signal value out_hys. A stabilization circuit for stabilization is configured.

  On the other hand, as will be described below, the classification circuit 80, the D flip-flop 54, the RS flip-flops 91 to 97, the arithmetic circuit 100, and the command generation circuit 110 finally convert the output signal value out_hys to the input signal value. A tracking circuit for matching with out is configured.

  In this follow-up circuit, a sub-clock reclr having a cycle that is a multiple of the clock CLK is used. The follow-up circuit determines the magnitude relationship between the input signal value out and the output signal value out_hys based on the transition of the difference value SUB in one cycle of the sub clock reclr. Based on the determination result, the output signal value out_hys is increased / decreased bit by bit in synchronism with the subclock recr so as to approach the input signal value out.

  Specifically, the classification circuit 80 receives the difference value SUB (= out_d−out_hys_d) from the subtraction circuit 60 every clock CLK. The classification circuit 80 outputs the output values OUT3, OUT2, OUT1, OUT0, OUTM1, OUTM2, and OUTM3 (hereinafter collectively referred to as the output value OUT) according to the difference value SUB in accordance with the following equation (6). Either one is set to “1”. The initial value of the output value OUT is set to “0”.

  For example, when the difference value SUB is 3 or more, the output value OUT3 is set to “1”, and when the difference value SUB is 2, the output value OUT2 is set to “1”. When the difference value SUB is −3 or less, the output value OUTM3 is set to “1”, and when the difference value SUB is −2, the output value OUTM2 is set to “1”.

  The output values OUT3, OUT2, OUT1, OUT0, OUTM1, OUTM2, and OUTM3 set to “1” or “0” by the classification circuit 80 are respectively provided to the subsequent stage RS flip-flops 91 to 97.

  The RS flip-flops 91 to 97 are set-reset type flip-flops. Each of the RS flip-flops 91 to 97 receives the output value OUT corresponding to the set terminal, and receives the sub clock reclr at the reset terminal. Each of the RS flip-flops 91 to 97 is set when the corresponding output value OUT is switched from 0 to 1, and outputs a signal value 1 from the output terminal Q. In addition, each of the RS flip-flops 91 to 97 enters a reset state in response to the rising edge of the sub clock reclr, and outputs a signal value 0 from the output terminal Q. The signal values (“1” or “0”) output from the RS flip-flops 91 to 97 are input to the arithmetic circuit 100 as input values LT3, LT2, LT1, LT0, LTM1, LTM2, and LTM3, respectively. As described above, the RS flip-flops 91 to 97 serve to hold the change of the difference value SUB in one cycle of the sub clock reclr and output it to the arithmetic circuit 100.

  The arithmetic circuit 100 calculates the maximum value and the minimum value of the difference value SUB based on the input values LT3, LT2, LT1, LT0, LTM1, LTM2, and LTM3. The arithmetic circuit 100 sends the calculated maximum value and minimum value to the command generation circuit 110 as output values OUTP and OUTM, respectively. Specifically, the arithmetic circuit 100 calculates the output value OUTP which is the maximum value of the difference value SUB using the following formula (7). In addition, the arithmetic circuit 100 calculates an output value OUTM that is the minimum value of the difference value SUB by using the following equation (8).

  For example, when the input value LT3 = 1, the output value OUTP is set to “3” regardless of the values of the input values LT2 and LT1. Note that the input value LT3 = 1 indicates that the difference value SUB is 3 or more during one cycle of the subclock reclr. In this case, the arithmetic circuit 100 determines the output value OUTP, which is the maximum value of the difference value SUB, to “3”.

  On the other hand, when the input value LT3 = 0 and the input value LT2 = 1, the output value OUTP is set to “2” regardless of the value of the input value LT1. The input values LT3 = 0 and LT2 = 1 indicate that the difference value SUB is 2 at the maximum during one cycle of the subclock reclr. In this case, the arithmetic circuit 100 determines the output value OUTP, which is the maximum value of the difference value SUB, to “2”.

  Further, when the input values LT3 and LT2 are both 0 and the input value LT1 = 1, the output value OUTP is set to “1”. The input values LT3 = LT2 = 0 and LT1 = 1 indicate that the difference value SUB is 1 at the maximum during one cycle of the subclock reclr. In this case, the arithmetic circuit 100 determines the output value OUTP, which is the maximum value of the difference value SUB, to “1”.

  The arithmetic circuit 100 also calculates the output value OUTM, which is the minimum value of the difference value SUB, by a similar method based on the input values LTM3, LTM2, and LTM1. As a result, the output value OUTM is determined to be one of −3, −2, −1, and 0.

  The command generation circuit 110 receives the output values OUTP and OUTM calculated by the arithmetic circuit 100 in synchronization with the clock CLK. The command generation circuit 110 generates an addition command UP for increasing the output signal value out_hys by 1 bit and a subtraction command DN for decreasing the output signal value out_hys by 1 bit according to the output values OUTP and OUTM. Specifically, the command generation circuit 110 adds the output value OUTP and the output value OUTM according to the following equation (9).

  When the absolute value of the output value OUTP is larger than the absolute value of the output value OUTM, the addition result indicates a value of 1 or more. This addition result indicates that the output signal value out_hys is lower than the input signal value out in one cycle of the sub clock reclr. Therefore, the command generation circuit 110 activates the addition command UP to “1” in order to bring the output signal value out_hys closer to the input signal value out.

  On the other hand, when the absolute value of the output value OUTM is larger than the absolute value of the output value OUTP, the addition result indicates a value of −1 or less. This addition result indicates that the output signal value out_hys is in a state exceeding the input signal value out in one cycle of the sub-clock reclr. Therefore, the command generation circuit 110 activates the subtraction command DN to “1” in order to bring the output signal value out_hys closer to the input signal value out.

  The addition command UP generated by the command generation circuit 110 is input to one input terminal of the AND circuit 120. The logical product circuit 120 outputs the logical product of the addition command UP and the sub clock reclr to the output circuit 70. The addition command UP is converted by the AND circuit 120 into a command that is activated to “1” during the period when the sub clock reclr is at the H level.

  The subtraction instruction DN generated by the instruction generation circuit 110 is input to one input terminal of the AND circuit 122. The logical product circuit 122 outputs a logical product of the subtraction command DN and the sub clock reclr to the output circuit 70. The subtraction command DN is converted by the AND circuit 122 into a command that is activated to “1” during the period when the sub clock reclr is at the H level.

  The output circuit 70 increases / decreases the output signal value out_hys by 1 bit according to the addition command UP and the subtraction command DN output from the AND circuits 120 and 122, respectively. The adjustment of the output signal value out_hys based on the addition command UP and the subtraction command DN has a lower processing priority than the generation of the output signal value out_hys based on the difference value SUB described above. . Therefore, when the difference value SUB is −3 bits or more and 3 bits or less, the output circuit 70 adjusts the output signal value out_hys according to the addition command UP and the subtraction command DN according to the following equation (10). That is, when the addition command UP is activated to “1”, the output circuit 70 sets a value obtained by adding 1 bit to the output signal value out_hys_d as the output signal value out_hys of the current clock. That is, the output signal value out_hys is increased by 1 bit in response to the addition command UP.

  On the other hand, when the subtraction command DN is activated to “1”, the output circuit 70 sets a value obtained by subtracting 1 bit from the output signal value out_hys_d as the output signal value out_hys of the current clock. That is, the output signal value out_hys is decreased by 1 bit in response to the subtraction command DN.

  FIG. 4 is a diagram illustrating a relationship between the input signal value out and the output signal value out_hys in the hysteresis circuit according to the embodiment. FIG. 4 also shows the sub-clock recr.

  Referring to FIG. 4, the input signal value out vibrates with a vibration width of 6 bits. In the output circuit 70, the positive threshold is set to 4 bits, and the negative threshold is set to -4 bits. Thus, when the difference value SUB between the input signal value out_d and the output signal value out_hys_d becomes 4 bits or more, the output signal value out_hys increases by 1 bit. Further, when the difference value SUB becomes -4 bits or less, the output signal value out_hys decreases by 1 bit.

  When the input signal value out vibrates with a 6-bit vibration width, the output signal value out_hys is not affected by the vibration of the input signal value out, and is a constant value (corresponding to the signal value at the center of the vibration width). ).

  In parallel with the generation of the output signal value out_hys, the magnitude relationship between the input signal value out and the output signal value out_hys in one cycle of the sub clock reclr is determined. As shown in FIG. 4, when the input signal value out exceeds the output signal value out_hys in one cycle of the sub clock reclr, the output signal value out_hys increases by 1 bit for each sub clock reclr. As a result, the output signal value out_hys finally matches the input signal value out.

  As described above, according to the hysteresis circuit according to the embodiment, a stable output signal value out_hys can be obtained even when the input signal value out has a vibration or a bit skip. Further, according to the hysteresis circuit according to the embodiment, the output signal value out_hys can be finally matched with the input signal value out.

[Modification of hysteresis circuit]
In the hysteresis circuit 30 of FIG. 3, the positive threshold value and the negative threshold value that the output circuit 70 uses for comparison with the difference value SUB can be set according to the vibration width of the input signal value out. Specifically, each of the positive threshold value and the negative threshold value is set to a value obtained by adding one bit to a half value of the vibration width of the input signal value out. For example, when the vibration width of the input signal value out is 8 bits, the positive threshold value is set to 5 bits and the negative threshold value is set to -5 bits.

  Thus, by setting the positive threshold value and the negative threshold value variably according to the vibration width of the input signal value out, it is possible to reliably eliminate the influence of the vibration of the input signal value out. Note that the vibration width of the input signal value out has a magnitude depending on the resolution of the A / D converter 20 in the previous stage. Therefore, the motor control system shown in FIG. 1 is operated to evaluate the vibration width of the input signal value out in advance, and the positive threshold value and the negative threshold value are set based on the evaluated vibration width of the input signal value out. be able to.

  FIG. 5 is a block diagram showing a modification of the hysteresis circuit 30 of FIG. Referring to FIG. 5, hysteresis circuit 30 </ b> A according to this modification is configured such that output circuit 70 reads a positive threshold value and a negative threshold value from register 210 in hysteresis circuit 30 according to the embodiment shown in FIG. 3. It is a thing. The microcomputer 200 acquires in advance the vibration width of the input signal value out by operating the motor control system of FIG. Then, the microcomputer 200 sets a positive threshold value and a negative threshold value based on the obtained vibration width of the input signal value out. The set positive threshold value and negative threshold value are stored in the register 210. When the motor control system is activated, the stored positive threshold value and negative threshold value are read from the register 210 into the output circuit 70.

  In the above embodiment, the configuration in which the hysteresis circuit according to the present invention is applied to the R / D converter has been described. However, the application of the present invention is not limited to the R / D converter. Specifically, the fact that the present invention can be applied to a hysteresis circuit that takes a digital signal as an input and generates an output signal corresponding to the hysteresis of the input signal will be described.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  1 motor driver, 2 motor control unit, 3 resolver, 4 R / D converter, 10 excitation signal generation unit, 20 A / D conversion unit, 30, 30A hysteresis circuit, 50, 52, 54 D flip-flop, 60 subtraction circuit, 70 output circuit, 80 classification circuit, 91-97 RS flip-flop, 100 arithmetic circuit, 110 command generation circuit, 120, 122 AND circuit, M1 AC motor.

Claims (9)

A hysteresis circuit that generates an output signal corresponding to the hysteresis of a digital input signal in synchronization with a clock,
A subtraction circuit for calculating a difference value between an input signal value one clock before and an output signal value one clock before;
An output circuit that generates and outputs an output signal value of a current clock according to a difference value from the subtracting circuit;
The output circuit is
When the difference value is greater than or equal to a positive threshold value, a value obtained by adding 1 bit to the output signal value one clock before is output as the output signal value of the current clock;
When the difference value is equal to or less than a negative threshold value, a value obtained by subtracting 1 bit from the output signal value of the previous clock is output as the output signal value of the current clock;
A hysteresis circuit that outputs the output signal value of the previous clock as the output signal value of the current clock when the difference value is less than the positive threshold value and greater than the negative threshold value.   The hysteresis circuit according to claim 1, wherein the positive threshold value and the negative threshold value are set according to a vibration width of the input signal value.   3. The hysteresis circuit according to claim 2, wherein each of the positive threshold value and the negative threshold value is set to a value obtained by adding one bit to a half value of a vibration width of the input signal value. An operation circuit that operates in synchronization with a subclock having a period that is a multiple of the clock, and that calculates a maximum value and a minimum value of the difference value in one period of the subclock;
The maximum value of the difference value from the arithmetic circuit and the minimum value of the difference value are added and an addition command is generated when the addition result is 1 or more, while the addition result is -1 or less. A command generation circuit for generating a subtraction command in some cases;
The output circuit is
When the addition command is received when the difference value is less than the positive threshold value and greater than the negative threshold value, a value obtained by adding one bit to the output signal value one clock before is obtained. , Output the current clock output signal value,
When the subtraction command is received when the difference value is less than the positive threshold value and greater than the negative threshold value, a value obtained by subtracting one bit from the output signal value one clock before is obtained. The hysteresis circuit according to any one of claims 1 to 3, wherein the hysteresis circuit outputs the output signal value of the current clock. A resolver / digital converter for converting an output signal of a resolver that detects a rotation angle of a rotating body into a digital angle signal,
An analog / digital converter that converts the output signal of the resolver into the angle signal;
In synchronization with the clock, an output signal corresponding to the hysteresis of the input signal from the analog / digital conversion unit is generated, and a hysteresis circuit that outputs the angle signal is provided.
The hysteresis circuit is:
A subtraction circuit for calculating a difference value between an input signal value one clock before and an output signal value one clock before;
An output circuit that generates and outputs an output signal value of a current clock according to a difference value from the subtracting circuit,
The output circuit is
When the difference value is greater than or equal to a positive threshold value, a value obtained by adding 1 bit to the output signal value one clock before is output as the output signal value of the current clock;
When the difference value is equal to or less than a negative threshold value, a value obtained by subtracting 1 bit from the output signal value of the previous clock is output as the output signal value of the current clock;
A resolver / digital converter that outputs the output signal value of the previous clock as the output signal value of the current clock when the difference value is less than the positive threshold value and greater than the negative threshold value. .   The resolver / digital converter according to claim 5, wherein the positive threshold value and the negative threshold value are set according to a vibration width of the input signal value.   The resolver / digital converter according to claim 6, wherein each of the positive threshold value and the negative threshold value is set to a value obtained by adding one bit to a half value of a vibration width of the input signal value. . An operation circuit that operates in synchronization with a subclock having a period that is a multiple of the clock, and that calculates a maximum value and a minimum value of the difference value in one period of the subclock;
The maximum value of the difference value from the arithmetic circuit and the minimum value of the difference value are added and an addition command is generated when the addition result is 1 or more, while the addition result is -1 or less. A command generation circuit for generating a subtraction command in some cases;
The output circuit is
When the addition command is received when the difference value is less than the positive threshold value and greater than the negative threshold value, a value obtained by adding one bit to the output signal value one clock before is obtained. , Output the current clock output signal value,
When the subtraction command is received when the difference value is less than the positive threshold value and greater than the negative threshold value, a value obtained by subtracting one bit from the output signal value one clock before is obtained. The resolver / digital converter according to any one of claims 5 to 7, wherein the resolver / digital converter outputs the output signal value of the current clock.   The resolver / digital converter according to claim 8, wherein the sub clock has a period that is a multiple of a period of an excitation signal input to the resolver.

Images