JP2014070956A - Image processing apparatus, visual inspection device, image processing method, and visual inspection method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technology for improving inspection processing efficiency in employing a processor having a plurality of cores.SOLUTION: A visual inspection device 1 detects a pattern defect formed on a substrate 9. The visual inspection device 1 includes: an image processing part 59 equipped with a GPU 591 having a plurality of GPU cores 5910; a buffer memory 53 storing an inspection image to be inspected; an inspection task holding part 51 which holds inspection tasks including a plurality of inspection commands and generated for each inspection section SEC formed by dividing the inspection image into plurality of sections; and a GPU control unit 57 which registers a second inspection command on the GPU 591 when there is no dependency between a first inspection command registered in advance on the GPU 591 and the second inspection command not registered on the GPU 591.

Description

  The present invention relates to a technique for processing an image using a processor having a plurality of cores.

  Conventionally, when detecting a defect in a circuit pattern formed on a substrate such as a semiconductor wafer, an appearance inspection is performed in which an image of the circuit pattern is acquired and a defect portion is extracted based on a comparison with a reference image serving as a reference. It has been broken. Recently, in order to perform processing at high speed, a parallel data processing type appearance inspection apparatus including a plurality of processors (processor elements) has been proposed (for example, Patent Document 1).

  Specifically, in the appearance inspection apparatus described in Patent Document 1, when dividing an image scanned by a line sensor, the overall control computer sets a condition for distributing the divided image to each of a plurality of processor elements. To do. Then, the image distribution processing unit divides the image according to the distribution condition, and transfers each of the images to the processor element. Each processor element performs a prescribed inspection process to extract a defect in the circuit pattern.

  Moreover, in the appearance inspection apparatus described in Patent Document 1, the range of an image to be cut out is adjusted based on the processing capability of the processor element and the calculation load for each inspection algorithm. As a result, the load is applied evenly to each processor element so that the processing capacity of the processor element is efficiently utilized.

JP 2011-028410 A

  Recent processors include a processor (multi-core processor) that includes a plurality of arithmetic cores inside and operates them in parallel to perform data processing at high speed. A GPU (Graphics Processing Unit) is known as one of such processors, and this GPU includes, for example, tens to thousands of cores, and is also called a massively parallel processor. It is also conceivable to apply such a multi-core processor to the above-described visual inspection apparatus.

  However, the invention of Patent Document 1 is intended to cause a plurality of processors to perform parallel processing. For this reason, Patent Document 1 does not consider the efficient execution of arithmetic processing in a multi-core processor. For this reason, even if a multi-core processor is applied to a conventional visual inspection apparatus, the efficiency of the inspection process cannot be improved.

  The present invention has been made in view of the above problems, and an object thereof is to provide a technique for improving the efficiency of inspection processing when a processor having a plurality of cores is used.

  In order to solve the above-described problem, a first aspect is an image processing apparatus, an image processing unit including a processor having a plurality of cores, an image storage unit that stores an inspection image to be inspected, and the inspection An inspection task holding unit for holding an inspection task including a plurality of inspection commands executed by the processor, which is generated for each inspection section obtained by dividing an image into a plurality of parts, and registers the plurality of inspection commands in the processor A processor control unit to be executed, and the processor control unit includes a first inspection command previously registered in the processor among the plurality of inspection commands included in one inspection task and an unregistered in the processor The second inspection command is registered in the processor when there is no dependency in the processing content with the second inspection command.

  According to a second aspect, in the image processing apparatus according to the first aspect, the processor control unit causes the processor to execute a plurality of inspection commands registered in the processor in parallel.

  A third aspect is the image processing apparatus according to the first or second aspect, wherein the image processing unit includes a plurality of the processors, and the plurality of inspection tasks are assigned to the plurality of processors. Each is distributed.

  Further, in a fourth aspect, in the image processing apparatus according to any one of the first to third aspects, the processor control unit is configured based on the types of the first inspection command and the second inspection command. It is determined whether or not the second command is registered in the processor.

  Further, a fifth aspect is an appearance inspection apparatus for inspecting a pattern formed on a substrate, the image processing apparatus according to any one of the first to fourth aspects, and the inspection image obtained by photographing the substrate. The image processing unit inspects a defect of a pattern formed on the substrate.

  According to a sixth aspect, in the visual inspection apparatus according to the fifth aspect, the plurality of inspection commands include a die inspection command for inspecting a non-repeated pattern and an array inspection command for inspecting a repetitive pattern.

  The seventh aspect is an image processing method, wherein (a) a plurality of processors executed by a processor having a plurality of cores is executed for each inspection section obtained by dividing an inspection image to be inspected into a plurality of sections. A step of generating an inspection task composed of inspection commands; and (b) a step of registering and executing the plurality of inspection commands in the processor, wherein the step (b) includes one inspection task. Among the plurality of inspection commands included, when there is no dependency in the processing content between the first inspection command previously registered in the processor and the second inspection command not registered in the processor, the processor Registering the second inspection command;

  According to an eighth aspect, in the image processing method according to the seventh aspect, (c) a step in which the processor executes the plurality of inspection commands registered in the processor in the step (b) in parallel. Further included.

  Further, a ninth aspect is an appearance inspection method for inspecting a pattern formed on a substrate, and (A) a step of acquiring an inspection image by photographing the substrate, and (B) a plurality of the inspection images. Generating a test task including a plurality of test commands executed by a processor having a plurality of cores for each test section obtained by dividing; and (C) registering and executing the plurality of test commands in the processor. The step (C) includes, among the plurality of inspection commands included in one inspection task, a first inspection command previously registered in the processor and a second unregistered in the processor. This is a step of registering the second inspection command in the processor when there is no dependency on the processing content with the inspection command.

  According to a tenth aspect, in the visual inspection method according to the ninth aspect, (D) a step in which the processor executes the plurality of inspection commands registered in the processor in the step (C) in parallel. Further included.

  According to the first to tenth aspects, when there is no dependency in the processing content between the first inspection command registered in the processor and the second inspection command not yet registered, the second inspection command Is registered in the processor. Thereby, since the first inspection command and the second inspection command can be executed in parallel in the same processor, the efficiency of the arithmetic processing can be improved.

  Moreover, according to the image processing apparatus which concerns on a 2nd aspect, a some test | inspection command can be processed in parallel.

  Moreover, according to the image processing apparatus which concerns on a 3rd aspect, a some test | inspection task can be processed in parallel.

  Moreover, according to the image processing apparatus which concerns on a 4th aspect, it can be made to determine quickly and appropriately whether a 2nd test command is registered.

  Moreover, according to the 5th aspect, a test | inspection image can be acquired and this can be test | inspected by image | photographing a board | substrate with an imaging | photography part.

  Moreover, according to the 6th aspect, the defect of a repeating pattern and a non-repeating pattern can each be test | inspected appropriately.

It is a schematic block diagram of the external appearance inspection apparatus which concerns on embodiment. It is a functional block diagram of the external appearance inspection apparatus which concerns on embodiment. It is a schematic plan view which shows an example of a board | substrate. FIG. 4 is a schematic plan view of one die shown in FIG. 3. It is a figure which shows an example of scan imaging | photography. It is a figure for demonstrating the process which sets an inspection section with respect to the image obtained by the scanning imaging | photography shown by FIG. It is a figure which shows the example of other scan imaging | photography. It is a figure for demonstrating the process which sets an inspection section with respect to the image obtained by the scanning imaging | photography shown by FIG. It is a figure explaining a mode that an inspection task is generated for every inspection section. It is a figure for demonstrating the example of a test | inspection command. It is a figure which shows an example of a time chart when GPU performs a some inspection command. It is a figure for demonstrating the example of the test | inspection command which cannot be performed in parallel. It is a figure which shows an example of a time chart when GPU which concerns on a comparative example performs a some test | inspection command. It is a figure for demonstrating the other example which divides | segments a test object area | region.

  Hereinafter, embodiments will be described in detail with reference to the drawings. However, the configuration described in this embodiment is merely an example, and is not intended to limit the scope of the present invention.

<1. First Embodiment>
<1.1. Configuration of Appearance Inspection Apparatus 1>
FIG. 1 is a schematic configuration diagram of an appearance inspection apparatus 1 according to the embodiment. FIG. 2 is a functional block diagram of the appearance inspection apparatus 1 according to the embodiment. In addition, in FIG. 1 and each subsequent figure, the dimension and number of each part may be exaggerated or simplified as needed for easy understanding. In addition, in FIG. 1 and subsequent drawings, in order to facilitate understanding of the positional relationship, an XYZ orthogonal coordinate system in which the Z-axis direction is the vertical direction and the XY plane is the horizontal plane may be attached.

  The appearance inspection apparatus 1 captures an image (image (such as a circuit pattern)) formed on a semiconductor substrate 9 (hereinafter simply referred to as “substrate 9”), which is an object to be inspected, by photographing a defect with a photographing unit 3. It is an apparatus for inspecting based on an inspection image. The appearance inspection apparatus 1 includes a stage 2 (substrate holding unit) that holds the substrate 9, a stage moving mechanism 21 that moves the stage 2 in the horizontal direction (X-axis direction and Y-axis direction), and a vertical upper side (+ Z side) of the substrate 9. ), A control unit 4 that controls the operation of each component of the appearance inspection apparatus 1 such as the stage 2, and an image processing apparatus that detects a defect in a pattern based on an image photographed by the photographing unit 3. 5 and a defect data processing unit 6 for processing the defect data acquired by the image processing apparatus 5.

  The stage moving mechanism 21 includes a Y-direction moving mechanism 22 that moves the stage 2 in the Y-axis direction, an X-direction moving mechanism 23 that moves in the X direction, and a stage that performs focus adjustment by moving the stage 2 in the Z-axis direction. An elevating mechanism 24 is provided. The Y-direction moving mechanism 22 has a ball screw (not shown) connected to the motor 221 and a nut member (not shown) screwed to the ball screw fixed to the X-direction moving mechanism 23. ing. As the motor 221 rotates, the X-direction moving mechanism 23 moves along the guide rail 222 in the Y-axis direction. The X-direction moving mechanism 23 has the same configuration as the Y-direction moving mechanism 22, and the stage 2 is moved in the X direction along the pair of guide rails 232 by rotating a ball screw (not shown) by the motor 231. The stage moving mechanism 21 may use a linear motion mechanism such as a linear motor in addition to a ball screw.

  The substrate 9 is fixed to the upper surface of the stage 2 by suction during inspection. For this reason, the substrate 9 can be moved relative to the imaging unit 3 by moving the stage 2 in the X direction or the Y direction by the stage moving mechanism 21. In the visual inspection apparatus 1, the substrate 9 is moved in the X-axis direction or the Y-axis direction, and visible light is irradiated onto the substrate 9 in a surface or line form from an irradiation unit such as a halogen lamp or an LED (not shown). The And the reflected light reflected by the board | substrate 9 is detected by the detector (here line sensor 31) with which the imaging | photography part 3 is provided. Note that instead of visible light, ultraviolet light or infrared light may be irradiated. Moreover, what emits an electron beam or a laser beam may be utilized as a light source.

  In the present embodiment, the stage moving mechanism 21 moves the stage 2 to move the substrate 9 relative to the photographing unit 3 in the XY plane. However, the stage 2 may be fixed and the photographing unit 3 may be moved. Of course, both the stage 2 and the photographing unit 3 may be moved individually. That is, the appearance inspection apparatus 1 may be configured in any manner as long as the substrate 9 can be moved relative to the imaging unit 3.

  The imaging unit 3 includes a line sensor 31. The line sensor 31 is configured by arranging a plurality of detection elements that detect an electron beam or laser light irradiated on the substrate 9 in a line. A detection signal detected by the line sensor 31 is appropriately converted into digital data by an AD converter (not shown), and is sequentially transmitted as an image signal to the buffer memory 53 of the image processing device 5 through a predetermined process such as a correction process. In this way, the inspection image to be inspected is stored in the buffer memory 53. The buffer memory 53 is an example of an image data storage unit. In addition, the imaging unit 3 stores the inspection image in the buffer memory 53 and also stores the number of lines captured by the line sensor 31 (the number of captured lines) in the buffer memory 53.

  In the present embodiment, the line sensor 31 is employed in the photographing unit 3, but an area sensor such as a CCD may be employed instead of the line sensor 31.

  The control unit 4 is configured as a general computer including a CPU (Central Processing Unit) and a RAM (Random Access Memory). The inspection recipe creation unit 41, the inspection task generation unit 43, and the stage control unit 45 illustrated in FIG. 2 are functional blocks that are realized in software by the CPU operating according to a program. Note that some or all of these functions may be realized in hardware by a dedicated circuit or the like.

  The inspection recipe creation unit 41 provides a GUI for creating an inspection recipe in order for the operator to determine the inspection contents to be executed in the appearance inspection apparatus 1. The inspection recipe is an inspection condition given by the operator before the inspection. The operator can inspect the inspection conditions (for example, the arrangement information of the die 91 on the substrate 9, the arrangement information of the repeated pattern region 93 and the repeated pattern region 95 in the same die 91, the inspection range, the inspection method, or the like via the operation unit 49. Set the inspection parameters. The inspection parameter includes, for example, a filter setting value for noise removal on the image, a threshold value (for example, a pixel density value) for determining a pattern defect, or the like.

  The inspection task generation unit 43 generates an inspection task based on the inspection recipe created by the inspection recipe creation unit 41. The inspection task is a unit of inspection processing executed by the GPU 591 described later. The inspection task includes, for example, coordinate information of a part to be inspected by each GPU 591 to be described later, an inspection type (die inspection or array inspection to be described later), or inspection parameters applied to individual inspection processing.

  The inspection task generation unit 43 sorts the plurality of inspection tasks that have been created by the number of lines for scanning imaging that can start inspection, and stores all inspection tasks in the inspection task holding unit 51 (queuing). Thereby, it becomes possible to start the inspection sequentially from the portion of the substrate 9 where the scanning imaging is completed.

  The stage control unit 45 controls the amount of movement, the moving speed, and the like of the stage 2 in the X-axis direction or Y-axis direction by controlling the driving of the motors 221 and 231. The stage control unit 45 controls the movement of the stage 2 so as to photograph a specific area on the substrate 9 designated by the inspection recipe.

  The control unit 4 includes a display unit 47 configured by a liquid crystal monitor or the like for displaying various information, and an operation unit configured by a mouse or a keyboard for an operator to input various information to the control unit 4. 49 is connected. In addition, it is also conceivable that the display unit 47 may function as part or all of the functions of the operation unit 49 by configuring the display unit 47 with a touch panel. Various instructions can be input to the control unit 4 via the operation unit 49 based on the information displayed on the display unit 47.

  Similar to the control unit 4, the image processing device 5 is configured as a general computer including a CPU, a RAM, and the like, and performs various arithmetic processes related to pattern defect detection. The image processing device 5 includes an inspection task holding unit 51, a buffer memory 53, and an image processing control unit 55. The image processing control unit 55 includes a plurality of GPU control units 57. The image processing control unit 55 is a functional block realized by software by the CPU operating according to a program (not shown). Further, the image processing apparatus 5 includes an image processing unit 59 having a plurality of GPUs 591. The operation of each of the plurality of GPUs 591 is controlled by the corresponding GPU control unit 57. Further, each GPU 591 constitutes a multi-core processor including a plurality of GPU cores 5910 (see FIG. 11).

  The control unit 4 and the image processing apparatus 5 are configured by two computers connected by a communication line such as a LAN, but may be configured by a single computer.

  The inspection task holding unit 51 is a storage unit (including one that temporarily stores information such as a RAM) for storing the inspection task generated by the inspection task generation unit 43. The image processing control unit 55 accesses the inspection task holding unit 51 (specifically, a plurality of GPU control units 57 access asynchronously and exclusively). Then, in the inspection task holding unit 51, one of a plurality of inspection tasks arranged in a predetermined order is appropriately taken out.

  As described above, the buffer memory 53 is a storage unit that sequentially stores image signals (image data) based on detection signals that are sequentially detected by the line sensor 31. The image signal stored in the buffer memory 53 is image data having a data amount corresponding to the number of times (that is, the number of lines) detected by the line sensor 31. The buffer memory 53 is an example of an image data storage unit.

  The image processing control unit 55 causes the plurality of GPUs 591 to sequentially execute new image processing according to the next new inspection task held in the inspection task holding unit 51 in the order in which image processing based on the inspection task is completed. . Thus, in the appearance inspection apparatus 1, it is not determined in advance which image processing unit 59 executes a plurality of inspection tasks. Therefore, in the appearance inspection apparatus 1, the GPU 591 that executes one of the plurality of inspection tasks is sequentially determined after the inspection is actually started. However, when starting the inspection, a GPU 591 for executing each inspection task may be determined in advance.

  As described above, each GPU control unit 57 controls a specific GPU 591 among the plurality of GPUs 591. The GPU control unit 57 accesses the inspection task holding unit 51 to acquire the inspection task, and operates the GPU 591 according to an instruction described in the inspection task. The GPU control unit 57 is an example of a processor control unit.

  Each GPU 591 is connected to an image processing memory 593. The GPU 591 and the image processing memory 593 are composed of, for example, one video card (graphic card), and are connected to the buffer memory 53 or the GPU control unit 57 via a PCI Express standard serial bus or the like. ing.

  As the GPU 591, for example, GPGPU (General Purpose Computing on Graphics Processing Unit) provided by nvidia, Inc. of the United States or the like can be used. The GPU 591 is a plurality of programmable shaders (program code (software) that calculates the appearance based on 3D models defined in 3D graphics and information on light sources, and hardware that executes the code. The programmable shader operates according to a predetermined program, and performs highly parallel arithmetic processing related to pattern defect detection. That is, this programmable shader constitutes a GPU core. For development of a program for operating the program shader, for example, various development environments such as CUDA (Compute Unified Device Architecture) and OpenCL provided by nVISIA, USA can be used.

  The image processing memory 593 is a storage unit that provides an area where the GPU 591 performs work. For example, an image processing memory 593 may be a GDDR (Graphics Double Data Rate) standard memory mounted on a general video card and suitable for graphic processing. Note that many commercially available video cards are equipped with a video memory of several gigabytes, and the image processing memory 593 has a sufficient capacity.

  The defect data processing unit 6 shown in FIG. 1 also includes a storage unit (such as a RAM that temporarily stores information such as a RAM) that collects defect information detected by each image processing unit 59 and stores an inspection result. ). Specifically, the defect information includes the coordinate information of the position where the pattern defect is detected, the area information of the defective portion, the density value of the defective pixel, and the like. Of course, the defect information is not limited to such information. The defect data processing unit 6 may be configured by a single computer including a CPU and a RAM, but the control unit 4 or the image processing device 5 may also have the function of the defect data processing unit 6. Conceivable.

<1.2. Pattern defect inspection processing>
When an inspection process is started in the appearance inspection apparatus 1, first, an inspection recipe is generated by the inspection recipe creation unit 41 based on an operation input by an operator. When creating the inspection recipe, the operator designates various inspection conditions such as an inspection range and an inspection method to be applied. The inspection task generation unit 43 creates an inspection task based on the created inspection recipe. The created inspection task is stored in the inspection task holding unit 51. In addition, the appearance inspection apparatus 1 moves the stage 2 according to the inspection recipe by the stage control unit 45 and performs imaging of the inspection range by the imaging unit 3.

  FIG. 3 is a schematic plan view showing an example of the substrate 9. A substrate 9 shown in FIG. 3 is a circular semiconductor wafer, and a plurality of dies 91 are formed on the surface thereof. An imaging area 300 shown in FIG. 3 indicates an area where the line sensor 31 performs scanning imaging along the Y-axis direction.

  FIG. 4 is a schematic plan view of one die 91 shown in FIG. The die 91 shown in FIG. 4 has a circuit pattern repeatability within the same region (hereinafter referred to as a non-repeated pattern region 93) and a circuit pattern repeatability within the same region such as a memory cell. A certain area (hereinafter referred to as a repeated pattern area 95) is mixed.

  FIG. 5 is a diagram illustrating an example of scan imaging. FIG. 6 is a diagram for explaining the process of setting the examination section SEC for the image obtained by the scan photographing shown in FIG.

  In the appearance inspection apparatus 1, an image obtained by scanning is divided into a plurality of images, and the divided image is set as an inspection section SEC. An inspection task is created for each inspection section SEC. The inspection section SEC is variable according to various conditions such as the size of the die 91, the amount of calculation required for the inspection, or the processing capability of the image processing unit 59, but the maximum size of the inspection section SEC is defined in advance. ing. This is because if the size of the examination section is too large, the amount of image processing may exceed the processing capacity of the image processing unit 59 (the processing capacity of the GPU 591, the memory capacity of the image processing memory 593, etc.). is there. Therefore, the maximum size of the examination section is determined in advance so that the image processing unit 59 can appropriately perform image processing.

  In the present embodiment, the horizontal width DT11 (the length in the X direction) of the inspection section SEC is set to match the horizontal width of the imaging region 300. The maximum height width DTM13 is determined in advance for the height width DT13 (the length in the Y direction) of the inspection section. That is, the inspection section SEC has the maximum size at the maximum height width DTM13. Note that the maximum width may be defined in advance for the width DT11 of the inspection section SEC, and may be changed as appropriate within the range up to the maximum width.

  Next, the size of the inspection section SEC is determined. In this embodiment, the size is determined by the size of the die 91. For example, in the example shown in FIG. 5, the maximum height width DTM13 of the inspection section is longer than the vertical length of one die 91. In such a case, the height width DT13 of the inspection section SEC is determined so as to include as many dies 91 as possible. That is, in the example shown in FIG. 5, the maximum height width DTM13 of the inspection section is slightly longer than the length in the vertical direction of two adjacent dies 91. Therefore, as shown in FIG. 6, the length from the −Y side end of the die 91 on the −Y side to the + Y side end of the die 91 adjacent to the die 91 on the + Y side is the inspection section. The SEC height width DT13 is set. The position of the inspection section SEC is also set so that these two adjacent dies 91 are just included.

  As described above, when the longitudinal length of the die 91 is relatively short, the inspection section SEC is set so as to include as many dies 91 as possible. Thereby, it can suppress that each test | inspection section SEC becomes small too much. If the inspection section SEC is made too small, the overhead time for communication or the like that occurs during the transfer processing of the image data becomes relatively large with respect to the transfer time of the image data itself, and transfer efficiency is greatly deteriorated. There is a case. Therefore, the transfer efficiency can be kept high by suppressing the inspection section SEC from becoming smaller.

  FIG. 7 is a diagram illustrating another example of scan photography. FIG. 8 is a diagram for explaining the process of setting the examination section SEC for the image obtained by the scan photographing shown in FIG.

  In the example shown in FIG. 7, unlike the examples shown in FIGS. 5 and 6, the longitudinal length of the die 91A is larger than the maximum height width DTM13 of the inspection section. In this case, when the vertical length of the die 91A is equally divided by the smallest possible number of divisions n (n is a natural number of 2 or more), the length of one is the maximum height width DTM13 of the inspection section SEC. Is not exceeded, the length of one portion is set as the height width DT13 of the inspection section SEC. For example, in the example shown in FIG. 7, the maximum height width DTM13 of the inspection section is shorter than the length of the die 91A in the vertical direction and more than half of the length in the vertical direction. For this reason, as shown in FIG. 8, the height width DT13 of the inspection section is set to a length corresponding to one when the die 91A is divided into two in the vertical direction.

  As described above, in the case of the relatively large die 91A, it is possible to prevent one inspection section from becoming too large by determining the height width DT13 of the inspection section by equally dividing in the vertical direction. As a result, there is no possibility that the image processing amount exceeds the processing capability of the image processing unit 59 (the processing capability of the GPU 591, the memory capacity of the image processing memory 593, etc.), and the image processing unit 59 appropriately performs image processing. be able to.

  Next, the point that an inspection task is created for each inspection section SEC will be described. In the following description, as shown in FIG. 6, a case where a comparatively small die 91 is obtained by scanning is described as an example. However, it goes without saying that even a relatively large die 91A as shown in FIG. 8 can be similarly inspected.

  FIG. 9 is a diagram illustrating a state in which an inspection task is generated for each inspection section SEC. When the inspection section SEC is set, the inspection task generation unit 43 generates one inspection task for each inspection section SEC. The inspection task is a unit of inspection processing distributed to each processor (GPU 591). In the example shown in FIG. 9, since three inspection sections SEC1 to SEC3 are set, inspection tasks T1 to T3 corresponding to these are generated. A plurality of inspection tasks may be generated in a reservoir for performing a plurality of types of inspections for one inspection section SEC.

  Each inspection task T1 to T3 includes a plurality of inspection commands (inspection commands C11, C12, C13..., Inspection commands C21, C22, C23..., Inspection command C31 in addition to the position information of the inspection sections SEC1 to SEC3. , C32, C33... The inspection command is a minimum execution unit of inspection processing executed by each processor (GPU 591).

  FIG. 10 is a diagram for explaining an example of the inspection command. In the present embodiment, different inspection methods are applied to the non-repeated pattern region 93 and the repeated pattern region 95. Specifically, a so-called die inspection is applied to the non-repeated pattern region 93. For the repeated pattern region 95, array inspection is applied.

  The die inspection applied to the non-repeated pattern region 93 is an inspection method for detecting a pattern defect by comparing a die 91 to be inspected with a die 91 different from the die 91. Different dies 91 can be selected at arbitrary positions. For example, the dies 91 adjacent in the direction parallel to the longitudinal direction of the line sensor 31 may be selected.

  The array inspection applied to the repetitive pattern region 95 is an inspection method for detecting a pattern defect by comparing repetitive patterns in one die 91 to be inspected. The two repeated patterns to be compared may be adjacent to each other or separated from each other.

  As described above, different inspections are applied to the non-repeated pattern region 93 and the repeated pattern region 95. For this reason, as shown in FIG. 10, the inspection section SEC <b> 1 is divided into a region corresponding to the non-repeated pattern region 93 and a region corresponding to the repeated pattern region 95. Further, in the present embodiment, the area divided into the non-repeating pattern area 93 and the repeating pattern area 95 is divided into rectangular areas. For this reason, the inspection section SEC1 shown in FIG. 10 is divided into 16 rectangular areas A1-1 to A1-16. Note that the inspection section SEC1 does not necessarily have to be divided into rectangular areas, but can be divided into areas of arbitrary shapes.

  Specifically, the rectangular areas A1-1 to A1-3, A1-5 to A1-7, A1-9 to A1-11, and A1-13 to A1-15 correspond to the non-repeating pattern area 93. Therefore, a die inspection command for causing the GPU 591 to perform die inspection is registered in the inspection task T1 for these areas. On the other hand, the rectangular areas A1-4, A1-8, A1-12, A1-16 correspond to the repeated pattern area 95. Therefore, for these areas, an array inspection command for causing the GPU 591 to perform array inspection is registered in the inspection task T1.

  Each GPU control unit 57 asynchronously and exclusively accesses the inspection task holding unit 51 to acquire one inspection task. Based on the information, the GPU control unit 57 that has acquired the inspection task first exceeds the number of acquired lines of scan shooting recorded in the buffer memory 53 beyond the number of acquired lines necessary for starting the inspection of this inspection task. Determine whether or not. If the number of captured lines does not exceed the number of captured lines necessary for the inspection, the GPU control unit 57 waits until it exceeds. If the number of captured capture lines exceeds the number of capture lines necessary for inspection, the GPU control unit 57 stores an image (inspection image) in a range to be inspected in the image processing memory 593 connected to the GPU 591. The data is fetched from the buffer memory 53.

  Next, the GPU control unit 57 acquires one inspection command from a plurality of inspection commands included in the inspection task, and registers the processing specified in the inspection command in the GPU 591. Further, the GPU control unit 57 acquires the next inspection command from the same inspection task, and between the inspection command (first inspection command) and the next inspection command (second inspection command) registered in advance, It is determined whether or not the processing content has a dependency. If there is no dependency, that is, if the previous test command and the new test command can be processed simultaneously, the next test command is sent to the GPU 591 without waiting for the previous test command to be completed. Register and have it run. In this way, the processing of test commands that can be executed in parallel is registered in the GPU 591 one after another asynchronously (that is, without waiting for completion of processing).

  FIG. 11 is a diagram illustrating an example of a time chart when the GPU 591 executes a plurality of inspection commands. In the example illustrated in FIG. 11, the GPU 591 includes 21 GPU cores 5910. The number of GPU cores is an example, and can be changed as appropriate. In the example shown in FIG. 11, the GPU 591 executes inspection commands C1-1 to C1-16. These inspection commands C1-1 to C1-16 correspond to a die inspection command or an array inspection command for inspecting the rectangular areas A1-1 to A1-16 shown in FIG. In FIG. 11, the horizontal axis indicates the number of GPU cores 5910 assigned to the execution of each inspection command, and the vertical axis indicates time.

In the example shown in FIG. 11, the number of GPU cores assigned to each inspection command is set as follows.
(Group 1) Inspection commands C1-1, C1-5, C1-9, C1-13... 21 (Group 2) Inspection commands C1-2, C1-6, C1-10, C1-14. 5 (group 3) inspection commands C1-3, C1-7, C1-11, C-15... 12 (group 4) inspection commands C1-4, C1-8, C1-12, C1-16. ..14 pieces

  The inspection commands for groups 1 to 3 correspond to die inspection commands, and the inspection commands for group 4 correspond to array inspection commands. Here, the die inspection command and the array inspection command are inspection commands that can be executed in parallel because there is no dependency on processing contents. That is, the inspection commands C1-1 to C1-16 are all inspection commands that can be executed in parallel with each other. However, the inspection commands of group 1 and group 4 have a relatively large number of allocated GPU cores, and cannot provide the GPU core 5910 for other inspection commands. For this reason, these inspection commands are executed one by one in order.

  On the other hand, even if the inspection commands for group 2 and group 3 are executed at the same time, the sum of the number of allocated GPU cores (= 7 + 11) does not exceed the total number of GPUs (= 21), so that GPU 591 can be executed in parallel. ing.

  In the above example, whether or not to execute a plurality of inspection commands simultaneously is determined based on the number of GPU cores assigned to each inspection command. However, in view of conditions such as the capacity of the register or on-chip memory consumed by each inspection command, it may be determined whether or not two or more inspection commands are registered and executed simultaneously.

  FIG. 12 is a diagram for explaining an example of a test command that cannot be executed in parallel. The inspection commands C1-1 to C1-16 executed in FIG. 11 are inspection commands that can be processed in parallel. On the other hand, when there is a dependency relationship between the processing contents of the inspection commands, the GPU 591 cannot execute these inspection commands at the same time.

  For example, after the die inspection or the array inspection, “mask processing” may be performed on the inspection result. Specifically, when there are various circumstances such that it is known that a defect always appears on a specific part on the die 91, the inspection result on the specific part is masked and discarded after the die inspection or the array inspection. There is a case. That is, the mask processing command C34 for causing the GPU 591 to execute the mask processing cannot be executed simultaneously with the die inspection commands C31 and C32 or the array inspection command C33 (see FIG. 12).

  As described above, since there is a dependency on the processing contents between the inspection command (second inspection command) to be registered next in the GPU 591 and the inspection command (first inspection command) registered in advance, If it cannot be executed, the GPU control unit 57 registers the next inspection command (second inspection command) in the GPU 591 after the previously registered inspection command (first inspection command) is completed.

  An example of an inspection command that cannot be executed simultaneously is “output processing”. Specifically, output processing refers to, for example, specifying the type of inspection (die inspection or array inspection) and the position of a defect when outputting defects detected by die inspection or array inspection to the defect data processing unit 6. This is a process for causing the GPU 591 to execute information, image extraction of a defective portion, and the like. An output processing command for executing this output processing may also be executed only after an array inspection command or a die inspection command. Therefore, such an output processing command is also registered in the GPU 591 after the array inspection command or the die inspection command is completed first.

  The GPU control unit 57 determines whether or not there is a dependency relationship between the processing contents of the inspection command registered first and the inspection command to be registered next (that is, whether parallel processing is possible). Judgment should be based on the type alone. Specifically, a command type such as “die inspection command”, “array inspection command”, “mask processing command”, or “output processing command” may be referred to. As a result, the GPU control unit 57 can register the inspection command in the GPU 591 at high speed and appropriately.

  As described above, when the GPU 591 completes the execution of all the inspection commands included in one inspection task, the GPU control unit 57 outputs the defect information generated by the GPU 591 to the defect data processing unit 6. Then, each GPU control unit 57 executes each inspection task in parallel with each GPU 591 so that all inspection tasks held in the inspection task holding unit 51 are executed sequentially. In addition, when all the inspection tasks stored in the inspection task holding unit 51 are completed, scan imaging is performed for another place on the substrate 9. In this way, the inspection of the desired range of the substrate 9 is performed.

<1.3. Effect>
As described above, in the present embodiment, processing is performed between the inspection command (first inspection command) registered in the GPU 591 and the inspection command (second registration command) registered next (unregistered). If there is no dependency in the contents, the next inspection command (second inspection command) is registered in the GPU 591. In the GPU 591, the previous inspection command (first inspection command) and the next inspection command (second inspection command) can be processed in parallel, so that the efficiency of arithmetic processing can be improved.

  FIG. 13 is a diagram illustrating an example of a time chart when the GPU 591 according to the comparative example executes a plurality of inspection commands. In the comparative example shown in FIG. 13, the inspection commands C1-1 to C1-16 are executed in order regardless of the dependency of the processing contents. In this case, there are many times when the GPU core 5910 is not operating, and the superiority of the GPU 591 that is a multi-core processor is not utilized.

  On the other hand, in this embodiment, as shown in FIG. 11, test commands that can be processed in parallel are executed in parallel by a plurality of GPU cores 5910. Thereby, the time when the GPU core 5910 is not operating can be significantly reduced. That is, the efficiency of arithmetic processing can be improved.

<2. Modification>
Although the embodiment has been described above, the present invention is not limited to the above, and various modifications are possible.

  For example, in the above embodiment, as shown in FIG. 10, the inspection section SEC1, which is the inspection target area, is divided into a non-repeated pattern area 93 and a repeated pattern area 95, and further divided into rectangular areas, An inspection command is assigned to each rectangular area. However, the method of dividing the inspection target region is not limited to such a method.

  For example, as shown in FIG. 14, when a rectangular inspection target region R11 and a substantially circular inspection target region R13 exist in one die 91B, these inspection target regions R11 and R13 are made into a large number of rectangular regions. It is possible to divide. In this way, by dividing the inspection section finely, in the inspection (die inspection or array inspection) applied to each rectangular area, the inspection condition (for example, a threshold value for determining whether or not the defect is present) is set to the rectangular area. Can be different for each. Thereby, a more detailed inspection can be performed.

  In the above embodiment, a plurality of GPUs 591 are used to perform the inspection processing in parallel. For example, it is conceivable that a plurality of CPUs are substituted for this. In this case, for example, a plurality of computers including a CPU and a RAM may be prepared, the GPU 591 may be replaced with a CPU, and the image processing memory 593 may be replaced with a RAM. It is conceivable to substitute a so-called multi-CPU in which a plurality of CPUs are mounted on one computer. In general, image processing related to defect detection can be performed at a higher speed when the GPU 591 is used than when the CPU is used.

  It is also possible to adopt a heterogeneous multi-core processor having a plurality of different processor cores such as Cell (Cell Broadband Engine (trademark of Sony Computer Entertainment Inc.)) instead of the GPU 591. .

  In the above embodiment, a dedicated image processing memory 593 is prepared for each GPU 591. However, each GPU 591 may be configured to access a common image processing memory.

  In the above embodiment, the substrate 9 is a semiconductor substrate. However, in the present invention, the glass substrate for photomask, the substrate for display device, the substrate for optical disk, the substrate for magnetic disk, the substrate for magneto-optical disk, the printed board, It is also effective when performing image processing or visual inspection processing of various substrates such as solar cell substrates.

  Furthermore, it goes without saying that the configurations shown in the above-described embodiments and modifications can be combined with each other or omitted as long as no contradiction arises.

DESCRIPTION OF SYMBOLS 1 Appearance inspection apparatus 2 Stage 21 Stage moving mechanism 3 Image pick-up part 31 Line sensor 4 Control part 41 Inspection recipe preparation part 43 Inspection task production | generation part 45 Stage control part 5 Image processing apparatus 51 Inspection task holding part 53 Buffer memory 55 Image processing control part 57 GPU control unit (processor control unit)
59 Image processor 5910 GPU core (core)
591 GPU (processor)
593 Image processing memory 6 Defect data processing unit 9 Substrate 91, 91A, 91B Die 93 Non-repeated pattern area 95 Repetitive pattern area A1-A16 Rectangular area C1-C16 Inspection command C31, C32 Die inspection command C33 Array inspection command C34 Mask processing Command DT11 Width DT13 Height Width DTM13 Maximum Height Width R11, R13 Inspection Area T1-T3 Inspection Task SEC, SEC1-SEC3 Inspection Section

Claims (10)

An image processing apparatus,
An image processing unit comprising a processor having a plurality of cores;
An image storage unit for storing an inspection image to be inspected;
An inspection task holding unit that holds an inspection task including a plurality of inspection commands executed by the processor, generated for each inspection section obtained by dividing the inspection image into a plurality of parts;
A processor control unit that registers and executes the plurality of inspection commands in the processor;
With
The processor control unit, among the plurality of inspection commands included in one inspection task, between a first inspection command previously registered in the processor and a second inspection command not registered in the processor, An image processing apparatus for registering the second inspection command in the processor when there is no dependency in processing contents. The image processing apparatus according to claim 1.
The processor control unit causes the processor to execute a plurality of inspection commands registered in the processor in parallel. The image processing apparatus according to claim 1 or 2,
The image processing unit includes a plurality of the processors,
An image processing apparatus, wherein a plurality of inspection tasks are respectively distributed to the plurality of processors. The image processing apparatus according to any one of claims 1 to 3,
The image processing apparatus, wherein the processor control unit determines whether to register the second command in the processor based on types of the first inspection command and the second inspection command. An appearance inspection apparatus for inspecting a pattern formed on a substrate,
An image processing apparatus according to any one of claims 1 to 4,
A photographing unit for photographing the substrate and obtaining the inspection image;
With
The image processing unit is an appearance inspection apparatus that inspects a defect of a pattern formed on the substrate. The appearance inspection apparatus according to claim 5,
The visual inspection apparatus, wherein the plurality of inspection commands include a die inspection command for inspecting a non-repeated pattern and an array inspection command for inspecting a repetitive pattern. An image processing method comprising:
(a) generating an inspection task composed of a plurality of inspection commands executed by a processor having a plurality of cores for each inspection section obtained by dividing an inspection image to be inspected into a plurality of sections;
(b) registering and executing the plurality of inspection commands in the processor;
Including
In the step (b), among the plurality of inspection commands included in one inspection task, between the first inspection command previously registered in the processor and the second inspection command not registered in the processor. An image processing method, which is a step of registering the second inspection command in the processor when there is no dependency in processing contents. The image processing method according to claim 7.
(c) a step in which the processor executes the plurality of inspection commands registered in the processor in the step (b) in parallel;
An image processing method further comprising: An appearance inspection method for inspecting a pattern formed on a substrate,
(A) a process of obtaining an inspection image by photographing the substrate;
(B) generating an inspection task including a plurality of inspection commands to be executed by a processor having a plurality of cores for each inspection section obtained by dividing the inspection image into a plurality of sections;
(C) registering and executing the plurality of inspection commands in the processor;
Including
In the step (C), among the plurality of inspection commands included in one inspection task, between the first inspection command previously registered in the processor and the second inspection command not registered in the processor. An appearance inspection method, which is a step of registering the second inspection command in the processor when there is no dependency in processing contents. The visual inspection method according to claim 9,
(D) a step in which the processor executes the plurality of inspection commands registered in the processor in the step (C) in parallel;
A visual inspection method further comprising:

Images