JP2014067811A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce source/drain resistance of a buffer circuit.SOLUTION: A semiconductor device comprises: power source wiring VDD and grounding wiring VSS which extend in an X direction; a P-type logic circuit region 100P arranged to overlap the power source wiring VDD; an N-type logic circuit region 100N arranged to overlap the grounding wiring VSS; and a P-type buffer circuit region 200P and an N-type buffer circuit region 200N which are arranged to overlap the power source wiring VDD and the grounding wiring VSS. A boundary 101 between the P-type logic circuit region 100P and the N-type logic circuit region 100N extends in an X direction and a boundary 201 between the P-type buffer circuit region 200P and the N-type buffer circuit region 200N extends in a Y direction. Because of this, the buffer circuit regions 200P, 200N can sufficiently utilize a cell width thereby to enable use of a layout where source/drain resistance can be decreased.

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a buffer circuit that requires a larger driving capability than a logic circuit.

  In designing a semiconductor device, a layout of a logic circuit having a basic function such as an inverter circuit or a NAND gate circuit is registered in advance as a “standard cell”, and a desired number of standard cells are combined to obtain a desired In general, a circuit block having a function is laid out on a semiconductor substrate. Standard cells are arranged along cell tracks (cell shelves) extending in the X direction. A plurality of cell tracks are prepared in the Y direction, and a circuit block having a desired function is formed by arranging predetermined standard cells on these tracks.

  In the standard cell arranged in the cell track, there is a buffer circuit for outputting a signal to another cell or another circuit area in addition to a cell for performing a logical operation. The buffer circuit needs a driving capability larger than that of a cell that performs a logical operation. In order to obtain a large driving capability, it is necessary to expand the channel width by connecting a plurality of transistors in parallel, as described in Patent Document 1, for example.

JP 2000-216263 A

  However, the source / drain resistance of the buffer circuit cannot be lowered sufficiently by simply connecting a plurality of transistors in parallel. For this reason, as the manufacturing process is further miniaturized, there is a possibility that an increase in current consumption and a decrease in switching speed may occur in the buffer circuit. From such a background, a layout capable of further reducing the source / drain resistance of the buffer circuit arranged in the cell track has been desired.

  A semiconductor device according to an aspect of the present invention is provided with first and second power supply wirings extending in parallel with a first direction, and partly overlapping the first and second power supply wirings. Is provided so as to partially overlap the first and second power supply lines, and a first conductivity type buffer circuit region including a plurality of first conductivity type transistors electrically connected to the first power supply lines. A second conductivity type buffer circuit region including a plurality of second conductivity type transistors, one end of which is electrically connected to the second power supply wiring, and the first conductivity type buffer circuit region and the second conductivity type. The boundary with the type buffer circuit region extends in a second direction intersecting the first direction, and the other ends of the plurality of first conductivity type transistors and the other end of the plurality of second conductivity type transistors are The plurality of first conductivity type tors are electrically short-circuited to each other. It said Njisuta end, the first being shorted together in a region which does not overlap with the power supply wiring, it is characterized.

  A semiconductor device according to another aspect of the present invention includes first and second power supply wires extending in parallel with a first direction, and a portion of the first power supply wire without overlapping the second power supply wire. A first conductivity type logic circuit region including a plurality of first conductivity type first transistors provided so as to overlap with the wiring and having one end electrically connected to the first power supply wiring; A plurality of second-conductivity-type second transistors which are provided so as to partially overlap the second power supply wiring without overlapping with the wiring and one end of which is electrically connected to the second power supply wiring. The second conductivity type logic circuit region is provided so as to partially overlap the first and second power supply lines, and one end of the first conductivity type is electrically connected to the first power supply line. A first conductivity type buffer circuit region including three transistors, and a part of the first conductivity type buffer circuit region. A second conductivity type buffer circuit region including a second transistor of the second conductivity type, which is provided so as to overlap with the second power supply wire and one end of which is electrically connected to the second power supply wire. A first boundary which is a boundary between the first conductivity type logic circuit region and the second conductivity type logic circuit region extends in the first direction, and the first conductivity type buffer circuit region and the first conductivity type A second boundary, which is a boundary with the two-conductivity type buffer circuit region, extends in a second direction intersecting the first direction, and the other end of the plurality of first transistors and the plurality of the plurality of first transistors. The other end of either of the second transistors is electrically short-circuited to each other and connected in common to the control electrodes of the third and fourth transistors, and the other end of the third transistor and the fourth transistor The other ends of the The features.

  According to the present invention, since the boundary between the first conductivity type buffer circuit region and the second conductivity type buffer circuit region is set in a direction crossing the extending direction of the power supply wiring, the cell of each buffer circuit region is The width can be fully utilized. As a result, a layout capable of lowering the resistance of the source / drain resistance and the like can be adopted, so that an increase in current consumption and a decrease in switching speed can be suppressed.

1 is a schematic plan view showing a layout of a semiconductor device according to a first embodiment of the present invention. It is sectional drawing along the AA line shown in FIG. FIG. 2 is a circuit diagram of a circuit realized by the layout shown in FIG. 1. It is a figure for demonstrating the difference in the waveform of the output signal by the difference in source / drain resistance, (a) shows a waveform in case source / drain resistance is relatively high resistance, (b) shows source / drain resistance. The waveform is shown when the drain resistance is relatively low. It is a top view for demonstrating the presence or absence of coupling of an input signal and an output signal, (a) shows the conventional layout which coupling produces, (b) shows the layout by embodiment which does not produce coupling. ing. FIG. 2 is a diagram in which a signal wiring S that passes through a logic circuit region 100 and a buffer circuit region 200 is added to FIG. FIG. 5 is a layout diagram showing a plurality of cell tracks in the first embodiment. FIG. 8 is a layout diagram according to a modification of FIG. 7. FIG. 6 is a layout diagram for explaining a relationship between a cell track, a power supply wiring VDD, and a ground wiring VSS. FIG. 5 is a layout diagram illustrating an example in which a power supply wiring VDD and a ground wiring VSS are arranged in a central region of a cell track CT. FIG. 5 is a layout diagram illustrating an example in which a power supply wiring VDD and a ground wiring VSS are arranged in a central region of a cell track CT. It is a figure which shows the wiring using the wiring layer M2 which connects the inside of a standard cell, (a) is when the power supply wiring VDD and the ground wiring VSS are arrange | positioned in the boundary of the cell track CT, (b) is power supply wiring VDD and grounding The case where the wiring VSS is arranged in the central region of the cell track CT is shown. (A), (b) is the figure which added the signal wiring S which passes a standard cell to FIG. 12 (a), (b), respectively. It is a diagram for explaining the relationship between an empty area FA and a P-type buffer circuit area 200P and an N-type buffer circuit area 200N. FIG. 6 is a schematic plan view showing a layout of a semiconductor device according to a second embodiment of the present invention. It is a figure which shows the wiring using the wiring layer M2 in 2nd Embodiment. FIG. 10 is a layout diagram for explaining a relationship between a cell track, a power supply wiring VDD, and a ground wiring VSS in the second embodiment. FIG. 6 is a schematic plan view showing a layout of a semiconductor device according to a third embodiment of the present invention. It is a figure which shows the wiring using the wiring layer M2 in 3rd Embodiment. FIG. 10 is a layout diagram for explaining a relationship between a cell track, a power supply wiring VDD, and a ground wiring VSS in the third embodiment. It is a figure for demonstrating the effect by 1st-3rd embodiment, (a) shows the conventional layout, (b) has shown the layout by 1st-3rd embodiment.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a schematic plan view showing a layout of a semiconductor device according to a first embodiment of the present invention, and shows a part of a cell track CT (cell shelf) defined on a semiconductor substrate. 2 is a cross-sectional view taken along the line AA shown in FIG.

  As shown in FIG. 1, the semiconductor device according to the present embodiment includes a power supply wiring VDD and a ground wiring VSS extending in the X direction, and a logic circuit provided so as to partially overlap the power supply wiring VDD and the ground wiring VSS. An area 100 and a buffer circuit area 200 are provided. The power supply wiring VDD and the ground wiring VSS are formed in the wiring layer M2, as shown in FIG. The logic circuit region 100 and the buffer circuit region 200 are arranged adjacent to each other in the X direction along the cell track CT. One end (upper end) of the cell track CT in the Y direction is covered with the power supply wiring VDD, and the other end (lower end) of the cell track CT in the Y direction is covered with the ground wiring VSS.

  Each of the logic circuit region 100 and the buffer circuit region 200 is a CMOS circuit, and includes a P-channel MOS transistor and an N-channel MOS transistor. P-channel MOS transistors included in the logic circuit region 100 are disposed in the P-type logic circuit region 100P, and N-channel MOS transistors included in the logic circuit region 100 are disposed in the N-type logic circuit region 100N. Similarly, a P-channel MOS transistor included in the buffer circuit region 200 is disposed in the P-type buffer circuit region 200P, and an N-channel MOS transistor included in the buffer circuit region 200 is disposed in the N-type buffer circuit region 200N. ing.

  As shown in FIG. 1, the boundary line 101 between the P-type logic circuit region 100P and the N-type logic circuit region 100N extends in the X direction, whereas the P-type buffer circuit region 200P and the N-type buffer circuit region The boundary line 201 with 200N extends in the Y direction. In other words, in the logic circuit region 100, the P-type logic circuit region 100P and the N-type logic circuit region 100N are arranged side by side in the Y direction, whereas in the buffer circuit region 200, the P-type buffer circuit region. 200P and the N-type buffer circuit region 200N are arranged side by side in the X direction. With this configuration, the P-type logic circuit region 100P is arranged so as to partially overlap the power supply wiring VDD without overlapping the ground wiring VSS, and the N-type logic circuit region 100N is not overlapped with the power supply wiring VDD. The part is arranged so as to overlap the ground wiring VSS. On the other hand, the P-type buffer circuit region 200P and the N-type buffer circuit region 200N are both arranged so as to partially overlap the power supply wiring VDD and the ground wiring VSS.

  Transistors (P-channel MOS transistors) formed in the P-type logic circuit region 100P and the P-type buffer circuit region 200P are connected to the power supply wiring VDD directly or via other transistors. On the other hand, the transistors (N-channel MOS transistors) formed in the N-type logic circuit region 100N and the N-type buffer circuit region 200N are connected to the ground wiring VSS directly or via other transistors. Also, the drain of the output stage transistor (P channel type MOS transistor) formed in the P type logic circuit region 100P and the drain of the output stage transistor (N channel type MOS transistor) formed in the N type logic circuit region 100N. Are short-circuited with each other to the gate electrode of the transistor (P-channel MOS transistor) formed in the P-type buffer circuit region 200P and the gate electrode of the transistor (N-channel MOS transistor) formed in the N-type buffer circuit region 200N. Commonly connected.

  FIG. 3 is a circuit diagram of a circuit realized by the layout shown in FIG.

  As shown in FIG. 3, transistors A to J are formed in the logic circuit region 100, and transistors K and L are formed in the buffer circuit region 200. Among these, the transistors A and B, the transistors C and D, the transistors I and J, and the transistors K and L all constitute an inverter circuit, and the transistors E to H constitute a NAND gate circuit. With the connection relationship shown in FIG. 3, the logic circuit region 100 functions as a NOR gate circuit that receives the input signals IN1 and IN2 and generates the output signal OUT1. On the other hand, the transistors K and L formed in the buffer circuit region 200 are equivalently one transistor each, but have a configuration in which a plurality of transistors are connected in parallel as shown in FIG. Yes. Specifically, the transistor K (P-channel MOS transistor) is composed of four transistors in which three sources SP1 to SP3 and two drains DP1 and DP2 are alternately arranged in the X direction. Type MOS transistor) includes two transistors in which two sources SN1 and SN2 and one drain DN are alternately arranged in the X direction. These source / drain regions are provided in the wells 20 and 30 in the semiconductor substrate 10 as shown in FIG. The well 20 and the well 30 are separated along the element isolation region 40.

  As shown in FIGS. 1 and 2, a gate electrode is provided between the source and drain of each transistor in plan view. A transistor K (P-channel MOS transistor) formed in the P-type buffer circuit region 200P has four gate electrodes GP1 to GP4, and a transistor L (N-channel MOS transistor) formed in the N-type buffer circuit region 200N. ) Has two gate electrodes GN1 and GN2. One end of the gate electrodes GP1 to GP4, GN1, and GN2 in the Y direction is short-circuited through the gate connection wiring G1, and the other end in the Y direction is short-circuited through the gate connection wiring G2. The gate connection wirings G1 and G2 are wirings formed in the same wiring layer GL as the gate electrodes GP1 to GP4, GN1 and GN2, and are arranged at positions overlapping the power supply wiring VDD or the ground wiring VSS.

  On the sources SP1 to SP3, the drains DP1 and DP2, the sources SN1 and SN2, and the drain DN, wiring portions W1 to W4 extending in the Y direction along these are formed. These wiring portions W1 to W4 are formed in a wiring layer WL that is higher than the gate electrode, and are connected to corresponding sources or drains via contact conductors CE1 to CE4, respectively. The wiring layer WL is a wiring layer using tungsten, for example, and has a slightly higher resistance than the upper wiring layers M1 and M2 using aluminum or the like. The wiring layers are separated by interlayer insulating films 50, 60, and 70.

  The wiring portion W2 corresponding to the drains DP1 and DP2 is surrounded by the gate electrodes GP1 and GP2 (GP3 and GP4) and the gate connection wirings G1 and G2 in plan view. Similarly, the wiring portion W4 corresponding to the drain DN is surrounded by the gate electrodes GN1 and GN2 and the gate connection wirings G1 and G2 in plan view.

  On the other hand, one end in the Y direction of the wiring portion W1 is short-circuited via the connection wiring W11, and the other end in the Y direction is short-circuited via the connection wiring W12. Although not shown, one end in the Y direction of the wiring portion W3 may also be short-circuited via the connection wiring. Further, the other end of the wiring portion W3 in the Y direction may be short-circuited through the connection wiring. These connection wirings W11 and W12 are both wirings formed in the same wiring layer WL as the wiring portions W1 to W4, and are arranged at positions overlapping the power supply wiring VDD and the ground wiring VSS, respectively. With this configuration, the wiring portion W2 is surrounded by the wiring portion W1 and the connection wirings W11 and W12.

  The connection wiring W11 disposed at a position overlapping the power supply wiring VDD is connected to the power supply wiring VDD via the contact conductor CE5. As a result, the source of the transistor K formed in the P-type buffer circuit region 200P is connected to the power supply wiring VDD. On the other hand, the wiring portion W3 disposed at a position overlapping the ground wiring VSS is connected to the ground wiring VSS via the contact conductor CE6. As a result, the source of the transistor L formed in the N-type buffer circuit region 200N is connected to the ground wiring VSS. The wiring portion W2 and the wiring portion W4 are connected to the output wiring OUT2 via the contact conductor CE7. As shown in FIG. 2, the output wiring OUT2 is a wiring provided in the wiring layer M1.

  As described above, since the buffer circuit region 200 includes the P-type buffer circuit region 200P and the N-type buffer circuit region 200N arranged in the X direction, these regions 200P and 200N are respectively in the Y direction within the cell track CT. The full width of can be used. As a result, the connection wiring W12 that commonly connects the far ends of the sources SP1 to SP3 can be disposed, and the source resistance can be reduced.

  Further, in the present embodiment, the auxiliary wiring BP1 is provided in the wiring layer M2, and the power supply wiring VDD and the vicinity of the far ends of the sources SP1 to SP3 are short-circuited via the auxiliary wiring BP1. Similarly, the auxiliary wiring BP2 is provided in the wiring layer M2, and the ground wiring VSS and the vicinity of the far ends of the sources SN1 and SN2 are short-circuited through the auxiliary wiring BP2. These auxiliary wirings BP1 and BP2 also reduce the source resistance. Specifically, according to the present embodiment, the source resistance, which was 120Ω in the conventional layout, can be reduced to about 80Ω.

  In addition, in the buffer circuit region 200, the drains DP1, DP2 and the drain DN are short-circuited by the low-resistance output wiring OUT2 provided in the wiring layer M1, so that the buffer circuit region 200 has a relatively high resistance like the logic circuit region 100. Compared with the case where the drain is short-circuited using the wiring layer WL, the drain resistance can be reduced.

  Thus, in this embodiment, since the source / drain resistance in the buffer circuit region 200 is lower than that in the conventional case, it is possible to suppress an increase in current consumption and a decrease in switching speed.

  FIG. 4 is a diagram for explaining a difference in waveform of an output signal due to a difference in source / drain resistance. FIG. 4A shows a waveform when the source / drain resistance is relatively high. ) Shows a waveform when the source / drain resistance is relatively low. As shown in FIG. 4, the time required for rising and falling of the output signal is shorter when the source / drain resistance is relatively low. For this reason, if the source / drain resistance is lowered, it becomes possible to transmit a signal at a higher speed.

  Moreover, as shown in FIG. 5A, in the conventional layout, a wiring (gate wiring) formed in the wiring layer GL and supplied with an input signal, and a wiring (drain) formed in the wiring layer WL and supplied with an output signal. Some locations CX intersect with the wiring), and this causes coupling between the input signal and the output signal. On the other hand, in the layout of this embodiment, as shown in FIG. 5B, a gate wiring formed in the wiring layer GL and supplied with an input signal, and a drain formed in the wiring layer WL and supplied with an output signal. Since there is no place where the wiring intersects, conventional coupling does not occur. Incidentally, although the gate wiring formed in the wiring layer GL and the drain wiring formed in the wiring layer M1 intersect, the wiring layer GL and the wiring layer M1 are separated from each other, so that the coupling generated is small. .

  Note that the layout of the transistors formed in the logic circuit region 100 is basically the same as the conventional one. That is, as shown in FIG. 1, in the P-type logic circuit region 100P, a source / drain region extending in the Y direction is provided between one end (upper end) in the Y direction of the cell track CT and the boundary line 101. At the same time, a gate electrode is provided between them in plan view, whereby several P-channel MOS transistors are formed. For the N-type logic circuit region 100N, a source / drain region extending in the Y direction is provided between the other end (lower end) of the cell track CT in the Y direction and the boundary line 101. Between these, a gate electrode is provided, whereby several N-channel MOS transistors are formed. Input signals IN1, IN2, etc. are input to each gate electrode, and a predetermined drain of the P-channel MOS transistor and a predetermined drain of the N-channel MOS transistor are connected to the wiring layer WL. Connected through. As a result, a predetermined logic gate circuit is realized.

  FIG. 6 is a diagram in which a signal wiring S passing through the logic circuit region 100 and the buffer circuit region 200 is added to FIG. As shown in FIG. 6, a large number of signal lines S extending in the X direction are arranged on the actual cell track CT. Since the wiring extending in the X direction is mainly formed in the wiring layer M2, when there is a signal wiring S passing through the buffer circuit region 200 in the X direction, it is necessary to leave the area in the wiring layer M2. . Therefore, for example, when the signal wiring S shown in FIG. 6 passes over the buffer circuit region 200, a portion extending in the Y direction among the auxiliary wirings BP1 and BP2, a wiring layer different from the wiring layer M2, For example, it is necessary to use the wiring layer M1 and the wiring layer (M3) disposed further above the wiring layer M2.

  FIG. 7 is a layout diagram showing a plurality of cell tracks. In the example shown in FIG. 7, the logic circuit area 110 and the buffer circuit area 210 are arranged in the cell track CT1, the logic circuit area 120 and the buffer circuit area 220 are arranged in the cell track CT2, and the logic circuit is arranged in the cell track CT3. Regions 130 and 140 are arranged. The buffer circuit area 210 is a circuit area for buffering output signals supplied from the logic circuit area 110, and the buffer circuit area 220 is a circuit area for buffering output signals supplied from the logic circuit area 120. As described above, in the example shown in FIG. 7, the logic circuit area and the corresponding buffer circuit area are arranged adjacent to each other in the X direction.

  FIG. 8 is a modification of FIG. 7, and auxiliary wirings BP3 and BP4 covering the connection portion W2 corresponding to the drains DP1 and DP2, auxiliary wiring BP5 covering the connection portion W4 corresponding to the drain DN, and auxiliary wirings BP3 and BP3. An auxiliary wiring BP6 for connecting BP4 is provided. Among these, the auxiliary wirings BP3 to BP5 are provided in the wiring layer M1, and the auxiliary wiring BP6 is provided in the wiring layer M2. The auxiliary wirings BP3 to BP5 are connected to the corresponding connection portions W2 or W4 through the through-hole conductors, thereby further reducing the drain resistance. For example, the drain resistance, which was 80Ω in the layout of FIG. 7, can be reduced to about 60Ω according to the layout of FIG.

  FIG. 9 is a layout diagram for explaining the relationship between the cell track, the power supply wiring VDD, and the ground wiring VSS. As shown in FIG. 9, in this embodiment, the power supply wiring VDD and the ground wiring VSS are alternately arranged in the X direction along the boundary of the cell track CT. The power supply wiring VDD and the ground wiring VSS are wirings formed in the wiring layer M2. Furthermore, a power supply wiring VDD1 and a ground wiring VSS1 extending in the Y direction so as to intersect the cell track CT are also provided. The power supply wiring VDD1 and the ground wiring VSS1 are wirings formed in the wiring layer M1, and are connected to the power supply wiring VDD and the ground wiring VSS through the through-hole conductor TH, respectively. With this configuration, a power supply network constructed in a mesh shape is formed.

  However, the positions of the power supply wiring VDD and the ground wiring VSS are not limited to this, and the power supply wiring VDD and the ground wiring VSS may be arranged on each cell track CT as shown in FIGS. . Also in such a layout, as shown in FIG. 10, since both ends in the Y direction of the connection portion W1 corresponding to the sources SP1 to SP3 are short-circuited by the connection wirings W11 and W12, the source resistance is reduced. . Furthermore, in the case of the layout shown in FIG. 10, the auxiliary wiring BP7 can be provided above the connection wiring W12. The auxiliary wiring BP7 is formed in the wiring layer M2, and plays a role of further reducing the resistance of the far ends of the sources SP1 to SP3. Similarly, the auxiliary wiring BP8 can be provided at the far end portions of the sources SN1 and SN2, and the resistance of the far ends of the sources SN1 and SN2 can be further reduced. The auxiliary wiring BP8 is also formed in the wiring layer M2.

  FIG. 12 is a diagram showing wiring using the wiring layer M2 for connecting the inside of the standard cell. FIG. 12A shows a case where the power supply wiring VDD and the ground wiring VSS are arranged at the boundary of the cell track CT as shown in FIG. FIG. 10B shows a case where the power supply wiring VDD and the ground wiring VSS are arranged in the central region of the cell track CT as shown in FIG. As shown in FIGS. 12A and 12B, in each case, the wiring 102 connecting the logic circuit region 100 is provided with a relatively high density, while the wiring connecting the buffer circuit region 200 is output. Only the wiring OUT2 is provided.

  FIGS. 13A and 13B are diagrams in which the signal wiring S passing through the standard cell is added to FIGS. 12A and 12B, respectively. The signal wiring S is provided in the wiring layer M2. Therefore, the area where these wirings provided in the wiring layer M2 do not exist is the empty area FA of the wiring layer M2, and the auxiliary wirings BP1, BP2 and the like shown in FIG. 1 can be arranged in this empty area FA. it can. As shown in FIGS. 13A and 13B, the logic circuit area 100 has almost no vacant area FA, whereas the buffer circuit area 200 has some vacant areas FA formed therein. In the present embodiment, since the source / drain resistance in the buffer circuit region 200 is reduced by using such an empty area FA, the occupied area does not increase as compared with the conventional layout.

  Moreover, as shown in FIG. 14, since the empty area FA extends in the X direction, it is always allocated to both the P-type buffer circuit area 200P and the N-type buffer circuit area 200N. On the other hand, in the conventional layout, since the P-type buffer circuit area 200P and the N-type buffer circuit area 200N are arranged in the Y direction, the empty area FA extending in the X direction is formed in one circuit area. Will only be assigned. For this reason, for example, even when it is desired to add an auxiliary wiring to the P-type buffer circuit area 200P, there is a case where the empty area FA exists only in the N-type buffer circuit area 200N and does not exist in the P-type buffer circuit area 200P. To do. In such a case, auxiliary wiring cannot be added to the P-type buffer circuit region 200P. However, in this embodiment, such a problem does not occur.

  FIG. 15 is a schematic plan view showing the layout of the semiconductor device according to the second embodiment of the present invention.

  As shown in FIG. 15, in this embodiment, the logic circuit areas 110, 120, 130, and 140 and the buffer circuit areas 210 and 220 are laid out in different cell tracks CT11 to CT13. As in the example shown in FIG. 7, the buffer circuit area 210 is a circuit area for buffering an output signal supplied from the logic circuit area 110, and the buffer circuit area 220 is an output signal supplied from the logic circuit area 120. Is a circuit area for buffering. As described above, in this embodiment, the logic circuit area and the buffer circuit area corresponding to the logic circuit area are arranged adjacent to each other in the Y direction.

  FIG. 16 is a diagram showing wiring using the wiring layer M2 in the present embodiment. As shown in FIG. 16, a large number of wirings 102 that connect the logic circuit region 100 are provided, while the wiring that connects the buffer circuit region 200 is only the output wiring OUT2. Thus, there is a large difference in the number of wirings using the wiring layer M2 between the logic circuit region 100 and the buffer circuit region 200. However, in this embodiment, the width in the Y direction of the logic circuit region 100 and the width in the Y direction of the buffer circuit region 200 are different and optimized, so that the cell size is reduced compared to the conventional layout. It can be downsized.

  In the present embodiment, as a result of the reduction in the width of the buffer circuit area 200 in the Y direction, there is almost no free area FA as in the first embodiment. For this reason, it is difficult to arrange the auxiliary wiring in the vacant area FA, but the length in the Y direction of the connection portions W1 and W2 is shorter than that in the first embodiment. In addition, the source / drain resistance can be sufficiently reduced. Specifically, according to the present embodiment, the source resistance, which was 120Ω in the conventional layout, can be reduced to about 40Ω. Further, according to the present embodiment, the drain resistance, which was 80Ω in the conventional layout, can be reduced to about 40Ω.

  FIG. 17 is a layout diagram for explaining the relationship between the cell track, the power supply wiring VDD, and the ground wiring VSS in the second embodiment. As shown in FIG. 17, in this embodiment, the power supply wiring VDD and the ground wiring VSS are arranged in the X direction along the end portions in the Y direction of the cell tracks CT11 to CT16. The cell tracks CT11, CT13, CT14, and CT16 are cell tracks on which the logic circuit region 100 is disposed, and the cell tracks CT12 and CT15 are cell tracks on which the buffer circuit region 200 is disposed.

  FIG. 18 is a schematic plan view showing the layout of the semiconductor device according to the third embodiment of the present invention. FIG. 19 is a diagram showing wiring using the wiring layer M2 in the present embodiment.

  As shown in FIGS. 18 and 19, in this embodiment, the widths of the cell tracks CT21 and CT22 are reduced in the Y direction in the portions where the buffer circuit regions 210 and 220 are arranged. With such a configuration, the width in the Y direction of the buffer circuit regions 210 and 220 is reduced, so that the same effect as in the second embodiment can be obtained.

  FIG. 20 is a layout diagram for explaining the relationship between the cell track, the power supply wiring VDD, and the ground wiring VSS in the third embodiment. In the example shown in FIG. 20, the width of the cell track CTB in which the buffer circuit area 200 is arranged is half the width of the cell track CTL in which the logic circuit area 100 is arranged. The power supply wiring VDD and the ground wiring VSS are alternately arranged in the X direction along the boundary of the cell track CTB, and the power supply wiring VDD and the ground wiring VSS are alternately arranged in the X direction along the boundary of the cell track CTL. Has been. As a result, a large number of buffer circuit areas 200 can be arranged together, and a useless empty area does not occur.

  As described above, according to the first to third embodiments, since the source / drain resistance in the buffer circuit region 200 is lower than that of the conventional one, an increase in current consumption and a decrease in switching speed are suppressed. It becomes possible to do. In addition, since the width in the X direction of the P-type buffer circuit region 200P and the width in the X direction of the N-type buffer circuit region 200N can be arbitrarily set, for example, a circuit formed in the buffer circuit region 200 is a NAND gate. Even if the circuit has a ratio different from that of the inverter circuit, such as a circuit or a NOR gate circuit, useless space does not occur. That is, in the conventional layout, when a NAND gate circuit or a NOR gate circuit is laid out, a useless space DS is generated on the semiconductor substrate as shown in FIG. 21A, but in the first to third embodiments. Accordingly, as shown in FIG. 21B, no useless space is generated. As a result, the area occupied on the chip can be reduced.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

10 Semiconductor substrate 20, 30 Well 40 Element isolation region 50, 60, 70 Interlayer insulating film 100, 110, 120, 130, 140 Logic circuit region 100N N-type logic circuit region 100P P-type logic circuit region 101, 201 Boundary line 102 Wiring 200, 210, 220 Buffer circuit area 200N N-type buffer circuit area 200P P-type buffer circuit area A to L Transistors BP1 to BP8 Auxiliary wiring CE1 to CE7 Contact conductor CT Cell track DN, DP1, DP2 Drain FA Empty area G1, G2 Gate Connection wiring GL wiring layer (gate wiring layer)
GP1-GP4, GN1, GN2 Gate electrodes M1, M2, WL Wiring layer S Signal wiring SN1, SN2, SP1-SP3 Source VDD, VDD1 Power supply wiring VSS, VSS1 Ground wiring W1-W4 Wiring parts W11, W12 Connection wiring

Claims (14)

First and second power supply lines extending parallel to the first direction;
A first conductivity type buffer circuit region including a plurality of first conductivity type transistors, one part of which is provided so as to overlap with the first and second power supply lines, and one end of which is electrically connected to the first power supply line When,
A second conductivity type buffer circuit region including a plurality of second conductivity type transistors, one part of which is provided so as to overlap with the first and second power supply lines, and one end of which is electrically connected to the second power supply line And comprising
A boundary between the first conductivity type buffer circuit region and the second conductivity type buffer circuit region extends in a second direction intersecting the first direction;
The other ends of the plurality of first conductivity type transistors and the other end of the plurality of second conductivity type transistors are electrically short-circuited with each other,
The semiconductor device according to claim 1, wherein the one ends of the plurality of first conductivity type transistors are short-circuited to each other in a region that does not overlap with the first power supply wiring.   The one end of the plurality of first conductivity type transistors is short-circuited to each other in the vicinity of at least one end portion in the second direction of the first conductivity type buffer circuit region. The semiconductor device described. The one end of the plurality of first conductivity type transistors is constituted by a plurality of first diffusion layers extending in the second direction,
The other end of the plurality of first conductivity type transistors is constituted by at least one second diffusion layer extending in the second direction,
The one end of the plurality of second conductivity type transistors is constituted by a plurality of third diffusion layers extending in the second direction,
The other end of the plurality of second conductivity type transistors is constituted by at least one fourth diffusion layer extending in the second direction,
The first and second diffusion layers are alternately arranged in the first direction,
The semiconductor device according to claim 1, wherein the third and fourth diffusion layers are alternately arranged in the first direction. The first conductivity type buffer circuit region includes:
A plurality of first wiring portions provided in the first wiring layer and extending in the second direction along the plurality of first diffusion layers so as to respectively overlap the plurality of first diffusion layers;
At least one second wiring portion provided in the first wiring layer and extending in the second direction along the second diffusion layer so as to overlap the second diffusion layer;
A first contact conductor connecting the plurality of first diffusion layers and the plurality of first wiring portions;
A second contact conductor connecting the second diffusion layer and the second wiring portion; and
The second conductivity type buffer circuit area includes:
A plurality of third wiring portions provided in the first wiring layer and extending in the second direction along the plurality of third diffusion layers so as to respectively overlap the plurality of third diffusion layers;
At least one fourth wiring portion provided in the first wiring layer and extending in the second direction along the fourth diffusion layer so as to overlap the fourth diffusion layer;
A third contact conductor connecting the plurality of third diffusion layers and the plurality of third wiring portions;
A fourth contact conductor connecting the fourth diffusion layer and the fourth wiring portion; and
4. The semiconductor device according to claim 3, wherein the plurality of first wiring portions are short-circuited to each other via a connection wiring formed in the first wiring layer.   The semiconductor device according to claim 4, wherein the second wiring portion is surrounded by the plurality of first wiring portions and the connection wiring. The first conductivity type transistor is one of a P-channel MOS transistor and an N-channel MOS transistor.
The second conductivity type transistor is the other of a P-channel MOS transistor and an N-channel MOS transistor;
The one end of the first conductivity type transistor and the second conductivity type transistor is a source,
6. The semiconductor device according to claim 4, wherein the other end of the first conductivity type transistor and the second conductivity type transistor is a drain. The first conductivity type buffer circuit region further includes a plurality of first gate electrodes provided in the second wiring layer and provided between the first and second diffusion layers in plan view;
The second conductivity type buffer circuit region further includes a plurality of second gate electrodes provided in the second wiring layer and provided between the third and fourth diffusion layers in plan view,
The semiconductor device according to claim 6, wherein the plurality of first gate electrodes and the plurality of second gate electrodes are electrically short-circuited with each other. One ends of the plurality of first and second gate electrodes in the second direction are short-circuited to each other via a first gate connection wiring formed in the second wiring layer,
The other ends of the plurality of first and second gate electrodes in the second direction are short-circuited to each other via a second gate connection wiring formed in the second wiring layer. The semiconductor device according to claim 7. The second wiring portion is surrounded by the plurality of first gate electrodes, the first gate connection wiring, and the second gate connection wiring in a plan view,
The fourth wiring portion is surrounded by the plurality of second gate electrodes, the first gate connection wiring, and the second gate connection wiring in a plan view. Item 9. The semiconductor device according to Item 8. A plurality of first conductivity type transistors that are provided so as to partially overlap the first power supply wiring without overlapping with the second power supply wiring and one end of which is electrically connected to the first power supply wiring. Including a first conductivity type logic circuit region;
A plurality of second conductivity type transistors that are provided so as to partially overlap the second power supply wiring without overlapping with the first power supply wiring, and one end of which is electrically connected to the second power supply wiring. A second conductivity type logic circuit region including
The semiconductor according to claim 7, wherein a boundary between the first conductivity type logic circuit region and the second conductivity type logic circuit region extends in the first direction. apparatus.   The output node provided in the first conductivity type logic circuit region and the output node provided in the second conductivity type logic circuit region are electrically connected in common to the plurality of first and second gate electrodes. The semiconductor device according to claim 10. First and second power supply lines extending parallel to the first direction;
A plurality of first conductivity type second electrodes are provided so as to partially overlap the first power supply wiring without overlapping with the second power supply wiring, and one end is electrically connected to the first power supply wiring. A first conductivity type logic circuit region including one transistor;
A plurality of second conductivity type second electrodes are provided so as to partially overlap the second power supply wiring without overlapping with the first power supply wiring, and one end is electrically connected to the second power supply wiring. A second conductivity type logic circuit region including two transistors;
A first conductivity type including a third transistor of the first conductivity type, a part of which is provided so as to overlap the first and second power supply wirings and one end of which is electrically connected to the first power supply wiring. A buffer circuit area;
A second conductivity type including a fourth transistor of the second conductivity type, a part of which is provided so as to overlap the first and second power supply wirings and one end of which is electrically connected to the second power supply wiring. A buffer circuit area, and
A first boundary that is a boundary between the first conductivity type logic circuit region and the second conductivity type logic circuit region extends in the first direction;
A second boundary, which is a boundary between the first conductivity type buffer circuit region and the second conductivity type buffer circuit region, extends in a second direction intersecting the first direction;
The other end of any of the plurality of first transistors and the other end of any of the plurality of second transistors are electrically short-circuited to each other and are commonly connected to the control electrodes of the third and fourth transistors. And
The other end of the third transistor and the other end of the fourth transistor are electrically short-circuited with each other. The plurality of first transistors include a first diffusion layer that constitutes the one end and a second diffusion layer that constitutes the other end, and the first and second diffusion layers have the first conductivity type. Extending in the second direction between one end of the logic circuit region in the second direction and the first boundary;
The plurality of second transistors include a third diffusion layer that constitutes the one end and a fourth diffusion layer that constitutes the other end, and the third and fourth diffusion layers have the second conductivity type. Extending in the second direction between one end of the logic circuit region in the second direction and the first boundary;
The third transistor includes a fifth diffusion layer constituting the one end and a sixth diffusion layer constituting the other end, and the fifth and sixth diffusion layers are the first conductivity type buffer circuit. Extending in the second direction between one end and the other end in the second direction of the region,
The fourth transistor includes a seventh diffusion layer forming the one end and an eighth diffusion layer forming the other end, and the seventh and eighth diffusion layers are the second conductivity type buffer circuit. The semiconductor device according to claim 12, wherein the semiconductor device extends in the second direction between one end and the other end in the second direction of the region. The one end of the first conductivity type logic circuit region in the second direction, the one end of the first conductivity type buffer circuit region in the second direction, and the second conductivity type buffer The one end portion in the second direction of the circuit region extends in a straight line in the first direction,
The one end of the second conductivity type logic circuit region in the second direction, the other end of the first conductivity type buffer circuit region in the second direction, and the second conductivity type buffer The semiconductor device according to claim 13, wherein the other end of the circuit region in the second direction extends in a straight line in the first direction.

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