JP2014065099A - Semiconductor device, and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wafer level chip scale package having a hollow sealing structure by forming a sealing film having a hollow structure at a wafer level on the principal surface of a semiconductor element.SOLUTION: After a TEOS oxide film is formed on the surface of a semiconductor device, a PSG film and a SiN film having gas permeability are formed on the surface of the TEOS oxide film, and a Poly-Si film is formed thereover. Moreover, a sacrifice layer is removed by gaseous HF through the PSG film, the SiN film and the Poly-Si film, and the uppermost layer is covered with a Poly-Si/SiC film. A chip-scale package having a thin-film hollow sealing structure can be realized on a semiconductor element.

Description

Embodiments described herein relate generally to a semiconductor device and a method for manufacturing the same.

  2. Description of the Related Art In recent years, high integration technology has progressed in semiconductor devices, and the integration technology of semiconductor elements constituting the semiconductor is also required to have high density. In particular, recent high integration technologies for semiconductor devices require integration technologies for electromechanical elements (MEMS) as well as high performance semiconductor element (LSI) integration technologies.

  MEMS (Micro Electro Mechanical System) is an electromechanical element having a micro structure manufactured using a silicon micromachining process. MEMS is expected to be applied in a wide range of electronic parts such as pressure sensors, acceleration sensors, and RF filters. One technique for integrating such MEMS and LSI is a high-density three-dimensional mounting technique in which each LSI and MEMS are stacked, but it is necessary to form vertical through holes in the LSI and MEMS. Therefore, there is a problem that the process cost is high. Therefore, a technique for highly integrating the same plane at a low cost without forming a through hole has been required.

  Typically, there are two methods for highly integrating on the same plane: SOC (System on Chip) and SIP (System in Package). The SOC is a method of integrating a plurality of elements (devices) by forming them on one chip. Although the SOC can increase the degree of device integration, there is a problem that the type of device that can be integrated is limited. For example, it is difficult to form a device made of another crystal system such as GaAs on a Si substrate due to process differences. In addition, there is a problem that the design period for realizing a new SOC is long and the development cost is high.

In contrast to this SOC, the SIP is such that each LSI chip is individually formed and then individually mounted on an integrated substrate. In this SIP, since each chip can be formed individually, there is no restriction on the chip to be integrated. Further, when a new system is realized, since an existing chip can be used, the design period can be shortened, so that the development cost can be reduced. However, since the chip integration density depends on the circuit board on which each chip is mounted, there is a problem that it is difficult to increase the density of the chip arrangement as compared with the SOC.

JP 2007-260866 A

The embodiment of the present invention is intended to easily enable high-density mounting of electronic devices by realizing a semiconductor device having a hollow structure as a wafer level chip scale package.

  A semiconductor device according to an embodiment of the present invention has a surface on which a plurality of semiconductor elements including at least a semiconductor substrate are formed. And this semiconductor device is provided with the hollow structure which has the surface which consists of the wall surface which consists of an insulating film, and the inorganic thin film provided with the Poly-Si thin film at least on a semiconductor substrate.

A method for manufacturing a semiconductor device according to another embodiment of the present invention is a method for manufacturing a semiconductor device having a surface on which a plurality of semiconductor elements including at least a semiconductor substrate are formed. This manufacturing method includes a step of forming an insulating film layer (BOX layer) on a surface of a semiconductor substrate, a step of forming an SOI layer on the surface, a step of removing a part of the SOI layer, an SOI layer, and an SOI layer. Forming a TEOS film on the surface of the insulating film layer exposed by etching away the layer; forming an inorganic thin film having at least a Poly-Si thin film layer on the surface; and subjecting the substrate to vapor phase HF treatment Thus, at least a step of removing a part of the insulating film layer and the TEOS film to form a hollow portion is provided.

It is principal part sectional drawing which shows the example of the semiconductor device which concerns on this Embodiment. It is principal part sectional drawing which shows the example of the semiconductor device which concerns on other embodiment. 1 is a plan view showing an example of a semiconductor device according to a first embodiment. It is process sectional drawing explaining the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing explaining the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing explaining the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing explaining the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing explaining the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is process sectional drawing explaining the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is process sectional drawing explaining the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is process sectional drawing explaining the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. Furthermore, it is principal part sectional drawing which shows the example of the semiconductor device which concerns on other embodiment.

  When an electromechanical element (MEMS element) is mounted on an electronic device, it is necessary to hermetically seal the MEMS element in order to protect the MEMS movable part. It has been performed that a MEMS package is mounted on a metric package and a cap portion is hollow-sealed by welding or the like.

  However, in this sealing method using a ceramic hermetic package, the package size is extremely large compared to a MEMS element, and the MEMS package size is a limiting condition for mounting on a small electronic device. In order to achieve this, there has been an increasing demand for practical use of a small MEMS package.

  In order to solve this problem, a structure in which MEMS hollow sealing is realized by mounting a silicon wafer having a concave portion on a MEMS as a cap can be considered.

  Since this method uses the same material as the MEMS forming silicon as the MEMS sealing material, it can prevent stress breakdown of the sealed portion due to the difference in thermal expansion coefficient and realize MEMS sealing at the wafer level. As a result, the MEMS sealing can be realized at a low cost, and there are advantages such that the size can be reduced as compared with the ceramic hermetic package.

However, since this MEMS wafer level package technology uses a silicon wafer having recesses as a sealing material, from the viewpoint of reducing the thickness of MEMS sealing, the silicon wafer becomes a limiting condition for reducing the thickness. There was a limit to miniaturization of equipment.
Specifically, the constraints on miniaturization include the integration of MEMS and MEMS that have been completed by inspecting and selecting LSIs and MEMSs that have been completed with their own manufacturing technology and dicing them into individual chips, and then rearranging them at the chip level. By restructuring as a wafer, there is a technology that makes it possible to achieve high integration that cannot be achieved by conventional SIP and composite that cannot be achieved by SOC in a short period of time (see Patent Document 1). In hollow sealing using a silicon wafer, the thickness of the MEMS sealing portion is a limiting condition for reducing the thickness of the integrated semiconductor device.

  For this reason, it is conceivable to seal the MEMS sealing portion at the wafer level using an organic resin film such as SU-8. However, since the organic resin film has low hermeticity, the MEMS element that can be used is There were restrictions.

  The semiconductor device and the manufacturing method thereof according to the present embodiment solve this conventional problem.

  Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS.

(Embodiment of semiconductor device)
Hereinafter, the semiconductor device according to the present embodiment will be described with reference to FIG. 1, FIG. 2, and FIG.
FIG. 1 is a cross-sectional view of the semiconductor device of the present embodiment. FIG. 2 is a cross-sectional view of a semiconductor device according to another embodiment. FIG. 3 is a plan view of the semiconductor device of the present embodiment.

As shown in FIG. 1, the semiconductor device of this embodiment includes an insulating film layer (BOX layer) 12 and an SOI layer formed on the insulating film layer (BOX layer) 12 on a semiconductor substrate 11. A MEMS fixed portion 13a and a MEMS movable portion 13b formed by processing, a TEOS oxide film 14, a first inorganic film layer 15 having an etching hole 15a, a second inorganic thin film 16, and an I / O electrode 17 are provided. I have. The semiconductor substrate 11, the insulating film layer 12, the TEOS oxide film 14, the first inorganic thin film 15 and the second inorganic thin film 16 constitute a hollow space that accommodates the MEMS element driving portion. .

In the embodiment of the semiconductor device described above, the insulating film layer (BOX layer) 12 and the TEOS oxide film 14 are adopted as materials constituting the side wall surface of the hollow space.
Here, the insulating film layer (BOX layer) and the TEOS oxide film are used as the side wall surface material by using the TEOS oxide film and using the TEOS oxide film as a support column and a space larger than the bending of the inorganic thin film on the MEMS movable portion This is because the sacrificial layer can be removed together with the insulating film layer (BOX layer) by re-filling the SOI region with TEOS.

  In the embodiment of the semiconductor device described above, the first and second inorganic thin films 15 and 16 are employed as the sealing member constituting the MEMS element hollow space. In this inorganic thin film, the airtightness, the MEMS, Mechanical strength for sealing an element, chemical stability in a semiconductor process, heat resistance, and the like are required. Particularly, a surface layer requires rigidity and airtightness. As long as the material satisfies these requirements, a single film may be used without using a plurality of thin film layers.

The material of the first inorganic thin film 15 is preferably selected from materials such as Poly-Si, PSG, SiN, and SiO. The first inorganic thin film 15 may be a composite thin film including a plurality of materials.
The material of the second inorganic thin film 16 is preferably a poly-Si / SiC composite thin film. This thin film has excellent properties in terms of hermetic retention including mechanical strength and moisture resistance.
In particular, it is preferable that at least one of the first and second inorganic thin films includes a Poly-Si layer.

  In the semiconductor device of this embodiment, there is a remarkable effect that semiconductor elements including MEMS can be integrated at high density. In addition, unlike conventional MEMS sealing using a silicon wafer having a concave portion, the MEMS hollow sealing is realized with an inorganic thin film, so that it is more reliable than the MEMS hollow sealing using an organic thin film. In addition to being improved, the integrated semiconductor device can be made extremely thin.

In the embodiment shown in FIG. 1, the first inorganic thin film 15 is a film provided with an etching hole for allowing gaseous HF to pass through. However, the first inorganic thin film 15 itself transmits gaseous HF. In the case of using a material having the property, as shown in FIG. 2, a film without an etching hole may be used.

FIG. 3 is a plan view of the semiconductor device shown in FIG. Components equivalent to those in FIG. 1 are given the same reference numerals. FIG. 3 is merely an example, and the MEMS layout can be changed as appropriate.

(Other Embodiments Related to Semiconductor Device)
In the above embodiment, the semiconductor device formed on the Si substrate has been described, but the present invention can also be applied to a compound semiconductor substrate. An example is shown in FIG. The semiconductor device of this embodiment is a cross-sectional view of a main part showing an example applied to a monolithic microwave integrated circuit (MMIC).
In FIG. 12, reference numeral 1201 denotes a compound semiconductor substrate, reference numeral 2012 denotes an insulating layer, and an upper layer 1203 denotes a compound semiconductor element region. An upper layer of the compound semiconductor region has a hollow space, and a first inorganic thin film 1204 having an etching hole is disposed on the upper layer. Further, the upper layer is a second inorganic thin film 1205.

(First Embodiment Regarding Method for Manufacturing Semiconductor Device)
Hereinafter, the manufacturing method of this embodiment for forming a hollow space and a plurality of semiconductor elements on a semiconductor substrate will be described with reference to FIGS. However, in the following embodiments, the description of the manufacturing process of semiconductor elements other than the MEMS element is omitted in the manufacturing method process of the semiconductor device.

(First step: FIG. 4A)
First, an insulating film layer (BOX layer) 34 is formed on the semiconductor substrate 31 by a CVD method or an oxidation method such as heating the semiconductor substrate in an oxidizing atmosphere containing oxygen gas or moisture. Subsequently, an SOI layer 33 is formed on the surface. Further, a resist is formed on the surface by a coating method or the like, and a resist pattern 32 for forming a movable part of the MEMS is formed by a method such as photolithography.

(Second step: FIG. 4B)
Using the resist pattern 32 as a mask, a processed groove constituting the MEMS is formed in the SOI layer 33 by a Deep-RIE method. In this process, the part other than the etched area becomes a MEMS movable part.

(Third step: FIG. 4C)
The resist pattern 32 is peeled off. As a stripping method, it is possible to employ a means such as an ashing method in which the resist is incinerated by using a resist stripping solution or heating in an oxidizing atmosphere.

(Fourth step: FIG. 5A)
A TEOS oxide film 41 is formed by LPCVD or the like so as to cover the processed groove of the SOI layer 33 on the surface of the semiconductor substrate in which the processed groove is formed in the second step.

(Fifth step: FIG. 5B)
A second TEOS oxide film 42 is formed on the TEOS oxide film 41 by the LPCVD method or the like.

(Sixth step: FIG. 5C)
A Poly-Si film 44 is formed on the surface of the first inorganic thin film 42 by LPCVD or the like.

(Seventh step: FIG. 5D)
A photoresist layer is formed on the surface of the Poly-Si film 44, and an etching hole pattern is formed in the photoresist layer according to a photolithographic method or the like.

(Eighth step: FIG. 6A)
Next, using the pattern of the photoresist layer as a mask, the Poly-Si film is etched to form an etching hole 44 c in the Poly-Si layer 44. This etching hole is for fulfilling the function of passing gaseous HF, and the diameter is preferably in the range of 1 μm to 30 μm.

(Ninth step: FIG. 6B)
Next, a gaseous HF treatment is performed through the etching hole 44c of the Poly-Si layer, thereby removing part of the TEOS oxide film layers 41 and 42 and the insulating film layer (BOX layer) 34 by etching. A hollow space in which the element can be operated is formed.
This etching is performed in order to provide a hollow space around the MEMS driving portion of the SOI film 33 so as to surround it, and a part of the TEOS oxide film 41 and the insulating film layer (BOX layer) 34 is formed. Leave and configure the wall surface of the hollow space. Such sacrificial layer etching can be performed by leaving the substrate to be processed in a gaseous HF atmosphere at 80 to 100 ° C. for about 300 to 600 seconds. The atmospheric concentration of gaseous HF is preferably in the range of 5 to 10% by volume.

(Tenth step: FIG. 6C)
Next, a second inorganic thin film 43 is formed on the surface of the Poly-Si layer 44 having the etching holes. As the second inorganic thin film, a SiC / Poly-Si film 43 is preferable. In this step, a Poly-Si layer and a SiC layer can be formed sequentially to form a thin film. Since this film serves as a protective film for sealing the MEMS element, it is preferable to use a material having excellent mechanical strength and airtightness retention. In this step, the second inorganic thin film can be formed by a sputtering method or the like. In this case, an oblique sputtering method using an etching hole as a shield is used so that the sputter metal does not enter the hollow space. It is preferable to use it.

(11th step: FIG. 7A)
Next, a resist 51 is formed on the surface of the SiC / Poly-Si film 43, and then a via pattern is formed in the resist 51. This is for providing an opening for taking out the I / O electrode terminal of the MEMS element.

(Twelfth step: FIG. 7B)
Using the resist 51 as a mask, the second inorganic thin film SiC / Poly-Si film 43 and the first inorganic thin film 44 are patterned to form an I / O electrode extraction opening 52 that reaches the SOI layer 33.

(13th step: FIG. 7C)
Next, an Al thin film 53 and a Ti thin film 54 are sequentially formed on the entire surface of the substrate 31.

(14th step: FIG. 7D)
Next, the Al thin film 53 and the Ti thin film 54 formed in a region other than the I / O extraction opening 52 are peeled off. The Al / Ti laminated thin film used in the above step 13 is merely an example, and a metal material such as another Au / Ni / Ti laminated thin film can also be adopted.

  Through the above steps, a semiconductor device including a MEMS element with a high element integration density can be formed.

As is clear from these process cross-sectional views, the hollow structure of the semiconductor device according to the present embodiment realizes the hollow structure using the thickness of the TEOS oxide film. Therefore, the reliability of the hollow structure greatly depends on the thickness of the TEOS oxide film. The TEOS oxide film thickness in the present embodiment is preferably a film thickness in which the sealing film does not come into contact with the MEMS movable portion due to stress deformation, from the relationship between the TEOS oxide film thickness and the deformation amount of the sealing film.
If necessary, a pillar material (reference numeral 20 in FIG. 3) that protects the deformation of the sealing film can be disposed in a region of the hollow structure that does not hinder the operation of the MEMS element. This column material can be realized as a region where the sacrificial layer is not etched in the hollow structure portion, and its size and arrangement are not particularly limited. Therefore, the structure of the column material is realized with the same structure as the laminated structure that realizes the hollow structure.

Second Embodiment Regarding Semiconductor Device Manufacturing Method
Hereinafter, another embodiment of the manufacturing method will be described with reference to FIGS.
In FIG. 8 and subsequent figures, elements equivalent to those in FIG. 4 to FIG.

(First Step to Third Step: (a) to (c) of FIG. 8)
Since these steps are the same as the first to third steps of FIG. 4 in the above embodiment, the description thereof is omitted.

(Fourth step: FIG. 9A)
A TEOS oxide film 41 is formed on the surface of the semiconductor substrate in which the processed grooves are formed in the third step.

(Fifth step: FIG. 9B)
A first inorganic thin film 42 is formed on the TEOS oxide film 41. As a material of the first inorganic thin film 42, a composite material including a Poly-Si film is preferable. This step can be performed by sequentially forming a thin film using a material such as PSG, SiN, Poly-Si, etc., using a commonly used inorganic thin film forming means. The first inorganic thin film 42 is excellent in liquid or gas permeability in order to etch away the sacrificial layer of MEMS, and is excellent in solid impermeability when forming the second inorganic thin film formed thereon. Is required. The first inorganic thin film 42 is preferably a material having characteristics such as airtightness retention, mechanical strength, and bonding properties with the TEOS film. In the above-described embodiment, an example in which the first inorganic thin film 42 is formed of three layers of a PSG film, a SiN film, and a Poly-Si film has been described. However, such a combination is merely an example, and a material having the above characteristics Of course, it can be used alone or in combination.

(Sixth step: FIG. 9C)
In this step, the hollow space 7 is formed in the same manner as the ninth step in the first embodiment related to the manufacturing method.

(Seventh step: FIG. 9D)
A second inorganic thin film 43 is formed on the surface of the first inorganic thin film 42. As the second inorganic thin film, a Poly-Si / SiC film 43 is preferable. Also in this step, as in the fifth step, the Poly-Si layer and the SiC layer can be sequentially formed to form a thin film. Since this film serves as a protective film for sealing the MEMS element, it is preferable to use a material having excellent mechanical strength and airtightness retention.

(Eighth Step to Eleventh Step: FIGS. 10A to 11A)
Since these steps are the same as the tenth step (FIG. 6C) to the fourteenth step (FIG. 7D) in the first embodiment, description thereof will be omitted.

  Through the above steps, a semiconductor device including a MEMS element with a high element integration density can be formed.

  As is clear from these process cross-sectional views, the hollow structure of the semiconductor device according to the present embodiment is preferable because the process of forming an etching hole in the first inorganic thin film can be omitted.

According to these embodiments, since it is possible to manufacture a semiconductor package having a hollow sealing structure with a thin film equivalent to a passivation film of a semiconductor device, a semiconductor package having a hollow structure with a thin film, which has been difficult until now, is obtained as a wafer. By realizing as a level chip scale package, high-density mounting of electronic devices can be easily achieved.

Hereinafter, embodiments will be further described by way of examples.
This example includes a step of forming a TEOS oxide film on a semiconductor element, a step of forming a first inorganic thin film including a Poly-Si film on the TEOS oxide film, and an etching hole opening portion in the first inorganic thin film. And a step of etching and removing the TEOS oxide film by gaseous HF through the etching opening of the first inorganic thin film.

Hereinafter, examples will be described in detail with reference to FIGS. As shown in FIGS. 4A to 4C, an oxide layer 34 is formed on a semiconductor substrate 31, and an SOI layer 33 is formed on the surface thereof. Then, a deep RIE method is employed to remove a part of the SOI layer and form the MEMS movable portion 33.
Next, as shown in FIGS. 5A to 5D, TEOS oxide films 41 and 42 are formed by LPCVD so as to fill the processing grooves between the MEMS movable parts 33 arranged in parallel. A Poly-Si film serving as a first inorganic thin film is deposited on the surface, and then a resist film (SU-8) having a pattern for forming etching holes in the Poly-Si film is formed.

  Next, as shown in FIGS. 6A to 6C, an etching hole is formed in Poly-Si using this resist film, and then the SU-8 film is peeled off. On the surface thereof, a Poly-Si film, A SiC film was sequentially formed to form a second inorganic thin film 43.

  Next, as shown in FIGS. 7A to 7D, an electrode terminal lead-out opening 53 is deposited in the second inorganic thin film 43, and the metal layer in the opening is deposited to form an I / O electrode 53.

  In this embodiment mode, the insulating film layer (BOX layer) and the TEOS film constituting the sacrificial layer are removed by etching with gaseous HF that has passed through the first inorganic thin film, and the MEMS sealing is used as the uppermost layer. In order to improve the rigidity and airtightness of the film, a Poly-Si / SiC film is deposited.

  By performing the above steps, the semiconductor device in which the MEMS movable portion shown in FIG. 1 (or FIG. 2) and FIG. 3 is hermetically sealed can be manufactured at the wafer level.

  As a result of evaluating a semiconductor device manufactured by such a process, a semiconductor chip of 2.9 mm × 2.9 mm × 0.65 mm is sealed using a sealing material in which a recess is formed on a conventional silicon substrate. The outer dimensions of 3.5 mm × 3.5 mm × 1.5 mm were required, but as a result of manufacturing using the manufacturing method according to the present invention, the outer dimensions of 2.9 mm × 2.9 mm × 0.75 mm were obtained at the wafer level. It became possible to seal, and it became possible to make it very small to 34% in volume ratio compared with the case of a prior art.

  Further, in the case of the sealing film for adhering the organic resin film that has been performed so far, the hollow portion could not be maintained at a high vacuum, but in this embodiment, the vacuum degree of the hollow portion is −75 MPa. It has been confirmed that the reliability can be greatly improved.

  Further, when the connection reliability of the semiconductor device according to this embodiment formed as described above was evaluated, the following results were obtained. Specifically, a semiconductor device having dimensions of 2.9 mm × 2.9 mm × 0.75 mm as shown in FIG. 1 and FIG. 2 used for explaining examples of the semiconductor device according to the present embodiment. This is a result of evaluating the connection reliability of a sample when integrated with a driving semiconductor chip by the integration technique disclosed in Japanese Patent Application Laid-Open No. 2007-260866. A case where the connection was opened even at one of the 256 pins was regarded as defective, the cumulative defect rate on the vertical axis, and the temperature cycle on the horizontal axis. The number of samples was 1000, and the temperature cycle test conditions were (-55 ° C. (30 min) to 25 ° C. (5 min) to 125 ° C. (30 min) to 25 ° C. (5 min)).

  As a result, the semiconductor device sealed according to the present technology is not confirmed to have poor connection up to 3000 cycles, as in the conventional semiconductor device sealed with a silicon substrate having a recess formed therein, and the integrated semiconductor device. Assured reliability was confirmed.

In the above embodiment, an etching hole is formed in the first inorganic thin film, and the TEOS oxide film layer and the insulating film layer (BOX layer) are removed by etching to form a hollow space. By using a thin film, a semiconductor device was formed in the same manner as in the above example without forming an etching hole, but almost the same result was obtained.

As mentioned above, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

11 Semiconductor substrate 12 Insulating film layer (BOX layer)
DESCRIPTION OF SYMBOLS 13 SOI layer 13a MEMS fixed part 13b MEMS movable part 14 TEOS oxide film 15 1st inorganic thin film 16 2nd inorganic thin film 17 I / O electrode 18 Hollow space 20 Column material 31 Semiconductor substrate 32 Resist film 33 SOI layer 34 Insulating film Layer (BOX layer)
35 processing groove 41 TEOS oxide film 42 first inorganic thin film 43 second inorganic thin film 51 resist film 52 I / O electrode opening 53 I / O electrode

Claims (8)

A semiconductor device in which a plurality of semiconductor elements are formed on a semiconductor substrate surface,
A semiconductor substrate;
A wall surface made of an insulating film layer (BOX layer) formed on the semiconductor substrate;
A semiconductor device, wherein a movable portion of the electromechanical element is disposed in a hollow space formed by at least a surface made of an inorganic thin film provided with a Poly-Si thin film.   The semiconductor device according to claim 1, wherein a SiC film is further formed on the Poly-Si film.   2. The semiconductor device according to claim 1, wherein an I / O electrode is formed to open the inorganic thin film and make electrical connection with an external circuit.   The integrated semiconductor device according to claim 1, wherein the plurality of semiconductor elements are electromechanical elements or compound semiconductor elements. A method of manufacturing a semiconductor device having a surface on which a plurality of semiconductor elements are formed on a semiconductor substrate,
A step of forming an insulating film layer (BOX layer) on the surface of the semiconductor substrate, a step of forming an SOI layer on the surface, and a step of removing a part of the SOI layer to form a movable part of an electromechanical element; Forming a TEOS oxide film on the surface of the insulating film layer (BOX layer) exposed by etching and removing the SOI layer and the SOI layer, and forming an inorganic thin film having at least a Poly-Si thin film layer on the surface And a step of removing the insulating film layer (BOX layer) and part of the TEOS film to form a hollow portion in which the movable portion of the electromechanical element is disposed by subjecting the substrate to vapor phase HF treatment. A method for manufacturing a semiconductor device, comprising:   6. The method of manufacturing an integrated semiconductor device according to claim 5, further comprising forming a Poly-Si film or a SiC film on the Poly-Si film.   6. The method of manufacturing a semiconductor device according to claim 5, further comprising the step of forming an I / O electrode for electrical connection with an external circuit on the TEOS oxide film. 6. The method of manufacturing an integrated semiconductor device according to claim 5, wherein the semiconductor element is an electromechanical element or a compound semiconductor.

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