JP2014056875A - Photoelectric conversion element and photoelectric conversion element manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a photoelectric conversion element and a photoelectric conversion element manufacturing method, which can achieve further improvement of characteristics of a hetero-junction back contact cell.SOLUTION: A photoelectric conversion element comprises: a first groove, a second groove and a salient between the first groove and the second groove which are formed on a part of a surface of a first conductivity type semiconductor substrate; a first conductivity type amorphous film formed on the first groove, the second groove and the salient; a second conductivity type amorphous film formed on a region of the surface of the semiconductor substrate other than the first groove, the second groove and the salient; a first conductivity type electrode layer for entirely covering the first conductivity type amorphous film; and a second conductivity type electrode layer for entirely covering the second conductivity type amorphous film, in which the first conductivity type electrode layer and the second conductivity type electrode layer are electrically insulated from each other.

Description

  The present invention relates to a photoelectric conversion element and a method for manufacturing the photoelectric conversion element.

  In recent years, a solar cell that directly converts solar energy into electric energy has been rapidly expected as a next-generation energy source particularly from the viewpoint of global environmental problems. There are various types of solar cells, such as those using compound semiconductors or organic materials, but the mainstream is currently using silicon crystals.

  Currently, the most manufactured and sold solar cells have a structure in which electrodes are respectively formed on a light receiving surface that is a surface on which sunlight is incident and a back surface that is opposite to the light receiving surface.

  However, when an electrode is formed on the light receiving surface, sunlight is reflected and absorbed by the electrode, so that the amount of incident sunlight is reduced by the area of the electrode. Therefore, for example, Patent Document 1 discloses a heterojunction back contact cell in which both an n-electrode emitter contact and a p-electrode base contact are formed on the back side of an n-type single crystal silicon substrate. .

  FIG. 19 is a schematic cross-sectional view of a heterojunction back contact cell disclosed in Patent Document 1 of the related art. In the heterojunction back contact cell shown in FIG. 19, a p + region 106 is formed in a partial region on the back surface of the n-type silicon substrate 101, and the region on the back surface of the n-type silicon substrate 101 other than the p + region 106. An i-type amorphous silicon film 110 and an n-type amorphous silicon film 111 are stacked in this order. A base contact 112 and an emitter contact 113 are formed on the p + region 106 and the n-type amorphous silicon film 111, respectively. It has a formed structure.

In a region other than the i-type amorphous silicon film 110 and the base contact 112 on the back surface of the n-type silicon substrate 101, a SiN _x film 103 is deposited. The light receiving surface of the n-type silicon substrate 101 is subjected to minute uneven processing to form a pyramidal etching structure 104. Furthermore, the surface injection layer 102 is formed in the etching structure 104 of the n-type silicon substrate 101 by diffusion of phosphorus, and a SiN _x film 108 used as an antireflection film is deposited on the surface injection layer 102. Has been.

  The heterojunction back contact cell having such a structure has a carrier on the back surface of the single crystal silicon substrate as compared with the conventional back contact cell in which the p + region and the n + region are respectively formed on the back surface of the single crystal silicon substrate. The recombination can be prevented, and the open circuit voltage becomes high, so that the characteristics are improved.

JP 2010-219527 A

  However, in the heterojunction back contact cell disclosed in Patent Document 1 shown in FIG. 19, light incident from the light receiving surface of the n-type silicon substrate 101 is not absorbed inside the n-type silicon substrate 101. In this case, the light is transmitted from between the base contact 112 and the emitter contact 113 to the outside, the short-circuit current density is lowered, and the characteristics may be lowered. Therefore, further improvement of the characteristics of the heterojunction back contact cell is desired.

  In view of the above circumstances, an object of the present invention is to provide a photoelectric conversion element and a method for manufacturing the photoelectric conversion element that can achieve further improvement in characteristics of the heterojunction back contact cell.

  The present invention includes a first conductivity type semiconductor substrate, and a part of the surface of the semiconductor substrate includes a first groove and a second groove, and a convex portion between the first groove and the second groove. The first conductivity type amorphous film is provided on the first groove, the second groove, and the convex portion, and the first groove and the second groove on the surface of the semiconductor substrate are provided. A second conductive type amorphous film is provided in a region other than the convex portion, and a first conductive type electrode layer covering the entire surface of the first conductive type amorphous film, and a second conductive type amorphous film The photoelectric conversion element has a second conductivity type electrode layer covering the entire surface of the film, and the first conductivity type electrode layer and the second conductivity type electrode layer are electrically insulated.

  Here, in the photoelectric conversion element of the present invention, it is preferable that a second convex portion smaller than the convex portion is further provided on the entire surface of the semiconductor substrate.

  In the photoelectric conversion element of the present invention, an i-type amorphous material is formed between the surface of the semiconductor substrate and the first conductive type amorphous film and between the surface of the semiconductor substrate and the second conductive type amorphous film. A film is preferably provided.

  Furthermore, the present invention provides a step of installing a first mask material on a portion of one surface of a first conductivity type semiconductor substrate, and removing a portion of the semiconductor substrate using the first mask material as a mask. Forming a first groove, a second groove, and a convex portion between the first groove and the second groove on the surface of the semiconductor substrate, and the first groove and the second groove. A step of installing the second mask material so that the convex portion is exposed from between the step, a step of removing a part of the surface of the convex portion using the second mask material as a mask, and a first surface of the semiconductor substrate Forming a second conductive amorphous film in a region other than the first groove, the second groove, and the convex portion, and a third mask material so as to cover the first groove, the second groove, and the convex portion And a second conductive type amorphous film so as to cover the region other than the first groove, the second groove and the convex portion on the surface of the semiconductor substrate and the third mask material A step of forming, a step of removing the third mask material and the second conductive type amorphous film on the third mask material, and a fourth mask material on the remaining portion of the second conductive type amorphous film. A step of installing, a step of forming a first conductive amorphous film so as to cover the fourth mask material, the first groove, the second groove, and the convex portion, and the fourth mask material and the fourth mask A step of removing the first conductive type amorphous film on the mask material; a first conductive type electrode layer covering the entire surface of the first conductive type amorphous film after removing the fourth mask material; Forming a second conductivity type electrode layer covering the entire surface of the two conductivity type amorphous film so that the first conductivity type electrode layer and the second conductivity type electrode layer are electrically insulated; The manufacturing method of the photoelectric conversion element containing these.

  Here, the method for manufacturing a photoelectric conversion element of the present invention further includes a step of forming a second convex portion smaller than the convex portion on the entire surface of the semiconductor substrate before the step of installing the third mask material. It is preferable to include.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the photoelectric conversion element which can achieve the further improvement of the characteristic of a heterojunction type back contact cell, and a photoelectric conversion element can be provided.

FIG. 3 is a schematic cross-sectional view of the heterojunction back contact cell according to the first embodiment. FIG. 6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment. FIG. 6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment. FIG. 6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment. FIG. 6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment. FIG. 6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment. 5 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of the first embodiment. FIG. FIG. 6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment. FIG. 6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment. FIG. 6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment. FIG. 6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment. FIG. 6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment. FIG. 6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment. FIG. 6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment. FIG. 6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment. FIG. 6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the first embodiment. FIG. 6 is a schematic cross-sectional view of a heterojunction back contact cell according to a second embodiment. FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the second embodiment. It is a typical sectional view of a heterojunction type back contact cell indicated by conventional patent documents 1.

  Embodiments of the present invention will be described below. In the drawings of the present invention, the same reference numerals represent the same or corresponding parts.

<Embodiment 1>
FIG. 1 is a schematic cross-sectional view of a heterojunction back contact cell according to Embodiment 1, which is an example of the photoelectric conversion element of the present invention. The heterojunction back contact cell of the first embodiment has a semiconductor substrate 1 made of n-type single crystal silicon, and a part of the back surface, which is one surface of the semiconductor substrate 1, has a first groove 4 and The 2nd groove | channel 5 and the convex part 6 between the 1st groove | channel 4 and the 2nd groove | channel 5 are provided. Here, the 1st groove | channel 4 and the 2nd groove | channel 5 are extended | stretched in the normal line direction of the paper surface of FIG. The protrusion 6 extends in the extending direction of the first groove 4 and the second groove 5 while protruding in the back surface direction of the semiconductor substrate 1.

  On the back surface of the semiconductor substrate 1, i-type amorphous silicon is formed on a region (hereinafter referred to as "groove formation region") 1b in which the first groove 4, the convex portion 6, and the second groove 5 are formed. The first i-type amorphous film 14, the first conductivity-type amorphous film 15 made of n-type amorphous silicon, the first electrode layer 16, and the second electrode layer 17 are laminated in this order. .

  The first conductivity type electrode layer 20b is composed of a laminate of the first electrode layer 16 and the second electrode layer 17 laminated on the back surface of the first conductivity type amorphous film 15, The entire back surface of the first conductivity type amorphous film 15 is covered with the first conductivity type electrode layer 20b.

  A second i-type amorphous film 11 made of i-type amorphous silicon, p-type is formed on a region other than the groove forming region 1 b (hereinafter referred to as “groove non-forming region”) 1 a on the back surface of the semiconductor substrate 1. The second conductivity type amorphous film 12 made of amorphous silicon, the first electrode layer 16 and the second electrode layer 17 are laminated in this order.

  In addition, the second conductive type electrode layer 20a is composed of a stacked body of the first electrode layer 16 and the second electrode layer 17 stacked on the back surface of the second conductive type amorphous film 12, The entire back surface of the second conductivity type amorphous film 12 is covered with the second conductivity type electrode layer 20a. The first conductivity type electrode layer 20b and the second conductivity type electrode layer 20a are electrically insulated because the first groove 4 and the second groove 5 are different in the height direction. ing.

  Note that “i-type” in this specification means that n-type or p-type impurities are not intentionally doped. For example, after manufacturing a photoelectric conversion element, n-type or p-type impurities are not present. Inevitable diffusion may cause n-type or p-type conductivity.

  In the present specification, “amorphous silicon” includes hydrogen atoms terminated with dangling bonds of silicon atoms such as amorphous silicon hydride.

  A texture structure 2 composed of fine pyramidal irregularities is formed on the light-receiving surface of the semiconductor substrate 1. On the texture structure 2 of the light-receiving surface of the semiconductor substrate 1, a passivation film 9 and an antireflection film 10 are formed. Formed in order.

  Hereinafter, an example of a method for manufacturing the heterojunction back contact cell of the first embodiment will be described with reference to schematic cross-sectional views of FIGS. First, as shown in FIG. 2, a texture structure 2 is formed on the entire light receiving surface of a semiconductor substrate 1 made of n-type single crystal silicon.

  The semiconductor substrate 1 is not limited to a substrate made of n-type single crystal silicon. For example, a conventionally known semiconductor substrate may be used.

  Although the thickness of the semiconductor substrate 1 is not specifically limited, For example, it can be 100 micrometers or more and 300 micrometers or less, Preferably it can be 100 micrometers or more and 200 micrometers or less. Further, the specific resistance of the semiconductor substrate 1 is not particularly limited, but may be, for example, 0.1 Ω · cm or more and 1 Ω · cm or less.

  Although the formation method of the texture structure 2 is not specifically limited, For example, conventionally well-known texture etching etc. can be used suitably.

  Next, as shown in FIG. 3, the first mask material 3 is placed on a part of the back surface of the semiconductor substrate 1.

  The material and installation method of the first mask material 3 are not particularly limited. For example, when the first mask material 3 is made of a photoresist, the first mask material 3 is placed on the entire back surface of the semiconductor substrate 1. After the coating, the first mask material 3 can be placed on a part of the back surface of the semiconductor substrate 1 by patterning the first mask material 3 by photolithography technique and etching technique.

  Next, as shown in FIG. 4, by removing a part of the back surface of the semiconductor substrate 1 using the first mask material 3 as a mask, a first groove 4 is formed on a part of the back surface of the semiconductor substrate 1. A second groove 5 and a convex portion 6 between the first groove 4 and the second groove 5 are formed.

Here, as a method of removing a part of the back surface of the semiconductor substrate 1 using the first mask material 3 as a mask, for example, dry etching or the like can be used. As the dry etching, for example, a reactive ion etching method using an ICP (Ion Coupling Plasma) dry etching apparatus using CF ₄ gas as an etching gas can be employed.

  It is preferable that the depth d of the first groove 4, the depth d of the second groove 5, and the height d of the convex portion 6 are 0.3 μm or more and 5 μm or less. When the depth d of the first groove 4, the depth d of the second groove 5, and the height d of the convex portion 6 are 0.3 μm or more, leakage between adjacent electrodes and the first i The deterioration of characteristics such as conversion efficiency due to deterioration of the type amorphous film 14 and the first conductive type amorphous film 15 can be suppressed. When the depth d of the first groove 4, the depth d of the second groove 5, and the height d of the convex portion 6 are 5 μm or less, the semiconductor substrate 1 does not become too thin. The deterioration of the characteristics can be effectively suppressed.

  The width W1 of the first groove 4 is preferably 500 μm or more. When the width W1 of the first groove 4 is 500 μm or more, the first conductivity type electrode layer 20b is connected to the wiring of the wiring sheet for electrically connecting the plurality of heterojunction back contact cells. In addition, misalignment is less likely to occur and electrical leakage is less likely to occur. The width W1 of the first groove 4 is preferably 10000 μm or less.

  The width W2 of the second groove 5 is preferably 500 μm or more. When the width W2 of the second groove 5 is 500 μm or more, the first conductivity type electrode layer 20b is connected to the wiring of the wiring sheet for electrically connecting a plurality of heterojunction back contact cells to collect current. At this time, it is difficult for positional deviation to occur, so that it is difficult to cause electrical leakage. The width W2 of the second groove 5 is preferably 10000 μm or less.

  The width W3 of the convex portion 6 is preferably 250 μm or more. When the width W3 of the convex portion 6 is 250 μm or more, the first conductivity type electrode layer 20b is connected to the wiring of the wiring sheet for electrically connecting a plurality of heterojunction back contact cells to collect current. It is possible to suppress the occurrence of connection failure during the operation and suppress the deterioration of the current extraction efficiency. Moreover, it is preferable that the width W3 of the convex part 6 is 50000 micrometers or less.

  Next, as shown in FIG. 5, the first mask material 3 is removed from the back surface of the semiconductor substrate 1. The method for removing the first mask material 3 is not particularly limited, and a conventionally known method can be used.

  Next, as shown in FIG. 6, the second mask material 7 is installed so that the convex portion 6 is exposed from between the first groove 4 and the second groove 5.

  The material and installation method of the second mask material 7 are not particularly limited. For example, when the second mask material 7 is made of a photoresist, the second mask material 7 is placed on the entire back surface of the semiconductor substrate 1. After the application, the second mask material 7 is patterned by the photolithography technique and the etching technique, so that the convex portion 6 is exposed from between the first groove 4 and the second groove 5. This can be done by installing the mask material 7.

  Next, as shown in FIG. 7, a part of the surface of the convex portion 6 is removed using the second mask material 7 as a mask. Thereby, the surface of the convex part 6 has a gentler slope than before removal of a part of the surface of the convex part 6. Thus, when the convex part 6 is formed so that the surface of the convex part 6 has a gentler slope than before removal of a part of the surface of the convex part 6, in the process described later, There is a tendency that the first i-type amorphous film 14 and the first conductivity-type amorphous film 15 can be continuously formed on the groove forming region 1b on the back surface without interruption.

  In this step, a part of the surface of the convex portion 6 is removed. However, since the surface of the convex portion 6 has a gentle slope, the surface of the convex portion 6 after the removal is removed. The width and height are almost the same as the width W3 and height d before the removal.

  Here, as a method of removing a part of the surface of the convex portion 6 using the second mask material 7 as a mask, conventionally known dry etching and / or wet etching can be used, for example.

  Next, as shown in FIG. 8, the second mask material 7 is removed from the back surface of the semiconductor substrate 1. The method for removing the second mask material 7 is not particularly limited, and a conventionally known method can be used.

  Next, as shown in FIG. 9, a passivation film 9 and an antireflection film 10 are stacked in this order on the texture structure 2 on the light receiving surface of the semiconductor substrate 1.

  As the passivation film 9 and the antireflection film 10, for example, a transparent conductive oxide film, a silicon nitride film, a silicon oxide film, an i-type amorphous silicon film, or the like can be stacked. The thickness of the laminate of the passivation film 9 and the antireflection film 10 can be about 100 nm, for example. The lamination method of the passivation film 9 and the antireflection film 10 is not particularly limited, and for example, a conventionally known plasma CVD (Chemical Vapor Deposition) method or sputtering method can be used.

  Next, as shown in FIG. 10, a third mask material 8 is placed on the groove forming region 1 b on the back surface of the semiconductor substrate 1.

  The material and installation method of the third mask material 8 are not particularly limited. For example, when the third mask material 8 is made of a photoresist, the third mask material 8 is placed on the entire back surface of the semiconductor substrate 1. After coating, the third mask material 8 is installed so as to cover only the groove forming region 1b on the back surface of the semiconductor substrate 1 by patterning the third mask material 8 by photolithography technique and etching technique. Can be performed.

  Next, as shown in FIG. 11, the second i-type amorphous film made of i-type amorphous silicon is formed on the groove non-forming region 1 a on the back surface of the semiconductor substrate 1 and on the back surface of the third mask material 8. The second conductivity type amorphous film 12 made of 11 and p-type amorphous silicon is laminated in this order, for example, by a plasma CVD method.

  The second i-type amorphous film 11 is not limited to a film made of i-type amorphous silicon. For example, a conventionally known i-type amorphous semiconductor film may be used. The thickness of the second i-type amorphous film 11 is not particularly limited, but may be, for example, 5 nm or more and 10 nm or less.

  The second conductive type amorphous film 12 is not limited to a film made of p-type amorphous silicon. For example, a conventionally known p-type amorphous semiconductor film may be used. Although the thickness of the 2nd conductivity type amorphous film 12 is not specifically limited, For example, it is 5 nm or more and 10 nm or less.

As the p-type impurity contained in the second conductive type amorphous film 12, for example, boron can be used, and the p type impurity concentration of the second conductive type amorphous film 12 is, for example, 5 × 10 ^19. / Cm ³ or so.

  Next, as shown in FIG. 12, the third mask material 8 is removed from the back surface of the semiconductor substrate 1. As a result, the second i-type amorphous film 11 and the second conductive amorphous film 12 on the third mask material 8 are removed together with the third mask material 8, and the groove on the back surface of the semiconductor substrate 1 is removed. The formation region 1b is exposed.

  The method for removing the third mask material 8 is not particularly limited, and a conventionally known method can be used.

  Next, as shown in FIG. 13, a fourth mask material 13 is placed on the back surface of the second conductive type amorphous film 12 which is the remaining part of the removal of the third mask material 8.

  The material and installation method of the fourth mask material 13 are not particularly limited. For example, when the fourth mask material 13 is made of a photoresist, the back surface of the second conductivity type amorphous film 12 and the semiconductor substrate 1. After the fourth mask material 13 is applied to the entire surface of the groove forming region 1b on the back surface of the first mask material, the fourth mask material 13 is patterned by a photolithography technique and an etching technique to thereby obtain the second conductivity type amorphous film. This can be done by installing the fourth mask material 13 only on the back surface of 12.

  Next, as shown in FIG. 14, the first i-type amorphous film 14 made of i-type amorphous silicon is formed on the back surface of the fourth mask material 13 and on the groove forming region 1 b on the back surface of the semiconductor substrate 1. The first conductive type amorphous film 15 made of n-type amorphous silicon is laminated in this order, for example, by a plasma CVD method.

  The first i-type amorphous film 14 is not limited to a film made of i-type amorphous silicon. For example, a conventionally known i-type amorphous semiconductor film may be used. The thickness of the first i-type amorphous film 14 is not particularly limited, but may be, for example, 5 nm or more and 10 nm or less.

  The first conductive amorphous film 15 is not limited to a film made of n-type amorphous silicon, and a conventionally known n-type amorphous semiconductor film may be used, for example. Although the thickness of the 1st conductivity type amorphous film 15 is not specifically limited, For example, it is 5 nm or more and 10 nm or less.

As the n-type impurity contained in the first conductivity type amorphous film 15, for example, phosphorus can be used, and the n-type impurity concentration of the first conductivity type amorphous film 15 is, for example, 5 × 10 ^19. / Cm ³ or so.

  Next, as shown in FIG. 15, the fourth mask material 13 is removed from the back surface of the second conductivity type amorphous film 12. As a result, the first i-type amorphous film 14 and the first conductive amorphous film 15 on the fourth mask material 13 are also removed together with the fourth mask material 13, and the second conductive amorphous material is removed. The back surface of the film 12 is exposed.

  The method for removing the fourth mask material 13 is not particularly limited, and a conventionally known method can be used.

  Next, as shown in FIG. 16, a step of forming the first electrode layer 16 on the entire back surface of the semiconductor substrate 1 after the removal of the fourth mask material 13 is performed. As a result, the first electrode layer 16 is formed on the entire back surface of the second conductivity type amorphous film 12 and on the entire surface of the first i-type amorphous film 14.

  As the first electrode layer 16, a conductive material can be used, and for example, ITO (Indium Tin Oxide) or the like can be used.

  The first electrode layer 16 can be formed, for example, by sputtering, and the thickness of the first electrode layer 16 can be, for example, 80 nm or less.

  Next, as shown in FIG. 1, a step of forming a second electrode layer 17 on the entire back surface of the first electrode layer 16 is performed. As a result, a second conductivity type electrode layer 20 a made of a laminate of the first electrode layer 16 and the second electrode layer 17 is formed on the entire back surface of the second conductivity type amorphous film 12. In addition, on the entire back surface of the first conductivity type amorphous film 15, a first conductivity type electrode layer 20b made of a laminate of the first electrode layer 16 and the second electrode layer 17 is formed. The As shown in FIG. 1, the first conductivity type electrode layer 20b and the second conductivity type electrode layer 20a are different in the height direction by the first groove 4 and the second groove 5. Therefore, it is electrically insulated.

  As the second electrode layer 17, a material having conductivity and capable of reflecting sunlight can be used. For example, aluminum or the like can be used.

  The second electrode layer 17 can be formed by, for example, a sputtering method, and the thickness of the second electrode layer 17 can be, for example, 0.5 μm or less.

  Thereafter, it is preferable to perform cleaning with thin hydrochloric acid or the like for peeling off the second conductivity type electrode layer 20a and the first conductivity type electrode layer 20b attached to the end face of the semiconductor substrate 1.

  As described above, the entire back surface of the first conductivity type amorphous film 15 is covered with the first conductivity type electrode layer 20b, and the entire back surface of the second conductivity type amorphous film 12 is covered with the second conductivity type electrode. The heterojunction back contact cell according to the first embodiment, which is covered with the layer 20a and has a configuration in which the first conductivity type electrode layer 20b and the second conductivity type electrode layer 20a are electrically insulated, is completed. .

  In the heterojunction back contact cell of the first embodiment, the electrode layers (the first conductivity type electrode layer 20b and the second conductivity type electrode layer 20a) are formed on the entire back surface of the semiconductor substrate 1. Even if the light incident from the light receiving surface of the semiconductor substrate 1 is not absorbed inside the semiconductor substrate 1, the semiconductor layer 1 has a semiconductor layer on the back surface of the semiconductor substrate 1 compared to the case of Patent Document 1. Since it can reflect in the inside of the board | substrate 1, a short circuit current density can be made high.

  Further, in the heterojunction back contact cell of the first embodiment, the entire back surface of the semiconductor substrate 1 is an i-type amorphous film (the first i-type amorphous film 14 and the second i-type amorphous film). Compared to the case of Patent Document 1 in which the i-type amorphous silicon film 110 is provided only in the region other than the p + region 106 on the back surface of the n-type silicon substrate 101 because it is in contact with the film 11). The recombination of carriers on the back surface of 1 can be prevented, and the open circuit voltage can be increased.

  For the reasons described above, in the heterojunction back contact cell of the first embodiment, characteristics such as short-circuit current density and open-circuit voltage can be improved as compared with the case of Patent Document 1.

  Further, in the heterojunction back contact cell of the first embodiment, the convex portion 6 is formed so that the surface of the convex portion 6 has a gentle slope, so that the groove forming region 1b on the back surface of the semiconductor substrate 1 is formed. Since the first i-type amorphous film 14 and the first conductivity-type amorphous film 15 can be continuously formed without interruption, the n-electrode covering the back surface of the p-electrode 20a and the convex portion 6 It is also possible to make the height of the apex 20b the same. Therefore, in this case, when the heterojunction back contact cells of the first embodiment are electrically connected by the wiring sheet provided with the wiring pattern on the insulating substrate, they are connected to the p-electrode 20a. Since it is not necessary to change the height of the wiring and the height of the wiring connected to the n-electrode 20b, the stability of the electrical connection between the electrode and the wiring is improved, and the productivity of the wiring sheet itself is also improved. be able to.

  Further, in the heterojunction back contact cell of the first embodiment, the first electrode layer 16 and the second electrode layer 17 are sequentially stacked and electrically separated from each other without particularly using a mask. Since the conductivity type electrode layer 20b and the second conductivity type electrode layer 20a can be formed, the productivity of the heterojunction back contact cell is improved.

<Embodiment 2>
FIG. 17 is a schematic cross-sectional view of a heterojunction back contact cell according to Embodiment 2, which is another example of the photoelectric conversion element of the present invention. The heterojunction back contact cell according to the second embodiment is characterized in that a second protrusion 18 smaller than the protrusion 6 is further provided on the entire back surface of the semiconductor substrate 1. The width and height of the second convex portion 18 are not particularly limited as long as they are smaller than the width and height of the convex portion 6, respectively, but may be, for example, 100 nm or more and 10 μm or less. Moreover, the shape of the 2nd convex part 18 can be made into the tetrahedron in which each 2nd convex part 18 has a triangular surface, for example.

  As in the heterojunction back contact cell of the second embodiment, the second protrusion 18 smaller than the protrusion 6 is provided on the entire back surface of the semiconductor substrate 1 to increase the optical path length inside the semiconductor substrate 1. Therefore, the amount of reflection of light from the back surface of the semiconductor substrate 1 to the light receiving surface side can be reduced, and the reflection loss of light can be reduced. As a result, in the heterojunction back contact cell of the second embodiment, the amount of light absorbed inside the semiconductor substrate 1 can be increased, so that higher conversion efficiency than that of the first embodiment can be achieved. It becomes.

  Hereinafter, an example of a method for manufacturing the heterojunction back contact cell of the second embodiment will be described. First, through the steps shown in FIGS. 2 to 8, the first groove 4, the second groove 5, and the convex portion 6 are formed on the back surface of the semiconductor substrate 1. The process up to this point is the same as in the first embodiment.

  Next, as shown in the schematic cross-sectional view of FIG. 18, after the protective film 21 is formed on the texture structure 21 on the light receiving surface of the semiconductor substrate 1, the back surface of the semiconductor substrate 1 is etched. Thereby, the 2nd convex part 18 smaller than the convex part 6 can be formed in the whole back surface of the semiconductor substrate 1. FIG.

  Here, the protective film 21 is not particularly limited as long as it can protect the light receiving surface at the time of etching the back surface of the semiconductor substrate 1. For example, a silicon oxide film or a silicon nitride film can be used.

  Moreover, although the etching method of the back surface of the semiconductor substrate 1 is not particularly limited, it is preferable to use texture etching using an alkaline solution. In this case, the second protrusion 18 can be more easily formed on the entire back surface of the semiconductor substrate 1.

  Thereafter, in the same manner as in the first embodiment, the heterojunction back contact cell of the second embodiment can be manufactured.

  Since the description other than the above in the second embodiment is the same as that in the first embodiment, the description thereof is omitted here.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  INDUSTRIAL APPLICATION This invention can be utilized for the manufacturing method of a photoelectric conversion element and a photoelectric conversion element, and can be suitably used especially for the manufacturing method of a heterojunction type back contact cell and a heterojunction type back contact cell.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 1a Groove non-formation area | region, 1b Groove formation area | region, 2 Texture structure, 3 1st mask material, 4 1st groove | channel, 5 2nd groove | channel, 6 convex part, 7 2nd mask material, 8 3rd mask material, 9 Passivation film, 10 Antireflection film, 11 2nd i-type amorphous film, 12 2nd conductivity type amorphous film, 13 4th mask material, 14 1st i-type non- Amorphous film, 15 1st conductivity type amorphous film, 16 1st electrode layer, 17 2nd electrode layer, 18 2nd convex part, 20a 2nd conductivity type electrode layer, 20b 1st conductivity type Electrode layer, 21 protective film, 101 n-type silicon substrate, 102 surface injection layer, 103,108 SiN _x film, 104 etching structure, 106 p + region, 110 i-type amorphous silicon film, 111 n-type amorphous silicon film, 112 Base contact, 113 Emitter contact .

Claims (5)

A first conductivity type semiconductor substrate;
A part of the surface of the semiconductor substrate is provided with a first groove, a second groove, and a convex portion between the first groove and the second groove,
A first conductive type amorphous film is provided on the first groove, the second groove, and the convex portion,
A second conductive type amorphous film is provided in a region other than the first groove, the second groove, and the convex portion on the surface of the semiconductor substrate, and the first conductive type amorphous film A first conductivity type electrode layer covering the entire surface; and a second conductivity type electrode layer covering the entire surface of the second conductivity type amorphous film;
A photoelectric conversion element, wherein the first conductivity type electrode layer and the second conductivity type electrode layer are electrically insulated.   The photoelectric conversion element according to claim 1, wherein a second protrusion smaller than the protrusion is further provided on the entire surface of the semiconductor substrate.   An i-type amorphous film is provided between the surface of the semiconductor substrate and the first conductive amorphous film, and between the surface of the semiconductor substrate and the second conductive amorphous film. The photoelectric conversion element according to claim 1 or 2. Installing a first mask material on a portion of one surface of a first conductivity type semiconductor substrate;
By removing a part of the semiconductor substrate using the first mask material as a mask, a first groove, a second groove, the first groove, and the second groove are formed on the surface of the semiconductor substrate. Forming a convex portion between the grooves;
Installing a second mask material so that the projection is exposed from between the first groove and the second groove;
Removing a part of the surface of the convex portion using the second mask material as a mask;
Forming a second conductivity type amorphous film in a region other than the first groove, the second groove and the convex portion on the surface of the semiconductor substrate;
Installing a third mask material so as to cover the first groove, the second groove, and the protrusion;
Forming a second conductivity type amorphous film so as to cover the first groove, the second groove and the region other than the convex portion on the surface of the semiconductor substrate and the third mask material;
Removing the third mask material and the second conductive amorphous film on the third mask material;
Installing a fourth mask material on the remaining portion of the second conductive type amorphous film;
Forming a first conductive type amorphous film so as to cover the fourth mask material, the first groove, the second groove, and the convex part;
Removing the fourth mask material and the first conductive type amorphous film on the fourth mask material;
After removing the fourth mask material, a first conductivity type electrode layer covering the entire surface of the first conductivity type amorphous film and a second conductivity type covering the entire surface of the second conductivity type amorphous film. Forming a first electrode layer so that the first conductivity type electrode layer and the second conductivity type electrode layer are electrically insulated from each other.   5. The photoelectric conversion according to claim 4, further comprising forming a second convex portion smaller than the convex portion on the entire surface of the semiconductor substrate before the step of installing the third mask material. Device manufacturing method.

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