JP2014049971A - Piezoelectric oscillator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a piezoelectric oscillator having stable characteristics by reducing the effect of thermal noise on a piezoelectric oscillator while effectively reducing heat of an integrated circuit element.SOLUTION: In a discrete type crystal oscillator in which an oscillation circuit is configured by mounting a crystal oscillator 2, an IC 3 and other electronic components on a circuit board, a mounting pattern including a plurality of pads 5c, 5d for an oscillator, on which the crystal oscillator 2 is mounted, and a plurality of pads for an integrated circuit, on which the integrated circuit element 3 is mounted, is formed on the upper face of the circuit board. An inter-laminated layer pattern GP at a reference potential is arranged in separation between laminated layers of the circuit board. The inter-laminated layer pattern GP includes a first inter-laminated layer pattern GP1 electrically and mechanically connected to a pad 6G for an integrated circuit at a reference potential, and a second inter-laminated layer pattern GP2 electrically and mechanically connected to a pad 5c for an oscillator at a reference potential.

Description

  The present invention relates to a piezoelectric oscillator in which an oscillation circuit is configured by mounting a piezoelectric vibrator and other electronic components on a circuit board, and more particularly to a piezoelectric oscillator whose frequency can be varied by controlling a voltage.

  As an example of a piezoelectric oscillator used for optical transmission equipment, video equipment, etc., there is a crystal oscillator called a discrete type, for example. In the crystal oscillator, an oscillation circuit is configured by mounting a crystal resonator and other electronic components on a laminated substrate in which a plurality of sheets made of an insulating material such as ceramic are laminated.

  In a discrete type crystal oscillator, a crystal resonator and other electronic components generate heat when energized. Among these components, the temperature of an integrated circuit element (IC) is particularly high. Therefore, in order to suppress the influence of the heat of the IC, which becomes a high temperature, on the crystal resonator, it is necessary to mount the crystal resonator as far as possible from the IC in the horizontal direction of the circuit board. However, due to the recent miniaturization of discrete-type crystal oscillators, there are restrictions on the disposition. On the other hand, a method of lowering the temperature of the circuit board by conducting the heat of the IC, which has become high in the vertical direction, to the lower side of the board through vias (Via) formed in the depth direction of the circuit board is conventionally known. (So-called heat sink).

  In order to suppress a reduction in frequency variable width due to the generation of parasitic capacitance in a voltage controlled piezoelectric oscillator, a piezoelectric oscillator including a reference potential wiring surface having a hollow portion in an intermediate layer of a circuit board is disclosed in Patent Document 1. According to the configuration of Patent Document 1, the reference potential wiring surface is formed integrally, and is formed over substantially the entire intermediate layer except for the hollow portion. FIG. 5 shows an example of a conventional crystal oscillator having a configuration in which the reference potential wiring surface is formed over substantially the entire intermediate layer.

  FIG. 5 is a top view of the lower layer of the circuit board (two layers) constituting the crystal oscillator. A dotted line in the figure is a projection display of a part of the mounting pattern formed on the upper surface of the circuit board, and reference numerals 5a to 5d denote vibrator pads on which a crystal vibrator is mounted. The IC is mounted in an area indicated by reference numeral 3. The above-described via is used as the heat conduction means in the depth direction of the circuit board, and the via V1 extending from the lower part of the IC to the lower part of the board and the via V2 extending from a part of the vibrator pad to the lower part of the board are one. It is electromechanically connected to the inter-stack pattern G of one reference potential. In such a configuration, even if the crystal unit is mounted at a position away from the IC, the heat of the IC that has become high temperature is also conducted to the crystal unit via the inter-stack pattern G and the via V2 having the reference potential. . As a result, there has been a problem that the crystal resonator is adversely affected by various heat generation characteristics of the crystal oscillator due to the heat generated by the IC and thermal noise caused by the heat generation.

JP 2001-144539 A

  The present invention has been made in view of the above point, and a piezoelectric oscillator having stable characteristics by effectively reducing the heat of an integrated circuit element and reducing the influence of thermal noise on the piezoelectric vibrator. Is intended to provide.

In order to achieve the above object, the present invention provides a piezoelectric oscillator in which an oscillation circuit is configured by mounting a piezoelectric vibrator, a semiconductor integrated circuit element, and other electronic components on a circuit board.
The circuit board is a multilayer substrate made of an insulator, and a mounting pattern on which a piezoelectric vibrator, a semiconductor integrated circuit element and other electronic components are mounted is formed on the upper surface of the uppermost substrate.
The mounting pattern includes a plurality of vibrator pads on which piezoelectric vibrators are mounted, and a plurality of integrated circuit pads on which semiconductor integrated circuit elements are mounted,
Between at least one of the circuit boards, a reference potential inter-layer pattern is provided separately,
The interlaminate pattern is
A first inter-stack pattern electromechanically connected to a reference potential integrated circuit pad among the plurality of integrated circuit pads;
Of the plurality of vibrator pads, the second laminate pattern is electromechanically connected to the vibrator pad having a reference potential.

  According to the above invention, the inter-stack pattern of the reference potential is provided separately between at least one circuit board stack, and the inter-stack pattern is connected to the reference potential pad among the plurality of integrated circuit pads. It consists of a first inter-stack pattern that is electromechanically connected, and a second inter-stack pattern that is electromechanically connected to a vibrator pad of a reference potential among the plurality of vibrator pads. With such a configuration, it is possible to suppress the heat of the IC that has reached a high temperature from being conducted to the piezoelectric vibrator side. This is because the first inter-layer pattern electromechanically connected to the reference potential integrated circuit pad is separated from the second inter-layer pattern electromechanically connected to the reference potential vibrator pad. This is because the conduction of heat conducted from the IC to the vibrator side can be blocked.

  Further, according to the above-described invention, the path of the current flowing through the IC is cut off by providing the reference potential inter-layer pattern separated between the layers, so that the influence of thermal noise can be reduced. As a result, the influence on the phase noise characteristics can be reduced.

  In order to achieve the above object, the first inter-stack pattern and the second inter-stack pattern are each electromechanically connected to a bottom pattern of a reference potential provided on the bottom surface of the lowermost substrate of the circuit board. May be.

  According to the above invention, in addition to the inter-stack pattern of the reference potential between the stacks, the bottom pattern of the reference potential is also formed on the lower surface of the lowermost substrate of the circuit board. With this configuration, the heat of the IC that has reached a high temperature can be conducted from the inter-stack pattern to the bottom pattern on the bottom surface of the lowermost substrate, for example, via vias that extend in the depth direction of the circuit board. That is, since heat can be dispersed by heat conduction from between the layers to the lower layer of the circuit board, the temperature of the entire circuit board can be easily made uniform. With the above-described configuration, it is possible to suppress the heat of the IC that has reached a high temperature from being conducted to the piezoelectric vibrator side, and it is also possible to suppress the warping of the circuit board due to thermal stress.

  According to the above invention, the electromagnetic shield is provided by arranging the bottom surface pattern on the bottom surface of the lowermost substrate so as to compensate for the region in which the electronic component on the top surface of the circuit board is mounted and does not overlap with the inter-stack pattern in plan view. The effect can be improved.

  In the above invention, the piezoelectric oscillator is mounted on an external substrate such as various electronic devices by arranging the vibrator pad corresponding to the external connection terminal for input / output of the piezoelectric vibrator so as to overlap with the interlaminate pattern in a plan view. Therefore, it is possible to prevent the change in the characteristics of the piezoelectric oscillator. This is due to the following reason.

  Even if the inter-stack pattern is formed in a layer below the input / output vibrator pad, if it is in a positional relationship that does not overlap in a plan view, a pair of vibrations is generated when the piezoelectric oscillator is mounted on an external substrate. When the child pad and the wiring pattern on the external substrate overlap in plan view, stray capacitance is generated.

  On the other hand, with the above-described configuration of the present invention, the pair of vibrator pads and the interlaminate pattern already overlap in a plan view before being mounted on the external substrate. It is possible to suppress an increase in stray capacitance due to overlapping of the pad and the wiring pattern of the external substrate in plan view. As a result, it is possible to prevent changes in the characteristics of the initially set piezoelectric oscillator accompanying an increase in stray capacitance.

  As described above, according to the present invention, a piezoelectric oscillator having stable characteristics can be provided by reducing the influence of thermal noise on the piezoelectric vibrator while effectively reducing the heat of the integrated circuit element. Can do.

The upper surface schematic diagram of the circuit board of the crystal oscillator which concerns on embodiment of this invention Schematic sectional view taken along line AA in FIG. The upper surface schematic diagram of the lower layer of the circuit board which concerns on embodiment of this invention The upper surface schematic diagram of the lower layer of the circuit board which concerns on embodiment of this invention Schematic diagram of the top surface of the circuit board under the conventional crystal oscillator

  Embodiments of the present invention will be described below with reference to the drawings. In the embodiment of the present invention, a discrete type crystal oscillator will be described as an example of a piezoelectric oscillator. The oscillation frequency output from the crystal oscillator in this embodiment is 350 to 800 MHz in fundamental wave oscillation. The oscillation frequency is an example, and the present invention can be applied to frequencies other than the oscillation frequency.

  An embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a schematic top view of a circuit board used in the crystal oscillator according to the first embodiment of the present invention, and shows a state where a plurality of electronic components are not mounted. In FIG. 1, a circuit board 1 is formed by laminating two ceramic green sheets, a lower layer 1a and an upper layer 1b (see FIG. 2), and is integrally formed by firing. In FIG. 1, the circuit board 1 has a substantially rectangular shape in plan view, and its outer dimensions are 7.0 mm × 5.0 mm. In addition, you may use glass epoxy resin as a base material of a circuit board other than a ceramic.

  A predetermined mounting pattern made of a metal conductor is formed on the upper surface 100 of the circuit board 1, and the crystal resonator 2, the integrated circuit element 3 (IC), and other electronic components (frequency adjusting member and voltage) are formed on the mounting pattern. An oscillation circuit is configured by mounting a coil, a capacitor, a resistor, a varicap diode, and the like constituting the control member. In this embodiment, gold (Au) is used for the mounting pattern. In FIG. 1, among the mounting patterns, four vibrator pads (5a to 5d) on which crystal vibrators are mounted and a pair of vibrator input / output terminals (4a, 4b) connected to the vibrator pads. ) And patterns other than the eight IC mounting pads (6) on which the IC is mounted are not shown. The approximate position where the crystal resonator 2 and the integrated circuit element 3 are mounted and the approximate position of the mounting pattern 4 in the area where other electronic components are mounted are indicated by dotted lines.

  In FIG. 1, among the eight IC mounting pads (6), the integrated circuit pad of the reference potential is indicated by reference numeral 6G. From the integrated circuit pad 6G of this reference potential, it is led out to a region sandwiched between other integrated circuit pad groups arranged on two opposite sides. In the portion led out to the region, four via groups V1 extending below the substrate of the upper layer 1b are formed and are electromechanically connected to a first inter-stack pattern GP1 described later. Here, the via group V1 has a structure in which a metal (copper in this embodiment) is filled in a substantially cylindrical through-hole penetrating the substrate of the upper layer 1b, and other vias V2 to V4 described later are also the same. It consists of the structure and material. The shape of the via is not limited to a substantially cylindrical shape, and may be a substantially conical shape, for example, or may be a shape other than a circle in plan view. Further, in this embodiment, the number of via groups is four as an example, and the number of vias is not limited to the number in the application of the present invention. Moreover, about the metal with which the inside of the said through-hole is filled, you may use a metal with favorable thermal conductivity other than copper.

  In FIG. 1, four vibrator pads 5a, 5b, 5c, and 5d are formed in the area on the upper surface 100 of the circuit board 1 where the crystal vibrator is mounted. These four vibrator pads are arranged in a rectangular shape in plan view on the circuit board upper surface 100 so as to correspond to the four external terminals on the bottom face of the crystal vibrator. The four vibrator pads 5a, 5b, 5c, and 5d are formed simultaneously with other mounting patterns on the circuit board upper surface 100, and are laminated in the order of tungsten, nickel plating, and gold plating from the circuit board side.

  Of the four transducer pads 5a to 5d, the pair of transducer pads 5a and 5b are arranged adjacent to one short side of a rectangle formed by using the transducer pads 5a to 5d as four corners. Has been. The adjacent pair of vibrator pads 5a and 5b is electrically connected to the excitation electrode formed on the crystal vibrating piece inside the crystal vibrator. The pair of vibrator pads 5a and 5b are connected to the pair of vibrator input / output terminals 4a and 4b via wirings DP1 and DP2, respectively. Here, the pair of vibrator input / output terminals 4a and 4b are part of a mounting pattern constituting an oscillation stage for exciting the crystal oscillator, and are connected to the crystal oscillator in series. One terminal of the input / output with respect to the (varicap diode) (in this embodiment, 4a is an output terminal, 4b is an input terminal). In the present embodiment, coils are mounted on the vibrator input / output terminals 4a and 4b, and are connected in series to the varicap diode. The electronic component mounted on the vibrator input / output terminal may be not only a coil but also a capacitor, a varicap diode, or the like.

  According to the above configuration, the pair of adjacent vibrator pads 5a and 5b are electrically connected to the excitation electrode formed on the crystal vibrating piece and are adjacent to the pair of vibrator input / output terminals 4a and 4b. Therefore, it is not necessary to route the wiring to the transducer pad far from the transducer input / output terminals 4a and 4b as in the prior art. As a result, the generation of stray capacitance due to the routing wiring can be suppressed. As a result, it is possible to suppress a decrease in the negative resistance value and prevent a decrease in the frequency variable amount.

  The pair of transducer pads 5c and 5d are arranged adjacent to the other short side of the rectangle and serve as reference potential transducer pads. The vibrator pad 5c is formed with a via V2 extending below the circuit board.

  Between the laminations of the circuit board 1 (boundary between the upper layer 1b and the lower layer 1a), an interlaminar pattern GP (hereinafter abbreviated as an interlaminar pattern) made of metal is formed (see FIG. 2). The inter-stack pattern GP of the reference potential is composed of the first inter-stack pattern GP1 and the second inter-stack pattern GP2, and is formed in a state of being separated from each other in one stack. Specifically, the inter-stack pattern GP of the reference potential is arranged at the position and size shown in FIG. 3 in plan view. That is, the first inter-stack pattern GP1 includes the via group V1 in a plan view and is smaller than the size of the IC in a plan view. By forming the first inter-stack pattern GP1 with such a size, diffusion of heat of the IC in the horizontal direction of the substrate can be suppressed.

  On the other hand, a bottom surface pattern (hereinafter abbreviated as a bottom surface pattern) 8 having a reference potential is formed on the lower surface 110 of the lower layer 1a (the bottom surface of the circuit board). In the embodiment of the present invention, the inter-stack pattern GP and the bottom surface pattern 8 are both formed of copper, but a metal other than copper can also be used.

  Three via groups V4 are formed on the base material of the lower layer 1a between the first inter-stack pattern GP1 and the bottom pattern 8. Further, four via groups V3 are also formed on the base material of the lower layer 1a between the second inter-stack pattern GP2 and the bottom pattern 8. In the drawings according to the embodiments of the present invention, for convenience of explanation, some of the plurality of vias formed are omitted.

  In the embodiment of the present invention, each via constituting the via group V3 has a one-to-one correspondence with each via constituting the via group V1 and is formed with substantially the same diameter. It is in a state aligned with. With such a configuration of the via and the inter-stack pattern, it is possible to suppress the heat of the IC that has reached a high temperature from being conducted to the crystal resonator side. This is because the first inter-stack pattern GP1 electromechanically connected to the reference potential integrated circuit pad 6G via the via group V1 is electromechanically connected to the reference potential vibrator pad 5c and the via V2. This is because the conduction to the vibrator side of the heat conducted from the IC can be blocked by separating from the connected second inter-stack pattern GP2.

  Further, in the present embodiment, a bottom pattern 8 having a reference potential is also formed on the lower surface of the lower layer 1a, and each of the via groups V3 and V4 is electromechanically connected to the bottom pattern 8. With such a structure, the heat of the IC having a high temperature can be conducted to the bottom surface pattern 8 via the route of the via group V1 → the inter-stack pattern GP1 → the via group V3. Since the heat conducted to the bottom pattern 8 is conducted to the via group V4 side, the heat can be dispersed from between the layers to the lower layer of the circuit board, and the temperature of the entire circuit board can be easily made uniform. As a result, it is possible to suppress the heat of the IC that has reached a high temperature from being conducted to the crystal resonator side, and it is also possible to suppress warping of the circuit board due to thermal stress. As described above, each via constituting the via group V3 and each via constituting the via group V1 are aligned in a substantially straight line in a cross-sectional view. The path of the direction becomes substantially the same straight line in a sectional view, and the influence on the signal by the stub can be reduced. This is particularly effective when the oscillation frequency is increased.

  According to the present invention, since the inter-stack pattern GP having the reference potential is provided in a state where it is separated between the stacks, the path of the current flowing through the IC is divided, so that the influence of thermal noise can be reduced. As a result, the influence on the phase noise characteristics can be reduced.

  As shown in FIG. 3, the second inter-stack pattern GP2 has a substantially trapezoidal shape in plan view, and is electromechanically connected to the via V2, the via group V4, and other vias (not shown). The planar view shape of the second inter-stack pattern GP2 is a shape for avoiding interference with a power line (not shown). Therefore, the plan view shape of the second inter-stack pattern may be different from the plan view shape of FIG. 3 according to the arrangement of the power supply lines.

  In FIG. 3, the second inter-stack pattern GP2 includes a part of the mounting pattern 4 in a region where other electronic components are mounted, the whole vibrator pads 5a and 5b, and a part of the vibrator pads 5c and 5d. It is in the state where it overlapped visually. That is, since the second inter-stack pattern GP2 is formed with an area including a part of the plurality of electronic components mounted on the upper surface of the substrate of the upper layer 1b in a plan view, an electromagnetic shielding effect can be obtained.

  In the embodiment of the present invention, as shown in FIG. 4, a bottom surface pattern 8 having a reference potential is formed on the lower surface of the lower layer 1a in an alphabetic “L” shape in plan view. Six functional terminals 7a to 7f (terminals that are conductively joined to an external substrate) are formed on the lower surface 110 of the lower layer 1a, and a part of the bottom surface pattern 8 also serves as a grounding terminal 7f. In the present embodiment, an insulating protective film (not shown) is formed in a region excluding the six functional terminals 7a to 7f on the substrate lower surface 110 of the lower layer 1a. The insulating protective film is made of an insulating resin material (resist) and plays a role of protecting the surface of the bottom pattern 8 made of metal from the external environment. In addition, the structure which does not form the said insulating protective film in the board | substrate lower surface 100 of the lower layer 1a may be sufficient.

  In addition, the electromagnetic shielding effect can be improved by arranging the bottom surface pattern so as to compensate for the region where the electronic component on the top surface of the circuit board is mounted and does not overlap with the inter-stack pattern GP in plan view.

  In the present embodiment, as shown in FIG. 4, the vibrator pad 5c having the reference potential is arranged so as to overlap the power supply terminal 7a on the lower surface of the substrate of the lower layer 1a in a plan view. With such an arrangement, noise included in the input current from the power supply terminal 7a can be reduced. Further, a part of the power supply terminal 7a overlaps with the second inter-stack pattern GP2 in a plan view, and an area where the vibrator pad 5c does not overlap with the power supply terminal 7a in a plan view is also the second inter-stack pattern GP2. A part of the cover is covered, and the above-described noise reduction effect can be improved.

  In the present embodiment, since the pair of vibrator pads 5a and 5b electrically connected to the excitation electrodes of the crystal vibrator overlap with the second inter-stack pattern GP2 and the bottom surface pattern 8 in plan view, the crystal It is possible to prevent a change in characteristics of the crystal oscillator after the oscillator is mounted on an external substrate of various electronic devices. This is because the vibrator pads 5a and 5b, the second inter-stack pattern GP2, and the bottom surface pattern 8 already overlap each other in plan view in the crystal oscillator.

  That is, when the vibrator pads 5a and 5b are in a positional relationship that does not overlap with the second inter-stack pattern GP2 and the bottom surface pattern 8 in plan view, the vibrator pads 5a and 5b are mounted when the crystal oscillator is mounted on the external substrate. When the wiring pattern on the external substrate and the wiring pattern overlap in plan view, stray capacitance is generated.

  On the other hand, in the above configuration, the vibrator pads 5a and 5b are already overlapped with the second inter-stack pattern GP2 and the bottom surface pattern 8 in a plan view before being mounted on the external substrate. It is possible to suppress an increase in stray capacitance due to overlapping of the pad for use and the wiring pattern in plan view. As a result, it is possible to prevent a change in the characteristics of the initially set crystal oscillator accompanying an increase in stray capacitance.

  In the present embodiment, a bottom pattern is formed in addition to the inter-stack pattern, but the present invention is applicable to a configuration in which only the inter-stack pattern is formed and the bottom pattern is not formed. In the present embodiment, a two-layer configuration is taken as an example of a multilayer circuit board, but the circuit board may be configured of three or more layers.

  The present invention can be implemented in various other forms without departing from the spirit or main features thereof. Therefore, the above-described embodiment is merely an example in all respects and should not be interpreted in a limited manner. The scope of the present invention is indicated by the claims, and is not restricted by the text of the specification. Further, all modifications and changes belonging to the equivalent scope of the claims are within the scope of the present invention.

  It can be applied to mass production of piezoelectric oscillators.

DESCRIPTION OF SYMBOLS 1 Circuit board 1a Lower layer board 1b Upper layer board 2 Crystal oscillator 3 Integrated circuit element 4a, 4b vibrator input / output terminal 5a-5d vibrator pad 6 integrated circuit pad 6G integrated circuit pad (reference potential)
7a-7f External connection terminal GP Inter-stack pattern GP1 First inter-stack pattern GP2 Second inter-stack pattern 8 Bottom pattern V1 Via V2-V4 Via group

Claims (2)

In a piezoelectric oscillator in which an oscillation circuit is configured by mounting a piezoelectric vibrator, a semiconductor integrated circuit element, and other electronic components on a circuit board,
The circuit board is a multilayer substrate made of an insulator, and a mounting pattern on which a piezoelectric vibrator, a semiconductor integrated circuit element and other electronic components are mounted is formed on the upper surface of the uppermost substrate.
The mounting pattern includes a plurality of vibrator pads on which piezoelectric vibrators are mounted, and a plurality of integrated circuit pads on which semiconductor integrated circuit elements are mounted,
Between at least one of the circuit boards, a reference potential inter-layer pattern is provided separately,
The interlaminate pattern is
A first inter-stack pattern electromechanically connected to a reference potential integrated circuit pad among the plurality of integrated circuit pads;
A piezoelectric oscillator comprising: a second inter-stack pattern electromechanically connected to a reference potential vibrator pad among the plurality of vibrator pads.   The first interlaminar pattern and the second interlaminar pattern are each electromechanically connected to a bottom pattern of a reference potential provided on the lower surface of the lowermost substrate of the circuit board. Item 2. The piezoelectric oscillator according to Item 1.

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