JP2014049843A - Multipoint-simultaneous high speed analog/digital conversion device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multipoint-simultaneous high speed analog/digital conversion device that simultaneously converts a plurality of analog input signals to digital signals in a simple circuit configuration.SOLUTION: The multipoint-simultaneous high speed analog/digital conversion device includes a plurality of analog/digital conversion sections for converting a plurality of analog input signals to digital output signals, and a control circuit (3) for comprehensively controlling the analog/digital conversion sections. The analog/digital conversion sections include a basic block and an additional block. The basic block has a comparison signal generator (1) for outputting a comparison signal repeating a monotonic increase or monotonic decrease, and a clock generator (2). The basic block and the additional block each have a comparator (4) for comparing the analog input signal with the comparison signal, and a counter (5). The control circuit controls the comparison signal generator such that the period of generating the digital output signals falls on a changeless period in which the comparison signal does not monotonically increase or monotonically decrease.

Description

  The present invention relates to a multipoint simultaneous high-speed analog / digital conversion device for simultaneously converting a plurality of analog input signals into digital signals with a simple circuit configuration.

  With the recent improvement in performance of information processing apparatuses, more information can be processed at higher speed. However, the increase in the speed of analog devices has not sufficiently followed the rapid increase in the speed of digital devices, and the analog portion including the analog / digital conversion (hereinafter referred to as A / D conversion) device is the bottle of the entire system. Often becomes a bottleneck. Therefore, it is expected to realize an analog device that can be applied to a high-speed digital device.

  In the successive approximation type, which is one of the conventional A / D conversion methods, the analog input signal to be converted and the comparison signal obtained by analog conversion of the digital value to be compared are compared bit by bit from the most significant digit, and the lowest order A method of calculating an A / D conversion value by repeating up to a digit is adopted.

  In addition, in the tilt type and follow-up type, which are other A / D conversion methods, an analog input signal to be converted (hereinafter abbreviated as an analog input signal) and a triangular wave with a constant period to be compared (hereinafter referred to as a comparison signal) And an A / D conversion value is calculated by counting a reference clock (hereinafter abbreviated as a clock) in a section where the output signal of the comparator is H level or L level. Yes.

  Further, when a plurality of analog input signals are converted simultaneously by a single A / D converter, a changeover switch is provided in front of the A / D converter and a plurality of analog input signals are A / D converted in a time division manner. Has been taken.

JP 2010-153981 A

However, the prior art has the following problems.
In a conventional A / D converter, when a circuit is simply parallelized in order to simultaneously convert a plurality of analog input signals, a digital / analog converter (hereinafter abbreviated as a comparison signal generator) that outputs a comparison signal is provided. The same number as the number of analog input signals is required. Therefore, there is a problem that the circuit is complicated and expensive.

  In addition, in order to convert a plurality of analog input signals, a signal changeover switch is provided in front of the A / D converter without parallelizing the circuits, and the plurality of analog input signals are time-division processed by one A / D conversion. Even in this case, there is a problem in that conversion cannot be performed at the same time because a shift occurs in the conversion timing of each analog input signal.

  Further, in the conventional tilt type and follow-up type, there is a problem that the clock count value reading process and the reset process are not completed from the completion of the clock count to the next count start. This is because when the analog input signal is close to the upper limit or lower limit of the triangular wave of the comparison signal, the time from the completion of falling of the comparison signal to the start of rising is short, so the time margin required for processing cannot be secured. Is the cause.

  Conventionally, this problem has been addressed by increasing the monotonically increasing amount of the comparison signal per clock (hereinafter abbreviated as a slope) in order to provide a margin for the upper limit value of the comparison signal.

However, when the digital / analog conversion resolution (hereinafter abbreviated as D / A conversion resolution) of the comparison signal generator is x (bit) and the time from the start of the triangular wave comparison signal to the completion of the fall is Ts, The required minimum frequency Fp of the clock expressed by the following equation (1) is proportional to the slope of the comparison signal when the resolution of the comparison signal (hereinafter abbreviated as signal resolution) is constant.
Fp = 2 ^x / Ts (1)

  Therefore, in order to increase the slope of the comparison signal while maintaining the signal resolution of the comparison signal, the necessary minimum frequency Fp of the clock must be increased. That is, there has been a problem that a comparison signal generator having a higher D / A conversion resolution must be used.

  The present invention has been made to solve the above-described problems, and provides a multi-point simultaneous high-speed analog / digital conversion apparatus capable of simultaneously converting a plurality of analog input signals into digital signals with a simple circuit configuration. For the purpose.

  A multi-point simultaneous high-speed analog / digital conversion device according to the present invention includes a plurality of analog / digital conversion units that individually output a plurality of clock count values corresponding to respective sizes of a plurality of analog input signals, and a plurality of analogs The digital control unit controls the digital output signal corresponding to each of the plurality of analog input signals based on a plurality of clock count values read from each of the plurality of analog / digital conversion units at regular intervals. A plurality of analog / digital converters, a basic block for digitally converting the first analog input signal of the plurality of analog input signals, and a plurality of analog For digital conversion processing of analog input signals other than the first analog input signal A comparison signal consisting of additional blocks individually provided for each force signal. The basic block repeats monotonically increasing or decreasing monotonically at regular intervals in order to specify the size of the analog input signal to be converted into digital data. The comparison of the magnitude relationship between the comparison signal generator that outputs the clock, the clock generator that generates the clock, the comparison signal output by the comparison signal generator, and the first analog input signal is performed. A comparator that outputs an L level signal when it is equal to or higher than the comparison signal, and outputs an H level signal when the first analog input signal is less than the comparison signal, and the output of the comparator is H level or L level. And a counter that counts the clock generated by the clock generator and outputs a clock count value corresponding to the first analog input signal. Each of the blocks compares the size of the comparison signal output from the comparison signal generator in the basic block with one analog input signal other than the first analog input signal, and the digital conversion target 1 A comparator that outputs an L level signal when one analog input signal is equal to or greater than a comparison signal, and outputs an H level signal when one analog input signal to be digitally converted is less than the comparison signal; A counter that counts clocks generated by a clock generator in a basic block and outputs a clock count value corresponding to one analog input signal to be digitally converted in a period when the output of The control circuit reads out a plurality of clock count values from a plurality of analog / digital converters and rotates a plurality of digital output signals at a constant frequency. The control signal is monotonically increased during the period in which the control circuit simultaneously generates multiple digital output signals at fixed intervals, while controlling the counters in multiple analog / digital converters so that they are generated simultaneously for each period. Alternatively, the comparison signal generator in the basic block is controlled so that there is no change period without monotonously decreasing.

  According to the multipoint simultaneous high-speed analog / digital conversion apparatus of the present invention, in the conventional A / D conversion apparatus, only one comparison signal generator is used to simultaneously A / D convert a plurality of analog input signals. The reference clock to be used by providing a non-change period for securing the time margin required for the clock count value reading process and the reset process from the start of falling of the comparison signal to the completion of rising. A simple circuit configuration that allows multiple analog input signals to be simultaneously processed without increasing the frequency of the analog signal to be greater than the product of the D / A conversion resolution of the comparison signal generator and the reciprocal of the time from the start to the end of the comparison signal. Thus, it is possible to obtain a multipoint simultaneous high-speed analog / digital conversion device that converts into a digital signal.

It is an illustration figure for demonstrating the basic operation | movement principle of an inclination type and a follow-up type A / D conversion system. It is an illustration figure which demonstrates operation | movement of the basic block of the multipoint simultaneous high-speed analog / digital converter in Embodiment 1 of this invention. FIG. 3 is a timing chart in the circuit of FIG. 2. It is an illustration figure which demonstrates the operation | movement of the whole multipoint simultaneous high-speed analog / digital conversion apparatus in Embodiment 1 of this invention. It is an illustration figure which shows a waveform when the inclination of the comparison signal in Embodiment 2 of this invention is changed. FIG. 5B is an exemplary diagram illustrating a relationship between a comparison signal and a clock in FIG. 5A. FIG. 5B is an exemplary diagram illustrating an operation when the inclination of the comparison signal is changed in FIG. 5B. It is an illustration figure which demonstrates the change of a waveform when the inclination of a comparison signal in Embodiment 2 of this invention is changed 3 steps within 1 period. It is an illustration figure explaining operation | movement when the low-pass filter is provided in Embodiment 3 of this invention. FIG. 8 is an exemplary diagram illustrating a change in a waveform of a comparison signal in the circuit of FIG. 7.

  Hereinafter, preferred embodiments of a multipoint simultaneous high-speed analog / digital conversion device according to the present invention will be described with reference to the drawings.

Embodiment 1 FIG.
FIG. 1 is an exemplary diagram for explaining the basic operation principle of the inclined type and follow-up type A / D conversion method. First, the basic operation principle of the tilt type and follow-up type A / D conversion system used in the multipoint simultaneous high speed analog / digital conversion apparatus of the present invention will be briefly described with reference to FIG.

In FIG. 1, the A / D conversion value V of the analog input signal to be obtained by the A / D converter is indicated by the height of the intersection of the analog input signal and the comparison signal. The height of this intersection is proportional to the time Tk from the start of rising of the triangular wave to the intersection, and this proportionality constant is the slope S of the comparison signal. Therefore, the A / D conversion value V of the analog input signal can be calculated as in the following equation (2).
V = S × Tk (2)

In the above description, the method of measuring the time Tk from the start of rising of the triangular wave to the intersection (tilt type) is used. Instead, the method of measuring the time Tt from the intersection of the triangular wave to the completion of falling (following type) is used. It can also be used. In this case, if the time from the start of rising to the completion of falling is Ts, Tt can be calculated as in the following equation (3).
Tt = Ts−Tk (3)

The above is the basic operation principle of the tilt type and follow-up type A / D conversion method. In the description of the first embodiment of the present invention, a follow-up A / D conversion method is assumed, but the basic idea is the same as that of the tilt type. For example, the A / D conversion value V of the analog input signal to be calculated can be calculated as in the following equation (4) using the relationship in the above equation (3).
V = S × (Ts−Tt) (4)

  From here, the operation | movement of each component in Embodiment 1 of this invention is demonstrated. In addition, the same code | symbol is attached | subjected and demonstrated about the part which is the same or it corresponds in each figure.

  FIG. 2 is an exemplary diagram for explaining the operation of the basic block of the multipoint simultaneous high-speed analog / digital conversion device in Embodiment 1 of the present invention. The basic block shown in FIG. 2 includes a comparison signal generator 1, a clock generator 2, a control circuit 3, a comparator 4, and a counter 5. With such a basic block configuration, the basic block of FIG. 2 can A / D convert one analog input signal 105.

  Hereinafter, the operation of the basic block will be described with reference to FIGS. FIG. 3 is a timing chart in the circuit of FIG. The comparison signal generator 1 outputs, as the comparison signal 101, a triangular wave having a constant cycle in which the rising edge monotonously increases at a constant monotonically increasing amount every clock and the falling edge changes vertically. At this time, the inclination (monotonically increasing amount per clock) and the upper limit value of the comparison signal 101 are controlled by the control signal 104 output from the control circuit 3.

  The comparison signal generator 1 starts outputting the comparison signal 101 at the timing when the control circuit 3 outputs the reset signal 103 (more precisely, the timing when the control circuit 3 changes from H level to L level). Therefore, not only the inclination of the comparison signal 101 but also the timing at which the comparison signal generator 1 starts outputting the comparison signal 101 is controlled by the control circuit 3.

  The comparator 4 compares the size of the comparison signal 101 and the analog input signal 105. When the analog input signal 105 is equal to or higher than the comparison signal 101, the comparator 4 outputs an L level signal, and when the analog input signal 105 is lower than the comparison signal 101. Outputs an H level signal as the comparator output signal 106.

  The counter 5 counts the period during which the comparator output signal 106 is maintained at the H level, using the clock 102 output from the clock generator 2, and outputs it as the clock count value 107. At this time, the counting start timing of the counter 5 is controlled by the reset signal 103 output from the control circuit 3.

  The control circuit 3 reads the clock count value 107 during the non-change period of the comparison signal 101 and calculates an A / D conversion value. Here, the non-change period is a period during which the comparison signal generator 1 continues to output the comparison signal 101 whose change amount per clock is 0 after the completion of the fall of the comparison signal 101.

  The A / D conversion value of the analog input signal 105 for one cycle is obtained by the above procedure. Thereafter, the control circuit 3 outputs a reset signal 103 to the comparison signal generator 1 and the counter 5 in order to start A / D conversion in the next cycle. The comparison signal generator 1 starts outputting the comparison signal 101 in the next period, and the counter 5 starts counting in the next period.

  By repeating the above procedure, the control circuit 3 can obtain the A / D conversion value of the analog input signal 105 in the period of the comparison signal 101.

  In the above description, the operation in the case of A / D converting one analog input signal 105 has been described. From here, the case in which a plurality of analog input signals 105 which are the subject of the present application are simultaneously A / D converted will be described. To do.

  FIG. 4 is an exemplary diagram for explaining the overall operation of the multipoint simultaneous high-speed analog / digital conversion apparatus according to Embodiment 1 of the present invention. FIG. 4 includes three blocks, A, B, and C, and each block A / D converts the analog input signals 105a, 105b, and 105c.

  A block A in FIG. 4 corresponds to the basic block in FIG. 2 and performs A / D conversion on the first analog input signal 105a among the plurality of analog input signals 105a, 105b, and 105c. Blocks B and C are additional blocks, and A / D convert the second analog input signal 105b and the third analog input signal 105c. These additional blocks B and C include one comparator 4b and 4c and one counter 5b and 5c, respectively, and share the comparison signal generator 1, clock generator 2, and control circuit 3 with the block A. Yes.

  Each of the blocks A, B, and C performs A / D conversion on one analog input signal 105 in parallel. Therefore, the configuration circuit of FIG. 4 can simultaneously A / D convert three analog input signals 105a, 105b, and 105c in total.

  In the configuration circuit of FIG. 4, the comparison signal generator 1, the clock generator 2, and the control circuit 3 are shared by the three blocks A to C as compared with the conventional circuit simply parallelized. There is a feature in that. That is, the configuration circuit of FIG. 4 has a simple circuit configuration in which the comparison signal generator 1 that outputs the comparison signal 101 shared by each block is centrally controlled by the control circuit 3.

  Thus, if the circuits are simply parallelized in order to simultaneously convert a plurality of analog input signals 105, the number of comparison signal generators 1 is required to be the same as the number of analog input signals 105, and the circuit is complicated and expensive. The problem is solved.

  Further, as described above, since the non-change period is provided after the completion of the falling edge of the comparison signal 101 generated by the comparison signal generator 1, the control circuit 3 has a plurality of analog input signals 105 a, 105 b, 105 c. It is possible to read the clock count value 107 corresponding to the above and output the reset signal 103 during this non-change period.

  This solves the problem that the time from the completion of the falling edge of the comparison signal 101 to the start of the rising edge, which is a problem in the conventional inclined type and the following type, is short, so that the time margin required for the processing cannot be secured.

  At the same time, the problem that the required minimum frequency of the clock must be increased in order to increase the slope of the comparison signal 101, which has been a conventional problem, is also solved. Therefore, the necessary minimum frequency of the clock does not need to be larger than the above formula (1).

  As described above, according to the first embodiment, in the conventional A / D converter, in order to simultaneously A / D convert a plurality of analog input signals, only one comparison signal generator is used in parallel. Furthermore, the frequency of the reference clock to be used is set by providing a non-change period for securing a time margin necessary for the read processing and reset processing of the clock count value from the start of falling of the comparison signal to the completion of rising. Multiple analog input signals can be converted into digital signals simultaneously with a simple circuit configuration without increasing the D / A conversion resolution of the comparison signal generator and the product of the reciprocal of the time from the start to the end of the comparison signal. A multipoint simultaneous high-speed analog / digital conversion device for conversion can be obtained.

  Further, since the falling edge of the comparison signal 101 is changed vertically, there is no error in one step of this stair compared with the case where the falling changes in a staircase pattern with a slope. It is possible to operate with higher accuracy and higher speed.

  In the above description, it is assumed that a follow-up A / D conversion method is used. However, the present invention is not limited to this method. For example, the basic idea is the same as in the case of the inclined type even when the inclined type method is used. The A / D conversion value of the analog input signal 105 can be calculated as S × Tk.

  In the above description, the H level is output when the comparison signal 101 is equal to or higher than the analog input signal 105, and the L level is output when the comparison signal 101 is lower than the analog input signal 105. However, the present invention is not limited to this combination. For example, the same effect can be obtained even if the comparator output signal 106 and the level counted by the counter 5 are simultaneously reversed.

  In the above description, the analog input signals 105 to be converted are assumed to be three of 105a, 105b, and 105c. However, in the present invention, the same effect can be obtained even when the number of analog input signals 105 is two, or four or more.

  In the above description, the comparison signal generator 1 outputs a triangular wave with a constant cycle in which the rising edge monotonously increases with a constant monotonically increasing amount every clock and the falling edge changes vertically. The present invention is not limited to this combination. For example, the same effect can be obtained by outputting a triangular wave in which the falling edge monotonously decreases at a constant monotonic decreasing amount every clock and the rising edge changes vertically.

Embodiment 2. FIG.
In the first embodiment, the method of providing the non-change period after the falling edge of the comparison signal 101 has been described. However, if a non-change period is provided, A / D conversion is delayed by this period. Therefore, in the second embodiment, the area of the analog input signal 105 is divided into a plurality of areas in accordance with the required signal resolution, and the inclination of the comparison signal 101 is individually set for each of the plurality of areas. By combining this method with the first embodiment described above, the case where the delay is improved and the A / D conversion speed is increased will be described.

  The configuration of the multipoint simultaneous high-speed analog / digital conversion apparatus in the second embodiment is the same as that in the first embodiment.

  First, consider changing the slope of the comparison signal 101 output from the comparison signal generator 1 in order to perform A / D conversion at high speed. FIG. 5a is an exemplary diagram showing a waveform when the slope of the comparison signal 101 is changed in the second embodiment of the present invention. The slope after the change (corresponding to the comparison signal 101 shown in FIG. 3) is four times that before the change.

  FIG. 5B is an exemplary diagram showing a relationship between the comparison signal 101 and the clock 102 in FIG. 5A. In FIG. 5b, the slope of the comparison signal 101 is 1 (digit / clock).

  On the other hand, FIG. 5c is an exemplary diagram for explaining the operation when the inclination of the comparison signal 101 of FIG. 5b is changed four times. Before the change, the slope of the comparison signal 101 was 1 (digit / clock), but after the change, it was 4 (digit / clock). That is, by increasing the slope by a factor of 4, the signal resolution is reduced by a factor of 4, but the A / D conversion speed is improved by a factor of 4 if the non-change period is ignored.

  As described above, when the D / A conversion resolution of the comparison signal generator 1 is constant, if the slope is increased by n times, the signal resolution decreases by n times, but the A / D conversion speed is ignored for the unchanged period. N times.

  Therefore, by utilizing this relationship, the slope of the comparison signal 101 is optimized according to the required signal resolution, so that the desired signal resolution can be achieved and the A / D conversion can be speeded up. Is possible. Furthermore, by increasing the speed in this way, it is possible to cover a delay corresponding to a non-change period.

  For example, when high signal resolution is required, the slope of the comparison signal 101 may be set to 1 (digit / clock) as shown in FIG. 5b. In this way, A / D conversion can be optimized at high speed while achieving a desired signal resolution.

  On the other hand, when the required signal resolution may be four times lower, the slope of the comparison signal 101 may be 4 (digits / clock) as shown in FIG. In this way, after achieving the desired signal resolution, the A / D conversion speed can be ignored for the unchanged period compared to the case where the slope is 1 (digit / clock) as shown in FIG. 5b. The speed can be increased 4 times.

  In the above description, the slope of the comparison signal 101 is constant within one period, but from here on, the area of the analog input signal 105, which is the subject of the present application, is divided into a plurality of areas depending on the required signal resolution. Consider dividing into regions and individually setting the slope of the comparison signal 101 in each region.

  FIG. 6 shows the relationship between the comparison signal 101 and the analog input signal 105 when the slope of the comparison signal 101 is changed in three steps within one period in the second embodiment of the present invention.

  In FIG. 6, the inclination of the comparison signal 101 is changed in three steps within one cycle. Here, when the analog input signal 105 is 0 to V1, V1 to V2, and V2 to Vmax, the slopes of the comparison signal 101 in each region are set to S1, S2, and S3, respectively.

  Even in this case, the idea in the case of one inclination can be applied as it is. That is, in each divided area, the inclination of the comparison signal 101 may be individually optimized according to the required signal resolution.

  For example, in FIG. 6, the required signal resolution of the comparison signal 101 is 2, 1, and 4 times in each region where the value of the analog input signal 105 is divided as 0 to V1, V1 to V2, and V2 to Vmax. It may be low. In this case, the slope of the comparison signal 101 in each region is individually set to 2, 1, 4 (digit / clock), respectively, to achieve a desired signal resolution, and the slope of all regions is 1. In comparison, A / D conversion can be speeded up.

Similarly, for the calculation of the A / D conversion value V of the analog input signal 105, the idea in the case of one slope can be applied as it is. For example, in FIG. 6, assuming that the clock count values 107 in the regions where the slope of the comparison signal 101 is S1, S2, and S3 are Tk1, Tk2, and Tk3, respectively, the A / D conversion value V is expressed by the following equation (5). It can be calculated as follows.
V = S1 * Tk1 + S2 * Tk2 + S3 * Tk3 (5)

  As described above, according to the second embodiment, the area of the analog input signal is divided into a plurality of areas according to the required signal resolution, and the inclination of the comparison signal 101 is set for each of the plurality of areas. By combining the method of individual setting with the previous embodiment 1, the desired signal resolution can be achieved, A / D conversion can be speeded up, and the delay for the unchanged period can be covered. It becomes.

  In the above description, the inclination of the comparison signal 101 within one period is divided into three areas and individually set. However, the present invention is not limited to this number of regions, and the same effect can be obtained even when the number of regions is two, or four or more.

  Further, when the frequency of the clock 102 is determined from the restriction of Ts, if there is a margin in the clock frequency, even if the frequency of the clock 102 is increased even if the slope is steep, A / D conversion can be performed without reducing the resolution.

Embodiment 3 FIG.
In the first and second embodiments, it is assumed that the comparison signal 101 has sufficient signal resolution and changes at least 1 (digit) every clock. On the other hand, in the third embodiment, even when the D / A conversion resolution of the comparison signal generator 1 is low and the waveform of the comparison signal 101 monotonously increases while maintaining a constant value for each of a plurality of clocks, Consider a method of improving the waveform of the comparison signal 101 to an analog comparison signal that gradually changes with each clock by providing the low-pass filter 6 in the subsequent stage of the comparison signal generator 1.

  FIG. 7 is an exemplary diagram for explaining the operation when the low-pass filter 6 is provided in the basic block of FIG. 2 in Embodiment 3 of the present invention. In FIG. 7, a low-pass filter 6 is further provided after the comparison signal generator 1 of FIG.

  FIG. 8 is an exemplary diagram for explaining a change in the waveform of the comparison signal 101 in the circuit of FIG. The comparison signals 101c and 101d are those before the low-pass filter 6 is provided. Each of the comparison signals 101c and 101d has a waveform having a sufficient signal resolution that changes by 1 (digit) every clock and a signal resolution that changes by 4 (digit) every 4 clocks. A low waveform is shown.

  From FIG. 8, even when the signal resolution is four times lower, such as the comparison signal 101d, the comparison signal 101e is gradually changed by the low-pass filter 6 and is close to the comparison signal 101c. It can be seen that the waveform is improved. That is, an equivalent result can be obtained by combining the low-D / A conversion resolution comparison signal generator 1 and the low-pass filter 6 instead of using the expensive high-D / A conversion resolution comparison signal generator 1.

  As described above, according to the third embodiment, even when the D / A conversion resolution of the comparison signal generator 1 is low and the waveform of the comparison signal 101 monotonously increases while maintaining a constant value for each of a plurality of clocks. By providing the low-pass filter 6 in the subsequent stage of the comparison signal generator 1, it is possible to obtain a multipoint simultaneous high-speed analog / digital conversion device that improves the waveform of the comparison signal 101 to an analog comparison signal that gradually changes with each clock. it can.

  In this case, the falling edge of the comparison signal 101 is also delayed. Therefore, by providing a discharge circuit in the circuit of the low-pass filter 6, the comparison signal 101 can be changed so as to be vertical when the signal falls.

  In the above description, the D / A conversion resolution of the comparison signal generator 1 that outputs the comparison signal 101d is four times lower than the D / A conversion resolution of the comparison signal generator 1 that outputs the comparison signal 101c. did. However, the present invention is not limited to this value, and the same effect can be obtained even when other resolutions are used.

Embodiment 4 FIG.
In the first embodiment, the method of providing the non-change period after the falling edge of the comparison signal 101 has been described. However, if a non-change period is provided, A / D conversion is delayed by this period. Therefore, in the third embodiment, the counter 5 is configured with a packaged PLD (Programmable Logic Device) or an ASIC (Applied Specific Integrated Circuit), so that the digital output signal can be generated at a high speed every fixed period. It is considered that the A / D conversion is speeded up after improving the delay by generating and combining with the first embodiment.

  In the first to third embodiments, it is assumed that the multipoint simultaneous high-speed analog / digital conversion apparatus has the counter 5 as an independent circuit. On the other hand, the counter 5 is composed of a packaged PLD, the clock count value 107 is placed in a register area provided in the PLD, and the control circuit 3 reads and writes the register area in a batch. By doing so, it is possible to generate a plurality of digital output signals at high speeds at regular intervals.

  As described above, according to the fourth embodiment, a method of generating a digital output signal at a high speed every fixed period by configuring the counter 5 with a packaged PLD is the same as that of the first embodiment. By combining with, the A / D conversion can be speeded up after achieving the desired signal resolution, and the delay for the unchanged period can be covered.

  The PLDs described above include PAL (Program-mmable Array Logic), CPLD (Complex PLD), and FPGA (Field Programmable Logic).

  In the first to fourth embodiments, the operation method of the comparison signal generator 1 is not specified, but the comparison signal 101 output from the comparison signal generator 1 is controlled by the control signal 104 output from the control circuit 3. Since it is controlled, it is not necessary to prepare a special comparison signal generator 1 for outputting the comparison signal 101, and a commercially available digital / analog converter can be used.

  Further, in Embodiments 1 to 4, an example in which the result of A / D conversion of the analog input signal 105 is calculated by the control circuit 3 by calculations as shown in the equations (2) to (5) is taken as an example. However, if the value of the clock count value 107 with respect to the analog input signal 105 is tabulated in advance and set in the control circuit 3, the arithmetic processing becomes unnecessary and the processing speed can be further increased.

  1 comparison signal generator, 2 clock generator, 3 control circuit, 4 comparator, 5 counter, 6 low-pass filter, 101 comparison signal, 102 clock, 103 reset signal, 104 control signal, 105 analog input signal, 106 comparator Output signal, 107 clock count value.

Claims (4)

A plurality of analog / digital converters for individually outputting a plurality of clock count values corresponding to respective sizes of a plurality of analog input signals;
General control of the plurality of analog / digital conversion units, corresponding to each of the plurality of analog input signals based on the plurality of clock count values read from each of the plurality of analog / digital conversion units at regular intervals And a control circuit for simultaneously generating a plurality of digital output signals at regular intervals,
The plurality of analog / digital conversion units include a basic block for digitally converting a first analog input signal of the plurality of analog input signals, and the first analog of the plurality of analog input signals. Consists of additional blocks individually provided for each input signal in order to digitally convert analog input signals other than input signals,
The basic block is
A comparison signal generator that outputs a comparison signal that repeats monotonic increase or monotonic decrease for each predetermined period in order to specify the magnitude of an analog input signal that is a digital conversion target;
A clock generator for generating a clock;
The comparison signal output from the comparison signal generator is compared with the first analog input signal, and an L level signal is output when the first analog input signal is equal to or greater than the comparison signal. A comparator that outputs an H level signal when the first analog input signal is less than the comparison signal;
A counter that counts the clock generated by the clock generator and outputs a clock count value corresponding to the first analog input signal during a period when the output of the comparator is at the H level or the L level. And
Each of the additional blocks is
The comparison signal output from the comparison signal generator in the basic block is compared with one analog input signal to be digitally converted other than the first analog input signal, and 1 of the digital conversion target is compared. A comparator that outputs an L level signal when one analog input signal is equal to or higher than the comparison signal, and outputs an H level signal when one analog input signal to be digitally converted is less than the comparison signal; ,
In a period in which the output of the comparator is at the H level or the L level, the clock generated by the clock generator in the basic block is counted and corresponds to one analog input signal to be converted to digital. A counter for outputting a clock count value,
The control circuit is configured to read the plurality of clock count values from the plurality of analog / digital conversion units and simultaneously generate the plurality of digital output signals for each predetermined period. In addition to overall control of each counter, a period in which the control circuit simultaneously generates the plurality of digital output signals for each fixed period is a non-change period in which the comparison signal does not monotonously increase or monotonously decrease. And controlling the comparison signal generator in the basic block. A multipoint simultaneous high-speed analog / digital converter. The multipoint simultaneous high-speed analog / digital conversion device according to claim 1,
The control circuit divides the area of the analog input signal into a plurality of areas according to a required resolution, and the monotonously increasing amount or the monotonic decreasing per one clock of the comparison signal for each of the plurality of areas. Output a control signal for individually setting the amount to the comparison signal generator in the basic block;
Based on the control signal output from the control circuit, the comparison signal generator determines whether the monotonically increasing amount or the monotonically decreasing amount is within a certain period according to the resolution required in each of the plurality of regions. A multi-point simultaneous high-speed analog / digital conversion device that outputs a comparison signal set individually in. In the multipoint simultaneous high-speed analog / digital conversion device according to claim 1 or 2,
The basic block further includes a low-pass filter provided at a subsequent stage of the comparison signal generator,
The comparison signal generator outputs, as the comparison signal, a signal that performs the monotone increase or the monotone decrease while maintaining a constant value for each of a plurality of clocks,
The low-pass filter filters the comparison signal output from the comparison signal generator into an analog comparison signal that gradually changes for each clock in the plurality of clocks, and the comparator in the basic block and the additional block A multi-point simultaneous high-speed analog / digital converter characterized by output to each of the comparators. The multipoint simultaneous high-speed analog / digital conversion device according to any one of claims 1 to 3,
The counter is composed of a packaged PLD or ASIC,
The clock count value is placed in a register area provided in the PLD or ASIC,
The multi-point simultaneous high-speed analog / digital conversion device, wherein the control circuit generates the plurality of digital output signals at high speed for each of the predetermined periods by collectively reading and writing the register area.

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