JP2014041885A - Wafer processing method - Google Patents

Wafer processing method Download PDF

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JP2014041885A
JP2014041885A JP2012182726A JP2012182726A JP2014041885A JP 2014041885 A JP2014041885 A JP 2014041885A JP 2012182726 A JP2012182726 A JP 2012182726A JP 2012182726 A JP2012182726 A JP 2012182726A JP 2014041885 A JP2014041885 A JP 2014041885A
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wafer
back surface
via electrode
resin
carrier plate
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JP6013831B2 (en
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Yasutaka Mizomoto
康隆 溝本
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Disco Corp
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Disco Abrasive Systems Ltd
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Abstract

PROBLEM TO BE SOLVED: To provide a wafer processing method capable of removing a resin protruding from a wafer to suppress resin dispersion in an etching step.SOLUTION: A wafer processing method includes the steps of: removing a chamfering part of a wafer W (chamfering part removing step); disposing a carrier plate P on a surface WS of the wafer via a resin J (carrier plate disposing step); detecting a depth of a Via electrode E (Via electrode detecting step); grinding a rear surface WR of the wafer (rear surface grinding step); protruding the Via electrode E by etching (etching step); and removing at least a resin JA protruding from an outer periphery of the wafer W in the resin J by cleaning the rear surface WR of the carrier plate P and a rear surface WR (cleaning step). The cleaning step is performed after the rear surface grinding step and before the etching step.

Description

本発明は、Via電極が埋設されたウエーハの加工方法に関する。   The present invention relates to a method for processing a wafer in which a Via electrode is embedded.

近年新たな3次元実装技術として複数の半導体チップを積層し、積層した半導体チップを貫く貫通電極(Via電極)を形成して半導体チップ同士を接続する積層技術や、複数の半導体ウエーハ同士を積層し、積層した半導体ウエーハを貫く貫通電極を形成して半導体ウエーハ同士を接続する積層技術(TSV:Through Silicon Via)が開発されつつある(例えば、特許文献1、2参照)。   In recent years, as a new three-dimensional mounting technology, a plurality of semiconductor chips are stacked, a through electrode (via electrode) penetrating the stacked semiconductor chips is formed, and a semiconductor chip is connected to each other, or a plurality of semiconductor wafers are stacked. A lamination technique (TSV: Through Silicon Via) for connecting semiconductor wafers by forming through electrodes penetrating the laminated semiconductor wafers is being developed (for example, see Patent Documents 1 and 2).

特開2004−207606号公報JP 2004-207606 A 特開2005−136187号公報JP 2005-136187 A

しかし、TSVプロセスにおいて、ウエーハをサブストレートに樹脂で貼着する際にウエーハの外周から樹脂がはみ出し、エッチング工程においてはみ出した樹脂がエッチング時に飛散しウエーハ表面に付着してしまうという問題がある。   However, in the TSV process, there is a problem that when the wafer is bonded to the substrate with the resin, the resin protrudes from the outer periphery of the wafer, and the resin protruding in the etching process is scattered during the etching and adheres to the wafer surface.

本発明は、上記問題に鑑みてなされたもので、その目的は、エッチング工程における樹脂の飛散を抑制するために、はみ出した樹脂を除去するためのウエーハの加工方法を提供することである。   The present invention has been made in view of the above problems, and an object of the present invention is to provide a wafer processing method for removing the protruding resin in order to suppress scattering of the resin in the etching process.

上述した課題を解決し目的を達成するために、請求項1記載の本発明に係るウエーハの加工方法は、半導体基板の表面に複数のデバイスが分割予定ラインによって区画され、デバイスの電極から半導体基板の裏面に向かって埋設されたVia電極を有するデバイス領域と、該デバイス領域を囲繞する外周余剰領域に面取り部を備えたウエーハを個々のデバイスに分割するウエーハの加工方法であって、外周余剰領域に切削ブレードを位置づけて所定の深さ切削し面取り部を除去する面取り部除去工程と、ウエーハの表面に樹脂を介してキャリアプレートを配設するキャリアプレート配設工程と、ウエーハの裏面からVia電極の深さを検出するVia電極検出工程と、Via電極が裏面に露出しない程度にウエーハの裏面を研削して薄化する裏面研削工程と、ウエーハの裏面から半導体基板をエッチングしてVia電極を突出させるエッチング工程と、ウエーハの裏面に絶縁膜を被覆する絶縁膜被覆工程と、裏面から突出したVia電極を削り絶縁膜から露出させると共にVia電極の頭を絶縁膜と同一面に仕上げる仕上げ工程と、Via電極の頭にバンプを配設するバンプ配設工程と、ウエーハの裏面にダイシングテープを貼着すると共にウエーハの表面からキャリアプレートを取り外しウエーハをダイシングテープに移し替える移し替え工程と、を少なくとも含み、該裏面研削工程の後でかつ該エッチング工程の前に、該キャリアプレート配設工程において使用した樹脂の一部が面取りされたウエーハの外周からはみ出していて、ウエーハの外周を支持しウエーハの裏面およびキャリアプレートの裏面を洗浄する洗浄工程において、少なくともそのはみ出した樹脂を除去することを特徴とする。   In order to solve the above-mentioned problems and achieve the object, a wafer processing method according to the present invention is characterized in that a plurality of devices are partitioned on a surface of a semiconductor substrate by lines to be divided, and the semiconductor substrate is separated from the device electrodes. A wafer processing method for dividing a wafer having a device region having a Via electrode embedded toward the back surface of the wafer and a chamfered portion in an outer peripheral surplus region surrounding the device region into individual devices, the outer peripheral surplus region A chamfered portion removing step of positioning a cutting blade at a predetermined depth to remove a chamfered portion, a carrier plate arranging step of arranging a carrier plate on the surface of the wafer via a resin, and a via electrode from the back surface of the wafer Via electrode detection process for detecting the depth of the wafer, and grinding and thinning the back surface of the wafer to the extent that the Via electrode is not exposed on the back surface A surface grinding step, an etching step of projecting a via electrode by etching a semiconductor substrate from the back surface of the wafer, an insulating film coating step of covering the back surface of the wafer with an insulating film, and a via electrode protruding from the back surface is shaved from the insulating film Finishing process of exposing and finishing the head of the Via electrode on the same surface as the insulating film, bump arranging process of arranging the bump on the head of the Via electrode, and attaching a dicing tape on the back surface of the wafer and from the surface of the wafer A transfer step of removing the carrier plate and transferring the wafer to a dicing tape, and after the back grinding step and before the etching step, a part of the resin used in the carrier plate disposing step is chamfered. Protruding from the outer periphery of the wafer, and supporting the outer periphery of the wafer, In the cleaning step of cleaning the back surface of the catcher rear plate, and removing at least that protruding resin.

本発明は、エッチング工程の前に少なくともウエーハの外周からはみ出した樹脂を除去するため、エッチング工程においてウエーハに貼着された樹脂が飛散することを抑制できる。   Since the present invention removes at least the resin protruding from the outer periphery of the wafer before the etching step, the resin attached to the wafer in the etching step can be prevented from scattering.

また、エッチング工程の前の洗浄工程において、少なくともウエーハの外周からはみ出した樹脂を除去するため、はみ出した樹脂を除去するために別途専用の工程を設ける必要が無く、生産性も低下することはない。   In addition, in the cleaning process before the etching process, at least the resin protruding from the outer periphery of the wafer is removed, so there is no need to provide a separate dedicated process for removing the protruding resin, and productivity is not reduced. .

図1は、実施形態に係るウエーハの加工方法により加工されるウエーハを示す図である。FIG. 1 is a view showing a wafer to be processed by the wafer processing method according to the embodiment. 図2は、実施形態に係るウエーハの加工方法の面取り部除去工程を示す断面図である。FIG. 2 is a cross-sectional view showing a chamfer removal step of the wafer processing method according to the embodiment. 図3は、実施形態に係るウエーハの加工方法のキャリアプレート配設工程を示す断面図である。FIG. 3 is a cross-sectional view illustrating a carrier plate disposing step of the wafer processing method according to the embodiment. 図4は、実施形態に係るウエーハの加工方法のVia電極検出工程を示す断面図である。FIG. 4 is a cross-sectional view illustrating a Via electrode detection step of the wafer processing method according to the embodiment. 図5は、実施形態に係るウエーハの加工方法の裏面研削工程を示す断面図である。FIG. 5 is a cross-sectional view illustrating a back surface grinding step of the wafer processing method according to the embodiment. 図6は、実施形態に係るウエーハの加工方法の洗浄工程を示す断面図である。FIG. 6 is a cross-sectional view showing a cleaning process of the wafer processing method according to the embodiment. 図7は、実施形態に係るウエーハの加工方法のエッチング工程を示す断面図である。FIG. 7 is a cross-sectional view showing an etching process of the wafer processing method according to the embodiment. 図8は、実施形態に係るウエーハの加工方法の絶縁膜被覆工程を示す断面図である。FIG. 8 is a cross-sectional view showing an insulating film coating step of the wafer processing method according to the embodiment. 図9は、実施形態に係るウエーハの加工方法の仕上げ工程を示す断面図である。FIG. 9 is a cross-sectional view illustrating a finishing process of the wafer processing method according to the embodiment. 図10は、実施形態に係るウエーハの加工方法のバンプ配設工程を示す断面図である。FIG. 10 is a cross-sectional view showing a bump disposing step of the wafer processing method according to the embodiment. 図11は、実施形態に係るウエーハの加工方法の移し替え工程を示す断面図である。FIG. 11 is a cross-sectional view illustrating a transfer process of the wafer processing method according to the embodiment.

本発明を実施するための形態(実施形態)につき、図面を参照しつつ詳細に説明する。以下の実施形態に記載した内容により本発明が限定されるものではない。また、以下に記載した構成要素には、当業者が容易に想定できるもの、実質的に同一のものが含まれる。さらに、以下に記載した構成は適宜組み合わせることが可能である。また、本発明の要旨を逸脱しない範囲で構成の種々の省略、置換又は変更を行うことができる。   DESCRIPTION OF EMBODIMENTS Embodiments (embodiments) for carrying out the present invention will be described in detail with reference to the drawings. The present invention is not limited by the contents described in the following embodiments. The constituent elements described below include those that can be easily assumed by those skilled in the art and those that are substantially the same. Furthermore, the structures described below can be combined as appropriate. Various omissions, substitutions, or changes in the configuration can be made without departing from the scope of the present invention.

本実施形態に係るウエーハの加工方法(以下、単に加工方法と呼ぶ)を、図1から図11に基づいて説明する。図1(a)は、実施形態に係る加工方法により加工されるウエーハを示す斜視図であり、図1(b)は、図1(a)中のIB−IB線に沿う断面図であり、図2は、図1(a)に示されたウエーハの面取り部を除去する面取り部除去工程の概要を示す断面図であり、図3は、図2に示されたウエーハにキャリアプレートが取り付けられるキャリアプレート配設工程の概要を示す断面図であり、図4は、図3に示されたウエーハのVia電極の深さを検出するVia電極検出工程の概要を示す断面図であり、図5は、図4に示されたキャリアプレートが配設されたウエーハの裏面に研削を施す裏面研削工程の概要を示す断面図であり、図6は、図5に示されたウエーハの裏面及びキャリアプレートを洗浄する洗浄工程の概要を示す断面図であり、図7は、図6に示されたウエーハの裏面にエッチングを施すエッチング工程の概要を示す断面図であり、図8は、図7に示されたウエーハの裏面に絶縁膜を被覆する絶縁膜被覆工程の概要を示す断面図であり、図9は、図8に示されたウエーハのVia電極の頭を露出させる仕上げ工程の概要を示す断面図であり、図10は、図9に示されたウエーハのVia電極の頭にバンプを配設するバンプ配設工程の概要を示す断面図であり、図11は、図10に示されたウエーハをダイシングテープに移し替える移し替え工程の概要を示す断面図である。   A wafer processing method (hereinafter simply referred to as a processing method) according to the present embodiment will be described with reference to FIGS. FIG. 1A is a perspective view showing a wafer processed by the processing method according to the embodiment, and FIG. 1B is a cross-sectional view taken along line IB-IB in FIG. FIG. 2 is a cross-sectional view showing an outline of a chamfered portion removing step for removing the chamfered portion of the wafer shown in FIG. 1A, and FIG. 3 shows a carrier plate attached to the wafer shown in FIG. FIG. 4 is a cross-sectional view showing an outline of the carrier plate arrangement process, FIG. 4 is a cross-sectional view showing an outline of the Via electrode detection process for detecting the depth of the Via electrode of the wafer shown in FIG. 3, and FIG. FIG. 6 is a cross-sectional view showing an outline of a back surface grinding process for grinding the back surface of the wafer on which the carrier plate shown in FIG. 4 is disposed, and FIG. 6 shows the back surface of the wafer and the carrier plate shown in FIG. It is sectional drawing which shows the outline | summary of the washing | cleaning process to wash | clean FIG. 7 is a cross-sectional view showing an outline of an etching process for etching the back surface of the wafer shown in FIG. 6, and FIG. 8 shows an insulating film coating for covering the back surface of the wafer shown in FIG. FIG. 9 is a cross-sectional view showing an outline of the process, FIG. 9 is a cross-sectional view showing an outline of the finishing process for exposing the head of the Via electrode of the wafer shown in FIG. 8, and FIG. 10 is shown in FIG. FIG. 11 is a cross-sectional view showing an outline of a bump disposing process for disposing a bump on the head of a via electrode of a wafer, and FIG. 11 is a cross-sectional view showing an outline of a transfer process for transferring the wafer shown in FIG. 10 to a dicing tape. FIG.

本実施形態に係る加工方法は、図1に示すウエーハWを個々のデバイスDに分割する加工方法である。   The processing method according to the present embodiment is a processing method for dividing the wafer W shown in FIG.

なお、本実施形態に係る加工方法により個々のデバイスDに分割される加工対象としてのウエーハW(半導体基板に相当)は、本実施形態では、シリコン、サファイア、ガリウムなどを母材とする円板状の半導体ウエーハや光デバイスウエーハである。ウエーハWは、図1(a)に示すように、表面WSに複数のデバイスDが分割予定ラインSによって区画されている。また、ウエーハWは、図1(b)に示すように、デバイスDの電極から裏面WRに向かって埋設されたVia電極Eを有するデバイス領域DRと、図1(a)に示すように、デバイス領域DRを囲繞する外周余剰領域GRに面取り部Cを備えている。Via電極Eは、銅などの金属で構成され、ウエーハWの表面WS側に端面が露出し、ウエーハWの厚み方向の中央まで、表面WSから裏面WRに向かって埋設されている。   Note that a wafer W (corresponding to a semiconductor substrate) to be divided into individual devices D by the processing method according to the present embodiment is a disk whose base material is silicon, sapphire, gallium, or the like in this embodiment. Semiconductor wafer or optical device wafer. In the wafer W, as shown in FIG. 1A, a plurality of devices D are partitioned on the surface WS by a division line S. Further, as shown in FIG. 1B, the wafer W includes a device region DR having a via electrode E embedded from the electrode of the device D toward the back surface WR, and a device region DR as shown in FIG. A chamfered portion C is provided in the outer peripheral surplus region GR that surrounds the region DR. The Via electrode E is made of a metal such as copper, and an end surface is exposed on the surface WS side of the wafer W, and is embedded from the surface WS toward the back surface WR up to the center in the thickness direction of the wafer W.

本実施形態に係る加工方法は、面取り部除去工程と、キャリアプレート配設工程と、Via電極検出工程と、裏面研削工程と、エッチング工程と、絶縁膜被覆工程と、仕上げ工程と、バンプ配設工程と、移し替え工程と、を少なくとも含んでいる。   The processing method according to the present embodiment includes a chamfered portion removing process, a carrier plate arranging process, a Via electrode detecting process, a back grinding process, an etching process, an insulating film coating process, a finishing process, and a bump arranging. At least a process and a transfer process.

本実施形態に係る加工方法は、まず、面取り部除去工程において、図2に示すように、ウエーハWの裏面WRを切削装置1のチャックテーブル2に載置し、チャックテーブル2にウエーハWを保持する。そして、切削装置1のチャックテーブル2をウエーハWとともに軸心回りに回転させ、切削装置1の図示しないスピンドルにより切削ブレード3を回転させる。そして、外周余剰領域GR上に切削ブレード3を位置付けて、切削ブレード3を所定の深さ降下させて、ウエーハWの外周部を所定の深さ切削し、面取り部Cを除去する。なお、本実施形態では、面取り部Cは、表面WS側から当該面取り部Cの厚みの半分程除去され、本発明では、面取り部除去工程では、面取り部Cの少なくとも一部を除去すれば良い。そして、キャリアプレート配設工程に進む。   In the processing method according to this embodiment, first, in the chamfered portion removing step, as shown in FIG. 2, the back surface WR of the wafer W is placed on the chuck table 2 of the cutting apparatus 1 and the wafer W is held on the chuck table 2. To do. Then, the chuck table 2 of the cutting device 1 is rotated around the axis together with the wafer W, and the cutting blade 3 is rotated by a spindle (not shown) of the cutting device 1. Then, the cutting blade 3 is positioned on the outer peripheral surplus region GR, the cutting blade 3 is lowered by a predetermined depth, the outer peripheral portion of the wafer W is cut to a predetermined depth, and the chamfered portion C is removed. In this embodiment, the chamfered portion C is removed from the surface WS side by about half of the thickness of the chamfered portion C. In the present invention, at least a part of the chamfered portion C may be removed in the chamfered portion removing step. . And it progresses to a carrier plate arrangement | positioning process.

キャリアプレート配設工程では、図3に示すように、ウエーハWの表面WSに粘着性を有する樹脂Jを貼着し、さらに樹脂JにキャリアプレートPを貼着する。こうして、ウエーハWの表面WSに樹脂Jを介してキャリアプレートPを配設する。なお、樹脂Jを構成する材質としては、例えば、紫外線が照射されると硬化するUV硬化型や加熱されると硬化するエポキシ樹脂やアクリル樹脂が用いられ、キャリアプレートPは、外径が面取り除去工程後のウエーハWの外径と略等しい円板状に形成されている。また、ウエーハWの表面WSに樹脂Jを介してキャリアプレートPが配設された際には、図3に示すように、樹脂Jのうちの一部の樹脂J(はみ出した樹脂を他の樹脂と区別して、以下符号JAで示す)が、面取り部Cが除去された後のウエーハWの外周からはみ出している。そして、Via電極検出工程に進む。   In the carrier plate disposing step, as shown in FIG. 3, an adhesive resin J is attached to the surface WS of the wafer W, and a carrier plate P is further attached to the resin J. Thus, the carrier plate P is disposed on the surface WS of the wafer W via the resin J. In addition, as a material constituting the resin J, for example, a UV curing type that cures when irradiated with ultraviolet rays, an epoxy resin or an acrylic resin that cures when heated, and the carrier plate P has a chamfered outer diameter is removed. It is formed in a disk shape substantially equal to the outer diameter of the wafer W after the process. Further, when the carrier plate P is disposed on the surface WS of the wafer W via the resin J, as shown in FIG. 3, a part of the resin J (the protruding resin is replaced with another resin). Is indicated by the symbol JA below) and protrudes from the outer periphery of the wafer W after the chamfered portion C is removed. And it progresses to a Via electrode detection process.

Via電極検出工程では、図4に示すように、ウエーハWに樹脂Jを介して配設されたキャリアプレートPを電極検出装置10のチャックテーブル11に載置し、チャックテーブル11にウエーハWを保持する。そして、電極検出装置10のスキャナ部12からウエーハWを透過する近赤外光又は赤外光などをウエーハWの裏面WRに向けて照射し、ウエーハWの表面WS、Via電極Eの裏面WR側の端面Ea、ウエーハWの裏面WRから反射された光を受光しつつ、スキャナ部12を裏面WRに沿って移動させる。そして、ウエーハWの屈折率等に基づいて、ウエーハWの裏面WRからのVia電極Eの裏面WR側の端面Eaの深さHを検出する。そして、裏面研削工程に進む。   In the Via electrode detection process, as shown in FIG. 4, the carrier plate P disposed on the wafer W via the resin J is placed on the chuck table 11 of the electrode detection device 10, and the wafer W is held on the chuck table 11. To do. Then, near-infrared light or infrared light that passes through the wafer W is irradiated from the scanner unit 12 of the electrode detection device 10 toward the back surface WR of the wafer W, and the front surface WS of the wafer W and the back surface WR side of the Via electrode E The scanner unit 12 is moved along the back surface WR while receiving the light reflected from the end surface Ea of the wafer W and the back surface WR of the wafer W. Then, based on the refractive index of the wafer W, the depth H of the end surface Ea on the back surface WR side of the Via electrode E from the back surface WR of the wafer W is detected. And it progresses to a back surface grinding process.

裏面研削工程では、図5に示すように、ウエーハWに樹脂Jを介して配設されたキャリアプレートPを、研削装置20のチャックテーブル21に載置し、チャックテーブル21にウエーハWを保持する。そして、研削装置20のチャックテーブル21をウエーハWとともに軸心回りに回転させ、研削装置20の研削砥石22をチャックテーブル21と同方向に軸心回りに回転させながらウエーハWの裏面WRに接触させる。そして、Via電極検出工程において検出したVia電極Eの裏面WR側の端面Eaの深さHに基づいて、Via電極Eの端面Eaが露出しない程度に、研削砥石22を所定の送り速度で下方に所定量研削送りして、ウエーハWの裏面WRを研削砥石22により研削し、ウエーハWを薄化する。そして、ウエーハWの厚みを半分程除去して、面取り部Cを除去する。   In the back grinding process, as shown in FIG. 5, the carrier plate P disposed on the wafer W via the resin J is placed on the chuck table 21 of the grinding device 20, and the wafer W is held on the chuck table 21. . Then, the chuck table 21 of the grinding device 20 is rotated around the axis together with the wafer W, and the grinding wheel 22 of the grinding device 20 is brought into contact with the back surface WR of the wafer W while rotating around the axis in the same direction as the chuck table 21. . Then, based on the depth H of the end surface Ea on the back surface WR side of the Via electrode E detected in the Via electrode detection step, the grinding wheel 22 is moved downward at a predetermined feed rate so that the end surface Ea of the Via electrode E is not exposed. A predetermined amount is ground and fed, and the back surface WR of the wafer W is ground by the grinding wheel 22 to thin the wafer W. Then, half the thickness of the wafer W is removed, and the chamfered portion C is removed.

エッチング工程では、裏面研削工程により研削加工が施されたウエーハWの裏面WR側をプラズマエッチングなどのエッチングを行い、ウエーハWの裏面WRを溶解侵食、食刻する。そして、図7に示すように、Via電極Eの端面EaをウエーハWの裏面WRよりも突出させる。そして、絶縁膜被覆工程に進む。   In the etching process, the back surface WR side of the wafer W that has been ground in the back surface grinding process is etched by plasma etching or the like, and the back surface WR of the wafer W is dissolved and etched. Then, as shown in FIG. 7, the end surface Ea of the Via electrode E is protruded from the back surface WR of the wafer W. Then, the process proceeds to the insulating film coating step.

絶縁膜被覆工程では、図8に示すように、ウエーハWの裏面WRに、該裏面WR及びVia電極Eの端面Eaを被覆する絶縁膜Zを被覆する。なお、絶縁膜Zの厚みは、一様である。そして、仕上げ工程に進む。   In the insulating film coating step, as shown in FIG. 8, the back surface WR of the wafer W is coated with an insulating film Z that covers the back surface WR and the end surface Ea of the Via electrode E. Note that the thickness of the insulating film Z is uniform. Then, the process proceeds to the finishing process.

仕上げ工程では、図9に示すように、ウエーハWに樹脂Jを介して配設されたキャリアプレートPを、研削装置30のチャックテーブル31に載置し、チャックテーブル31にウエーハWを保持する。そして、研削装置30のチャックテーブル31をウエーハWとともに軸心回りに回転させ、研削装置30の研削砥石32をチャックテーブル31と同方向に軸心回りに回転させながらウエーハWの裏面WRを被覆した絶縁膜Zに接触させる。研削砥石32を所定の送り速度で下方に所定量研削送りして、Via電極Eの端面Ea上の絶縁膜Z、裏面WRから突出したVia電極Eを研削砥石32により研削して絶縁膜Zから露出させると共にVia電極Eの頭Ebを絶縁膜Zと同一面に仕上げる。なお、仕上げ工程に用いる研削装置30は、裏面研削工程で用いられる研削装置20と同一であっても良く、異なっていても良く、構成の一部が同一で残りが異なるものであっても良い。そして、バンプ配設工程に進む。   In the finishing process, as shown in FIG. 9, the carrier plate P disposed on the wafer W via the resin J is placed on the chuck table 31 of the grinding device 30, and the wafer W is held on the chuck table 31. Then, the chuck table 31 of the grinding device 30 is rotated around the axis together with the wafer W, and the back surface WR of the wafer W is coated while the grinding wheel 32 of the grinding device 30 is rotated around the axis in the same direction as the chuck table 31. Contact with the insulating film Z. The grinding wheel 32 is ground by a predetermined amount at a predetermined feed rate, and the insulating film Z on the end surface Ea of the Via electrode E and the Via electrode E protruding from the back surface WR are ground by the grinding wheel 32 to be removed from the insulating film Z. The head Eb of the Via electrode E is finished on the same surface as the insulating film Z while being exposed. Note that the grinding device 30 used in the finishing process may be the same as or different from the grinding device 20 used in the back surface grinding process, and a part of the configuration may be the same and the rest may be different. . And it progresses to a bump arrangement | positioning process.

バンプ配設工程では、図10に示すように、各Via電極Eの頭EbにバンプVを配設する。そして、移し替え工程に進む。移し替え工程では、ウエーハWをキャリアプレートP毎反転させ、ウエーハWの裏面WRに、外縁部に環状フレームFが貼着されたダイシングテープTを、バンプVを介して貼着する。そして、樹脂Jを硬化させるなどして、図11に示すように、ウエーハWの表面WSからキャリアプレートPを樹脂Jとともに取り外し、ウエーハWをキャリアプレートPからダイシングテープTに移し替える。その後、切削加工やレーザー加工等によりウエーハWを個々のデバイスDに分割する。   In the bump disposing step, the bump V is disposed on the head Eb of each Via electrode E as shown in FIG. Then, the process proceeds to the transfer process. In the transfer step, the wafer W is reversed for each carrier plate P, and the dicing tape T with the annular frame F attached to the outer edge portion is attached to the back surface WR of the wafer W via the bumps V. Then, the resin J is cured, for example, and the carrier plate P is removed together with the resin J from the surface WS of the wafer W, and the wafer W is transferred from the carrier plate P to the dicing tape T as shown in FIG. Thereafter, the wafer W is divided into individual devices D by cutting or laser processing.

また、本実施形態の加工方法は、洗浄工程が含まれる。洗浄工程は、裏面研削工程の後でかつエッチング工程の前に実行される。洗浄工程では、図6に示すように、洗浄装置40の複数の軸心回りに回転自在なエッジクランプ41間に、樹脂Jを介してキャリアプレートPが配設されたウエーハWを、ウエーハWが上側、キャリアプレートPが下側に位置するように挟み込む。すると、キャリアプレート配設工程において使用した樹脂Jのうちの面取りされたウエーハWの外周からはみ出している樹脂JA(樹脂の一部に相当)が、エッジクランプ41の軸心方向の中央の外周面に設けられた砥石42に当接する。こうして、洗浄工程では、複数(本実施形態では三つ)のエッジクランプ41間にウエーハWを挟みこんで、ウエーハWの外周を支持する。   Moreover, the processing method of this embodiment includes a cleaning step. The cleaning process is performed after the back grinding process and before the etching process. In the cleaning process, as shown in FIG. 6, the wafer W is a wafer W in which a carrier plate P is disposed via a resin J between edge clamps 41 that are rotatable around a plurality of axes of the cleaning device 40. The carrier plate P is sandwiched so that the carrier plate P is located on the lower side. Then, the resin JA (corresponding to a part of the resin) protruding from the outer periphery of the chamfered wafer W in the resin J used in the carrier plate arranging step is the outer peripheral surface in the center of the edge clamp 41 in the axial center direction. Abuts against the grindstone 42 provided on the surface. Thus, in the cleaning process, the wafer W is sandwiched between a plurality (three in the present embodiment) of the edge clamps 41 to support the outer periphery of the wafer W.

そして、複数のエッジクランプ41のうちの一つのエッジクランプ41をモータ43により軸心回りに回転させる。すると、一つのエッジクランプ41の回転によりウエーハWが回転し、残りエッジクランプ41もウエーハWの回転により連れ回りする。また、洗浄装置40のウエーハWの上方に配設された洗浄液噴射ノズル44から例えば純水などの洗浄液45をウエーハWの裏面WRに向けて噴出し、洗浄装置40のウエーハWの下方に配設された洗浄ローラ46を回転させながらキャリアプレートPの裏面Paに接触させる。すると、ウエーハWの回転による遠心力により、ウエーハWに向けて噴射された洗浄液45が、ウエーハW上を外周方向に流れて、ウエーハWの裏面WRなどに付着したコンタミとともにウエーハW上から流れ落ち、ウエーハWの裏面WRを洗浄する。   Then, one edge clamp 41 of the plurality of edge clamps 41 is rotated around the axis by the motor 43. Then, the wafer W is rotated by the rotation of one edge clamp 41, and the remaining edge clamp 41 is also rotated by the rotation of the wafer W. Further, a cleaning liquid 45 such as pure water is ejected from the cleaning liquid injection nozzle 44 disposed above the wafer W of the cleaning apparatus 40 toward the back surface WR of the wafer W, and is disposed below the wafer W of the cleaning apparatus 40. The cleaning roller 46 thus rotated is brought into contact with the back surface Pa of the carrier plate P. Then, due to the centrifugal force caused by the rotation of the wafer W, the cleaning liquid 45 sprayed toward the wafer W flows on the wafer W in the outer peripheral direction, and flows down from the wafer W together with the contamination adhered to the back surface WR of the wafer W, The back surface WR of the wafer W is cleaned.

また、洗浄装置40は、洗浄ローラ46に複数の洗浄水供給口(図示していない)を有しており、これらの洗浄水供給口から洗浄水が噴射され、洗浄ローラ46によりキャリアプレートPの裏面Paを洗浄する。さらに、モータ43により直接回転されずにウエーハWと連れ回りするエッジクランプ41とウエーハWの回転速度差により、砥石42が樹脂JAを研削し、このウエーハWの外周からはみ出した樹脂JAを削り取って、除去する。所定時間、洗浄装置40による洗浄を行なうと、エッチング工程に進む。なお、ウエーハWと連れ回りするエッジクランプ41とウエーハWの回転速度差を生じさせるために、モータ43により回転されずにウエーハWと連れ回りするエッジクランプ41の回転を抑制する回転抑制手段を設けても良い。   Further, the cleaning device 40 has a plurality of cleaning water supply ports (not shown) in the cleaning roller 46, and cleaning water is jetted from these cleaning water supply ports, and the cleaning roller 46 causes the carrier plate P to The back surface Pa is cleaned. Further, the grinding wheel 42 grinds the resin JA due to the difference in rotational speed between the wafer W and the edge clamp 41 that rotates with the wafer W without being directly rotated by the motor 43, and scrapes off the resin JA protruding from the outer periphery of the wafer W. ,Remove. When cleaning is performed by the cleaning device 40 for a predetermined time, the process proceeds to an etching process. In order to cause a difference in rotational speed between the edge clamp 41 that rotates with the wafer W and the wafer W, rotation suppression means that suppresses the rotation of the edge clamp 41 that rotates with the wafer W without being rotated by the motor 43 is provided. May be.

以上のように、本実施形態に係る加工方法は、エッチング工程の前にウエーハWの外周からはみ出した樹脂JAを除去するため、エッチング工程においてウエーハWに貼着された樹脂Jが飛散することを抑制できる。   As described above, the processing method according to this embodiment removes the resin JA that protrudes from the outer periphery of the wafer W before the etching process, so that the resin J attached to the wafer W in the etching process is scattered. Can be suppressed.

また、ウエーハWを洗浄する洗浄工程において、ウエーハWの外周からはみ出した樹脂JAを除去するので、はみ出した樹脂JAを除去するために別途専用の工程を行なう必要が無く、生産性も低下することはない。さらに、洗浄装置40が洗浄工程において、ウエーハWの外周からはみ出した樹脂JAを除去するので、はみ出した樹脂JAを除去するために別途専用の樹脂除去装置を設ける必要が無く、コストの高騰を抑制できる。   In addition, since the resin JA that protrudes from the outer periphery of the wafer W is removed in the cleaning process for cleaning the wafer W, it is not necessary to perform a separate dedicated process to remove the protruding resin JA, and productivity is also reduced. There is no. Further, since the cleaning device 40 removes the resin JA that protrudes from the outer periphery of the wafer W in the cleaning process, it is not necessary to provide a dedicated resin removing device to remove the protruding resin JA, thereby suppressing an increase in cost. it can.

本実施形態に係る加工方法では、面取り部除去工程において面取りされたウエーハWの外周からはみ出した樹脂JAを除去しているが、ウエーハWとキャリアプレートPとが位置ずれしない範囲において樹脂JのうちのウエーハWの外周からはみ出すことなくウエーハWとキャリアプレートPとで挟まれた樹脂Jの外周部を除去しても良い。要するに、本発明では、洗浄工程において、少なくともウエーハWの外周からはみ出した樹脂JAを除去すれば良い。   In the processing method according to the present embodiment, the resin JA protruding from the outer periphery of the wafer W chamfered in the chamfered portion removing step is removed, but the resin J is within a range in which the wafer W and the carrier plate P are not misaligned. The outer peripheral portion of the resin J sandwiched between the wafer W and the carrier plate P may be removed without protruding from the outer periphery of the wafer W. In short, in the present invention, at least the resin JA protruding from the outer periphery of the wafer W may be removed in the cleaning process.

なお、本発明は上記実施形態に限定されるものではない。即ち、本発明の骨子を逸脱しない範囲で種々変形して実施することができる。   The present invention is not limited to the above embodiment. That is, various modifications can be made without departing from the scope of the present invention.

3 切削ブレード
W ウエーハ(半導体基板)
WS 表面
WR 裏面
J,JA 樹脂
P キャリアプレート
Pa 裏面
D デバイス
S 分割予定ライン
E Via電極
Eb 頭
H 深さ
DR デバイス領域
GR 外周余剰領域
C 面取り部
T ダイシングテープ
V バンプ
Z 絶縁膜
3 Cutting blade W Wafer (semiconductor substrate)
WS surface WR back surface J, JA Resin P Carrier plate Pa back surface D Device S Divided line E Via electrode Eb Head H Depth DR Device region GR Peripheral surplus region C Chamfer T Dicing tape V Bump Z Insulating film

Claims (1)

半導体基板の表面に複数のデバイスが分割予定ラインによって区画され、デバイスの電極から半導体基板の裏面に向かって埋設されたVia電極を有するデバイス領域と、該デバイス領域を囲繞する外周余剰領域に面取り部を備えたウエーハを個々のデバイスに分割するウエーハの加工方法であって、
外周余剰領域に切削ブレードを位置づけて所定の深さ切削し面取り部を除去する面取り部除去工程と、
ウエーハの表面に樹脂を介してキャリアプレートを配設するキャリアプレート配設工程と、
ウエーハの裏面からVia電極の深さを検出するVia電極検出工程と、
Via電極が裏面に露出しない程度にウエーハの裏面を研削して薄化する裏面研削工程と、
ウエーハの裏面から半導体基板をエッチングしてVia電極を突出させるエッチング工程と、
ウエーハの裏面に絶縁膜を被覆する絶縁膜被覆工程と、
裏面から突出したVia電極を削り絶縁膜から露出させると共にVia電極の頭を絶縁膜と同一面に仕上げる仕上げ工程と、
Via電極の頭にバンプを配設するバンプ配設工程と、
ウエーハの裏面にダイシングテープを貼着すると共にウエーハの表面からキャリアプレートを取り外しウエーハをダイシングテープに移し替える移し替え工程と、
を少なくとも含み、
該裏面研削工程の後でかつ該エッチング工程の前に、該キャリアプレート配設工程において使用した樹脂の一部が面取りされたウエーハの外周からはみ出していて、ウエーハの外周を支持しウエーハの裏面およびキャリアプレートの裏面を洗浄する洗浄工程において、少なくともそのはみ出した樹脂を除去するウエーハの加工方法。
A plurality of devices are partitioned by dividing lines on the surface of the semiconductor substrate, a device region having a Via electrode embedded from the device electrode toward the back surface of the semiconductor substrate, and a chamfered portion in an outer peripheral surplus region surrounding the device region A wafer processing method for dividing a wafer provided with a wafer into individual devices,
A chamfered portion removing step of positioning a cutting blade in the outer peripheral surplus area and cutting a predetermined depth to remove the chamfered portion;
A carrier plate disposing step of disposing a carrier plate on the surface of the wafer via a resin;
A Via electrode detection step of detecting the depth of the Via electrode from the back surface of the wafer;
A back grinding process for grinding and thinning the back surface of the wafer to such an extent that the Via electrode is not exposed on the back surface;
An etching step of etching the semiconductor substrate from the back surface of the wafer to project the Via electrode;
An insulating film coating process for coating the back surface of the wafer with an insulating film;
A finishing step in which the via electrode protruding from the back surface is scraped to be exposed from the insulating film and the head of the via electrode is finished on the same plane as the insulating film;
A bump disposing step of disposing a bump on the head of the Via electrode;
A transfer step of attaching a dicing tape to the back surface of the wafer, removing the carrier plate from the front surface of the wafer, and transferring the wafer to the dicing tape;
Including at least
After the back grinding step and before the etching step, a part of the resin used in the carrier plate arranging step protrudes from the outer periphery of the chamfered wafer, supports the outer periphery of the wafer, A wafer processing method for removing at least the protruding resin in a cleaning step of cleaning the back surface of the carrier plate.
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