JP2014041869A - Lamination multiple core lsi - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an LSI having a three-dimentional stack structure which allows AVS (power source voltage control) without increasing the number of undermost layer boll electrodes and has a structure of easily releasing generated heat to the outside.SOLUTION: An LSI with a plurality of cores being laminated includes power source means provided independently for each of the cores, primary input power source supply means configured to make common among the cores a primary input power source supply of the power source means for each core, operation lower limit voltage detection means for detecting an operation lower limit voltage of each core, and secondary output setup means for setting up a secondary output voltage of the power source means of each core so as to correspond to a detected value by the operation lower limit voltage detection means.

Description

  The present invention relates to heat dissipation when multi-cores for image processing are stacked.

  In recent years, in digital cameras, the flow of high-resolution moving image processing is remarkable, and image processing with a high-resolution frame size such as 4K2K is being performed. As the frame size increases, the amount of image processing increases. Therefore, a system that performs image processing using a multi-core LSI composed of a plurality of DSP chips has been proposed. In order to cope with high-speed signal transmission between multichips, there is a laminated chip in which core chips are laminated in the vertical direction and mounted. In a multi-core chip stacked in the vertical direction, heat in each core is concentrated, and there is a concern that the operation of the DSP chip becomes unstable.

  In Patent Document 1, a proposal is made to reduce the wasteful power by holding the defective manufacturing chip information in the stacked RAM chip, inactivating the power generation circuit of the defective chip.

JP 2011-123955 A

  However, in the above conventional example, the power consumption is reduced by shutting off the power supply at the defective part, but the power consumption during normal operation cannot be reduced.

In an LSI in which a plurality of cores are stacked,
An independent power supply for each core;
Primary input power supply means in which the primary input power supply of each core power supply means is shared among the cores;
An operation lower limit voltage detecting means for detecting an operation lower limit voltage of each core;
Secondary output setting means for setting a secondary output voltage of the power supply means of each core corresponding to a detection value by the operation lower limit voltage detection means.

  According to the present invention, in an LSI having a 3D stack structure, AVS (power supply voltage control) can be performed without increasing the number of ball electrodes in the lowest layer, and power consumption in each core can be reduced. Or, by operating the core of a production lot that generates a lot of heat due to manufacturing variations with a lower operating voltage than normal products, use LSIs in a production lot that could not be used due to power consumption and heat generation problems. It is possible to improve the yield of LSI.

System configuration diagram of Embodiment 1 Configuration diagram of the signal processing unit 104 according to the first embodiment. ID-CODE table of Example 1 Flow chart of the first embodiment Configuration diagram of the signal processing unit 104 according to the second embodiment.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is an overall configuration diagram of a video camcorder for explaining an embodiment of the present invention. The photographed image is formed by the lens 101 and enters the CMOS sensor 102. In the CMOS sensor 102, photoelectric conversion is performed and input to the AFE 103. The AFE 103 converts it into digital video data and inputs it to the signal processing unit 104. The signal processing unit 104 generates video data for recording and displaying moving images and still images according to the shooting mode, and sends them to the display unit 107 and the recording unit 108. The display unit 107 is composed of a panel or EVF, for example, and displays video data. The recording unit 108 is composed of, for example, a hard disk, a USB memory, an SD card, etc., and records video data.

  FIG. 2 is a diagram showing the structure of the signal processing unit 104. Reference numerals 101 to 104 denote solder balls for soldering connection with a main board (not shown), 101 denotes a power supply solder ball, and 102, 103, and 104 denote signal solder balls. 110 to 113 are silicon interposers, and 120 to 123 are CPU cores. Reference numerals 131 to 134 denote DCDC converters formed in the silicon interposers 110 to 113. An inductor, a capacitor, and an amplifier circuit are formed on the silicon interposer to form a drop voltage type DCDC converter. The DCDC converter 131 supplies power to the CPU core 120.

  Similarly, the DCDC converter 132 supplies power to the CPU core 121, the DCDC converter 133 supplies power to the CPU core 122, and the DCDC converter 134 supplies power to the CPU core 123.

  141 is a via (hereinafter referred to as TSV) penetrating the silicon interposers 110 to 113 and the CPU cores 120 to 123 and the silicon interposer. The power from the power supply solder ball 101 is supplied to the DCDC converters 131 to 134. As a power supply line.

  The CPU cores 120 to 123 vary in the operable lower limit voltage due to manufacturing variations. When the CPU core is manufactured, the operable lower limit voltage due to manufacturing variation is measured, and as shown in FIG. 3, ID-CODE corresponding to the operable lower limit voltage is written in the CPU core. For example, if the operation can be guaranteed only at 1.00 V, 0 is written in ID-CODE. Those capable of operating at high speed can operate normally even when the set operating voltage is lowered. For example, ID-CODE 7 is written in a CPU core operable at 0.86V. Specifically, ID-CODE is written by burning out the aluminum wiring layers 151 to 154 by laser irradiation.

  When the CPU cores 120 to 123 are selected and stacked as the signal processing unit 104, the CPU cores 120 to 123 are stacked in the descending order of the ID-CODE from the order close to the solder balls 101 to 104. That is, the layers are stacked in order from the lowest operation lower limit voltage value. The above is the description when the signal processing unit 104 is manufactured.

  FIG. 4 is a flowchart at the time of normal use of the video camcorder. Each of the CPU cores 120 to 123 operates independently with the same algorithm. The operation of the CPU core 120 will be described. When the power of the video camcorder is turned on in S101, the CPU core 120 sets the output voltage of the DCDC converter 131 to 1.0V. In step S102, the CPU core 120 reads ID_CODE 151. Next, in S104, the output of the DCDC converter 131 is set to the operation lower limit voltage value corresponding to the read ID-CODE value, and the process ends in S105. At this time, the power supply voltage is lowered step by step so that the target voltage value is gradually increased so as not to cause a sudden voltage change. The CPU cores 121, 122, and 123 perform the same operation.

  Although power loss occurs in the DCDC converters 131 to 134 in proportion to the difference between the primary voltage of the power supply line via the power supply solder balls 101 and the supply voltage to the CPU core 120, the DCDC converters 131 to 134 are generated. Is adjacent to the TSV 141, and heat generated by power loss in the DCDC converters 131 to 134 escapes to the main board (not shown) via the TSV 141 and the solder ball 101. In addition, since the operating voltages of the CPU cores 120 to 123 are set to the lower limit voltages at which the CPU cores 120 to 123 operate by the DCDC converters 131 to 134, the power consumption in the CPU cores 120 to 123 can be reduced. The generated heat at 120 to 123 is also reduced, and the temperature increase of the signal processing unit 104 as a whole can be suppressed.

  When the signal processing unit 104 is manufactured, the ID-CODE values are stacked in the order of the same or larger values. That is, the CPU cores are stacked in the order of the same or lower operable voltage from the side closer to the solder balls 101-104. In FIG. 2, the operable voltage of the CPU core is CPU core 120 = <CPU core 121 = <CPU core 122 = <CPU core 123, and the power loss in the DCDC converter is DCDC converter 131> = DCDC converter 132>. = DCDC converter 133> = DCDC converter 134 increases in order. Heat generated by the power loss in the DCDC converters 131 to 134 is quickly radiated to the main board (not shown) via the TSV 141 and the solder balls 101. However, since the thermal resistance value is increased by the length of the TSV, the heat dissipation is DCDC converter 131> = DCDC converter 132> = DCDC converter 133> = DCDC converter 134, so that the entire signal processing unit 104. As a result, the heat dissipation of the generated heat is improved.

  FIG. 5 is a diagram illustrating the structure of the signal processing unit 104 in the second embodiment.

  Reference numerals 201 to 204 denote solder balls for soldering connection with a main board (not shown), 201 denotes a power supply solder ball, and 202, 203, and 204 denote signal solder balls. 210 is a silicon interposer, and 220 to 223 are CPU cores. Reference numerals 231 to 234 denote DCDC converters formed with the silicon interposer 210. An inductor, a capacitor, and an amplifier circuit are formed on the silicon interposer to form a drop voltage type DCDC converter. The DCDC converter 231 supplies power to the CPU core 120 via the TSV 261. Similarly, the DCDC converter 232 supplies power to the CPU core 221, the DCDC converter 233 supplies power to the CPU core 222, and the DCDC converter 234 supplies power to the CPU core 223.

  A TSV 260 in the silicon interposer 210 is connected to a power supply solder ball 201 and supplies a primary current to the DCDC converters 231 to 234. The output current of the DCDC converter 231 supplies power to the CPU core 220 via the TSV 261. The output current of the DCDC converter 232 supplies power to the CPU core 221 via the TSV262. The output current of the DCDC converter 233 supplies power to the CPU core 222 via the TSV263. The output current of the DCDC converter 234 supplies power to the CPU core 223 via the TSV 264.

  The CPU cores 220 to 223 vary in the operable lower limit voltage due to manufacturing variations. When the CPU core is manufactured, an operable lower limit voltage due to manufacturing variation is measured, and an ID-CODE corresponding to the operable lower limit voltage is written in the CPU core. 251 to 254 are ID-CODEs indicating the operable lower limit voltages of the respective CPU cores.

  The CPU 220 sets the output voltage of the DCDC converter 231 corresponding to the ID-CODE 251. Similarly, the CPU 221 sets the output voltage of the DCDC converter 232 corresponding to the ID-CODE 251, the CPU 222 sets the output voltage of the DCDC converter 233 corresponding to the ID-CODE 252, and the CPU 223 corresponds to the ID-CODE 253. Then, the output voltage of the DCDC converter 234 is set.

  Heat generated by power loss in the DCDC converter 231 to DCDC converter 234 is radiated to the main board (not shown) via the TSV 260 and the solder balls 201.

  When the signal processing unit 104 is manufactured, the ID-CODE values are stacked in the same or larger order, and the CPU core operable voltages are stacked in the same or lower order in order from the closest to the solder balls 201 to 204. Then, heat is radiated to the main board (not shown) via the solder balls 201-204.

FIG.
101: Lens 102: CMOS sensor 103: AFE
104: Signal processing unit 107: Display unit 108: Recording unit
101: Solder balls 102 to 104 for power supply: Solder balls for signal,
110 to 113: Silicon interposers 120 to 123: CPU cores 131 to 134: DCDC converter 141: TSV (through via)
151-152: ID-CODE

Claims (6)

In an LSI in which a plurality of cores are stacked,
An independent power supply for each core;
Primary input power supply means in which the primary input power supply of each core power supply means is shared among the cores;
An operation lower limit voltage detecting means for detecting an operation lower limit voltage of each core;
A secondary output setting means for setting a secondary output voltage of the power supply means of each core corresponding to a detection value by the operation lower limit voltage detection means. An LSI in which a plurality of cores are stacked. 2. The plurality of cores according to claim 1, wherein the primary input power supply means is a primary power supply line through a via (TSV) penetrating from a common solder ball into each core. LSI. 3. The LSI having a plurality of cores stacked according to claim 2, wherein the LSI has a silicon interposer for each core, and the power supply means for each core is formed in the silicon interposer. 4. The LSI according to claim 3, wherein the power supply means for each core is located in the vicinity of a via (TSV) penetrating through each core. 2. The LSI in which a plurality of cores are stacked according to claim 1, wherein the cores are stacked in the order of the magnitude of the operation lower limit voltage value of each of the cores. 6. The plurality of cores according to claim 5, wherein the cores are stacked in order from the direction in which the heat radiation property is good, in order of decreasing the operation lower limit voltage value of each of the cores. LSI.