JP2014033167A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2014033167A
JP2014033167A JP2012174474A JP2012174474A JP2014033167A JP 2014033167 A JP2014033167 A JP 2014033167A JP 2012174474 A JP2012174474 A JP 2012174474A JP 2012174474 A JP2012174474 A JP 2012174474A JP 2014033167 A JP2014033167 A JP 2014033167A
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integrated circuit
semiconductor integrated
semiconductor device
semiconductor
insulating layer
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Japanese (ja)
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Hidekazu Hosomi
英一 細美
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Toshiba Corp
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Toshiba Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device excellent in heat dissipation in a structure having a plurality of semiconductor chip.SOLUTION: In a semiconductor device, two semiconductor chips are formed so as to face each other and are directly connected to external terminals and a power source or signals. By this structure, a package structure capable of mounting a semiconductor chip with large power consumption can be achieved.

Description

本発明の実施形態は、半導体装置に関する。   Embodiments described herein relate generally to a semiconductor device.

近年、例えば、ロジックデバイスとメモリとの間の信号伝送の高速化を図るため、ロジックＩＣ（Ｉｎｔｅｇｒａｔｅｄ Ｃｉｒｃｕｉｔ）とメモリＩＣとを向き合わせて接続させる、所謂ＣｏＣ（Ｃｈｉｐ ｏｎ Ｃｈｉｐ）技術が実用化されつつある。   In recent years, for example, in order to increase the speed of signal transmission between a logic device and a memory, so-called CoC (Chip on Chip) technology in which a logic IC (Integrated Circuit) and a memory IC are connected to face each other has been put into practical use. It's getting on.

しかし、従来の一般的なＣｏＣ技術では、ＩＣパッケージ全体がモールド樹脂で覆われているため、消費電力の大きいＩＣを搭載することが困難であった。   However, in the conventional general CoC technology, since the entire IC package is covered with the mold resin, it is difficult to mount an IC with high power consumption.

また、新たなＣｏＣ技術の一つであるＳＭＡＦＴＩ（Ｓｍａｒｔ ｃｈｉｐ ｃｏｎｎｅｃｔｉｏｎ ｗｉｔｈ ｆｅｅｄｔｈｒｏｕｇｈ ｉｎｔｅｒｐｏｓｅｒ）技術も検討されている。しかし、ＳＭＡＦＴＩ技術では、ロジックＩＣがＩＣパッケージのＢＧＡ（Ｂａｌｌ−Ｇｒｉｄ Ａｒｒａｙ）面に搭載されることとなるため、実装時に半導体チップが実装ボードに接触する等してダメージが入ることが懸念される。また、ロジックＩＣの放熱が困難なため、従来の一般的なＣｏＣ技術と同様、消費電力が大きいＩＣに対して適用することが困難である。   Also, SMAFTI (Smart chip connection with feedthrough interposer) technology, which is one of the new CoC technologies, has been studied. However, in the SMAFTI technology, since the logic IC is mounted on the BGA (Ball-Grid Array) surface of the IC package, there is a concern that the semiconductor chip may come into contact with the mounting board at the time of mounting and damage may occur. . In addition, since it is difficult to dissipate heat from the logic IC, it is difficult to apply to an IC that consumes a large amount of power as in the conventional general CoC technology.

特開２００８−１９２８１５JP2008-192815

本発明の実施形態は、上記問題点を解決するためになされたもので、複数の半導体チップを有する構造に於いて、放熱性に優れた半導体装置を提供することを目的とする。   Embodiments of the present invention have been made to solve the above problems, and an object of the present invention is to provide a semiconductor device having excellent heat dissipation in a structure having a plurality of semiconductor chips.

上記目的を達成するために、本発明による一形態の半導体装置は、第一の半導体集積回路と、第二の半導体集積回路と、前記第一の半導体集積回路および前記第二の半導体集積回路との間に形成される絶縁層と、前記絶縁層内に形成されるビアおよび導体層と、前記第二の半導体集積回路を、回路面が露出するように覆うモールド樹脂と、前記モールド樹脂内に形成されたスルーホールを介して前記導体層と接続される外部端子とを具備し、前記第一の半導体集積回路と前記第二の半導体集積回路とは、互いの回路面が向かい合って形成されると共に、前記ビアおよび前記導体層を介して互いに電気的に接続されており、ひいては前記スルーホールを介して前記外部端子に電気的に接続されていることを特徴とする。   In order to achieve the above object, a semiconductor device according to an embodiment of the present invention includes a first semiconductor integrated circuit, a second semiconductor integrated circuit, the first semiconductor integrated circuit, and the second semiconductor integrated circuit. An insulating layer formed between, a via and a conductor layer formed in the insulating layer, a mold resin that covers the second semiconductor integrated circuit so that a circuit surface is exposed, and the mold resin An external terminal connected to the conductor layer through the formed through hole, and the first semiconductor integrated circuit and the second semiconductor integrated circuit are formed with their circuit surfaces facing each other. At the same time, they are electrically connected to each other through the via and the conductor layer, and thus are electrically connected to the external terminal through the through hole.

また、本発明による他の形態の半導体装置は、第一の半導体集積回路と、第二の半導体集積回路と、前記第一の半導体集積回路および前記第二の半導体集積回路との間に形成される絶縁層と、前記絶縁層内に形成されるビアおよび導体層と、前記第二の半導体集積回路を、回路面が露出するように覆うモールド樹脂と、前記モールド樹脂内に形成されたスルーホールを介して前記導体層と接続される外部端子と、前記外部端子と接するように形成されたパッケージ基板と、前記第一の半導体集積回路、前記第二の半導体集積回路、前記モールド樹脂、および前記外部端子を覆うように形成されたヒートスプレッダとを具備し、前記第一の半導体集積回路と前記第二の半導体集積回路とは、互いの回路面が向かい合って形成されると共に、前記ビアおよび前記導体層を介して互いに電気的に接続されており、ひいては前記スルーホールを介して前記外部端子に接続されていること、および、前記第二の半導体集積回路と前記ヒートスプレッダとが熱伝導材を介して接していることを特徴とする。   According to another aspect of the present invention, there is provided a semiconductor device formed between a first semiconductor integrated circuit, a second semiconductor integrated circuit, the first semiconductor integrated circuit, and the second semiconductor integrated circuit. An insulating layer, a via and a conductor layer formed in the insulating layer, a mold resin that covers the second semiconductor integrated circuit so that a circuit surface is exposed, and a through hole formed in the mold resin An external terminal connected to the conductor layer through the package substrate, a package substrate formed so as to be in contact with the external terminal, the first semiconductor integrated circuit, the second semiconductor integrated circuit, the mold resin, and the A heat spreader formed to cover an external terminal, and the first semiconductor integrated circuit and the second semiconductor integrated circuit are formed with their circuit surfaces facing each other, and Are electrically connected to each other through the conductor layer, and are connected to the external terminal through the through hole, and the second semiconductor integrated circuit and the heat spreader are in thermal conduction. It is in contact with each other through a material.

本発明の実施形態に係る半導体装置のモジュール構造を示す断面図。Sectional drawing which shows the module structure of the semiconductor device which concerns on embodiment of this invention. 本発明の実施形態に係る半導体装置のパッケージ構造を示す断面図。Sectional drawing which shows the package structure of the semiconductor device which concerns on embodiment of this invention. 本発明の実施形態に係る半導体装置の形成工程を工程順に示した断面図。Sectional drawing which showed the formation process of the semiconductor device which concerns on embodiment of this invention to process order. 本発明の実施形態に係る半導体装置の形成工程を工程順に示した断面図。Sectional drawing which showed the formation process of the semiconductor device which concerns on embodiment of this invention to process order. 本発明の実施形態に係る半導体装置の形成工程を工程順に示した断面図。Sectional drawing which showed the formation process of the semiconductor device which concerns on embodiment of this invention to process order. 本発明の実施形態に係る半導体装置の形成工程を工程順に示した断面図。Sectional drawing which showed the formation process of the semiconductor device which concerns on embodiment of this invention to process order. 本発明のその他の実施形態に係る半導体装置のパッケージ構造を示す断面図。Sectional drawing which shows the package structure of the semiconductor device which concerns on other embodiment of this invention.

本発明の実施形態を以下に図面を参照して説明する。   Embodiments of the present invention will be described below with reference to the drawings.

本発明の実施形態に於いては、ＣｏＣ技術によって接続される全てのＩＣが、外部接続端子によって直接電源等と接続されること、および消費電力の大きいＩＣを搭載可能とすることを特徴としている。   The embodiment of the present invention is characterized in that all ICs connected by the CoC technology are directly connected to a power source or the like by an external connection terminal, and an IC with high power consumption can be mounted. .

先ず、本発明の実施形態による半導体装置のモジュールＭの構造について説明する。   First, the structure of the module M of the semiconductor device according to the embodiment of the present invention will be described.

図１は、本発明の実施形態に係る半導体装置のモジュール構造を示す断面図である。   FIG. 1 is a cross-sectional view showing a module structure of a semiconductor device according to an embodiment of the present invention.

図１に示すように、フェイス・ダウン接続される消費電力の大きな第一のＩＣ１、例えばロジックＩＣと、第一のＩＣ１より消費電力が小さくフェイス・アップ接続される第二のＩＣ２、例えばメモリＩＣとが、第一の絶縁層３および第二の絶縁層４内に複数形成されたビア５を介して向き合わせに接続される。   As shown in FIG. 1, a first IC 1 having a large power consumption, such as a logic IC, which is connected face-down, and a second IC 2 having a power consumption smaller than that of the first IC 1, for example, a memory IC. Are connected to face each other through a plurality of vias 5 formed in the first insulating layer 3 and the second insulating layer 4.

第一の絶縁膜３および第二の絶縁膜４内には各ＩＣから配線を引き出すための第一の導体層６および第二の導体層７が形成されている。   In the first insulating film 3 and the second insulating film 4, a first conductor layer 6 and a second conductor layer 7 are formed for drawing out wiring from each IC.

第一のＩＣ１および第一の絶縁層３は、接続用パッド８および半田等の低融点金属からなるバンプ９により互いが接続されており、第一のＩＣ１および第一の絶縁層３間はアンダーフィル１０によって覆われている。各バンプ９同士の間隔は４０−５０μｍ程度である。尚、第二のＩＣ２はモールド樹脂１１内に形成されている。   The first IC 1 and the first insulating layer 3 are connected to each other by a connection pad 8 and a bump 9 made of a low melting point metal such as solder, and the first IC 1 and the first insulating layer 3 are underscored. Covered by the fill 10. The interval between the bumps 9 is about 40-50 μm. The second IC 2 is formed in the mold resin 11.

モールド樹脂１１内に形成された第二のＩＣ２は、モールド樹脂１１を貫通するように形成されたスルーホール１２を介して、複数の第一の外部端子１３、例えばはんだボール、と第一の導体層６および第二の導体層７とに接続されている。   The second IC 2 formed in the mold resin 11 has a plurality of first external terminals 13 such as solder balls and a first conductor through a through hole 12 formed so as to penetrate the mold resin 11. It is connected to the layer 6 and the second conductor layer 7.

各第一の外部端子１３同士の間隔を２００μｍ程度とすることで、通常のフリップチップ技術を用いたデバイスと同様に扱うことができ、フリップチップ・パッケージに搭載することが可能となる。   By setting the interval between the first external terminals 13 to about 200 μm, it can be handled in the same manner as a device using a normal flip chip technology, and can be mounted on a flip chip package.

次に、本発明の実施形態による半導体装置のパッケージＰの構造について説明する。   Next, the structure of the package P of the semiconductor device according to the embodiment of the present invention will be described.

図２は、図１に示したモジュールＭを含んだ、本発明の実施形態に係る半導体装置のパッケージ構造を示す断面図である。   FIG. 2 is a cross-sectional view showing the package structure of the semiconductor device according to the embodiment of the present invention, including the module M shown in FIG.

図２に示すように、モジュールＭはパッケージ基板１４上に形成され、接着剤１５によってパッケージ基板１４と接続されているヒートスプレッダ１６によって覆われている。第一のＩＣ１とヒートスプレッダ１６とは、熱伝導材１７を介して接している。また、パッケージ基板１４のモジュールＭが形成されていない下面には、複数の第二の外部端子１８、例えばはんだボールが形成されている。   As shown in FIG. 2, the module M is formed on the package substrate 14 and covered with a heat spreader 16 connected to the package substrate 14 with an adhesive 15. The first IC 1 and the heat spreader 16 are in contact with each other via a heat conductive material 17. A plurality of second external terminals 18, for example, solder balls, are formed on the lower surface of the package substrate 14 where the module M is not formed.

図２に示したパッケージＰの構造では、放熱用のヒートスプレッダ１６が熱伝導材１７を介して第一のＩＣ１に搭載され、第一のＩＣ１がモールド樹脂等で覆われていないため、第一のＩＣ１の消費電力が大きく多くの熱を放出する場合でも対応することが可能となる。   In the structure of the package P shown in FIG. 2, the heat spreader 16 for heat dissipation is mounted on the first IC 1 via the heat conductive material 17, and the first IC 1 is not covered with a mold resin or the like. It is possible to cope with the case where the power consumption of the IC 1 is large and a large amount of heat is released.

次に、図３から図６を参照して、本発明の実施形態において、上述したモジュールＭおよびパッケージＰの製造方法を説明する。   Next, a method for manufacturing the module M and the package P described above in the embodiment of the present invention will be described with reference to FIGS.

先ず、図３（ａ）に示すように、支持基板１９と第二のＩＣ２とを接着材料２０を介して貼り付け、図３（ｂ）に示すように、接着材料２０を介して支持基板１９上に第二のＩＣ２を覆うようにモールド樹脂１１を形成する。この際、ＩＣの表面（素子が形成されている面）を支持基板１９に対向するように貼り付ける。尚、図示しないが、支持基板１９上に複数のＩＣを貼り付けることも可能である。次に、図３（ｃ）に示すように、支持基板１９および接着材料２０の剥離を行い、必要に応じて、余剰の接着材料２０を除去するための洗浄を行う。これにより、モールド樹脂１１内に第二のＩＣ２が埋め込まれ、ＩＣ表面が露出した状態となる。   First, as shown in FIG. 3A, the support substrate 19 and the second IC 2 are attached via the adhesive material 20, and as shown in FIG. 3B, the support substrate 19 is interposed via the adhesive material 20. A mold resin 11 is formed on the second IC 2 so as to cover the second IC 2. At this time, the surface of the IC (the surface on which the element is formed) is attached so as to face the support substrate 19. Although not shown, a plurality of ICs can be pasted on the support substrate 19. Next, as shown in FIG. 3C, the support substrate 19 and the adhesive material 20 are peeled off, and cleaning is performed as necessary to remove the excess adhesive material 20. As a result, the second IC 2 is embedded in the mold resin 11 and the IC surface is exposed.

以降に記載する図４乃至図６に関しては、図３と比較し上下反転した図となっている。   4 to 6 to be described later are upside down in comparison with FIG.

そして、図４（ａ）に示すように、モールド樹脂１１および露出した第二のＩＣ２表面上に第一の絶縁層３を形成する。絶縁層の材料としては、無機材料（例えば、ＳｉＯ２等。）あるいは有機系材料（例えば、ポリイミド、プリプレグ等。）のどちらでも使用することができる。次に、図４（ｂ）および（ｃ）に示すように、第一の絶縁層３内にビア５を形成後、第二のＩＣ２から配線を引き出すための第一の導体層６を形成する。必要に応じて上記工程を繰り返すことで、絶縁層と導体層とを幾重にも重ね合わせることが可能あるが、本実施形態においては、第一の絶縁層３上に第二の絶縁層４が、そして第二の絶縁層４内にビア５および第二の導体層７が形成された構造を有している。最上層の絶縁層および導体層、即ち本実施形態における第二の絶縁層４および第二の導体層７上に、外部への接続用パッド８を形成する。更にその上に半田等の低融点金属やＮｉ等の金属層を形成することも可能だが、本実施形態においてはバンプ９が形成されている。そして、バンプ９上に第一のＩＣ１をフリップチップ搭載する。   Then, as shown in FIG. 4A, the first insulating layer 3 is formed on the mold resin 11 and the exposed second IC 2 surface. As the material of the insulating layer, either an inorganic material (for example, SiO 2) or an organic material (for example, polyimide, prepreg) can be used. Next, as shown in FIGS. 4B and 4C, after forming the via 5 in the first insulating layer 3, the first conductor layer 6 for drawing the wiring from the second IC 2 is formed. . By repeating the above steps as necessary, the insulating layer and the conductor layer can be stacked several times, but in the present embodiment, the second insulating layer 4 is formed on the first insulating layer 3. The via 5 and the second conductor layer 7 are formed in the second insulating layer 4. A pad 8 for connection to the outside is formed on the uppermost insulating layer and conductor layer, that is, on the second insulating layer 4 and the second conductor layer 7 in this embodiment. Further, a low melting point metal such as solder or a metal layer such as Ni can be formed thereon, but in this embodiment, bumps 9 are formed. Then, the first IC 1 is flip-chip mounted on the bump 9.

そして、図５（ａ）に示すように、第一のＩＣ１と第二の絶縁層４の間に保護用の樹脂（アンダーフィル１０）の注入を行う。尚、本工程は、図４に示すフリップチップ搭載と同時に行うことも可能である。その後、図５（ｂ）に示すように、モールド樹脂１１にレーザー等により、第一の導体層６の下面が露出するようにスルーホール１２を形成し、図６（ａ）に示すように、スルーホール１２内に導体材料（例えば、半田ペースト。）を埋め込む。そして、図６（ｂ）に示すように、導体材料の埋め込まれたスルーホール１２の下面に接するように第一の外部端子１３（例えば、半田ボール。）を形成し、モジュールＭが完成する。   Then, as shown in FIG. 5A, a protective resin (underfill 10) is injected between the first IC 1 and the second insulating layer 4. This step can be performed simultaneously with the flip chip mounting shown in FIG. Thereafter, as shown in FIG. 5B, a through hole 12 is formed in the mold resin 11 with a laser or the like so that the lower surface of the first conductor layer 6 is exposed. As shown in FIG. A conductive material (for example, solder paste) is embedded in the through hole 12. Then, as shown in FIG. 6B, the first external terminal 13 (for example, a solder ball) is formed so as to be in contact with the lower surface of the through hole 12 in which the conductor material is embedded, and the module M is completed.

図６（ｂ）のモジュールＭに、通常の方法によりパッケージングを行ったものが、図２に示したパッケージＰである。尚、図７に示すように、パッケージ基板１４上にモジュールＭを形成し、第一のＩＣ１上に熱伝導材１７を介してヒートシンク２１を形成することも可能である。   A package P shown in FIG. 2 is obtained by packaging the module M in FIG. 6B by a normal method. As shown in FIG. 7, the module M can be formed on the package substrate 14 and the heat sink 21 can be formed on the first IC 1 via the heat conductive material 17.

本発明は、上記実施形態に限定されるものではなく、発明の要旨を逸脱しない範囲で、種々、変更して実施してもよいことは勿論である。   The present invention is not limited to the above-described embodiment, and it is needless to say that various modifications may be made without departing from the spirit of the invention.

１ 第一のＩＣ
２ 第二のＩＣ
３ 第一の絶縁層
４ 第二の絶縁層
５ ビア
６ 第一の導体層
７ 第二の導体層
８ 接続用パッド
９ バンプ
１０ アンダーフィル
１１ モールド樹脂
１２ スルーホール
１３ 第一の外部端子
１４ パッケージ基板
１５ 接着剤
１６ ヒートスプレッダ
１７ 熱伝導材
１８ 第二の外部端子
１９ 支持基板
２０ 接着材料
２１ ヒートシンク
Ｍ モジュール
Ｐ パッケージ 1 First IC
2 Second IC
3 First insulating layer 4 Second insulating layer 5 Via 6 First conductor layer 7 Second conductor layer 8 Connection pad 9 Bump 10 Underfill 11 Mold resin 12 Through hole 13 First external terminal 14 Package substrate 15 Adhesive 16 Heat Spreader 17 Thermal Conductive Material 18 Second External Terminal 19 Support Substrate 20 Adhesive Material 21 Heat Sink M Module P Package

Claims (5)

第一の半導体集積回路と、
第二の半導体集積回路と、
前記第一の半導体集積回路および前記第二の半導体集積回路との間に形成される絶縁層と、
前記絶縁層内に形成されるビアおよび導体層と、
前記第二の半導体集積回路を、回路面が露出するように覆うモールド樹脂と、
前記モールド樹脂内に形成されたスルーホールを介して前記導体層と接続される外部端子と、
を具備し、
前記第一の半導体集積回路と前記第二の半導体集積回路とは、互いの回路面が向かい合って形成されると共に、前記ビアおよび前記導体層を介して互いに電気的に接続されており、ひいては前記スルーホールを介して前記外部端子に電気的に接続されていることを特徴とする半導体装置。 A first semiconductor integrated circuit;
A second semiconductor integrated circuit;
An insulating layer formed between the first semiconductor integrated circuit and the second semiconductor integrated circuit;
Vias and conductor layers formed in the insulating layer;
Mold resin that covers the second semiconductor integrated circuit so that the circuit surface is exposed;
External terminals connected to the conductor layer through through holes formed in the mold resin,
Comprising
The first semiconductor integrated circuit and the second semiconductor integrated circuit are formed so that their circuit surfaces face each other, and are electrically connected to each other via the via and the conductor layer, and as a result A semiconductor device, wherein the semiconductor device is electrically connected to the external terminal through a through hole. 前記第一の半導体集積回路が論理集積回路であり、前記第二の半導体集積回路がメモリ集積回路であることを特徴とする請求項１記載の半導体装置。   2. The semiconductor device according to claim 1, wherein the first semiconductor integrated circuit is a logic integrated circuit, and the second semiconductor integrated circuit is a memory integrated circuit. 前記第二の半導体集積回路と比較して前記第一の半導体集積回路の方が、消費する電力が大きいことを特徴とする請求項１記載の半導体装置。   2. The semiconductor device according to claim 1, wherein the first semiconductor integrated circuit consumes more power than the second semiconductor integrated circuit. 前記外部端子が、２００マイクロメートル程度の間隔で複数個形成されることを特徴とする請求項１記載の半導体装置。   2. The semiconductor device according to claim 1, wherein a plurality of the external terminals are formed at intervals of about 200 micrometers. 第一の半導体集積回路と、
第二の半導体集積回路と、
前記第一の半導体集積回路および前記第二の半導体集積回路との間に形成される絶縁層と、
前記絶縁層内に形成されるビアおよび導体層と、
前記第二の半導体集積回路を、回路面が露出するように覆うモールド樹脂と、
前記モールド樹脂内に形成されたスルーホールを介して前記導体層と接続される外部端子と、
前記外部端子と接するように形成されたパッケージ基板と、
前記第一の半導体集積回路、前記第二の半導体集積回路、前記モールド樹脂、および前記外部端子を覆うように形成されたヒートスプレッダと、
を具備し、
前記第一の半導体集積回路と前記第二の半導体集積回路とは、互いの回路面が向かい合って形成されると共に、前記ビアおよび前記導体層を介して互いに電気的に接続されており、ひいては前記スルーホールを介して前記外部端子に接続されていること、
および、前記第二の半導体集積回路と前記ヒートスプレッダとが熱伝導材を介して接していることを特徴とする半導体装置。 A first semiconductor integrated circuit;
A second semiconductor integrated circuit;
An insulating layer formed between the first semiconductor integrated circuit and the second semiconductor integrated circuit;
Vias and conductor layers formed in the insulating layer;
Mold resin that covers the second semiconductor integrated circuit so that the circuit surface is exposed;
External terminals connected to the conductor layer through through holes formed in the mold resin,
A package substrate formed in contact with the external terminal;
A heat spreader formed so as to cover the first semiconductor integrated circuit, the second semiconductor integrated circuit, the mold resin, and the external terminals;
Comprising
The first semiconductor integrated circuit and the second semiconductor integrated circuit are formed so that their circuit surfaces face each other, and are electrically connected to each other via the via and the conductor layer, and as a result Connected to the external terminal through a through hole;
The semiconductor device is characterized in that the second semiconductor integrated circuit and the heat spreader are in contact with each other through a heat conductive material.
JP2012174474A 2012-08-06 2012-08-06 Semiconductor device Pending JP2014033167A (en)

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