JP2014033100A - Mounting method - Google Patents

Mounting method Download PDF

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JP2014033100A
JP2014033100A JP2012173094A JP2012173094A JP2014033100A JP 2014033100 A JP2014033100 A JP 2014033100A JP 2012173094 A JP2012173094 A JP 2012173094A JP 2012173094 A JP2012173094 A JP 2012173094A JP 2014033100 A JP2014033100 A JP 2014033100A
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Prior art keywords
bonding
substrate
chip
metal layer
chips
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Takanori Akeda
孝典 明田
Yoshiharu Sanagawa
佳治 佐名川
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Panasonic Corp
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Panasonic Corp
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Priority to JP2012173094A priority Critical patent/JP2014033100A/en
Priority to PCT/JP2013/001597 priority patent/WO2014020790A1/en
Priority to TW102110512A priority patent/TW201407693A/en
Publication of JP2014033100A publication Critical patent/JP2014033100A/en
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K20/00—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
    • B23K20/02—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating by means of a press ; Diffusion bonding
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
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    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2101/00—Articles made by soldering, welding or cutting
    • B23K2101/36—Electric or electronic devices
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Abstract

PROBLEM TO BE SOLVED: To provide a mounting method capable of reducing the tact time.SOLUTION: The mounting method for mounting plural chips 2 onto a base board 1 includes: a temporary joint process to pre-bond each of the chips 2 to the base board 1; and a full-bonding process to fully bond each of the chips 2 which are pre-bonded on the base board 1 to base board 1. In the temporary joint process, a first basic step including a first step and a second step repeats by the times identical to the number of the chips 2 to be mounted on the base board 1. In the first step, positioning is made between a first metal layer 11 of the base board 1 and a second metal layer 21 of the chips 2. In the second step, the pre-bonding is made between the second metal layer 21 and the first metal layer 11 by using the solid phase diffusion bonding. In full bonding process, the second metal layer 21 of the chips 2 and the first metal layers 11 of the base board 1 which are pre-bonded on the base board 1 are fully bonded on the base board 1 using the liquid phase diffusion bonding.

Description

本発明は、基板上に複数個のチップを実装する実装方法に関するものである。   The present invention relates to a mounting method for mounting a plurality of chips on a substrate.

従来から、基板上に複数個のチップを実装する実装方法が知られている（例えば、特許文献１）。特許文献１に記載された実装方法は、ダイボンド装置のステージの表面側に基板を載置する基板載置工程と、チップとステージの表面側に載置された基板との互いの接合面を接触させチップ側から加熱することによりチップと基板との互いの接合面を加熱して両者を接合させる接合工程とを備えている。   Conventionally, a mounting method for mounting a plurality of chips on a substrate is known (for example, Patent Document 1). In the mounting method described in Patent Document 1, the substrate mounting step of mounting the substrate on the surface side of the stage of the die bonding apparatus and the bonding surfaces of the chip and the substrate mounted on the surface side of the stage are brought into contact with each other. And a bonding step of heating the bonding surfaces of the chip and the substrate to bond them together by heating from the chip side.

基板載置工程においては、基板におけるチップの接合予定領域とステージとの間に断熱層が介在する形で基板をステージの表面側に載置する。チップとしては、厚み方向の両面に電極（図示せず）が形成されたＬＥＤチップが例示されている。このＬＥＤチップは、裏面側（基板に近い側）の電極からなるチップ側接合用電極がＡｕＳｎにより形成されている。また、基板としては、シリコンウェハを用いて形成されたものが例示されている。この基板は、各チップそれぞれの接合予定領域（搭載位置）に、基板側接合用電極としてダイパッド部が形成されている。ダイパッド部は、Ｔｉ膜と当該Ｔｉ膜上に形成されたＡｕ膜との積層構造を有しており、表面側の部位がＡｕにより形成されている。   In the substrate placing step, the substrate is placed on the surface side of the stage in such a manner that a heat insulating layer is interposed between the region where the chip is to be bonded to the substrate and the stage. As the chip, an LED chip in which electrodes (not shown) are formed on both surfaces in the thickness direction is illustrated. In this LED chip, a chip-side bonding electrode composed of an electrode on the back surface side (side closer to the substrate) is formed of AuSn. In addition, as the substrate, a substrate formed using a silicon wafer is illustrated. In this substrate, a die pad portion is formed as a substrate-side bonding electrode in each bonding planned region (mounting position) of each chip. The die pad portion has a laminated structure of a Ti film and an Au film formed on the Ti film, and a portion on the surface side is formed of Au.

接合工程では、所定の過程を、ウェハに実装するＬＥＤチップの個数に応じて繰り返し行う。所定の過程では、ダイボンド装置のヘッドに設けられた吸着コレットによりＬＥＤチップを吸着保持し、ヘッドのヒータにより吸着コレットを介してＬＥＤチップを規定の接合温度に加熱した状態で、チップ側接合用電極と基板側接合用電極との接合面同士を接触させ、ヘッド側からＬＥＤチップに適宜の圧力を規定時間だけ印加することにより、チップ側接合用電極と基板側接合用電極とを共晶接合させる。規定の接合温度は、例えば、チップ側接合用電極の材料であるＡｕＳｎの溶融温度よりも高い温度である。また、適宜の圧力は、例えば、２〜５０ｋｇ／ｃｍ２である。また、規定時間は、例えば、１０秒程度である。 In the bonding step, a predetermined process is repeated according to the number of LED chips mounted on the wafer. In a predetermined process, the LED chip is adsorbed and held by the adsorption collet provided in the head of the die bonding apparatus, and the LED chip is heated to a prescribed bonding temperature via the adsorption collet by the head heater, and the chip side bonding electrode The contact surfaces of the substrate side bonding electrode and the substrate side bonding electrode are brought into contact with each other, and an appropriate pressure is applied to the LED chip from the head side for a specified time to eutectically bond the chip side bonding electrode and the substrate side bonding electrode. . The prescribed bonding temperature is, for example, a temperature higher than the melting temperature of AuSn that is a material of the chip-side bonding electrode. Moreover, a suitable pressure is 2-50 kg / cm < 2 >, for example. The specified time is, for example, about 10 seconds.

特開２００９−１３０２９３号公報JP 2009-130293 A

ところで、特許文献１に記載された実装方法では、チップを吸着コレットにより吸着する前に、ダイボンド装置の認識装置によりチップを高精度に認識する必要があると推考される。さらに、特許文献１に記載された実装方法では、チップ側接合用電極と基板側接合用電極との接触面同士を接触させる前に、ステージの表面側の基板における接合予定領域を認識装置により高精度に認識し、チップと基板とを位置合わせする必要があると推考される。また、特許文献１に記載された実装方法の接合工程では、上述の所定の過程を、ウェハに実装するＬＥＤチップの個数に応じて繰り返し行う必要がある。このため、上述の実装方法では、生産ラインにおける実装工程のタクトタイムの短縮化が難しく、実装工程のスループットの向上が難しい。なお、認識装置は、カメラ、画像処理部及びモニタにより構成されるのが一般的である。   By the way, in the mounting method described in Patent Document 1, it is presumed that the chip needs to be recognized with high accuracy by the recognition device of the die bonding apparatus before the chip is sucked by the suction collet. Furthermore, in the mounting method described in Patent Document 1, before the contact surfaces of the chip-side bonding electrode and the substrate-side bonding electrode are brought into contact with each other, the bonding scheduled region on the substrate on the surface side of the stage is increased by a recognition device. It is assumed that it is necessary to recognize the accuracy and align the chip and the substrate. Further, in the bonding step of the mounting method described in Patent Document 1, it is necessary to repeat the above-described predetermined process according to the number of LED chips mounted on the wafer. For this reason, in the mounting method described above, it is difficult to shorten the tact time of the mounting process in the production line, and it is difficult to improve the throughput of the mounting process. Note that the recognition device is generally configured by a camera, an image processing unit, and a monitor.

本発明は上記事由に鑑みて為されたものであり、その目的は、タクトタイムの短縮化を図ることが可能な実装方法を提供することにある。   The present invention has been made in view of the above-described reasons, and an object thereof is to provide a mounting method capable of shortening the tact time.

本発明の実装方法は、基板上に複数個のチップを実装する実装方法であって、前記基板に前記各チップの各々を仮接合する仮接合工程と、前記基板に仮接合された前記各チップの各々を前記基板に本接合する本接合工程とを備え、前記仮接合工程は、前記基板の第１金属層と前記チップの第２金属層とを位置合わせする第１ステップと、前記第１ステップの後に前記チップ側から加圧して前記チップの前記第２金属層と前記基板の前記第１金属層とを固相拡散接合することで前記基板に前記チップを仮接合する第２ステップとからなる第１基本工程を、前記基板に実装する前記チップの数だけ繰り返し、前記本接合工程では、前記基板に仮接合されている前記各チップの各々の前記第２金属層と前記基板の前記各第１金属層とを液相拡散接合することで前記各チップを一括して前記基板に本接合する。   The mounting method of the present invention is a mounting method for mounting a plurality of chips on a substrate, wherein each chip is temporarily bonded to the substrate, and each chip temporarily bonded to the substrate. And a first bonding step of aligning the first metal layer of the substrate and the second metal layer of the chip, and the first bonding step of bonding the first metal layer to the substrate. After the step, the second step of temporarily bonding the chip to the substrate by applying pressure from the chip side and solid-phase diffusion bonding the second metal layer of the chip and the first metal layer of the substrate. The first basic step is repeated by the number of the chips to be mounted on the substrate. In the main bonding step, the second metal layer of each of the chips temporarily bonded to the substrate and each of the substrates Liquid phase diffusion bonding with the first metal layer Collectively the respective chips Rukoto be present bonded to the substrate.

この実装方法において、前記固相拡散接合は、第１規定温度で行い、前記液相拡散接合は、前記第１規定温度よりも高い第２規定温度で行うようにし、前記第２規定温度は、前記各チップ側と前記基板側との少なくとも一方の加熱により到達させる温度であることが好ましい。   In this mounting method, the solid phase diffusion bonding is performed at a first specified temperature, the liquid phase diffusion bonding is performed at a second specified temperature higher than the first specified temperature, and the second specified temperature is The temperature is preferably reached by heating at least one of the chip side and the substrate side.

この実装方法において、前記固相拡散接合は、超音波接合もしくは表面活性化接合であることが好ましい。   In this mounting method, the solid phase diffusion bonding is preferably ultrasonic bonding or surface activated bonding.

請求項１の発明は、タクトタイムの短縮化を図ることが可能になるという効果がある。   The invention of claim 1 has an effect that the tact time can be shortened.

実施形態の実装方法の説明図である。It is explanatory drawing of the mounting method of embodiment. 実施形態の実装方法における第１基本工程の説明図である。It is explanatory drawing of the 1st basic process in the mounting method of embodiment. 実施形態の実装方法における基板へのチップの実装形態の説明図である。It is explanatory drawing of the mounting form of the chip | tip on the board | substrate in the mounting method of embodiment. 実施形態の実装方法における第１基本工程の他の説明図である。It is another explanatory view of the 1st basic process in the mounting method of an embodiment. 実施形態の実装方法における第１基本工程の更に他の説明図である。It is another explanatory view of the 1st basic process in the mounting method of an embodiment. 実施形態の実装方法における第１基本工程の別の説明図である。It is another explanatory drawing of the 1st basic process in the mounting method of an embodiment.

以下では、本実施形態の実装方法について、図１〜図６に基づいて説明する。なお、図１（ａ）〜（ｃ）は、各々の左側の図が概略斜視図、右側の図が概略断面図である。   Below, the mounting method of this embodiment is demonstrated based on FIGS. In FIGS. 1A to 1C, the left side of each figure is a schematic perspective view, and the right side figure is a schematic cross-sectional view.

本実施形態の実装方法は、図１（ｃ）に示すように、基板１上に複数個のチップ２を実装する実装方法である。この実装方法は、基板１に各チップ２の各々を仮接合する仮接合工程（図１（ａ）参照）と、基板１に仮接合された各チップ２の各々を基板１に本接合する本接合工程（図１（ｂ）参照）とを備える。この実装方法では、仮接合の後よりも本接合の後のほうが、基板１と各チップ２の各々との接合強度が高くなる。   The mounting method of this embodiment is a mounting method of mounting a plurality of chips 2 on a substrate 1 as shown in FIG. In this mounting method, a temporary bonding step (see FIG. 1A) for temporarily bonding each of the chips 2 to the substrate 1 and a main bonding of each of the chips 2 temporarily bonded to the substrate 1 to the substrate 1 are performed. Joining process (refer FIG.1 (b)). In this mounting method, the bonding strength between the substrate 1 and each of the chips 2 is higher after the main bonding than after the temporary bonding.

仮接合工程は、第１基本工程を、基板１に実装するチップ２の数だけ繰り返す。第１基本工程は、第１ステップと、第２ステップとからなる。   In the temporary bonding process, the first basic process is repeated by the number of chips 2 mounted on the substrate 1. The first basic process includes a first step and a second step.

第１ステップでは、基板１の第１金属層１１とチップ２の第２金属層２１とを位置合わせする。   In the first step, the first metal layer 11 of the substrate 1 and the second metal layer 21 of the chip 2 are aligned.

第２ステップでは、第１ステップの後にチップ２側から加圧してチップ２の第２金属層２１と基板１の第１金属層１１とを第１規定温度において固相拡散接合することで基板１にチップ２を仮接合する。固相拡散接合は、チップ２の第２金属層２１と基板１の第１金属層１１との接合面間を固相状態で接合する方法である。第１規定温度は、第２金属層２１及び第１金属層１１が溶融しない温度に設定する。仮接合は、本接合の前に基板１の定められた位置にチップ２を位置決めした状態で保持するための接合を意味している。   In the second step, the substrate 1 is subjected to solid-phase diffusion bonding at the first specified temperature by applying pressure from the chip 2 side after the first step and bonding the second metal layer 21 of the chip 2 and the first metal layer 11 of the substrate 1. The chip 2 is temporarily joined to. The solid phase diffusion bonding is a method in which the bonding surfaces of the second metal layer 21 of the chip 2 and the first metal layer 11 of the substrate 1 are bonded in a solid state. The first specified temperature is set to a temperature at which the second metal layer 21 and the first metal layer 11 do not melt. Temporary bonding means bonding for holding the chip 2 in a state where the chip 2 is positioned at a predetermined position of the substrate 1 before the main bonding.

本接合工程は、基板１に仮接合されている各チップ２の各々の第２金属層２１と基板１の各第１金属層１１とを液相拡散接合することで各チップ２を基板１に本接合する。これにより、各チップ２の各々は、第２金属層２１と第１金属層１１との合金層からなる接合層３１を介して基板１に接合される。本接合は、各チップ２の各々と基板１との接合状態を、より接合強度が高く且つ安定した接合状態とする最終的な接合を意味している。本接合工程では、各チップ２の各々の第２金属層２１と基板１の各第１金属層１１とを第２規定温度において液相拡散接合する。第２規定温度は、第２金属層２１及び第１金属層１１が溶融する温度に設定する。したがって、第２規定温度は、相対的に第１規定温度よりも高い温度に設定する。   In this bonding step, each chip 2 is bonded to the substrate 1 by liquid phase diffusion bonding of each second metal layer 21 of each chip 2 temporarily bonded to the substrate 1 and each first metal layer 11 of the substrate 1. This is joined. Thereby, each of the chips 2 is bonded to the substrate 1 via the bonding layer 31 made of an alloy layer of the second metal layer 21 and the first metal layer 11. The main bonding means a final bonding in which the bonding state between each chip 2 and the substrate 1 is a bonding state having a higher bonding strength and a stable bonding state. In the main bonding step, each second metal layer 21 of each chip 2 and each first metal layer 11 of the substrate 1 are liquid phase diffusion bonded at a second specified temperature. The second specified temperature is set to a temperature at which the second metal layer 21 and the first metal layer 11 are melted. Therefore, the second specified temperature is set to a temperature that is relatively higher than the first specified temperature.

仮接合工程と本接合工程とは、別々の設備を用いて行うことができる。ところで、生産ラインにおいては、基板１に複数個のチップ２を実装する実装工程に複数の基板１が仕掛かることになる。これに対し、本実施形態の実装方法では、仮接合工程と本接合工程とを別々の設備を用いて行うことができるので、互いに異なる２枚の基板１に対して仮接合工程と本接合工程とを並行して行うことができる。ここで、仮接合工程は、第２ステップにおいて第２金属層２１と第１金属層１１とを固相拡散接合することで仮接合するので、第１ステップの後に続けて液相拡散接合を行う場合に比べて、所要時間（作業時間）を短くすることとが可能となる。また、本接合工程は、基板１に各チップ２が仮接合された状態で各チップ２の各々の第２金属層２１と基板１の各第１金属層１１とを液相拡散接合することで各チップ２を基板１に本接合するので、第１ステップのようにチップ２を高精度に認識してピックアップする必要がない。これにより、本接合工程では、第１ステップの後に続けて液相拡散接合を行う場合に比べて、所要時間を短くすることが可能となる。よって、本実施形態の実装方法では、仮接合工程と本接合工程とを並行して行うことにより、実装工程のタクトタイムの短縮化を図ることが可能になり、実装工程のスループットの向上を図ることが可能となる。また、特許文献１の実装方法では、ヘッドのヒータにより吸着コレットを介してＬＥＤチップを規定の接合温度に加熱した状態で、チップ側接合用電極と基板側接合用電極との接合面同士を接触させるので、熱ゆらぎや熱膨張などに起因してチップ側接合用電極と基板側接合用電極との高精度の位置合わせが難しい場合も考えられる。これに対し、本実施形態の実装方法では、本接合を行う第２規定温度よりも相対的に低い第１規定温度で仮接合を行うので、高精度の位置合わせが容易になる。   The temporary joining step and the main joining step can be performed using separate facilities. By the way, in the production line, a plurality of substrates 1 are set in a mounting process for mounting a plurality of chips 2 on the substrate 1. On the other hand, in the mounting method of the present embodiment, the temporary bonding step and the main bonding step can be performed using different equipment, so the temporary bonding step and the main bonding step are performed on two different substrates 1. Can be performed in parallel. Here, since the temporary bonding process temporarily bonds the second metal layer 21 and the first metal layer 11 by solid phase diffusion bonding in the second step, the liquid phase diffusion bonding is performed after the first step. Compared to the case, the required time (working time) can be shortened. Further, the main bonding step is performed by liquid phase diffusion bonding of each second metal layer 21 of each chip 2 and each first metal layer 11 of the substrate 1 in a state where each chip 2 is temporarily bonded to the substrate 1. Since each chip 2 is permanently bonded to the substrate 1, it is not necessary to recognize and pick up the chip 2 with high accuracy as in the first step. Thereby, in this joining process, it becomes possible to shorten required time compared with the case where liquid phase diffusion joining is performed after the 1st step. Therefore, in the mounting method of the present embodiment, it is possible to shorten the tact time of the mounting process by performing the temporary bonding process and the main bonding process in parallel, and to improve the throughput of the mounting process. It becomes possible. Further, in the mounting method disclosed in Patent Document 1, the bonding surfaces of the chip-side bonding electrode and the substrate-side bonding electrode are brought into contact with each other in a state where the LED chip is heated to a predetermined bonding temperature via a suction collet by a head heater. Therefore, there may be a case where it is difficult to align the chip-side bonding electrode and the substrate-side bonding electrode with high accuracy due to thermal fluctuation or thermal expansion. On the other hand, in the mounting method according to the present embodiment, the temporary bonding is performed at the first specified temperature that is relatively lower than the second specified temperature at which the main bonding is performed.

仮接合工程と本接合工程とは、別々の設備として、例えば、２つのダイボンド装置を用いることができる。各ダイボンド装置は、ボンディングヘッド、ステージ、認識装置、制御装置などを備えている。ボンディングヘッド、ステージ及び認識装置は、制御装置によって制御される。制御装置は、マイクロコンピュータに適宜のプログラムを搭載することによって構成される主制御部と、主制御部の指示に基づいてボンディングヘッド、ステージ及び認識装置それぞれを制御する個別制御部とを備えている。認識装置は、カメラ、画像処理部及びモニタにより構成される。なお、ダイボンド装置の構成は、特に限定するものではない。また、仮接合工程及び本接合工程それぞれを行う各設備は、ダイボンド装置に限定するものではない。   In the temporary bonding step and the main bonding step, for example, two die bonding apparatuses can be used as separate facilities. Each die bonding device includes a bonding head, a stage, a recognition device, a control device, and the like. The bonding head, stage and recognition device are controlled by a control device. The control device includes a main control unit configured by mounting an appropriate program on the microcomputer, and an individual control unit that controls the bonding head, the stage, and the recognition device based on instructions from the main control unit. . The recognition device includes a camera, an image processing unit, and a monitor. The configuration of the die bonding apparatus is not particularly limited. Moreover, each equipment which performs each of a temporary joining process and a main joining process is not limited to a die-bonding apparatus.

以下では説明の便宜上、仮接合工程を行うダイボンド装置を第１ダイボンド装置、本接合工程を行うダイボンド装置を第２ダイボンド装置と称する。   Hereinafter, for convenience of explanation, the die bonding apparatus that performs the temporary bonding process is referred to as a first die bonding apparatus, and the die bonding apparatus that performs the main bonding process is referred to as a second die bonding apparatus.

基板１としては、例えば、シリコンウェハから形成され各チップ２の搭載予定領域の各々に第１金属層１１が設けられたウェハを採用することができる。基板１は、シリコンウェハから形成されたウェハの場合、シリコンウェハの表面にシリコン酸化膜などからなる絶縁膜が形成されているのが好ましい。第１金属層１１は、例えば、Ａｕ膜により構成することができる。第１金属層１１と絶縁膜との間には、例えば、Ｔｉ膜などの下地層を介在させてもよい。第１金属層１１がＡｕ膜であり、絶縁膜がシリコン酸化膜である場合、Ｔｉ膜は、バリア層の役割を果たすことができる。第１金属層１１と絶縁膜との間に介在させる下地層の材料は、Ｔｉに限らず、例えば、Ｃｒ、Ｎｂ、Ｚｒ、ＴｉＮ、ＴａＮなどでもよい。   As the substrate 1, for example, a wafer formed of a silicon wafer and provided with the first metal layer 11 in each of the regions where the chips 2 are to be mounted can be employed. In the case where the substrate 1 is a wafer formed from a silicon wafer, it is preferable that an insulating film made of a silicon oxide film or the like is formed on the surface of the silicon wafer. The first metal layer 11 can be composed of, for example, an Au film. For example, a base layer such as a Ti film may be interposed between the first metal layer 11 and the insulating film. When the first metal layer 11 is an Au film and the insulating film is a silicon oxide film, the Ti film can serve as a barrier layer. The material of the underlayer interposed between the first metal layer 11 and the insulating film is not limited to Ti, and may be, for example, Cr, Nb, Zr, TiN, TaN, or the like.

シリコンウェハとしては、例えば、直径が５０〜３００ｍｍ、厚みが２００〜１０００μｍ程度のものを用いることができる。   For example, a silicon wafer having a diameter of 50 to 300 mm and a thickness of about 200 to 1000 μm can be used.

基板１の材料は、シリコンに限らず、例えば、窒化アルミニウムや、アルミナなどでもよい。基板１の材料としてシリコンを採用する場合には、基板１が上述の絶縁膜を備えるのが好ましいが、基板１の材料として窒化アルミニウムやアルミナなどの絶縁材料を採用する場合には、基板１に絶縁膜を設けなくてもよい。   The material of the substrate 1 is not limited to silicon, and may be, for example, aluminum nitride or alumina. When silicon is used as the material of the substrate 1, the substrate 1 is preferably provided with the above-described insulating film. However, when an insulating material such as aluminum nitride or alumina is used as the material of the substrate 1, An insulating film is not necessarily provided.

チップ２としては、例えば、ＬＥＤチップを採用することができる。ＬＥＤチップとしては、例えば、チップサイズが０．３ｍｍ□（０．３ｍｍ×０．３ｍｍ）や０．４５ｍｍ□や１ｍｍ□のものなどを用いることができる。また、ＬＥＤチップの平面形状は、正方形状に限らず、例えば、長方形状などでもよい。ＬＥＤチップの平面形状が、長方形状の場合、ＬＥＤチップのチップサイズとしては、例えば、０．５ｍｍ×０．２４ｍｍのものなどを用いることができる。   As the chip 2, for example, an LED chip can be adopted. As the LED chip, for example, a chip having a chip size of 0.3 mm □ (0.3 mm × 0.3 mm), 0.45 mm □, or 1 mm □ can be used. Further, the planar shape of the LED chip is not limited to a square shape, and may be a rectangular shape, for example. When the planar shape of the LED chip is rectangular, the chip size of the LED chip can be, for example, 0.5 mm × 0.24 mm.

ＬＥＤチップの発光波長は、特に限定するものではない。よって、ＬＥＤチップとしては、例えば、紫外ＬＥＤチップ、紫色ＬＥＤチップ、青色ＬＥＤチップ、緑色ＬＥＤチップ、黄色ＬＥＤチップ、橙色ＬＥＤチップ、赤色ＬＥＤチップなどを採用することができる。また、ＬＥＤチップとしては、白色ＬＥＤチップを採用することもできる。   The emission wavelength of the LED chip is not particularly limited. Therefore, as the LED chip, for example, an ultraviolet LED chip, a purple LED chip, a blue LED chip, a green LED chip, a yellow LED chip, an orange LED chip, or a red LED chip can be employed. Moreover, a white LED chip can also be adopted as the LED chip.

ＬＥＤチップとしては、図３（ａ）に示すように、主表面側に第１電極２ａが形成され、裏面側に第２電極２ｂが形成されたＬＥＤチップを採用することができる。このＬＥＤチップは、第２電極２ｂに第２金属層２１が積層されたものでもよいし、第２電極２ｂの最表面側が第２金属層２１を構成するものでもよいし、第２電極２ｂが第２金属層２１を構成するものでもよい。なお、図３（ａ）の実装形態において、第１電極２ａと第２電極２ｂとは、一方がアノード電極、他方がカソード電極である。   As the LED chip, as shown in FIG. 3A, an LED chip in which the first electrode 2a is formed on the main surface side and the second electrode 2b is formed on the back surface side can be adopted. This LED chip may be one in which the second metal layer 21 is laminated on the second electrode 2b, the outermost surface side of the second electrode 2b may constitute the second metal layer 21, or the second electrode 2b The second metal layer 21 may be configured. 3A, one of the first electrode 2a and the second electrode 2b is an anode electrode and the other is a cathode electrode.

また、ＬＥＤチップとしては、図３（ｂ）に示すように、厚み方向の一面側に第１電極２ａ及び第２電極２ｂが形成されたＬＥＤチップを採用することができる。このＬＥＤチップは、第１電極２ａ及び第２電極２ｂの各々に第２金属層２１が積層されたものでもよいし、第１電極２ａ及び第２電極２ｂの各々の最表面側が第２金属層２１を構成するものでもよいし、第１電極２ａ及び第２電極２ｂの各々が第２金属層２１を構成するものでもよい。なお、図３（ｂ）の実装形態において、第１電極２ａと第２電極２ｂとは、一方がアノード電極、他方がカソード電極である。   Moreover, as an LED chip, as shown in FIG.3 (b), the LED chip in which the 1st electrode 2a and the 2nd electrode 2b were formed in the one surface side of the thickness direction is employable. This LED chip may be one in which the second metal layer 21 is laminated on each of the first electrode 2a and the second electrode 2b, and the outermost surface side of each of the first electrode 2a and the second electrode 2b is the second metal layer. 21, or each of the first electrode 2 a and the second electrode 2 b may constitute the second metal layer 21. In the mounting form of FIG. 3B, one of the first electrode 2a and the second electrode 2b is an anode electrode and the other is a cathode electrode.

第２金属層２１及び第１金属層１１の各材料としては、フラックスレスの材料を採用する。   As each material of the 2nd metal layer 21 and the 1st metal layer 11, a fluxless material is employ | adopted.

チップ２は、第２金属層２１の材料として、例えば、フラックスレスのＡｕＳｎを採用することができる。フラックスレスのＡｕＳｎ層は、例えば、めっき法やスパッタ法などにより形成することができる。   The chip 2 can employ, for example, fluxless AuSn as the material of the second metal layer 21. The fluxless AuSn layer can be formed by, for example, a plating method or a sputtering method.

チップ２の第２金属層２１と基板１の第１金属層１１との材料の組み合わせは、ＡｕＳｎ−Ａｕに限らず、例えば、Ａｕ−ＡｕＳｎでもよい。チップ２の第２金属層２１と基板１の第１金属層１１との材料の組み合わせをＡｕＳｎ−ＡｕやＡｕ−ＡｕＳｎとした場合には、例えば、複数個のチップ２が実装された基板１や、複数個のチップ２が実装された基板１から分割されたモジュールを、マザーボートなどにＳｕＡｇＣｕを用いて２次実装する場合に、接合層３１が再溶融するのを防ぐことが可能となる。   The combination of materials of the second metal layer 21 of the chip 2 and the first metal layer 11 of the substrate 1 is not limited to AuSn—Au, and may be, for example, Au—AuSn. When the combination of the materials of the second metal layer 21 of the chip 2 and the first metal layer 11 of the substrate 1 is AuSn—Au or Au—AuSn, for example, the substrate 1 on which a plurality of chips 2 are mounted, When the module divided from the substrate 1 on which the plurality of chips 2 are mounted is secondarily mounted on a mother board or the like using SuAgCu, it is possible to prevent the bonding layer 31 from being remelted.

また、チップ２の第２金属層２１と基板１の第１金属層１１との材料の組み合わせは、ＡｕＧｅ−Ａｕ、Ａｕ−ＡｕＧｅ、ＳｎＢｉ−Ｓｎ、Ｓｎ−ＳｎＢｉ、ＳｎＣｕ−Ｃｕ、Ｃｕ−ＳｎＣｕなどでもよい。   Moreover, the combination of the material of the 2nd metal layer 21 of the chip | tip 2 and the 1st metal layer 11 of the board | substrate 1 is AuGe-Au, Au-AuGe, SnBi-Sn, Sn-SnBi, SnCu-Cu, Cu-SnCu etc. But you can.

チップ２としてＬＥＤチップを採用し、第２金属層２１と第１金属層１１とを液相拡散接合することで形成される接合層３１をＡｕＳｎ層とする場合には、上述の例に限らず、例えば、図４〜図６のいずれかの構成例も考えられる。図４に示した構成例では、チップ２の第２金属層２１をＡｕ層２１ａとし、基板１の第１金属層１１を、Ｓｎ層もしくはＡｕＳｎ層からなる第１層１１ａと、この第１層１１ａ上のＡｕ層からなる第２層１１ｂとで構成している。これにより、基板１は、第１金属層１１におけるＳｎ層が酸化するのを抑制することが可能となる。   When the LED chip is adopted as the chip 2 and the bonding layer 31 formed by liquid phase diffusion bonding of the second metal layer 21 and the first metal layer 11 is an AuSn layer, the present invention is not limited to the above example. For example, any one of the configuration examples in FIGS. 4 to 6 is also conceivable. In the configuration example shown in FIG. 4, the second metal layer 21 of the chip 2 is an Au layer 21a, the first metal layer 11 of the substrate 1 is a first layer 11a composed of an Sn layer or an AuSn layer, and the first layer. And a second layer 11b made of an Au layer on 11a. As a result, the substrate 1 can suppress oxidation of the Sn layer in the first metal layer 11.

図５に示した構成例では、チップ２の第２金属層２１をＡｕ層２１ａとし、基板１の第１金属層１１を、Ｓｎ層１１ｃとＡｕ層１１ｄとが交互に積層され最表層がＡｕ層１１ｄとされた多層構造としている。これにより、基板１は、第１金属層１１におけるＳｎ層１１ｃが酸化するのを抑制することが可能となる。また、本接合工程では、Ｓｎを溶融させた際のＡｕＳｎの形成を容易にすることが可能となる。   In the configuration example shown in FIG. 5, the second metal layer 21 of the chip 2 is an Au layer 21a, and the first metal layer 11 of the substrate 1 is alternately laminated with Sn layers 11c and Au layers 11d, and the outermost layer is Au. A multi-layer structure is formed as the layer 11d. Thereby, the substrate 1 can suppress oxidation of the Sn layer 11 c in the first metal layer 11. Further, in the main joining step, it is possible to easily form AuSn when Sn is melted.

図６に示した構成例では、チップ２の第２金属層２１をＡｕ層２１ａとし、基板１の第１金属層１１を、格子状のスリットが形成された平面形状のＡｕＳｎ層１１ｅとしている。これにより、本接合工程では、ＡｕＳｎ層１１ｅを溶融させた際に、接合の起点（合金化の起こる箇所）がばらつくのを抑制することが可能となり、接合強度のばらつきや、接合面積のばらつき、未接合領域などを低減させることが可能となる。   In the configuration example shown in FIG. 6, the second metal layer 21 of the chip 2 is an Au layer 21a, and the first metal layer 11 of the substrate 1 is a planar AuSn layer 11e in which lattice-shaped slits are formed. As a result, in the main bonding step, it is possible to suppress variation in the starting point of the bonding (where the alloying occurs) when the AuSn layer 11e is melted. It is possible to reduce unbonded regions and the like.

チップ２は、ＬＥＤチップに限らない。チップ２は、例えば、レーザダイオードチップ、フォトダイオードチップ、ＧａＮ系ＨＥＭＴ（high electron mobility transistor）チップ、ＭＥＭＳ（microelectro mechanical systems）チップ、赤外線センサチップ、ＩＣチップなどでもよい。ＭＥＭＳチップとしては、例えば、加速度センサチップ、圧力センサチップなどを採用することができる。   The chip 2 is not limited to the LED chip. The chip 2 may be, for example, a laser diode chip, a photodiode chip, a GaN-based HEMT (high electron mobility transistor) chip, a MEMS (microelectro mechanical systems) chip, an infrared sensor chip, an IC chip, or the like. As the MEMS chip, for example, an acceleration sensor chip, a pressure sensor chip, or the like can be employed.

チップ２は、チップサイズについても特に限定するものではなく、例えば０．２ｍｍ□〜５ｍｍ□程度のものを用いることができる。また、チップ２の平面視での外周形状は、正方形状に限らず、例えば、長方形状でもよい。   The chip 2 is not particularly limited with respect to the chip size, and for example, a chip having a size of about 0.2 mm □ to 5 mm □ can be used. Further, the outer peripheral shape of the chip 2 in plan view is not limited to a square shape, and may be, for example, a rectangular shape.

チップ２は、厚みについても特に限定するものではなく、例えば０．１〜１ｍｍ程度のものを用いることができる。   The thickness of the chip 2 is not particularly limited, and for example, a chip having a thickness of about 0.1 to 1 mm can be used.

仮接合工程は、第１ダイボンド装置のステージ３ａ（図１（ａ）参照）の表面側に基板１を載置する第１基板載置工程の後に行う。ステージ３ａには、上記表面側に載置される基板１などを吸着するための複数の吸気孔（図示せず）が周部に形成されている。これにより、第１ダイボンド装置は、ステージ３ａの上記表面側に載置した基板１を吸着した状態で保持することができる。   The temporary bonding step is performed after the first substrate mounting step of mounting the substrate 1 on the surface side of the stage 3a (see FIG. 1A) of the first die bonding apparatus. In the stage 3a, a plurality of air intake holes (not shown) for adsorbing the substrate 1 and the like placed on the surface side are formed in the peripheral portion. Thereby, the 1st die-bonding apparatus can hold | maintain the state which adsorb | sucked the board | substrate 1 mounted in the said surface side of the stage 3a.

仮接合工程の第１ステップでは、基板１に対してチップ２を位置合わせする。より具体的に説明すれば、第１ステップでは、例えば、ウェハテープ（粘着性樹脂テープ）やチップトレイなどに保持されているチップ２を第１ダイボンド装置のコレット５ａにより真空吸着してピックアップする前に、ピックアップ対象のチップ２を第１ダイボンド装置の認識装置（図示せず）により高精度に認識する。その後、第１ダイボンド装置のステージ３ａの表面側の基板１における接合予定領域を認識装置により高精度に認識し、コレット５ａにより真空吸着しているチップ２と基板１とを位置合わせする（例えば、チップ２の姿勢を修正するチップアライメントを行う）。粘着性樹脂テープとしては、例えば、紫外線硬化型のダイシングテープや熱硬化型のダイシングテープなどがある。なお、粘着性樹脂テープは、ダイシング時に強い粘着力でチップ２を保持しているが、ダイシング後に紫外線照射や赤外線照射により粘着性を低下させることで、ピックアップ性を高めることができる。   In the first step of the temporary bonding process, the chip 2 is aligned with the substrate 1. More specifically, in the first step, for example, before the chip 2 held on a wafer tape (adhesive resin tape) or a chip tray is vacuum picked up by the collet 5a of the first die bonding apparatus and picked up. In addition, the chip 2 to be picked up is recognized with high accuracy by the recognition device (not shown) of the first die bonding apparatus. Thereafter, the bonding scheduled region in the substrate 1 on the surface side of the stage 3a of the first die bonding apparatus is recognized with high accuracy by the recognition device, and the chip 2 and the substrate 1 vacuum-adsorbed by the collet 5a are aligned (for example, Chip alignment for correcting the posture of the chip 2 is performed). Examples of the adhesive resin tape include an ultraviolet curable dicing tape and a thermosetting dicing tape. The adhesive resin tape holds the chip 2 with a strong adhesive force at the time of dicing. However, the pick-up property can be improved by reducing the adhesiveness by ultraviolet irradiation or infrared irradiation after dicing.

仮接合工程の第２ステップでは、チップ２と基板１との接合面同士を接触させ、チップ２側から加圧してチップ２の第２金属層２１と基板１の第１金属層１１とを第１規定温度で固相拡散接合する。本実施形態の実装方法では、この固相拡散接合により、チップ２と基板１とが仮接合される。第２ステップでは、ボンディングヘッド４ａのヒータ（図示せず）によりコレット５ａを介してチップ２を第１規定温度に加熱する。第２ステップでは、チップ２を第１規定温度よりもやや高い温度に加熱してから、チップ２と基板１との接合面同士を接触させることで第１規定温度となるようにしているが、チップ２と基板１との接合面同士を接触させてから第１規定温度となるように加熱してもよい。   In the second step of the temporary bonding process, the bonding surfaces of the chip 2 and the substrate 1 are brought into contact with each other, and the second metal layer 21 of the chip 2 and the first metal layer 11 of the substrate 1 are bonded by pressing from the chip 2 side. Solid phase diffusion bonding at 1 normal temperature. In the mounting method of the present embodiment, the chip 2 and the substrate 1 are temporarily bonded by this solid phase diffusion bonding. In the second step, the chip 2 is heated to the first specified temperature via the collet 5a by a heater (not shown) of the bonding head 4a. In the second step, after the chip 2 is heated to a temperature slightly higher than the first specified temperature, the bonding surfaces of the chip 2 and the substrate 1 are brought into contact with each other so that the first specified temperature is reached. You may heat so that it may become 1st specified temperature after making the joining surfaces of the chip | tip 2 and the board | substrate 1 contact.

固相拡散接合は、例えば、超音波接合もしくは表面活性化接合であることが好ましい。これにより、第２ステップでは、チップ２や基板１の加熱温度を比較的低温としながらも仮接合することができるので、仮接合前にチップ２と基板１との少なくとも一方を加熱した状態でも、高精度な位置合わせが可能となる。   The solid phase diffusion bonding is preferably, for example, ultrasonic bonding or surface activated bonding. Thereby, in the 2nd step, since temporary heating can be performed while the heating temperature of the chip 2 and the substrate 1 is relatively low, even in a state where at least one of the chip 2 and the substrate 1 is heated before temporary bonding, High-precision positioning is possible.

超音波接合は、超音波振動を利用して行う固相拡散接合である。超音波接合としては、所定の加熱状態のもとで圧力と超音波振動とを利用して接合する超音波併用熱圧着が好ましい。超音波併用熱圧着では、圧力と超音波振動とを利用して常温で接合する場合に比べて、接合強度を高めることが可能となる。また、超音波併用熱圧着では、熱圧着に比べて、より低温での接合が可能となる。   Ultrasonic bonding is solid phase diffusion bonding performed using ultrasonic vibration. As ultrasonic bonding, ultrasonic thermocompression bonding is preferable, in which bonding is performed using pressure and ultrasonic vibration under a predetermined heating state. In the thermocompression bonding using ultrasonic waves, it is possible to increase the bonding strength as compared with the case where bonding is performed at normal temperature using pressure and ultrasonic vibration. In addition, in the thermocompression bonding with ultrasonic waves, bonding at a lower temperature is possible as compared with thermocompression bonding.

表面活性化接合は、接合前に互いの接合表面へアルゴンのプラズマ若しくはイオンビーム若しくは原子ビームを真空中で照射して各接合表面の清浄化・活性化を行ってから、接合表面同士を接触させ、第１規定温度下で適宜の荷重を印加して直接接合する。第１規定温度は、例えば、常温〜１００℃程度の範囲で設定することができる。ここで、表面活性化接合は、例えば、第１規定温度を例えば８０℃〜１００℃の範囲で設定すれば、常温の場合に比べて、接合強度を高めることが可能となる。なお、表面活性化接合は、アルゴンのプラズマ若しくはイオンビーム若しくは原子ビームに限らず、例えば、ヘリウムやネオンなどのプラズマ若しくはイオンビーム若しくは原子ビームを利用するようにしてもよい。   In surface activation bonding, each bonding surface is irradiated with argon plasma, ion beam or atomic beam in vacuum before bonding to clean and activate each bonding surface, and then the bonding surfaces are brought into contact with each other. Direct bonding is performed by applying an appropriate load under the first specified temperature. The first specified temperature can be set, for example, in the range of room temperature to about 100 ° C. Here, in the surface activation bonding, for example, if the first specified temperature is set in a range of 80 ° C. to 100 ° C., for example, the bonding strength can be increased as compared with the case of normal temperature. The surface activated bonding is not limited to argon plasma, ion beam, or atomic beam, but may be plasma such as helium or neon, ion beam, or atomic beam.

固相拡散接合を行う際の接合条件は、接合界面のボイド率（未接合率）が例えば３０％以下となるように設定するのが好ましい。ボイド率は、例えば、所望の接合領域の面積（例えば、チップ２の第２金属層２１の面積）に占める未接合領域の面積の割合として規定することができる。所望の接合領域の面積及び未接合領域の面積は、例えば、固相拡散接合を行った後に、例えば、超音波顕微鏡による観察を行うことで得られる超音波顕微鏡像図から推測することができる。   It is preferable to set the bonding conditions when performing solid phase diffusion bonding so that the void ratio (unbonded ratio) at the bonding interface is, for example, 30% or less. The void ratio can be defined, for example, as a ratio of the area of the unjoined region to the area of the desired joined region (for example, the area of the second metal layer 21 of the chip 2). The area of the desired bonded region and the area of the unbonded region can be estimated from, for example, an ultrasonic microscope image obtained by performing observation with an ultrasonic microscope after performing solid phase diffusion bonding.

なお、固相拡散接合を行う第２ステップでは、接合時にチップ２と基板１との少なくとも一方を加熱することにより、接合強度を向上させることが可能となる。   In the second step in which solid phase diffusion bonding is performed, it is possible to improve the bonding strength by heating at least one of the chip 2 and the substrate 1 during bonding.

第２ステップは、空気雰囲気中ではなく、制御された雰囲気中で行うことが好ましい。制御された雰囲気としては、例えば、不活性ガス雰囲気、真空雰囲気、還元性ガス雰囲気などが挙げられる。不活性ガス雰囲気としては、例えば、Ｎ２ガス雰囲気、アルゴンガス雰囲気などが挙げられる。還元性ガス雰囲気としては、例えば、Ｈ２ガス雰囲気が挙げられる。第２ステップでは、雰囲気を不活性ガス雰囲気もしくは真空雰囲気とすることにより、酸化を抑制することが可能となる。また、第２ステップでは、雰囲気を還元性ガス雰囲気とすることにより、不要な酸化物を除去することが可能となる。 The second step is preferably performed in a controlled atmosphere, not in an air atmosphere. Examples of the controlled atmosphere include an inert gas atmosphere, a vacuum atmosphere, and a reducing gas atmosphere. The inert gas atmosphere, eg, N 2 gas atmosphere, such as argon gas atmosphere and the like. Examples of the reducing gas atmosphere include an H 2 gas atmosphere. In the second step, it is possible to suppress oxidation by setting the atmosphere to an inert gas atmosphere or a vacuum atmosphere. In the second step, unnecessary atmosphere can be removed by setting the atmosphere to a reducing gas atmosphere.

本接合工程は、第２ダイボンド装置のステージ３ｂ（図１（ｂ）参照）の表面側に基板１を載置する第２基板載置工程の後に行う。ステージ３ｂには、上記表面側に載置される基板１などを吸着するための複数の吸気孔（図示せず）が周部に形成されている。これにより、第２ダイボンド装置は、ステージ３ｂの上記表面側に載置した基板１を吸着した状態で保持することができる。   This main joining process is performed after the 2nd board | substrate mounting process which mounts the board | substrate 1 on the surface side of the stage 3b (refer FIG.1 (b)) of a 2nd die-bonding apparatus. A plurality of intake holes (not shown) for adsorbing the substrate 1 and the like placed on the front surface side are formed in the periphery of the stage 3b. Thereby, the 2nd die-bonding apparatus can hold | maintain in the state which adsorb | sucked the board | substrate 1 mounted in the said surface side of the stage 3b.

本接合工程では、まず、基板１に仮接合されている複数個のチップ２のうちの特定のチップ２或いはステージ３ｂ上の基板１のアライメントマークを認識する。より具体的に説明すれば、本接合工程では、まず、第２ダイボンド装置のステージ３ｂに吸着されている基板１上の特定のチップ２或いは基板１のアライメントマークを第２ダイボンド装置の認識装置（図示せず）により簡易に認識し、ボンディングヘッド（図示せず）に設けられている実装ツール６と基板１とを位置合わせする。なお、第２ダイボンド装置は、特定のチップ２或いは基板１を簡易に認識すればよいから、チップ２を高精度に認識する場合に比べて、画像処理部での画像処理を簡略化することができ、認識に要する時間を短縮することが可能となる。   In the main bonding step, first, an alignment mark of the substrate 1 on the specific chip 2 or the stage 3b among the plurality of chips 2 temporarily bonded to the substrate 1 is recognized. More specifically, in this bonding step, first, a specific chip 2 on the substrate 1 adsorbed by the stage 3b of the second die bonding apparatus or an alignment mark of the substrate 1 is recognized by a recognition apparatus ( The mounting tool 6 provided in the bonding head (not shown) and the substrate 1 are aligned with each other by simply recognizing it by a not shown. Since the second die bonding apparatus only needs to easily recognize the specific chip 2 or the substrate 1, the image processing in the image processing unit can be simplified as compared with the case where the chip 2 is recognized with high accuracy. And the time required for recognition can be shortened.

本接合工程では、その後、第２金属層２１及び第１金属層１１を溶融させる第２規定温度で各チップ２の各々を基板１に対して本接合する。より具体的に説明すれば、本接合工程では、実装ツール６により各チップ２側から加熱して各チップ２の各々と基板１とを液相拡散接合する。液相拡散接合は、各チップ２の第１金属層２１と基板１の第１金属層１１とを一時的に溶融、液化した後、拡散を利用し等温凝固させる方法である。ここでは、チップ２の第２金属層２１と基板１の第１金属層１１とを共晶接合させるようにしている。共晶接合は、液相拡散接合のうち液化に対して共晶反応を利用する接合方法である。   In the main bonding step, each chip 2 is then main bonded to the substrate 1 at a second specified temperature at which the second metal layer 21 and the first metal layer 11 are melted. More specifically, in this bonding step, each chip 2 and the substrate 1 are bonded by liquid phase diffusion bonding by heating from the chip 2 side by the mounting tool 6. The liquid phase diffusion bonding is a method in which the first metal layer 21 of each chip 2 and the first metal layer 11 of the substrate 1 are temporarily melted and liquefied and then isothermally solidified using diffusion. Here, the second metal layer 21 of the chip 2 and the first metal layer 11 of the substrate 1 are eutectic bonded. Eutectic bonding is a bonding method that utilizes a eutectic reaction for liquefaction among liquid phase diffusion bonding.

本接合工程では、実装ツール６を基板１上の全てのチップ２に接触させ、実装ツール６のヒータ（図示せず）により各チップ２の各々を第２規定温度に加熱した状態で、実装ツール６側からチップ２に適宜の規定圧力を規定時間だけ印加する。これにより、本接合工程では、各チップ２の第２金属層２１と基板１の第１金属層１１とを共晶接合させる。第２規定温度は、例えば、第２金属層２１の材料がＡｕＳｎ、第１金属層１１の材料がＡｕの場合、ＡｕＳｎの溶融温度よりも高い温度に設定すればよい。規定圧力は、例えば、１個のチップ当りの荷重が２２〜５０ｋｇ／ｃｍ２程度の範囲となるように適宜設定すればよい。また、規定時間は、例えば、０．５〜１０秒程度の範囲で適宜設定すればよい。なお、実装ツール６としては、例えば、シリコンウェハや金属板などを利用することができる。 In this bonding process, the mounting tool 6 is brought into contact with all the chips 2 on the substrate 1 and each of the chips 2 is heated to the second specified temperature by a heater (not shown) of the mounting tool 6. An appropriate specified pressure is applied to the chip 2 from the 6 side for a specified time. Thus, in the main bonding step, the second metal layer 21 of each chip 2 and the first metal layer 11 of the substrate 1 are eutectic bonded. For example, when the material of the second metal layer 21 is AuSn and the material of the first metal layer 11 is Au, the second specified temperature may be set to a temperature higher than the melting temperature of AuSn. The specified pressure may be appropriately set so that, for example, the load per chip is in the range of about 22 to 50 kg / cm 2 . Moreover, what is necessary is just to set the regulation time suitably in the range of about 0.5-10 seconds, for example. For example, a silicon wafer or a metal plate can be used as the mounting tool 6.

本接合工程は、空気雰囲気中ではなく、制御された雰囲気中で行うことが好ましい。制御された雰囲気としては、例えば、不活性ガス雰囲気、真空雰囲気、還元性ガス雰囲気などが挙げられる。不活性ガス雰囲気としては、例えば、Ｎ２ガス雰囲気、アルゴンガス雰囲気などが挙げられる。還元性ガス雰囲気としては、例えば、Ｈ２ガス雰囲気が挙げられる。本接合工程では、雰囲気を不活性ガス雰囲気もしくは真空雰囲気とすることにより、酸化を抑制することが可能となる。また、本接合工程では、雰囲気を還元性ガス雰囲気とすることにより、不要な酸化物を除去することが可能となる。 This bonding process is preferably performed in a controlled atmosphere, not in an air atmosphere. Examples of the controlled atmosphere include an inert gas atmosphere, a vacuum atmosphere, and a reducing gas atmosphere. The inert gas atmosphere, eg, N 2 gas atmosphere, such as argon gas atmosphere and the like. Examples of the reducing gas atmosphere include an H 2 gas atmosphere. In the main bonding step, it is possible to suppress oxidation by setting the atmosphere to an inert gas atmosphere or a vacuum atmosphere. Further, in this bonding step, unnecessary oxides can be removed by setting the atmosphere to a reducing gas atmosphere.

本接合工程では、基板１側からの加熱を行っていないが、各チップ２側からの加熱だけでなく、ステージ３ｂのヒータ（図示せず）によりステージ３ｂを介して基板１側からの加熱も行うようにしてもよい。ここで、第２金属層２１の材料がＡｕＳｎ、第１金属層１１の材料がＡｕの場合には、基板１よりも各チップ２側の温度が高くなるように、ボンディングヘッドのヒータ及びステージ３ｂのヒータそれぞれの温度を設定することが好ましい。なお、ステージ３ｂのヒータの温度は、ＡｕＳｎの融点以下に設定するのが好ましい。   In this bonding step, heating from the substrate 1 side is not performed, but not only heating from each chip 2 side, but also heating from the substrate 1 side via the stage 3b by a heater (not shown) of the stage 3b. You may make it perform. Here, when the material of the second metal layer 21 is AuSn and the material of the first metal layer 11 is Au, the heater of the bonding head and the stage 3b are set so that the temperature on each chip 2 side becomes higher than the substrate 1. It is preferable to set the temperature of each heater. In addition, it is preferable to set the temperature of the heater of the stage 3b below the melting point of AuSn.

液相拡散接合を行う際の接合条件は、接合界面のボイド率（未接合率）が例えば２０％以下となるように設定するのが好ましい。ボイド率は、例えば、所望の接合領域の面積（例えば、所望の接合層３１の面積）に占める未接合領域の面積の割合として規定することができる。所望の接合領域の面積及び未接合領域の面積は、例えば、液相拡散接合を行った後に、例えば、超音波顕微鏡による観察を行うことで得られる超音波顕微鏡像図から推測することができる。   It is preferable to set the bonding conditions when performing liquid phase diffusion bonding so that the void ratio (unbonded ratio) at the bonding interface is, for example, 20% or less. The void ratio can be defined as, for example, the ratio of the area of the unjoined region to the area of the desired joined region (for example, the area of the desired joined layer 31). The area of the desired bonded region and the unbonded region can be estimated from, for example, an ultrasonic microscope image obtained by performing observation with an ultrasonic microscope after performing liquid phase diffusion bonding.

本接合工程で用いる設備は、上述の第２ダイボンド装置に限定するものではない。また、上述の第２ダイボンド装置を用いた本接合工程では、基板１上の各チップ２を実装ツール６により加圧しているが、各チップ２の加圧は適宜行えばよく、各チップ２の加圧を行わないようにしてもよい。この場合には、本接合工程で用いる設備として、各種のアニール装置やホットプレートなどを採用することもでき、画像認識を利用した位置合わせを不要とすることができる。本接合工程で用いる設備は、基板１や各チップ２を直接的に加熱するものに限らず、基板１及び各チップ２の周囲の雰囲気を加熱するものでもよい。   The equipment used in the main joining process is not limited to the second die bonding apparatus described above. Further, in the main bonding step using the above-described second die bonding apparatus, each chip 2 on the substrate 1 is pressurized by the mounting tool 6, but each chip 2 may be appropriately pressed. You may make it not pressurize. In this case, various annealing apparatuses, hot plates, etc. can be adopted as equipment used in the main joining step, and alignment using image recognition can be made unnecessary. The equipment used in this bonding step is not limited to the one that directly heats the substrate 1 and each chip 2, and may be one that heats the atmosphere around the substrate 1 and each chip 2.

本実施形態の実装方法では、仮接合の後に本接合を行うことにより、接合強度を向上させることが可能となるとともに、ボイドを低減することが可能となる。これにより、本実施形態の実装方法では、各チップ２の各々と基板１との間の熱抵抗を低減することが可能となるとともに、熱抵抗のばらつきを低減することが可能となる。   In the mounting method of the present embodiment, by performing the main bonding after the temporary bonding, it is possible to improve the bonding strength and reduce the voids. As a result, in the mounting method of the present embodiment, it is possible to reduce the thermal resistance between each of the chips 2 and the substrate 1 and to reduce variations in thermal resistance.

以上説明した本実施形態の実装方法は、基板１に各チップ２の各々を仮接合する仮接合工程と、基板１に仮接合された各チップ２の各々を基板１に本接合する本接合工程とを備える。ここで、仮接合工程は、第１ステップと第２ステップとからなる第１基本工程を、基板１に実装するチップ２の数だけ繰り返す。第１ステップは、基板１の第１金属層１１とチップ２の第２金属層２１とを位置合わせする。第２ステップは、第２金属層２１と第１金属層１１とを固相拡散接合することで仮接合する。また、本接合工程は、基板１に仮接合されている各チップ２の各々の第２金属層２１と基板１の各第１金属層１１とを液相拡散接合することで各チップ２を一括して基板１に本接合する。よって、本実施形態の実装方法では、仮接合工程と本接合工程とを別々の設備を用いて行うことができるので、互いに異なる２枚の基板１に対して仮接合工程と本接合工程とを並行して行うことが可能となる。よって、本実施形態の実装方法では、実装工程のタクトタイムの短縮化を図ることが可能となる。また、基板１を加熱した状態でチップ２を一個ずつ液相拡散接合する場合には、最初に液相拡散接合したチップ２と最後に液相拡散接合したチップ２とで熱履歴差が大きい。これに対して、本実施形態の実装方法では、仮接合工程での仮接合を行う際に常温もしくはチップ２側からのみの加熱を行うようにし、本接合工程では各チップ２を一括して基板１に本接合するようにしているので、基板１上の複数個のチップ２に熱履歴差が発生するのを抑制することが可能となる。これにより、本実施形態の実装方法では、実装工程に起因したチップ２間の特性ばらつきを低減することが可能となるとともに、基板１に初期に本接合されたチップ２の寿命が他のチップ２に比べて短くなるのを抑制することが可能となる。   The mounting method of the present embodiment described above includes a temporary bonding step of temporarily bonding each chip 2 to the substrate 1 and a main bonding step of finally bonding each of the chips 2 temporarily bonded to the substrate 1 to the substrate 1. With. Here, in the temporary bonding process, the first basic process including the first step and the second step is repeated by the number of chips 2 mounted on the substrate 1. In the first step, the first metal layer 11 of the substrate 1 and the second metal layer 21 of the chip 2 are aligned. In the second step, the second metal layer 21 and the first metal layer 11 are temporarily bonded by solid phase diffusion bonding. Further, in this bonding step, each chip 2 is collectively bonded by liquid phase diffusion bonding of each second metal layer 21 of each chip 2 temporarily bonded to the substrate 1 and each first metal layer 11 of the substrate 1. Then, main bonding is performed to the substrate 1. Therefore, in the mounting method of the present embodiment, the temporary bonding step and the main bonding step can be performed using different equipment, so the temporary bonding step and the main bonding step are performed on two different substrates 1. It can be performed in parallel. Therefore, in the mounting method of the present embodiment, it is possible to reduce the tact time of the mounting process. Further, when the chips 2 are subjected to liquid phase diffusion bonding one by one while the substrate 1 is heated, there is a large difference in thermal history between the first liquid phase diffusion bonded chip 2 and the last liquid phase diffusion bonded chip 2. On the other hand, in the mounting method of the present embodiment, when performing temporary bonding in the temporary bonding process, heating is performed only at room temperature or from the chip 2 side. Therefore, it is possible to suppress the occurrence of a thermal history difference between the plurality of chips 2 on the substrate 1. Thereby, in the mounting method of the present embodiment, it is possible to reduce the characteristic variation between the chips 2 due to the mounting process, and the lifetime of the chip 2 that is initially bonded to the substrate 1 is the other chip 2. It becomes possible to suppress shortening compared with.

この実装方法においては、固相拡散接合を第１規定温度で行い、液相拡散接合を第１規定温度よりも高い第２規定温度で行うようにし、第２規定温度を、チップ２側と基板１側との少なくとも一方の加熱により到達させる温度とすることが好ましい。これにより、この実装方法では、チップ２と基板１との本接合の前後において、チップ２の位置がずれるのを抑制することが可能となり、また、基板１上の複数個のチップ２の熱履歴を揃えることが可能となる。   In this mounting method, solid phase diffusion bonding is performed at a first specified temperature, liquid phase diffusion bonding is performed at a second specified temperature higher than the first specified temperature, and the second specified temperature is set between the chip 2 side and the substrate. It is preferable to set the temperature to be reached by heating at least one of the first side. Thereby, in this mounting method, it is possible to suppress the displacement of the position of the chip 2 before and after the main bonding of the chip 2 and the substrate 1, and the thermal history of the plurality of chips 2 on the substrate 1. Can be arranged.

また、実装方法では、基板１としてシリコンウェハから形成されたウェハを採用することにより、第１金属層１１の下地の表面粗さを小さくすることが可能となり、第１金属層１１の表面粗さを小さくすることが可能となる。よって、この実装方法では、第１金属層１１の表面粗さに起因した仮接合や本接合でのボイドの発生を抑制することが可能となり、接合強度を向上させることが可能となる。第１金属層１１の表面粗さについては、例えば、ＪＩＳ Ｂ ０６０１−２００１（ＩＳＯ ４２８７−１９９７）で規定されている算術平均粗さＲａが１０ｎｍ以下であることが好ましく、数ｎｍ以下であることが、より好ましい。   Further, in the mounting method, by employing a wafer formed from a silicon wafer as the substrate 1, it becomes possible to reduce the surface roughness of the base of the first metal layer 11, and the surface roughness of the first metal layer 11. Can be reduced. Therefore, in this mounting method, it is possible to suppress the generation of voids in the temporary bonding and the main bonding due to the surface roughness of the first metal layer 11, and the bonding strength can be improved. About the surface roughness of the 1st metal layer 11, it is preferable that arithmetic mean roughness Ra prescribed | regulated by JISB0601-2001 (ISO 4287-1997) is 10 nm or less, for example, it is several nm or less Is more preferable.

１ 基板
２ チップ
１１ 第１金属層
２１ 第２金属層 1 substrate 2 chip 11 first metal layer 21 second metal layer

Claims (3)

基板上に複数個のチップを実装する実装方法であって、前記基板に前記各チップの各々を仮接合する仮接合工程と、前記基板に仮接合された前記各チップの各々を前記基板に本接合する本接合工程とを備え、前記仮接合工程は、前記基板の第１金属層と前記チップの第２金属層とを位置合わせする第１ステップと、前記第１ステップの後に前記チップ側から加圧して前記チップの前記第２金属層と前記基板の前記第１金属層とを固相拡散接合することで前記基板に前記チップを仮接合する第２ステップとからなる第１基本工程を、前記基板に実装する前記チップの数だけ繰り返し、前記本接合工程では、前記基板に仮接合されている前記各チップの各々の前記第２金属層と前記基板の前記各第１金属層とを液相拡散接合することで前記各チップを一括して前記基板に本接合することを特徴とする実装方法。   A mounting method for mounting a plurality of chips on a substrate, the step of temporarily bonding each of the chips to the substrate, and the step of temporarily bonding each of the chips temporarily bonded to the substrate to the substrate The temporary bonding step includes a first step of aligning the first metal layer of the substrate and the second metal layer of the chip, and the chip side after the first step. A first basic process comprising a second step of temporarily bonding the chip to the substrate by applying solid-phase diffusion bonding to the second metal layer of the chip and the first metal layer of the substrate by applying pressure. The number of chips mounted on the substrate is repeated, and in the main bonding step, the second metal layer of each chip temporarily bonded to the substrate and the first metal layer of the substrate are liquidated. By performing phase diffusion bonding, Mounting method characterized by the bonding to the substrate in a lump. 前記固相拡散接合は、第１規定温度で行い、前記液相拡散接合は、前記第１規定温度よりも高い第２規定温度で行うようにし、前記第２規定温度は、前記各チップ側と前記基板側との少なくとも一方の加熱により到達させる温度であることを特徴とする請求項１記載の実装方法。   The solid phase diffusion bonding is performed at a first specified temperature, and the liquid phase diffusion bonding is performed at a second specified temperature that is higher than the first specified temperature. The mounting method according to claim 1, wherein the temperature is reached by heating at least one of the substrate and the substrate. 前記固相拡散接合は、超音波接合もしくは表面活性化接合であることを特徴とする請求項１又は２記載の実装方法。   3. The mounting method according to claim 1, wherein the solid phase diffusion bonding is ultrasonic bonding or surface activated bonding.
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JP2016092078A (en) * 2014-10-30 2016-05-23 株式会社東芝 Semiconductor chip bonding method and semiconductor chip bonding device
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US11018112B2 (en) 2014-10-30 2021-05-25 Kabushiki Kaisha Toshiba Bonding method of semiconductor chip and bonding apparatus of semiconductor chip
KR20160064334A (en) * 2014-11-27 2016-06-08 한국광기술원 method of manufacturing light emitting diode using phosphor sheet
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