JP2014032555A - Cache memory controller and cache memory control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce data transfer processing between a main memory and a cache memory in the case where there is processing using data which does not need data holding after a read request from an access master.SOLUTION: A cache memory controller includes transfer attribute management means 50 for defining the necessity of data holding after reading from an access master in each memory area obtained by dividing a memory area of a main memory, hit detection means 10 for detecting whether to be a cache error to an access request, and request control means 30 for securing a cache line in a cache memory in the case of detecting a cache error when receiving a write request from the access master, and writing data subjected the write request from the access master in the secured cache line without performing data transfer from the main memory to the cache memory if data holding after reading a memory area including an address to which the access master performs the write request is defined as unnecessary.

Description

  The present invention relates to a cache memory control device that realizes access processing from an access master to a main memory via a cache memory.

  An electronic device is equipped with a main memory, and when executing processing such as computer program execution and data processing such as video, audio, and communication, data being processed can be written to and read from the main memory. Generally done. In recent years, the storage capacity of this main memory has been steadily increasing, and some communication devices and image processing apparatuses are equipped with a semiconductor memory of several gigabytes to several terabytes, for example, a DRAM (Dynamic Random Access Memory). . Further, an architecture in which a plurality of access masters including a processor core and a DMA (Dynamic Memory Access) circuit access a main memory is mainstream.

  In such a case, since one or more access masters access the main memory at high speed, a semiconductor memory capable of high-speed data access, such as SRAM (Static Random Memory) rather than DRAM, is provided as a cache memory. Is generally hierarchized. Here, the cache memory is located between the access master and the main memory. When a part of the data stored in the main memory is stored in the cache memory, the access master makes an access request to the main memory. In addition, when the corresponding data is stored in the cache memory, the data stored in the cache memory is written or read based on the request of the access master without accessing the main memory. As a result, it is possible to cope with access to a cache memory capable of accessing data faster than the main memory, and the apparent access speed to the main memory can be increased. In particular, if frequently used data is stored in the cache memory, the effect of speeding up by the cache memory becomes more prominent as the access master requests access to frequently used data.

  Here, the cache memory control when the access master issues a read request to the main memory will be described. When data corresponding to the address requested by the access master is stored on the cache memory side, the cache memory control device accesses the cache memory, reads the data stored in the cache memory, and outputs the data to the access master. . On the other hand, when the data is not stored in the cache memory, a cache line for temporarily transferring the data requested to be read from the access master is secured in the cache memory. Here, the cache line is a memory area that is a management unit of the cache memory, and the memory area is constituted by a plurality of cache lines in the cache memory. Data transfer with the main memory is performed in cache line units (or called line units).

  Data in the memory area of the cache line unit including the address requested to be read from the access master is transferred from the main memory to the cache line secured as described above. After performing this data transfer, the data at the address requested to be read is output to the access master. Here, when an access master requests access to the main memory, the data at the corresponding address is stored in the cache memory is called a cache hit, and the data not stored in the cache memory is called a cache miss.

  Next, cache memory control when the access master issues a write request to the main memory will be described. When the cache line corresponding to the corresponding address requested to be written is stored in the cache memory, that is, when a cache hit occurs, the data is written to the cache line including the corresponding address in the cache memory. On the other hand, in the case of a cache miss, a cache line for transferring the data requested to be read from the access master is once reserved in the cache memory, and the corresponding cache line data stored in the main memory is transferred to the cache memory. After the transfer, the data is written to the cache line including the corresponding address in the cache memory.

  At this time, when all the cache lines are in use, it is necessary to save from the cache memory to the main memory and secure a memory area including the corresponding address in the cache memory in units of cache lines in order to secure an empty line. Arise. As an algorithm for selecting a cache line to be evacuated, an LRU (Least Recently Used) method that selects a cache line that has not been referred to for the longest time, or an LFU (Least Frequently Used) that selects a line that has been referred to the least frequently. The method is known.

  By providing the cache memory in such a manner and arranging the memories in a hierarchical manner, access to the main memory is concentrated at the time of a cache miss and cache evacuation for securing a free line. In other words, in the data transfer from the access master to the main memory, as the probability of a cache hit decreases and the occurrence of a cache miss increases, the access to the main memory increases, which hinders the speed of data transfer. .

  In particular, when accessing a single main memory from a plurality of access masters, there is an increase in the number of accesses to different memory address areas. Therefore, there is a problem that the probability of a cache hit decreases and the time required for the entire processing increases. It was. In addition, when memory access related to task processing of one access master and memory access related to task processing of the other access master are mixed, cache evacuation is performed to secure an empty line during task processing of one access master. If the cache line of the data necessary for the task processing of the other access master is saved when a memory access is performed, a memory miss occurs when the memory access is performed by the task processing of the other access master, which hinders the speeding up of task processing. There was a problem of becoming. In addition, since the semiconductor memory used for the cache memory is faster in access than the main memory, the cost is high. Therefore, depending on the increase in the capacity of the cache memory, the cost of the entire system increases.

  Therefore, in a system that processes multiple tasks in parallel, each task is managed in association with each memory area obtained by dividing the memory area of the cache memory. There has been a method of eliminating a cache miss caused by (see, for example, Patent Document 1).

JP-A-2004-178571 (pages 8-15, FIG. 1)

  In the conventional method, if a cache miss occurs when a write request is issued from the access master, a cache line for once writing the data requested to be written to the cache memory is secured, and the cache line including the address for which the write request is made The data corresponding to the minute address is transferred from the main memory to the cache line secured in the cache memory. However, even if the data at the address requested to be written is data that is requested to be read only once, if there is a cache miss, data transfer processing between the main memory and the cache memory is always required, and the processing of the entire processing system There was a problem that the speed would be adversely affected.

  The present invention has been made to solve the above-described problems, and is the main in the case of a cache miss when there is a process using data that does not require data retention after a read request is made by the access master. An object of the present invention is to provide a cache memory control device that improves the overall processing speed by reducing data transfer processing between a memory and a cache memory.

  In the cache memory control device according to the present invention, the memory area of the main memory is divided, and the transfer for defining and managing the necessity of holding data after being read from the access master for each of the divided memory areas Attribute management means, hit detection means for detecting whether or not a cache line corresponding to an address requested to be accessed from the access master exists in the cache memory, and based on the access request from the access master, the main memory Request control means for performing data transfer between the data and the cache memory, and writing data to or reading data from the cache memory, wherein the request control means is that the access request from the access master is a write request. Address for which the hit detection means is requested to access When it is detected that the corresponding cache line does not exist in the cache memory, a cache line corresponding to the address requested to be accessed is secured to the cache memory, and the transfer attribute management means in the divided memory area If the memory area containing the address requested by the access master is defined to hold data after being read from the access master, it corresponds to the cache line corresponding to the address requested to be written. The data transferred to the cache line that secures the data stored in the address area of the main memory is then written to the cache line that secures the data requested to be written by the access master, and the divided Out of memory area If it is defined by the transfer attribute management means that the memory area including the address requested by the access master to be written is not required to hold data after being read from the access master, the data transfer is not performed. The data requested by the access master to be written is written in the secured cache line.

  According to the present invention, the memory area of the main memory is divided, and the divided memory areas are associated with the definition of necessity of holding data after a read request is issued from the access master, and determined as a cache miss. When a cache miss occurs when a write request is made for data that does not need to be retained after a read request is made by the access master by writing only to the cache memory without transferring the data of the corresponding cache line from the main memory. In addition, data transfer processing between the main memory and the cache memory becomes unnecessary. As a result, the data transfer processing between the main memory and the cache memory can be reduced and the processing speed of the entire system can be improved.

1 is a block diagram showing configurations of a cache memory control unit 100 and a processing system according to the present invention. FIG. It is a figure which shows an example of the content of the attribute which the attribute management means 50 manages. It is a flowchart which shows the process of the request control means 30 in the case of a write request. It is a flowchart which shows the process of the request control means 30 in the case of a read request.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a configuration of a cache memory control device 100 and a processing system according to Embodiment 1 of the present invention. In FIG. 1, the cache memory control means 100 is connected to a cache memory 150, access masters 200 and 210, and a main memory 300. As shown in FIG. 1, the plurality of access masters 200 and 210 are connected to a common bus line.

  The access masters 200 and 210 execute processing in the processing system, and may be microprocessors that execute based on computer program data stored in the main memory 300, or general-purpose circuits such as DMA circuits. It may be. The operation for requesting access to the main memory 300 performs the same operation.

  The main memory 300 stores data used in the processing system and is composed of a semiconductor memory such as a DRAM.

  Next, interface signals between the access master 200 and the cache memory control device 100 in the processing system shown in FIG. 1 will be described. The access type information 221 indicates the type of access request to the main memory 300 by the access master 200 and indicates whether a write (write) request or a read (read) request is made. The address data 222 indicates the address of the main memory 300 requested by the access master 200 for access. The write data 223 is data that is output when the access master 200 writes to the main memory 300. The read data 224 is data output from the cache memory control device 100 when the access master 200 reads data stored in the main memory 300.

  Similarly, interface signals between the access master 210 and the cache memory control device 100 in the processing system shown in FIG. 1 will be described. The access type information 225 indicates the type of access request to the main memory 300 by the access master 210 and indicates whether a write (write) request or a read (read) request is being made. The address data 226 indicates the address of the main memory 300 requested by the access master 210 for access. The write data 227 is data that is output when the access master 210 writes to the main memory 300. The read data 228 is data output from the cache memory control device 100 when the access master 210 reads data stored in the main memory 300.

  In addition to the interface signal between the access masters 200 and 210 and the cache memory control means 100 shown in FIG. 1, the length of data accessed by the access masters 200 and 210 is output, and the cache memory control device 100 displays access response information. May be exchanged. Further, FIG. 1 shows a processing system in which two access masters 200 and 210 are connected to the cache memory control unit 100, but the number of access masters may be one or more arbitrary numbers. May be shared.

  The cache memory 150 is capable of transferring data at a higher speed than the main memory 300, and is composed of a semiconductor memory such as an SRAM. Further, data can be written to or read from the cache memory control device 100 in a predetermined data amount unit. This predetermined amount of data is called a line. For example, 64 bytes of data in the main memory 300 are stored with the line unit being 64 bytes. If the line unit is 64 bytes and the bit width for one address of the main memory 300 is 32 bytes, the data transfer between the main memory 300 and the cache memory 150 is performed by transferring two addresses of the main memory 300 together. It will be. Data transfer between the main memory 300 and the cache memory 150 is also called line copying. The cache memory 150 is composed of a plurality of cache lines, with the memory area in units of lines as one cache line.

  Next, the cache memory control device 100 will be described. The cache memory control device 100 includes hit detection means 10, read monitoring means 20, request control means 30, tag memory 40, and attribute management means 50.

  The tag memory 40 stores address information of data stored in each cache line of the cache memory 150 in the main memory 300 and a flag indicating whether the data of each cache line is valid or invalid. Here, when this flag is valid, it means a state where data exists in the cache line, and when it is invalid, it means a state where data does not exist in the cache line.

  The hit detection means 10 is connected to the tag memory 40 so that information stored in the tag memory 40 can be read. Further, when there is an access request from the access master 200 or 210, whether or not a cache line corresponding to the access requested address exists in the cache memory 150 is determined based on the address information and flag stored in the tag memory 40. To do.

  The detection result 232 indicating whether or not the cache line corresponding to the access requested address exists in the cache memory 150 and the address information 233 on the cache memory 150 are output. The detection result 232 is information indicating a cache hit when the cache line corresponding to the access requested address exists in the cache memory 150, and cache information when the cache line corresponding to the access requested address does not exist in the cache memory 150. Information indicating a mistake.

  For example, among the information on each cache line in the tag memory 40, the address information of the cache line whose flag is valid is sequentially compared with the address data output from the access master requesting the access. . If there is address information that matches the address data requested to be accessed among the address information of the cache line in which the flag is valid, the cache memory 150 includes data requested by the access masters 200 and 210. If there is no matching address information, it is determined that there is no data in the cache memory 150 that the access masters 200 and 210 have requested access to.

  The read monitoring means 20 monitors the access type information 221 and 225 and address data input from the access masters 200 and 210 for each cache line of the cache memory 150, and stores the cache lines read by the access masters 200 and 210, respectively. . The read monitoring unit 20 includes storage elements corresponding to the number of cache lines in the cache memory 150 multiplied by the number of access masters.

  The operation of the lead monitoring means 20 will be described. The read monitoring unit 20 obtains a detection result 232 indicating whether or not the cache line corresponding to the access requested address exists in the cache memory 150 and address information 233 on the cache memory 150.

  Further, the read monitoring means 20 detects the position in the cache line of the cache memory 150 corresponding to the address information 233 from the lower address among the address data input from the access masters 200 and 210. If it is determined from the lower address that the end of the data constituting the cache line of the cache memory 150 has been accessed, the cache line information corresponding to the address information 233 of the access masters 200 and 210 that issued the access is stored as read. By determining the read state from the lower address to be read, the read state can be monitored with a simple configuration.

  The request control means 30 accesses the cache memory 150 when the data of the address requested to be accessed is stored in the cache memory 150. When the data of the address requested to be accessed is not stored in the cache memory 150, processing according to the access type information 221 and 225 is performed.

  In order to identify whether or not the data is temporary data, the attribute management unit 50 divides the main memory 300 into one or more areas and defines attributes for each divided memory area. The contents of the attributes defined by the attribute management means 50 are shown in FIG.

  The attribute management means 50 divides the main memory 300 into one or more memory areas and defines attributes for each divided memory area. For example, by storing information on the start address of each divided memory area of the main memory 300, each divided memory area is defined. Here, the defined memory area always has a size of one line or more of the cache memory 150, and is defined so that the same cache line does not extend over a plurality of areas when stored in the cache memory 150.

  Further, for each defined memory area, whether or not it is a memory area (temporary data area) for storing temporary data is defined and stored. Here, the temporary data is updated when the access master writes the new data after the same or different access master reads the data written by one access master once. Data that is not read-accessed by any access master during the period up to

  The definition is based on, for example, a program executed in the processing system, and any access master is not read-accessed during a period from when any access master reads once until a new data write request is made. It is defined by whether or not the address area is assigned for data.

  The temporary data area means that when a certain cache line on the cache memory 150 is updated and the access masters 200 and 210 complete reading the cache line, the next data update to the memory area occurs. In the meantime, this indicates that a read request to the memory area does not occur. Furthermore, in the case of a temporary data area, by defining and storing an access master that reads the memory area, it is possible to easily determine whether a memory area other than the defined access master is requesting to read the memory area.

  FIG. 2 is a diagram showing the contents of the attributes defined by the attribute management means 50. As shown in FIG. 2, by defining the start address information, it can be determined that the memory area of the main memory 300 is divided into a defined number of memory areas, and the address data requested to be accessed. Can be determined in which memory area. In addition, by storing information indicating whether or not the temporary data area stores temporary data in association with each memory area and the information of the access master that reads the memory area, the address data requested to be accessed becomes temporary data. It is possible to determine whether the access master is defined as a read request or not. Here, the access master defined as a read request is called a read master.

  Next, the operation of the cache memory control unit when the access masters 200 and 210 make an access request to the main memory 300 will be described.

  FIG. 3 is a flowchart showing the processing performed by the request control means 30 when it indicates that the access masters 200 and 210 are making a write request to the main memory 300.

  First, the hit detection means 10 determines whether or not a cache line corresponding to the access requested address exists in the cache memory 150 from the address data requested to be accessed and the information stored in the tag memory 40. The request control unit 30 obtains the determination result and the address information 233 on the cache memory 150 from the hit detection unit 10 (step S400).

  In step S400, when the data of the address requested to be accessed exists in the cache memory 150 (Yes), the request control means 30 determines that the cache on the cache memory 150 indicated by the address information 233 obtained from the hit detection means 10 is used. Write data is stored in the line (step S440), and the write process is completed.

  In step S400, when the data of the address requested to be accessed does not exist in the cache memory 150 (No), a cache line for storing the write data of the address requested to be written is secured on the cache memory 150 ( Step S410). Here, when data is already stored in all the cache lines of the cache memory 150, the cache line for storing the write data requested to be written is saved by saving the cache line stored in the past to the main memory 300. Secure.

  Next, the request control means 30 determines whether or not the write data at the address requested to be written is temporary data from the address data requested to be accessed and the information stored in the attribute management means 50 (step). S420).

  In step S420, if the memory area requested by the access masters 200, 210 is not a temporary data area, the request control means 30 uses the cache memory that secured the data stored in the main memory 300 in step S410. Line copying is performed to 150 cache lines (step S430). Thereafter, the request control means 30 overwrites the copied cache line with the write data requested to be written by the access masters 200 and 210 (step S440). Thereafter, when the access master 200, 210 makes a write request to this cache line, it becomes a case where the write area exists in the cache memory 150 in step S400 (Yes), so the cache memory 150 in step S440. Overwrites the write data.

  On the other hand, if it is determined in step S420 that the area to be written is a temporary data area (Yes), the access masters 200 and 210 are newly secured in view of the characteristics of the temporary data area in which only the written memory area is read. For the cache line, the line copy from the main memory 300 to the cache memory 150 is not performed, and the data 223 and 227 input from the access masters 200 and 210 are written to the secured cache line (step S440). Complete the write process.

  As a result, in step S420, it is determined whether the data at the write-requested address is temporary data, and the data is transferred from the main memory 300 only when the data is not temporary data. Therefore, the data to be accessed does not exist in the cache memory. In addition, the number of times the cache memory control unit 100 accesses the main memory 300 can be reduced.

  FIG. 4 is a flowchart showing the processing performed by the request control means 30 when the access masters 200 and 210 indicate that they are making a read (read) request to the main memory 300.

  First, the hit detection means 10 determines whether or not a cache line corresponding to the access requested address exists in the cache memory 150 from the address data requested to be accessed and the information stored in the tag memory 40. The request control unit 30 obtains the determination result and the address information 233 on the cache memory 150 from the hit detection unit 10 (step S500).

  In step S500, when the data of the address requested to be accessed exists in the cache memory 150 (Yes), the request control unit 30 caches the cache memory 150 indicated by the address information 233 obtained from the hit detection unit 10. The corresponding data is read from the line and output as read data (step S540), and the read process is completed.

  In step S500, if the data at the address requested to access does not exist in the cache memory 150 (No), a cache line for reading the write data at the address requested to be read is secured on the cache memory 150 (step S500). S510). Here, when data is already stored in all the cache lines of the cache memory, a cache line for storing the data requested to be read is secured by saving the cache line stored in the past to the main memory.

  The request control means 30 performs line copying of the data stored in the main memory 300 to the cache line of the cache memory 150 secured in step S510 (step S530). Thereafter, the request control means 30 reads the corresponding data from the cache line on the copied cache memory 150 and outputs it as read data (step S540).

  Next, in step S550, the request control unit 30 obtains the attribute of the area read from the attribute management unit 50, and if the memory area read by the access masters 200 and 210 is a temporary data area, the request control unit 30 further performs step S560. Then, the read state of the read cache memory 150 to the cache line is obtained from the read monitoring means 20.

  The read monitoring unit 20 includes read state storage flags corresponding to the number of cache lines in the cache memory 150 × the number of access masters, and updates the read state storage flags with access type signals and address data from the access masters 200 and 210. . For example, when the access master 200 makes a write request and the detection result of the hit detection means 10 indicates a cache hit, the read monitoring means 20 detects that the address data 222 is the end address of the cache line, and Of the read status storage flag of the line, information indicating “unread” as the read status of the access master 200 is stored.

  Thereafter, when the access master 200 makes a read request for the data at the address transferred to the cache line, the read monitoring means 20 reads from the detection result 232 and the address data 222 to the end address of the cache line in the cache memory. If it is detected, the read status of the access master 200 in the read status storage flag of the cache line is updated to information indicating “read”.

  If the read status of the read master defined by the attribute management means 50 is information indicating “read”, the cache line is released from the cache memory 150. Specifically, the flag of the corresponding cache line on the tag memory 40 is changed from valid to invalid (step S570). When a plurality of read masters are defined in the attribute management means 50, if all the read statuses of the defined read masters are “read”, the cache line is released from the cache memory 150.

  As described above, in steps S550 to S570, it is identified from the address data of the access masters 200 and 210 that have requested reading whether or not the cache line storing the data to be read is defined as a temporary data area. If the cache line is a temporary data area and the defined access masters 200 and 210 have finished reading the data of the cache line, the cache line can be released from the cache memory 150 without being held. Data of another cache line on the memory 300 can be stored in the cache memory 150. Since the released cache line is not read-accessed by the same access master or another access master until a certain access master writes to the next, the number of accesses to the main memory 300 due to a cache miss after release is reduced. Can be reduced.

  For example, when the processing system shown in FIG. 1 is a communication processing device such as a network service subscriber terminal, when the communication processing device receives communication data from a subscriber terminal such as a PC, the communication data is temporarily stored in the main memory 300. The communication data is stored according to the network protocol, and the stored communication data is read out and output to the network. After the communication data is output to the network, it is temporary data that is read again only after being updated to new communication data without being read again while being stored in the main memory 300.

  Further, since the saving from the cache memory 150 to the main memory 300 can be omitted when the cache line is released, the number of accesses to the main memory 300 can be reduced. As shown in FIG. 1, two systems of access signals 221 to 223 and 225 to 227 input from the access masters 200 and 210 are individually input to the hit detection unit 10, the read monitoring unit 20, and the request control unit 30. The cache memory control unit 100 may select one of the two systems 221 to 223 and 225 to 227 to sequentially receive the access, hit detection unit 10, read The monitoring unit 20 and the request control unit 30 may be configured such that any one of the signals of the access masters 200 and 210 is sequentially input.

DESCRIPTION OF SYMBOLS 10 Hit detection means 20 Read monitoring means 30 Request control means 40 Tag memory 50 Attribute management means 100 Cache memory control means 150 Cache memory 200, 210 Access master 300 Main memory

Claims (6)

Transfer attribute management means for defining and managing the necessity of data retention after the memory area of the main memory is divided and read from the access master for each of the divided memory areas;
Hit detection means for detecting whether or not a cache line corresponding to an address requested to be accessed from the access master exists in the cache memory;
A request control means for performing data transfer between the main memory and the cache memory and writing or reading data to or from the cache memory based on an access request from the access master;
The request control means, when the access request from the access master is a write request and the hit detection means detects that the cache line corresponding to the access requested address does not exist in the cache memory, the cache memory Secure a cache line corresponding to the address requested to be accessed,
If the memory area including the address requested by the access master to be written by the transfer attribute management means among the divided memory areas is defined to hold data after being read from the access master The data transferred to the cache line that secures the data stored in the address area of the main memory corresponding to the cache line corresponding to the address for which the write request is made, and then the data requested by the access master to be written Write to the reserved cache line,
If the memory area including the address requested by the access master to be written by the transfer attribute management means among the divided memory areas is defined as needing no data retention after being read from the access master A cache memory control device, wherein the data requested by the access master to be written is written to the secured cache line without performing the data transfer. For each access master, it further comprises a read monitoring means for storing cache line information corresponding to a read request from the access master,
The transfer attribute management means further defines and manages an access master that performs read access for each of the divided memory areas of the main memory,
The request control means, based on the information from the read monitoring means and the information defined by the transfer attribute management means, the defined access master completes the read for the cache line corresponding to the read request from the access master. 2. The cache memory control device according to claim 1, wherein when it is determined that the cache line has been read, the cache line corresponding to the read request from the access master is released. The read monitoring means reads all data of the cache line when the read request from the access master is a read request to the last data of the cache line corresponding to the read request from the access master. The cache memory control device according to claim 2, wherein the cache memory control device stores and determines that it has been performed. A transfer attribute management step that divides the memory area of the main memory and defines and manages whether to hold data after being read from the access master for each of the divided memory areas;
A hit detection step of detecting whether a cache line corresponding to an address requested to be accessed from the access master exists in a cache memory;
A request control step for performing data transfer between the main memory and the cache memory and writing or reading data to or from the cache memory based on an access request from the access master;
In the request control step, when the access request from the access master is a write request and the hit detection means detects that the cache line corresponding to the access requested address does not exist in the cache memory, the cache memory Secure a cache line corresponding to the address requested to be accessed,
If the memory area including the address requested by the access master in the transfer attribute management step among the divided memory areas is defined as needing to hold data after being read from the access master The data transferred to the cache line that secures the data stored in the address area of the main memory corresponding to the cache line corresponding to the address for which the write request is made, and then the data requested by the access master to be written Write to the reserved cache line,
If the memory area including the address requested by the access master in the transfer attribute management step among the divided memory areas is defined as holding data after being read from the access master is unnecessary A cache memory control method, wherein the data requested to be written by the access master is written to the cache line secured without performing the data transfer. A read monitoring step for storing information of a cache line corresponding to a read request from the access master for each access master is further provided,
The transfer attribute management step further defines and manages an access master that performs read access for each of the divided memory areas of the main memory,
In the request control step, the defined access master completes the read for the cache line corresponding to the read request from the access master based on the information from the read monitoring step and the information defined in the transfer attribute management step. 5. The cache memory control method according to claim 4, wherein when it is determined that the cache line is satisfied, the cache line corresponding to the read request from the access master is released. The read monitoring step reads all data of the cache line when the read request from the access master is a read request to the last data of the cache line corresponding to the read request from the access master. 6. The cache memory control method according to claim 5, wherein the determination is made and stored.

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