CN114579480A - Page missing processing method, device and system, electronic equipment and storage medium - Google Patents
Page missing processing method, device and system, electronic equipment and storage medium Download PDFInfo
- Publication number
- CN114579480A CN114579480A CN202210258980.XA CN202210258980A CN114579480A CN 114579480 A CN114579480 A CN 114579480A CN 202210258980 A CN202210258980 A CN 202210258980A CN 114579480 A CN114579480 A CN 114579480A
- Authority
- CN
- China
- Prior art keywords
- page
- missing
- data
- processing
- processing unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000003672 processing method Methods 0.000 title claims abstract description 11
- 238000012545 processing Methods 0.000 claims abstract description 281
- 238000000034 method Methods 0.000 claims abstract description 36
- 230000001960 triggered effect Effects 0.000 claims abstract description 7
- 238000004891 communication Methods 0.000 claims description 35
- 238000004590 computer program Methods 0.000 claims description 8
- 238000004458 analytical method Methods 0.000 claims description 3
- 238000007726 management method Methods 0.000 description 7
- 230000008569 process Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 230000009471 action Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000013507 mapping Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000012549 training Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1009—Address translation using page tables, e.g. page table structures
Abstract
The application discloses a page fault processing method, device and system, electronic equipment and a storage medium. The method comprises the following steps: receiving an out-of-page processing request from a central processing unit, wherein the out-of-page processing request is triggered by the central processing unit when determining that an out-of-page exists in a page table entry; analyzing the missing page processing request to obtain the missing page processing information carried by the missing page processing request; executing data writing operation or data reading operation in a target storage object based on the page missing processing information to obtain a processing result, wherein the target storage object is deployed in the FPGA chip; and feeding back the processing result to the central processing unit so that the central processing unit updates the page table entry according to the processing result. According to the method and the device, when the central processing unit determines that the page table entries have page faults, the FPGA chip is requested to execute the page fault processing operation, the mode of accessing the FPGA chip to replace the original mode of accessing a disk is adopted, the central processing unit can access the disk quickly, and meanwhile a large amount of central processing unit resources do not need to be consumed.
Description
Technical Field
The present application relates to the field of computer technologies, and in particular, to a method, an apparatus, a system, an electronic device, and a storage medium for processing missing pages.
Background
Modern operating systems implement virtual memory technology, considering main memory as an address space cache stored on disk, where only the active area is kept. When the physical memory of the system is not enough, the operating system performs page swapping to transfer pages back and forth between the disk and the main memory, and because the disk access speed is slow, frequent disk access inevitably causes system performance degradation.
In the address mapping process, if the page to be accessed is found not to be in the memory in the page, a page missing interrupt is generated. When a page fault interrupt occurs, if there is no free page in the operating system memory, the operating system must select a page in the memory to move it out of the memory, so as to make room for the page to be called in. And the rule used to select which page to cull is called the page replacement algorithm. The currently used page replacement algorithms mainly include an optimal replacement algorithm (OPT), a first-in first-out replacement algorithm (FIFO), and a least recently used algorithm (LRU).
The various algorithms described above are from a software perspective, and reduce the page swapping times by reducing the page swapping between the main memory and the disk through a reasonable swapping policy, but the swapping medium is still a disk or a flash memory. The CPU accesses the main memory for hundreds of clock cycles, whereas accessing the disk requires millions of clock cycles, and therefore, each page swap is performed, a large amount of CPU resources are consumed, thereby reducing the overall performance.
Disclosure of Invention
In order to solve the technical problems or at least partially solve the technical problems, the application provides a missing page processing method, a missing page processing device, a missing page processing system, an electronic device and a storage medium.
According to an aspect of the embodiments of the present application, there is provided a page fault processing method applied to an FPGA chip, the method including:
receiving a page fault processing request from a central processing unit, wherein the page fault processing request is triggered by the central processing unit when determining that a page fault exists in a page table entry;
analyzing the missing page processing request to obtain missing page processing information carried by the missing page processing request;
executing data writing operation or data reading operation in a target storage object based on the page missing processing information to obtain a processing result, wherein the target storage object is deployed in the FPGA chip;
and feeding back the processing result to the central processing unit so that the central processing unit updates the page table entry according to the processing result.
Further, the analyzing the missing page processing request to obtain the missing page processing information carried by the missing page processing request includes:
calling a computer quick link protocol to analyze the missing page processing request to obtain original missing page processing information;
extracting a target identifier and associated data of the target identifier from the original page fault processing information, and determining the target identifier and the associated data as the page fault processing information, wherein the target identifier is used for indicating to execute a data writing operation or a data reading operation.
Further, before performing a data write operation or a data read operation in the target memory object based on the page fault processing information to obtain a processing result, the method further includes:
and determining the target storage object based on a target identifier in the page missing processing information, wherein the target storage object is a memory of the FPGA chip under the condition that the target identifier is used for indicating to execute a data writing operation, and the target storage object is a random access memory of the FPGA chip under the condition that the target identifier is used for indicating to execute a data reading operation.
Further, the executing a data write operation or a data read operation in the target storage object based on the page fault processing information to obtain a processing result includes:
executing an interrupt operation on a communication link between the FPGA chip and the central processing unit under the condition that a target identifier carried in the page missing processing information is used for indicating to execute data writing operation;
detecting whether the first data exists in a buffer connected with the FPGA chip;
writing the first data into the memory from the buffer area under the condition that the first data exists in the buffer area, wherein the first data is the data written into the buffer area by the central processing unit after the communication link is interrupted;
and updating page table information of a page table in the memory by using the first data to obtain updated page table information, and determining the updated page table information as the processing result.
Further, the executing a data write operation or a data read operation in the target storage object based on the page fault processing information to obtain a processing result includes:
under the condition that a target identifier carried in the page fault processing information is used for indicating to execute data reading operation, acquiring a page fault address from associated data of the target identifier;
inquiring whether the missing page address exists in a buffer area connected with the FPGA chip to obtain an inquiry result;
and executing data reading operation corresponding to the query result to obtain the processing result.
Further, the executing the data reading operation corresponding to the query result includes:
generating first notification information under the condition that the page fault address exists in the query result, wherein the first notification information is used for notifying the central processing unit to read second data corresponding to the page fault address from the buffer area;
and reading the updating data from the MEM controller connected with the FPGA chip under the condition that the page fault address does not exist in the query result, writing the updating data into the buffer area, updating the fast table information in the random access memory, and sending second notification information to the central processing unit, wherein the second notification information is used for notifying the central processing unit to read the second data corresponding to the page fault address from the buffer area.
According to another aspect of the embodiments of the present application, there is also provided an apparatus for processing missing pages, including:
the page fault processing device comprises a receiving module, a processing module and a processing module, wherein the receiving module is used for receiving a page fault processing request from a central processing unit, and the page fault processing request is triggered when the central processing unit determines that a page fault exists in a page table entry;
the analysis module is used for analyzing the missing page processing request to obtain the missing page processing information carried by the missing page processing request;
the execution module is used for executing data writing operation or data reading operation in a target storage object based on the page missing processing information to obtain a processing result, wherein the target storage object is deployed in the FPGA chip;
and the sending module is used for feeding back the processing result to the central processing unit so that the central processing unit updates the page table entry according to the processing result.
According to another aspect of the embodiments of the present application, there is also provided a page fault processing system, including: a central processing unit and an FPGA chip;
the central processing unit is used for acquiring a virtual address, generating a page table entry address according to the virtual address, reading a page table entry from a memory according to the page table entry address, detecting the page table entry, and sending a missing page processing request to the FPGA chip under the condition that a missing page exists in the page table entry;
the FPGA chip is used for receiving a missing page processing request from the central processing unit; analyzing the missing page processing request to obtain missing page processing information carried by the missing page processing request; executing data writing operation or data reading operation in a target storage object based on the page missing processing information to obtain a processing result, wherein the target storage object is deployed in the FPGA chip; and feeding back the processing result to the central processing unit so that the central processing unit updates the page table entry according to the processing result.
According to another aspect of the embodiments of the present application, there is also provided a storage medium including a stored program that executes the above steps when the program is executed.
According to another aspect of the embodiments of the present application, there is also provided an electronic apparatus, including a processor, a communication interface, a memory, and a communication bus, where the processor, the communication interface, and the memory complete communication with each other through the communication bus; wherein: a memory for storing a computer program; a processor for executing the steps of the method by running the program stored in the memory.
Embodiments of the present application also provide a computer program product containing instructions, which when run on a computer, cause the computer to perform the steps of the above method.
Compared with the prior art, the technical scheme provided by the embodiment of the application has the following advantages: according to the method and the device, when the central processing unit determines that the page table entries have page faults, the FPGA chip is requested to execute the page fault processing operation, the mode of accessing the FPGA chip to replace the original mode of accessing a disk is adopted, the central processing unit can access the disk quickly, and meanwhile a large amount of central processing unit resources do not need to be consumed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application.
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.
Fig. 1 is a flowchart of a page fault processing method according to an embodiment of the present application;
fig. 2 is an internal schematic diagram of an FPGA chip according to an embodiment of the present disclosure;
fig. 3 is a flowchart of a page fault processing method according to another embodiment of the present application;
fig. 4 is a block diagram of a page fault processing apparatus according to an embodiment of the present application;
FIG. 5 is a block diagram of a page fault processing system according to an embodiment of the present application;
fig. 6 is an external schematic view of an FPGA chip according to an embodiment of the present disclosure;
fig. 7 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application, it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments, and the illustrative embodiments and descriptions thereof of the present application are used for explaining the present application and do not constitute a limitation to the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another similar entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The embodiment of the application provides a method, a device and a system for processing missing pages, electronic equipment and a storage medium. The method provided by the embodiment of the present invention may be applied to any required electronic device, for example, the electronic device may be an electronic device such as a server and a terminal, and the method is not specifically limited herein, and for convenience of description, the method is hereinafter simply referred to as an electronic device.
According to an aspect of an embodiment of the present application, a method embodiment of a page fault processing method is provided. Fig. 1 is a flowchart of a page fault processing method according to an embodiment of the present application, and as shown in fig. 1, the method includes:
step S11, a page fault processing request is received from the central processing unit, where the page fault processing request is triggered by the central processing unit when it is determined that there is a page fault in the page table entry.
The method provided by the embodiment of the application is applied to the FPGA chip, the FPGA chip is deployed in the page fault processing system, and the FPGA chip is in communication connection with a central processing unit in the page fault processing system. It should be noted that the central processing unit may obtain the virtual address, generate a page table entry address according to the virtual address, read a page table entry from the memory according to the page table entry address, detect the page table entry, and send a missing page processing request to the FPGA chip when there is a missing page in the page table entry. And after receiving the missing page processing request, the FPGA chip executes corresponding missing page processing operation according to the missing page processing request.
Specifically, as shown in fig. 2, the FPGA chip includes: the CXL subsystem (including cxl.io, cxl.mem subprotocol layer, CXL coherence Engine, and CXL phy), a fast table control unit, a bus arbitration management module, a MEM controller, a control register, a status register, and the like. The CXL.io subprotocol is used for realizing IO communication between HOST and FPGA, and comprises functions of link training, command sending, msi-x interruption and the like, the CXL.mem subprotocol is used for MEM access control, and the TLB cache control unit is used for MEM caching. The bus arbitration management module is responsible for access arbitration of the plurality of MEMs.
In the embodiment of the application, before the FPGA chip receives the page fault processing request, a communication link between the FPGA chip and the central processing unit is initialized to wait for the central processing unit to send the page fault processing request, and after the page fault processing request exists in the communication link, the cxl.
And step S12, analyzing the missing page processing request to obtain the missing page processing information carried by the missing page processing request.
In this embodiment of the present application, as shown in fig. 3, in step S12, parsing the missing page processing request to obtain the missing page processing information carried in the missing page processing request includes the following steps a1-a 2:
step A1, a computer quick link protocol is called to analyze the missing page processing request, and original missing page processing information is obtained.
In this embodiment of the present application, the FPGA chip may invoke a computer quick link protocol (cxl. io subprotocol) to analyze the missing page processing request, and the obtained original missing page processing information includes: target identification, data source, address, page fault or swap information. The target identifier is used to indicate that a data write operation or a data read operation is performed, and it should be noted that if the target identifier is the data write identifier, a page swap operation needs to be performed. If the target identifier is the data reading identifier, the page missing operation needs to be executed.
Step a2, extracting the target identifier and the associated data of the target identifier from the original page missing processing information, and determining the target identifier and the associated data as the page missing processing information.
In the embodiment of the application, the target identifier and the associated data of the target identifier are extracted from the original page missing processing information, and when the target identifier is the data writing identifier, the associated data of the target identifier does not need to be extracted from the original page missing processing information. And under the condition that the target identifier is a data reading identifier, extracting a page missing address from the original page missing processing information, and taking the page missing address as associated data. And after the target identification and the associated address are obtained, determining the target identification and the associated data as page missing processing information.
And step S13, executing data writing operation or data reading operation in the target storage object based on the page fault processing information to obtain a processing result, wherein the target storage object is deployed in the FPGA chip.
In this embodiment of the present application, before performing a data write operation or a data read operation in a target storage object based on the missing page processing information and obtaining a processing result, the method further includes: and determining a target storage object based on the target identification in the missing page processing information.
In the embodiment of the present application, the target identifier is used to indicate that a data write operation or a data read operation is to be performed. At the moment, different target storage objects are set according to data reading operation or data writing operation, meanwhile, a page table is stored in the internal memory of the FPGA chip, and a fast table is stored in the random access memory of the FPGA chip. Therefore, in the case that the target identifier is used for indicating to execute the data writing operation, the target storage object is the memory of the FPGA chip, and in the case that the target identifier is used for indicating to execute the data reading operation, the target storage object is the random access memory of the FPGA chip.
In the embodiment of the present application, step S13, executing a data write operation or a data read operation in the target storage object based on the page fault processing information, and obtaining a processing result, includes the following steps B1-B4:
and step B1, executing interruption operation to the communication link between the FPGA chip and the central processing unit under the condition that the target identification carried in the page fault processing information is used for indicating to execute data writing operation.
And step B2, detecting whether the buffer connected with the FPGA chip has first data.
And step B3, writing the first data into the memory from the buffer area under the condition that the first data exists in the buffer area, wherein the first data is the data which is written into the buffer area by the central processing unit after the communication link is interrupted.
Step B4, the page table information of the page table in the memory is updated by using the first data, so as to obtain updated page table information, and the updated page table information is determined as the processing result.
In the embodiment of the application, when the target identifier is used to indicate that data writing operation is to be performed, an interruption operation is performed on a communication link between the FPGA chip and the central processing unit, and at this time, the central processing unit detects that the communication link is interrupted, and the central processing unit directly writes the first data into the buffer area. It should be noted that the FPGA chip notifies the central processing unit by interrupting the communication link, so that the central processing unit sends the first data to the buffer area when the communication link is interrupted.
In the embodiment of the application, whether the buffer area of the FPGA chip has the first data or not is determined, and the first data is written into the memory of the FPGA chip from the buffer area under the condition that the buffer area has the first data. And then updating page table information in the memory, and determining the updated page table information as a processing result. It should be noted that, in the embodiment of the present application, the page table is disposed in the FPGA chip, and data sent by the central processing unit can be stored in the memory of the FPGA chip when performing page switching, so that the page table is transferred from the system disk to the inner side of the FPGA chip for storage, which is convenient for the central processing unit to access quickly, does not consume a large amount of resources of the central processing unit, and improves the access efficiency of the central processing unit.
In the embodiment of the present application, step S13, executing a data write operation or a data read operation in the target storage object based on the page fault processing information, and obtaining a processing result, includes the following steps C1-C3:
and step C1, acquiring the page fault address from the associated data of the target identifier when the target identifier carried in the page fault processing information is used for indicating to execute the data reading operation.
And step C2, inquiring whether the buffer area connected with the FPGA chip has a missing page address or not to obtain an inquiry result.
And step C3, executing the data reading operation corresponding to the query result to obtain a processing result.
In the embodiment of the application, when the target identifier is used to indicate to execute a data reading operation, the FPGA chip may directly obtain a missing page address from the associated data, then query whether the missing page address exists in the buffer, execute a corresponding data reading operation according to the query result,
specifically, the executing of the data reading operation corresponding to the query result includes the following steps C301 to C302:
and generating first notification information under the condition that the page fault address exists in the query result, wherein the first notification information is used for notifying the central processing unit to read the second data corresponding to the page fault address from the buffer area.
Or, when the inquiry result shows that the page missing address does not exist, reading the updated data from the MEM controller connected with the FPGA chip, writing the updated data into the buffer, updating the cache table information in the random access memory, and sending second notification information to the central processing unit, wherein the second notification information is used for notifying the central processing unit to read the second data corresponding to the page missing address from the buffer.
In the embodiment of the present application, when the query result indicates that a page fault address exists, the first notification information is taken as a processing result. And taking the second notification information as a processing result when the inquiry result is that the page fault address does not exist.
Step S14, feeding back the processing result to the central processing unit, so that the central processing unit updates the page table entry according to the processing result.
According to the method and the device, when the central processing unit determines that the page table entries have page faults, the FPGA chip is requested to execute the page fault processing operation, the mode of accessing the FPGA chip to replace the original mode of accessing a disk is adopted, the central processing unit can access the disk quickly, and meanwhile a large amount of central processing unit resources do not need to be consumed.
Fig. 4 is a block diagram of an apparatus for processing page faults provided in an embodiment of the present application, where the apparatus may be implemented as part or all of an electronic device through software, hardware, or a combination of the two. As shown in fig. 4, the apparatus includes:
a receiving module 31, configured to receive a page fault processing request from a central processing unit, where the page fault processing request is triggered by the central processing unit when determining that a page fault exists in a page table entry;
the analyzing module 32 is configured to analyze the missing page processing request to obtain missing page processing information carried by the missing page processing request;
the execution module 33 is configured to perform a data writing operation or a data reading operation in a target storage object based on the missing page processing information to obtain a processing result, where the target storage object is deployed in the FPGA chip;
and a sending module 34, configured to feed back the processing result to the central processing unit, so that the central processing unit updates the page table entry according to the processing result.
In the embodiment of the application, the analysis module is used for calling a computer quick link protocol to analyze the missing page processing request to obtain original missing page processing information; and extracting a target identifier and associated data of the target identifier from the original page missing processing information, and determining the target identifier and the associated data as the page missing processing information, wherein the target identifier is used for indicating that data writing operation or data reading operation is executed.
In this embodiment of the present application, the missing page processing apparatus further includes: and the determining module is used for determining a target storage object based on a target identifier in the page missing processing information, wherein the target storage object is a memory of the FPGA chip under the condition that the target identifier is used for indicating to execute a data writing operation, and the target storage object is a random access memory of the FPGA chip under the condition that the target identifier is used for indicating to execute a data reading operation.
In the embodiment of the present application, the execution module is configured to execute an interrupt operation on a communication link between the FPGA chip and the central processing unit when the target identifier carried in the page fault processing information is used to indicate that a data write operation is executed; detecting whether first data exist in a buffer connected with the FPGA chip; under the condition that first data exist in the buffer area, writing the first data into the memory from the buffer area, wherein the first data are the data written into the buffer area by the central processing unit after the communication link is interrupted; and updating page table information of a page table in the memory by using the first data to obtain updated page table information, and determining the updated page table information as a processing result.
In this embodiment of the present application, the execution module is configured to, when a target identifier carried in the page fault processing information is used to indicate that a data reading operation is to be performed, obtain a page fault address from associated data of the target identifier; inquiring whether a missing page address exists in a buffer area connected with the FPGA chip to obtain an inquiry result; and executing data reading operation corresponding to the query result.
In this embodiment of the present application, the execution module is configured to send, to the central processing unit, first notification information when the query result indicates that a page missing address exists, so that the central processing unit reads, according to the first notification information, second data corresponding to the page missing address from the buffer; and when the inquiry result shows that the missing page address does not exist, reading the updated data from the MEM controller connected with the FPGA chip, writing the updated data into the buffer area, and sending second notification information to the central processing unit, so that the central processing unit reads the second data corresponding to the missing page address from the updated data in the buffer area according to the second notification information.
Fig. 5 is a block diagram of a page fault processing system provided in an embodiment of the present application, where the system may be implemented as part of or all of an electronic device through software, hardware, or a combination of the two. As shown in fig. 5, the system includes: a central processor 51 and an FPGA chip 52;
the central processing unit 51 is configured to obtain a virtual address, generate a page table entry address according to the virtual address, read a page table entry from the memory according to the page table entry address, detect the page table entry, and send a missing page processing request to the FPGA chip when there is a missing page in the page table entry;
the FPGA chip 52 is used for receiving a missing page processing request from the central processing unit; analyzing the missing page processing request to obtain the missing page processing information carried by the missing page processing request; executing data writing operation or data reading operation in a target storage object based on the page missing processing information to obtain a processing result, wherein the target storage object is deployed in the FPGA chip; and feeding back the processing result to the central processing unit so that the central processing unit updates the page table entry according to the processing result.
In the embodiment of the present application, the FPGA chip is connected to the CPLD, the flash memory, and the plurality of MEM controllers, as shown in fig. 6, the system uses the FPGA as a main processing chip, the CPLD is used for power management and board management, and supports 4-channel high-capacity DDR, the interface uses the CXL protocol, and is compatible with the PCIe protocol in physical form, and the board can be directly inserted into the PCIe slot of the motherboard through a gold finger.
In the application embodiment, the processing flow of the system is as follows:
step 1: the central processing unit generates a virtual address.
Step 2: the memory management unit of the central processing unit generates a page table entry address according to the virtual address generated by the central processing unit.
And step 3: and reading the memory to obtain the page table entry corresponding to the page table entry address.
And 4, step 4: the memory management unit judges whether the effective flag bit of the page table entry is 0, if the effective flag bit of the page table entry is 0, the page table entry triggers a page missing processing request, and the FPGA chip executes a page missing exception handling program.
And 5: and the missing page exception processing program determines missing page or exchange page related information and sends the information to CXL HOST.
Step 6: and the CXL HOST realizes the MEM read-write operation on the FPGA side through CXL.io and CXL.mem. And the new page is called into the local memory, and simultaneously the system updates the page table entry in the local memory.
And 7: and returning the page missing processing program to the original process, and executing the instruction causing the page missing again. Because the new page is cached in memory, the memory management unit will hit, thereby generating a physical address and the process will continue to execute.
An embodiment of the present application further provides an electronic device, as shown in fig. 7, the electronic device may include: a processor 1501, a communication interface 1502, a memory 1503 and a communication bus 1504, wherein the processor 1501, the communication interface 1502 and the memory 1503 complete communication with each other through the communication bus 1504.
A memory 1503 for storing a computer program;
the processor 1501 is configured to implement the steps of the above embodiments when executing the computer program stored in the memory 1503.
The communication bus mentioned in the above terminal may be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown, but this does not mean that there is only one bus or one type of bus.
The communication interface is used for communication between the terminal and other equipment.
The Memory may include a Random Access Memory (RAM) or a non-volatile Memory (non-volatile Memory), such as at least one disk Memory. Optionally, the memory may also be at least one memory device located remotely from the processor.
The Processor may be a general-purpose Processor, and includes a Central Processing Unit (CPU), a Network Processor (NP), and the like; the Integrated Circuit may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, a discrete Gate or transistor logic device, or a discrete hardware component.
In another embodiment provided by the present application, a computer-readable storage medium is further provided, in which instructions are stored, and when the instructions are executed on a computer, the computer is caused to execute the missing page processing method in any one of the above embodiments.
In yet another embodiment provided by the present application, there is also provided a computer program product containing instructions which, when run on a computer, cause the computer to perform the page fault handling method described in any of the above embodiments.
In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the application to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire (e.g., coaxial cable, fiber optic, digital subscriber line) or wirelessly (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that incorporates one or more of the available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk), among others.
The above description is only for the preferred embodiment of the present application, and is not intended to limit the scope of the present application. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application are included in the protection scope of the present application.
The previous description is only an example of the present application, and is provided to enable any person skilled in the art to understand or implement the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A page fault processing method is characterized by being applied to an FPGA chip, and comprises the following steps:
receiving a page fault processing request from a central processing unit, wherein the page fault processing request is triggered by the central processing unit when determining that a page fault exists in a page table entry;
analyzing the missing page processing request to obtain the missing page processing information carried by the missing page processing request;
executing data writing operation or data reading operation in a target storage object based on the page missing processing information to obtain a processing result, wherein the target storage object is deployed in the FPGA chip;
and feeding back the processing result to the central processing unit so that the central processing unit updates the page table entry according to the processing result.
2. The method according to claim 1, wherein the analyzing the missing page processing request to obtain the missing page processing information carried by the missing page processing request includes:
calling a computer quick link protocol to analyze the missing page processing request to obtain original missing page processing information;
extracting a target identifier and associated data of the target identifier from the original page fault processing information, and determining the target identifier and the associated data as the page fault processing information, wherein the target identifier is used for indicating to execute a data writing operation or a data reading operation.
3. The method of claim 2, wherein before performing a data write operation or a data read operation in a target memory object based on the page fault handling information to obtain a handling result, the method further comprises:
and determining the target storage object based on a target identifier in the page missing processing information, wherein the target storage object is a memory of the FPGA chip under the condition that the target identifier is used for indicating to execute a data writing operation, and the target storage object is a random access memory of the FPGA chip under the condition that the target identifier is used for indicating to execute a data reading operation.
4. The method of claim 3, wherein performing a data write operation or a data read operation in the target memory object based on the page fault processing information to obtain a processing result comprises:
executing an interrupt operation on a communication link between the FPGA chip and the central processing unit under the condition that a target identifier carried in the missing page processing information is used for indicating execution of data writing operation;
detecting whether first data exist in a buffer area connected with the FPGA chip;
writing the first data into the memory from a buffer area under the condition that the first data exists in the buffer area, wherein the first data is the data written into the buffer area by the central processing unit after the communication link is interrupted;
and updating page table information of a page table in the memory by using the first data to obtain updated page table information, and determining the updated page table information as the processing result.
5. The method of claim 3, wherein performing a data write operation or a data read operation in the target memory object based on the page fault processing information to obtain a processing result comprises:
under the condition that a target identifier carried in the page fault processing information is used for indicating to execute data reading operation, acquiring a page fault address from associated data of the target identifier;
inquiring whether the missing page address exists in a buffer area connected with the FPGA chip to obtain an inquiry result;
and executing data reading operation corresponding to the query result to obtain the processing result.
6. The method of claim 5, wherein the performing the data reading operation corresponding to the query result comprises:
generating first notification information under the condition that the page fault address exists in the query result, wherein the first notification information is used for notifying the central processing unit to read second data corresponding to the page fault address from the buffer area;
and reading the updating data from the MEM controller connected with the FPGA chip under the condition that the page fault address does not exist in the query result, writing the updating data into the buffer area, updating the fast table information in the random access memory, and sending second notification information to the central processing unit, wherein the second notification information is used for notifying the central processing unit to read the second data corresponding to the page fault address from the buffer area.
7. An apparatus for processing missing pages, comprising:
the page fault processing device comprises a receiving module, a processing module and a processing module, wherein the receiving module is used for receiving a page fault processing request from a central processing unit, and the page fault processing request is triggered when the central processing unit determines that a page fault exists in a page table entry;
the analysis module is used for analyzing the missing page processing request to obtain the missing page processing information carried by the missing page processing request;
the execution module is used for executing data writing operation or data reading operation in a target storage object based on the page missing processing information to obtain a processing result, wherein the target storage object is deployed in the FPGA chip;
and the sending module is used for feeding back the processing result to the central processing unit so that the central processing unit updates the page table entry according to the processing result.
8. A page fault handling system, comprising: a central processing unit and an FPGA chip;
the central processing unit is used for acquiring a virtual address, generating a page table entry address according to the virtual address, reading a page table entry from a memory according to the page table entry address, detecting the page table entry, and sending a missing page processing request to the FPGA chip under the condition that a missing page exists in the page table entry;
the FPGA chip is used for receiving a missing page processing request from the central processing unit; analyzing the missing page processing request to obtain missing page processing information carried by the missing page processing request; executing data writing operation or data reading operation in a target storage object based on the missing page processing information to obtain a processing result, wherein the target storage object is deployed in the FPGA chip; and feeding back the processing result to the central processing unit so that the central processing unit updates the page table entry according to the processing result.
9. A storage medium, characterized in that the storage medium comprises a stored program, wherein the program is operative to perform the method steps of any of the preceding claims 1 to 6.
10. An electronic device is characterized by comprising a processor, a communication interface, a memory and a communication bus, wherein the processor and the communication interface are used for realizing mutual communication by the memory through the communication bus; wherein:
a memory for storing a computer program;
a processor for performing the method steps of any of claims 1 to 6 by executing a program stored on a memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210258980.XA CN114579480A (en) | 2022-03-10 | 2022-03-10 | Page missing processing method, device and system, electronic equipment and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210258980.XA CN114579480A (en) | 2022-03-10 | 2022-03-10 | Page missing processing method, device and system, electronic equipment and storage medium |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114579480A true CN114579480A (en) | 2022-06-03 |
Family
ID=81780547
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210258980.XA Pending CN114579480A (en) | 2022-03-10 | 2022-03-10 | Page missing processing method, device and system, electronic equipment and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114579480A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116431530A (en) * | 2023-02-08 | 2023-07-14 | 北京超弦存储器研究院 | CXL memory module, memory processing method and computer system |
| WO2024021995A1 (en) * | 2022-07-25 | 2024-02-01 | 华为技术有限公司 | Memory access method and apparatus |
-
2022
- 2022-03-10 CN CN202210258980.XA patent/CN114579480A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024021995A1 (en) * | 2022-07-25 | 2024-02-01 | 华为技术有限公司 | Memory access method and apparatus |
| CN116431530A (en) * | 2023-02-08 | 2023-07-14 | 北京超弦存储器研究院 | CXL memory module, memory processing method and computer system |
| CN116431530B (en) * | 2023-02-08 | 2024-03-15 | 北京超弦存储器研究院 | CXL memory module, memory processing method and computer system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111177029B (en) | System and method for managing software-defined persistent memory | |
| US7366835B2 (en) | Data access responding system, storage system, client apparatus, cache apparatus, and method for accessing data access responding system | |
| US7613884B2 (en) | Multiprocessor system and method ensuring coherency between a main memory and a cache memory | |
| JP3987577B2 (en) | Method and apparatus for caching system management mode information along with other information | |
| CN114579480A (en) | Page missing processing method, device and system, electronic equipment and storage medium | |
| CN111338561B (en) | Memory controller and memory page management method | |
| JP4474570B2 (en) | Cache coherency control method | |
| JP2000250813A (en) | Data managing method for i/o cache memory | |
| JP2695017B2 (en) | Data transfer method | |
| CN112214247A (en) | System starting method and related equipment | |
| CN116414735A (en) | Data storage method, system, storage access configuration method and related equipment | |
| US8719499B2 (en) | Cache-line based notification | |
| JP5254710B2 (en) | Data transfer device, data transfer method and processor | |
| US20210374063A1 (en) | Method for processing page fault by processor | |
| KR20040067063A (en) | The low power consumption cache memory device of a digital signal processor and the control method of the cache memory device | |
| CN116601616A (en) | Data processing device, method and related equipment | |
| JP2002024007A (en) | Processor system | |
| CN112612726B (en) | Data storage method and device based on cache consistency, processing chip and server | |
| US20240103913A1 (en) | Task scheduling method and system, and hardware task scheduler | |
| US20230169012A1 (en) | Electronic device and method for co-operating software and hardware | |
| US20230280904A1 (en) | Monitoring memory locations to identify whether data stored at the memory locations has been modified | |
| JP3517884B2 (en) | Data processing device | |
| CN108804020B (en) | Storage processing method and device | |
| US9798479B2 (en) | Relocatable and resizable tables in a computing device | |
| JPH05158793A (en) | Parallel cache memory |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |