WO2024021995A1

WO2024021995A1 - Memory access method and apparatus

Info

Publication number: WO2024021995A1
Application number: PCT/CN2023/104015
Authority: WO
Inventors: 韦康; 李海程; 王楠
Original assignee: 华为技术有限公司
Priority date: 2022-07-25
Filing date: 2023-06-29
Publication date: 2024-02-01
Also published as: CN117407326A

Abstract

Embodiments of the present application provide a memory access method and apparatus. The method comprises: during the handling of a page fault corresponding to a virtual address space, according to a handling component label used for identifying a target handling component corresponding to the virtual address space, directly instructing the target handling component to perform fault handling on the page fault, that is, solving the problem of page fault, so that a requester of an access request can access the virtual address space. Thus, according to the present application, inter-process communication between a specific page fault handling component and the target handling component may be reduced, thereby improving memory access efficiency.

Description

Memory access method and device

This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on July 25, 2022, with application number 202210878562.0 and the application title "Memory Access Method and Device", the entire content of which is incorporated into this application by reference. .

Technical field

Embodiments of the present application relate to the field of computers, and in particular, to a memory access method and device.

Background technique

The microkernel architecture is an operating system architecture that includes a microkernel and system services. Among them, the microkernel is used to implement the core functions of the operating system in the kernel state, such as tasks, threads, and kernel state memory management. System services include multiple components, which are used to implement process management, file management, and user-mode memory management of the operating system in user mode.

In related technologies, the operating system usually uses a delayed loading mechanism for memory access: when allocating memory for a user's access request, it only allocates a virtual address space and does not allocate an actual physical address space. In this way, a page fault will be triggered when the operating system accesses the virtual address space. At this time, the kernel of the operating system can detect the page fault exception and call the page fault exception handler (page fault handler) to allocate the physical address space corresponding to the virtual address space. Based on the allocation result, the memory access requester can access the physical address space to achieve memory access.

However, in an operating system with a microkernel architecture, the microkernel is in the kernel mode and lacks sufficient page fault exception handling information. It needs to be called in the user mode through a specific page fault exception handler in the system service (such as the user mode memory management service). The page fault exception handler. In this way, inter-process communication (IPC) is formed between different page fault exception handlers, causing the efficiency of memory access to be greatly affected.

Contents of the invention

This application provides a memory access method and device to solve the above problems. In this method, the virtual address space is allocated a processing component label in advance to avoid inter-process communication between a specific page fault exception processing component and the target processing component, thereby improving the efficiency of memory access.

In a first aspect, embodiments of the present application provide a memory access method. The method includes: obtaining a first access request, which is used to indicate access to the first virtual address space; if a memory access request corresponding to the first virtual address space is detected. First page missing exception, obtain the processing component label of the first virtual address space; wherein, the processing component label of the first virtual address space is used to identify the first processing component corresponding to the first virtual address space; based on the first virtual address space The processing component label instructs the first processing component to perform exception processing on the first page missing exception. The first processing component performs exception processing on the first page missing exception, which may include allocating a physical address space for the first virtual address space, that is, the first After the exception caused by the page fault exception has been resolved, the requester of the first access request, such as the first memory access request component, can access the first virtual address space normally.

In the embodiment of the present application, by adding a processing component label to the virtual address space in advance, the target processing component can be directly instructed to handle the page missing exception based on the label for page missing exceptions that occur during memory access, thereby avoiding specific page missing exceptions. The efficiency decrease caused by the inter-process interaction between the exception handling component and the target processing component improves the memory access efficiency. Among them, the processing component label can directly indicate the exception handling component corresponding to the virtual address space. Compared with the fixed division of the virtual address space range, it can ensure the flexible use of the virtual address space and avoid application scenarios caused by the fixed division of the virtual address space range. Not compatible.

Exemplarily, FIG. 9 is an exemplary schematic diagram of a scenario of adding an exception handling component label provided by the embodiment of the present application. As shown in Figure 9, the first virtual address space may be virtual address space 1, and accordingly, the processing component label may be label 2. FIG. 15 is a schematic diagram of a processing scenario illustrating an exemplary page fault exception processing method. As shown in Figure 15, if the processing component label of the first virtual address space is a file type label, the first processing component can provide file memory page fault exception processing services.

According to the first aspect, obtaining a processing component label of the first virtual address space includes:

According to the first virtual address space, search the processing component label from the page table; wherein, the processing component label is included in the target page table entry of the page table of the first virtual address space; the page table is when the first virtual address space is pre-allocated. Establish; the target page table entry is a page table entry in the page table used to record the physical address space information corresponding to the first virtual address space.

In the embodiment of the present application, the present application creates a page table before handling the page fault exception, for example, when allocating virtual memory space. In this way, this application can use the page table to record the exception handler label, thereby using the exception handler label to handle page missing exceptions. The exception handler label can be added to the virtual address space without introducing a complex data structure.

Exemplarily, FIG. 10c is a structural diagram of a page table for recording tags provided by an embodiment of the present application; FIG. 10d is another structural diagram of a page table for recording tags provided by an embodiment of the present application. As shown in Figure 10c or Figure 10d, the first virtual address space can be the virtual address space VA, and the page table of the first virtual address space can be the Level 0 Page Table in Figure 10c; or the first virtual address space. The page table may be a multi-level page table as shown in Figure 10d. The target page table entry is the page table entry where the exception handler label Lablem is located in the page table shown in Figure 10c or Figure 10d.

According to the first aspect, or any implementation of the first aspect above, the processing result of the first processing component may include updating the page table; wherein updating the page table is for the first processing component to allocate a physical address space to the first virtual address space. , and the target page table entry is updated based on the physical address space; thus, the first memory access request component can access the first virtual address space based on the updated page table.

In the embodiment of the present application, after allocating a physical address space to the first virtual address space, the first processing component updates the target page table entry based on the physical address space to obtain an updated page table, thereby ensuring that the page missing exception is resolved, and Access to the first virtual address space based on updating the page table.

Exemplarily, FIG. 10a is an exemplary structural diagram of a page table when mapping has been established; FIG. 10b is an exemplary structural diagram of a page table when mapping has been established. As shown in Figure 10c or Figure 10d, the update page table may be the page table shown in Figure 10c or Figure 10d.

According to the first aspect, or any implementation of the above first aspect, the processing component label is generated according to the memory type of the first virtual address space and the component identifier of the processing component corresponding to the memory type.

In the embodiment of the present application, the processing component label is generated by using the memory type of the first virtual address space and the component identification of the corresponding processing component, which can ensure the accuracy of the processing component identified by the processing component label.

According to the first aspect, or any implementation of the above first aspect, in response to the processing feedback information of the first processing component, after accessing the first virtual address space, the method further includes:

Obtain a second access request, the second access request is used to indicate access to the second virtual address space;

If a second page fault exception corresponding to the second virtual address space is detected, obtain the processing component label of the second virtual address space; wherein, the processing component label of the second virtual address space is used to identify the processing component label corresponding to the second virtual address space. second processing component;

Detect whether the processing component label of the second virtual address space meets the preset conditions;

If not, instruct the designated processing component to handle the second page fault exception. Designating a processing component to handle the second page missing exception may include allocating a physical address space for the second virtual address space. That is, the exception caused by the second page missing exception has been resolved, and the requester of the second access request, such as the second The memory access request component can normally access the second virtual address space.

In the embodiment of this application, by specifying a processing component, that is, providing a default processing component for page missing exceptions, it is possible to deal with the situation where the processing component label does not meet the preset conditions, thereby further improving the success rate of memory access and improving user experience.

For example, if the processing component label does not meet the preset conditions, it may include: the processing component label does not exist in the page table, or the format of the processing component label does not comply with the preset label format (such as the label is "empty" or the label does not contain the processing component). logo, etc.). In other words, if the processing component label does not meet the preset conditions, it means that the acquisition of the processing component label fails.

According to the first aspect, or any implementation of the above first aspect, the designated processing component is an anonymous page processing component; accordingly, if the memory type of the first virtual address space is the anonymous page type, allocate The processing component label of is empty.

In the embodiment of the present application, for the scenario where the anonymous memory type virtual address space occupies a relatively large proportion, the anonymous page processing component is used as the designated processing component, so that there is no need to add a processing component label to the first virtual address space of the anonymous page type to streamline the missing information. Page exception handling process and reduce storage space costs, thereby further improving the efficiency of memory access

For example, the page fault exception handling label may not be added to the physical address space page table entry corresponding to the virtual address space of the anonymous memory type. For example, the physical address space page table entry may be empty, or may be "unlabeled" in Figure 15.

According to the first aspect, or any implementation of the first aspect above, instructing the first processing component to perform exception handling on the first page fault exception based on the processing component tag of the first virtual address space includes:

Determine the target processing component information based on the processing component label of the first virtual address space and the pre-established correspondence between the label and the processing component information;

Based on the target processing component information, instruct the first processing component to perform exception processing on the first page fault exception.

In the embodiment of the present application, the target processing component information is determined through the pre-established corresponding relationship between tags and processing component information, so that the first processing component can be timely and accurately instructed to perform exception processing through the target processing component information. Compared with directly marking the processing component information on the processing component label, through the corresponding relationship between the label and the processing component information, the convenience of maintaining the corresponding relationship between the first processing component and the processing component label can be improved. For example, when the target processing component information is updated, there is no need to reassign the processing component label, and the corresponding relationship can be updated.

According to the first aspect, or any implementation of the above first aspect, if a first page fault exception corresponding to the first virtual address space is detected, before obtaining the processing component label of the first virtual address space, the method further includes:

In response to the pre-assigned at least one processing component tag, generate a key-value pair based on the at least one processing component tag and the processing component information respectively corresponding to the at least one processing component tag;

Create a page fault exception handling table that records key-value pairs, and obtain the corresponding relationship between pre-established labels and processing component information.

In the embodiment of the present application, key-value pairs are generated through at least one processing component tag and processing component information corresponding to at least one processing component tag, so as to create a page fault exception handling table that records the key-value pairs. In this way, the corresponding relationship between the pre-established tags and the processing component information is in the form of key-value pairs, making the query faster and further improving efficiency.

Exemplarily, FIG. 13 is an exemplary structural diagram of a page fault exception handling table. As shown in Figure 13, the page fault exception handling table can be the table in Figure 13, the processing component label is label label1, and the corresponding processing component information is entry fault handler entry 1.

In a second aspect, embodiments of the present application provide a memory access device, which includes:

A request acquisition module configured to acquire a first access request, where the first access request is used to indicate access to the first virtual address space;

The label acquisition module is configured to obtain a processing component label of the first virtual address space if a first page fault exception corresponding to the first virtual address space is detected; wherein the processing component label of the first virtual address space is used to identify the corresponding the first processing component in the first virtual address space;

The exception handling module is configured to instruct the first processing component to perform exception handling on the first page fault exception based on the processing component label of the first virtual address space. The first processing component performs exception processing on the first page missing exception, which may include allocating a physical address space for the first virtual address space. That is, the exception caused by the first page missing exception has been resolved, and the requester of the first access request, for example, A memory access request component can normally access the first virtual address space.

According to the second aspect, the tag acquisition module is further configured as:

According to the first virtual address space, search the processing component label from the page table; wherein, the processing component label is included in the target page table entry of the page table of the first virtual address space (belonging to, or located in, do not write it as an action); The page table is established when the first virtual address space is pre-allocated; the target page table entry is a page table entry in the page table used to record the physical address space information corresponding to the first virtual address space.

According to the second aspect, or any implementation of the second aspect above, the processing result of the first processing component may include updating the page table; wherein updating the page table means that the first processing component allocates a physical address space to the first virtual address space. , and is obtained by updating the target page table entry based on the physical address space; thus, the first memory access request component can access the first virtual address space based on the updated page table.

According to the second aspect, or any implementation of the above second aspect, the processing component label is generated according to the memory type of the first virtual address space and the component identifier of the processing component corresponding to the memory type.

According to the second aspect, or any implementation of the second aspect above, the request acquisition module is further configured to obtain a second access request, and the second access request is used to indicate access to the second virtual address space;

The label acquisition module is also configured to obtain a processing component label of the second virtual address space if a second page fault exception corresponding to the second virtual address space is detected; wherein the processing component label of the second virtual address space is used to identify Corresponding to the second processing component of the second virtual address space; detecting whether the processing component label of the second virtual address space meets the preset condition;

The exception handling module is also configured to instruct the designated processing component to perform exception handling on the second page fault exception if it is not satisfied. Designating a processing component to handle the second page missing exception may include allocating a physical address space for the second virtual address space. That is, the exception caused by the second page missing exception has been resolved, and the requester of the second access request, such as the second The memory access request component can normally access the second virtual address space.

According to the second aspect, or any implementation of the second aspect above, the designated processing component is an anonymous page processing component; accordingly, if the memory type of the first virtual address space is the anonymous page type, allocate The processing component label of is empty.

According to the second aspect, or any implementation of the second aspect above, the exception handling module is further configured as:

Determine the target based on the processing component label of the first virtual address space and the pre-established correspondence between the label and the processing component information. Process component information;

According to the second aspect, or any implementation of the second aspect above, the device further includes:

The registration module is configured to respond to the pre-assigned at least one processing component tag, generate a key-value pair based on the at least one processing component tag and the processing component information respectively corresponding to the at least one processing component tag; create a record key-value pair The page missing exception handling table obtains the corresponding relationship between pre-established labels and processing component information.

The second aspect and any implementation manner of the second aspect respectively correspond to the first aspect and any implementation manner of the first aspect. The technical effects corresponding to the second aspect and any implementation manner of the second aspect may be referred to the technical effects corresponding to the above-mentioned first aspect and any implementation manner of the first aspect, which will not be described again here.

In a third aspect, embodiments of the present application provide an electronic device, including: a processor and a transceiver; a memory for storing one or more programs; when the one or more programs are processed by the one or more processors Execution causes the one or more processors to implement the method in the first aspect or any possible implementation manner of the first aspect.

In a fourth aspect, embodiments of the present application provide a computer-readable storage medium, including a computer program, which is characterized in that when the computer program is run on a computer system, the computer system is caused to execute the first aspect or the first aspect. method in any possible implementation of the aspect.

In a fifth aspect, embodiments of the present application provide a chip, including one or more interface circuits and one or more processors; the interface circuit is used to receive signals from a memory of an electronic device and send the data to the processor. The signal includes a computer instruction stored in a memory; when the processor executes the computer instruction, the electronic device is caused to perform any of the possible tasks of the second to third aspects or the second to third aspects. Methods in the implementation.

In a sixth aspect, embodiments of the present application provide a computer program, which includes instructions for executing the method in the first aspect or any possible implementation of the first aspect.

Description of drawings

Figure 1 is a schematic structural diagram of an exemplary microkernel architecture;

Figure 2 is a schematic diagram of multiple page fault exception handling services exemplarily shown;

Figure 3 is a schematic flow chart of an exemplary memory access method;

Figure 4 is a schematic diagram of a processing scenario illustrating an exemplary page missing exception processing method;

Figure 5 is a structural diagram of an exemplary page fault exception handling architecture;

Figure 6 is a structural diagram of an exemplary page fault exception handling architecture;

Figure 7 is an exemplary structural diagram of the electronic device 600 provided by the embodiment of the present application;

Figure 8 is an exemplary flow chart of adding an exception handling component label provided by the embodiment of the present application;

Figure 9 is an exemplary schematic diagram of a scenario for adding an exception handling component label provided by an embodiment of the present application;

Figure 10a is an exemplary structural diagram of a page table when mapping has been established;

Figure 10b is an exemplary structural diagram of the page table when mapping has been established;

Figure 10c is a structural diagram of a page table for recording tags provided by an embodiment of the present application;

Figure 10d is another structural diagram of a page table for recording tags provided by an embodiment of the present application;

Figure 11 is a structural diagram of an exemplary page fault exception handling architecture;

Figure 12 is an exemplary flow chart of the memory access method provided by the embodiment of the present application;

Figure 13 is an exemplary structural diagram of a page fault exception handling table;

Figure 14a is a structural diagram of an exemplary page fault exception handling architecture;

Figure 14b is a structural diagram of an exemplary page fault exception handling architecture;

Figure 15 is a schematic diagram of a processing scenario illustrating an exemplary page fault exception handling method;

Figure 16 is an exemplary schematic block diagram of a device 1600 provided by an embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of this application.

The term "and/or" in this article is just an association relationship that describes related objects, indicating that three relationships can exist. For example, A and/or B can mean: A exists alone, A and B exist simultaneously, and they exist alone. B these three situations.

The terms “first” and “second” in the description and claims of the embodiments of this application are used to distinguish different objects, rather than to describe a specific order of objects. For example, the first target object, the second target object, etc. are used to distinguish different target objects, rather than to describe a specific order of the target objects.

In the embodiments of this application, words such as "exemplary" or "for example" are used to represent examples, illustrations or explanations. Any embodiment or design described as "exemplary" or "such as" in the embodiments of the present application is not to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the words "exemplary" or "such as" is intended to present the concept in a concrete manner.

In the description of the embodiments of this application, unless otherwise specified, the meaning of “plurality” refers to two or more. For example, multiple processing units refer to two or more processing units; multiple systems refer to two or more systems.

Figure 1 is a schematic structural diagram of an exemplary microkernel architecture. As shown in Figure 1, the microkernel architecture includes: system service layer and kernel layer, which uses a delay processing mechanism for memory access. When the microkernel performs memory access, it triggers a page missing exception of the delay processing mechanism. The page missing exception means that the virtual address space requested to be accessed does not have a corresponding physical address space. The microkernel architecture's handling of page missing exceptions includes the following steps:

S101, the microkernel sends page fault information to the memory management service.

The memory management service refers to the memory management service running in the kernel state. For example, the page fault information may include: the virtual address space requested by the memory access that triggers the page fault exception, that is, the virtual memory, the access request identifier and other information based on which the memory management service allocates the physical address space. Among them, the virtual address space refers to the address space set separately by the operating system for each process to ensure the isolation of the process. Virtual address space can also be called virtual memory, which is a logical concept of memory.

Corresponding to the virtual address space is the physical address space, which can also be called physical memory. Physical address space refers to the actual memory resources. The operating system associates the virtual address space with the physical address space to achieve actual access to memory resources, thereby achieving more flexible access and management of actual memory through the logical concept of virtual address space.

S102. The memory management service forwards the page fault information to the page fault exception handling service.

This memory management service runs in kernel mode and can serve as a specific page fault exception handler. The memory management service can determine the page missing exception handler based on the page missing information, thereby forwarding the page missing information to the page missing exception handling service. In the microkernel architecture, different system services (such as memory management services, file management services, driver management services, etc.) are usually distributed in the form of components in independent service processes. Among them, access requests for different system services access different virtual address spaces.

Exemplarily, FIG. 2 is a schematic diagram illustrating multiple page fault exception handling services. As shown in Figure 2, the operating system can divide the virtual address space into unfixed divisions: anonymous memory, IO memory, file memory and IO memory, etc. Unfixed partitioning can result in IO memory corresponding to two different virtual address space ranges. The non-fixed division can be carried out according to the usage requirements of the virtual address space, and can be flexibly changed according to the usage requirements.

Continuing to refer to Figure 2, when a memory access requester accesses one of the above virtual address spaces, a page fault exception is triggered and page fault information is generated. Therefore, the microkernel can capture the page fault exception and the page fault information, and the memory management service can determine the exception handling service, that is, the exception handler, to handle the page fault exception in different address spaces based on the page fault information forwarded by the microkernel. For example, anonymous memory page fault exception processing services for anonymous memory (such as kernel mode or user mode memory management services), file memory page fault exception processing services for file memory (such as file management services), IO memory page fault exception processing services Processing services (such as driver management services). It can be seen that there is inter-process communication (IPC) for such memory access. For example, inter-process communication between memory management services and file management services. Memory access has certain requirements for efficiency and is a performance-sensitive path. IPC has a large negative impact on performance-sensitive paths, resulting in a decrease in memory access efficiency.

Exemplarily, FIG. 3 is a schematic flow chart of a memory access method. As shown in Figure 3, memory access applied to the microkernel architecture shown in Figure 1 can include the following steps:

S301, the memory management service allocates a virtual address space.

For example, the memory management service can allocate a virtual address space when receiving a memory allocation instruction sent by the microkernel. Among them, the memory allocation instruction is generated when the microkernel obtains (such as detects and receives) a memory access request from a memory access requester (such as a memory access request component) and sends it to the memory management service. The memory allocation instruction may include the identification of the access request, information about the target object requested to be accessed, etc.

S302, the microkernel detects a page fault exception in the virtual address space.

After the memory management allocates the virtual address space, the memory requester accesses the virtual address space. At this time, according to the delayed loading mechanism, the microkernel captures the page fault exception caused by the memory requester's access to the virtual address space, that is, it detects the page fault exception in the virtual address space.

S303, the microkernel sends page fault information to the memory management service.

When the microkernel detects a page missing exception in the virtual address space, it sends page missing information to the memory management service.

S304. The memory management service sends the page fault information to the page fault exception handling service.

S303 to S304 in the embodiment of FIG. 3 are the same steps as S101 to S102 in the embodiment of FIG. 1. For details, please refer to the description of the embodiment of FIG. 1 and will not be described again here.

S305: The page fault exception handling service allocates a physical address space based on the page fault information.

After the page fault exception handling service receives the page fault information sent by the memory management service, it can allocate the physical address space based on the page fault information. For example, the page fault exception handling service can select one physical page from multiple physical pages obtained by dividing the physical storage space (such as memory) according to the page fault information, and determine it as the allocated physical address space. Alternatively, the page missing exception handling service can copy the data on the physical storage space (such as a disk) to a certain physical page in the memory through the file management module and the driver module based on the page missing information, and then determine the physical page as the allocated The physical address space is. For specific physical address space allocation methods, please refer to relevant existing technologies and will not be described again here.

S306: The page fault exception handling service creates a page table that records the mapping relationship between the virtual address space and the physical address space based on the allocation result.

After the page fault exception handling service allocates the physical address space, it can create a page table that records the mapping relationship between the virtual address space and the physical address space based on the allocation result, that is, the allocated physical address space. The page table is a data structure, and the recorded mapping relationship can realize the association between the virtual address space and the physical address space.

S307: The page fault exception handling service stores the page table.

After the page fault exception handling service creates the page table, it can store the page table in a storage space that the microkernel can access, for example, in memory.

S308: The page fault exception handling service sends exception handling feedback to the microkernel.

In one case, after the page fault exception handling service stores the page table, it can send exception handling feedback to the microkernel to inform the microkernel that the page fault exception processing is completed. In another case, the page fault exception handling service does not need to inform the microkernel that the page fault exception processing is completed, and there is no need to send exception handling feedback to the microkernel. The page fault exception handling service completes the page fault exception processing, which may include: the page fault exception processing service allocates a physical address space to the virtual address space where the page fault exception occurs. In this way, the memory access requester can access the virtual address space according to the page table. For example, the memory access requester accesses the virtual address space according to the page table, which may include: the memory access requester determines the target physical address space corresponding to the virtual address space according to the mapping relationship recorded in the page table, and accesses the target physical address space. address space. It can be understood that the access method of the memory access requester to the target physical address space can be determined according to the target access request, which may specifically include: reading the target resource in the target physical address space, or writing the target resource into the target physical address space. . The target access request refers to the access request corresponding to the above-mentioned virtual address space, and the target resource can be determined based on the resource identifier and other information indicated by the target access request.

The above microkernel's detection of page missing exceptions, and the specific ways in which the memory access requester accesses the memory after the page missing exception handling service completes the page missing exception processing are all exemplary descriptions. For details, please refer to the relevant prior art. This application describes This is not a limitation.

FIG. 4 is a schematic diagram of a processing scenario illustrating an exemplary page fault exception processing method. As shown in Figure 4, the operating system performs a fixed division of the virtual address space, and the resulting anonymous memory, file memory and IO memory respectively correspond to unique virtual address space ranges. For example, see Figure 2. The IO memory under the unfixed division in Figure 2 can correspond to two different virtual address space ranges, while the fixed division in Figure 4 The lower IO memory corresponds to a unique virtual address space range. Different virtual address space ranges correspond to different page fault exception handling services. For example, the virtual address space range of anonymous memory corresponds to the anonymous memory page missing exception handling service, the virtual address space range of file memory corresponds to the file memory page missing exception handling service, and the virtual address space range of IO memory corresponds to the IO memory page missing exception handling service. When a page missing exception occurs, the microkernel can directly determine the page missing exception handling service based on the virtual address space range of the virtual address space corresponding to the page missing exception. In this way, the microkernel can interact directly with the page fault exception handler without going through the memory management service, reducing inter-process communication.

However, in the embodiment of Figure 4, the virtual address space is fixedly divided, resulting in the inability to flexibly divide it according to usage requirements. Such fixed restrictions can also easily lead to limited applicable scenarios. Exemplarily, the Portable Operating System Interface of UNIX (POSIX, which is the general name of a series of interrelated standards defined by IEEE for software to run on various UNIX operating systems) does not apply to anonymous memory. , the virtual address ranges of file memory and IO memory are limited, causing the embodiment in Figure 4 to be incompatible with POSIX.

The embodiment of this application provides a memory access method. In this method, when the microkernel detects a page fault exception in the virtual address space corresponding to the access request, it can directly determine the page fault exception processing service based on the exception handling component label of the virtual address space, thereby directly communicating with the page fault exception processing service Interaction to achieve memory access. In this way, the inter-process interaction between the specific exception handler and the page fault exception handler can be avoided, thereby improving the efficiency of memory access. Among them, the processing component tag added according to the memory type of the virtual address space can directly indicate the page fault exception processing component of the memory type. Compared with the fixed division of the virtual address space range according to the memory type, the flexibility of the virtual address space can be guaranteed. Use to avoid incompatibility problems in application scenarios caused by fixed division of virtual address space ranges.

For the convenience of description, the following embodiments of the present application will be described using a microkernel as an example. The memory access method in this application is also applicable to wireless radio frequency remote units (RRUs), smart TVs, laptop computers, and desktop computers. Electronic devices such as small computers, handheld computers (such as tablet computers, smart phones, etc.), smart wearable devices (such as smart bracelets, smart watches, smart rings, etc.).

The embodiments of the present application can be applied to the core of electronic equipment. Exemplarily, FIG. 5 is a structural diagram of an exemplary page fault exception handling architecture. As shown in Figure 5, the electronic device may include an operating system with a microkernel architecture, which specifically may include a system service layer and a kernel layer. In the embodiment of the present application, page fault exception processing is performed through the microkernel of the kernel layer and the page fault exception processing service of the system service layer to implement memory access.

It can be understood that the structures illustrated in the embodiments of the present application do not constitute specific limitations to the above-mentioned electronic devices. In other embodiments of the present application, the above-mentioned electronic device may include more or fewer components than shown in the figures, or some components may be combined, some components may be separated, or some components may be arranged differently. The components illustrated may be implemented in hardware, software, or a combination of software and hardware.

In an example, FIG. 6 is a structural diagram illustrating a page fault exception handling architecture. As shown in FIG. 6 , the operating system in the above-mentioned electronic device may include a microkernel architecture with multiple operating domains. The architecture shown in Figure 6 is similar to Figure 5, except that the number of operating domains is n, and n is greater than 1. For example, running domain D1, running domain D2,..., and running domain Dn. Each runtime domain is used to run system services belonging to different processes. For example, the page fault exception handling service may include multiple processes running in the running domain D1 to the running domain Dn. That is to say, the page missing exception handling service may run in each running domain, and different running domains are independent of each other. The microkernel performs the same processing and interaction on each operating domain. The operating systems of multiple operating domains provided in this embodiment are generally used in scenarios where resource isolation is required. For example, in a car OS (Operating System) scenario, the control subsystem and entertainment subsystem have isolation requirements. The car OS can have the architecture shown in Figure 6.

In another example, the above-mentioned electronic device may have another structure, which structure is also applicable to electronic devices such as smartphones. FIG. 7 is an exemplary structural diagram of an electronic device 600 provided by an embodiment of the present application. As shown in FIG. 7 , the electronic device 600 may be an electronic device belonging to the architecture shown in FIG. 5 or FIG. 6 .

It should be understood that the electronic device 600 shown in FIG. 7 is only an example, and the electronic device 600 may have more or fewer components than shown in the figure, may combine two or more components, or may Available in different component configurations. The various components shown in Figure 7 may be implemented in hardware, software, or a combination of hardware and software including one or more signal processing and/or application specific integrated circuits.

The electronic device 600 may include: a processor 610, an external memory interface 620, an internal memory 621, a universal serial bus (USB) interface 630, a charging management module 640, a power management module 641, a battery 642, an antenna 1, an antenna 2. Mobile communication module 650, wireless communication module 660, audio module 670, speaker 670A, receiver 670B, microphone 670C, headphone connector Port 670D, sensor module 680, button 690, motor 691, indicator 692, camera 693, display screen 694, and subscriber identification module (subscriber identification module, SIM) card interface 695, etc. The sensor module 680 may include a pressure sensor 680A, a gyro sensor 680B, an air pressure sensor 680C, a magnetic sensor 680D, an acceleration sensor 680E, a distance sensor 680F, a proximity light sensor 680G, a fingerprint sensor 680H, a temperature sensor 680J, a touch sensor 680K, and ambient light. Sensor 680L, bone conduction sensor 680M, etc.

The processor 610 may include one or more processing units. For example, the processor 610 may include an application processor (application processor, AP), a modem processor, a graphics processing unit (GPU), and an image signal processor. (image signal processor, ISP), controller, memory, video codec, digital signal processor (digital signal processor, DSP), baseband processor, and/or neural-network processing unit (NPU) wait. Among them, different processing units can be independent devices or integrated in one or more processors.

The controller may be the nerve center and command center of the electronic device 600 . The controller can generate operation control signals based on the instruction operation code and timing signals to complete the control of fetching and executing instructions.

The processor 610 may also be provided with a memory for storing instructions and data. In some embodiments, the memory in processor 610 is cache memory. This memory may hold instructions or data that have been recently used or recycled by processor 610 . If processor 610 needs to use the instructions or data again, it can be called directly from the memory. Repeated access is avoided and the waiting time of the processor 610 is reduced, thus improving the efficiency of the system.

In some embodiments, processor 610 may include one or more interfaces. Interfaces may include integrated circuit (inter-integrated circuit, I2C) interface, integrated circuit built-in audio (inter-integrated circuit sound, I2S) interface, pulse code modulation (pulse code modulation, PCM) interface, universal asynchronous receiver and transmitter (universal asynchronous receiver/transmitter (UART) interface, mobile industry processor interface (MIPI), general-purpose input/output (GPIO) interface, subscriber identity module (SIM) interface, and /or universal serial bus (USB) interface, etc.

The I2C interface is a bidirectional synchronous serial bus, including a serial data line (SDA) and a serial clock line (derail clock line, SCL). In some embodiments, processor 610 may include multiple sets of I2C buses. The processor 610 can separately couple the touch sensor 680K, charger, flash, camera 693, etc. through different I2C bus interfaces. For example, the processor 610 can be coupled to the touch sensor 580K through an I2C interface, so that the processor 610 and the touch sensor 680K communicate through the I2C bus interface to implement the touch function of the electronic device 600 .

The I2S interface can be used for audio communication. In some embodiments, processor 610 may include multiple sets of I2S buses. The processor 610 can be coupled with the audio module 670 through the I2S bus to implement communication between the processor 610 and the audio module 670. In some embodiments, the audio module 670 can transmit audio signals to the wireless communication module 660 through the I2S interface to implement the function of answering calls through a Bluetooth headset.

The PCM interface can also be used for audio communications to sample, quantize and encode analog signals. In some embodiments, the audio module 670 and the wireless communication module 660 may be coupled through a PCM bus interface. In some embodiments, the audio module 670 can also transmit audio signals to the wireless communication module 660 through the PCM interface to implement the function of answering calls through a Bluetooth headset. Both the I2S interface and the PCM interface can be used for audio communication.

The UART interface is a universal serial data bus used for asynchronous communication. The bus can be a bidirectional communication bus. It converts the data to be transmitted between serial communication and parallel communication. In some embodiments, a UART interface is typically used to connect the processor 610 and the wireless communication module 660 . For example, the processor 610 communicates with the Bluetooth module in the wireless communication module 660 through the UART interface to implement the Bluetooth function. In some embodiments, the audio module 670 can transmit audio signals to the wireless communication module 660 through the UART interface to implement the function of playing music through the Bluetooth headset.

The MIPI interface can be used to connect the processor 610 with peripheral devices such as the display screen 694 and the camera 693 . MIPI interfaces include camera serial interface (CSI), display serial interface (DSI), etc. In some embodiments, the processor 610 and the camera 693 communicate through the CSI interface to implement the shooting function of the electronic device 600 . The processor 610 and the display screen 694 communicate through the DSI interface to implement the display function of the electronic device 600 .

The GPIO interface can be configured through software. The GPIO interface can be configured as a control signal or as a data signal. In some embodiments, the GPIO interface can be used to connect the processor 610 with the camera 693, display screen 694, wireless communication module 660, audio module 670, sensor module 680, etc. The GPIO interface can also be configured as an I2C interface, I2S interface, UART interface, MIPI Interface etc.

The USB interface 630 is an interface that complies with the USB standard specifications. Specifically, it can be a Mini USB interface, a Micro USB interface, a USB Type C interface, etc. The USB interface 530 can be used to connect a charger to charge the electronic device 600, and can also be used to transmit data between the electronic device 600 and peripheral devices. It can also be used to connect headphones to play audio through them. This interface can also be used to connect other electronic devices, such as AR devices, etc.

It should be understood that the interface connection relationship between the modules illustrated in the embodiment of the present application is only a schematic illustration and does not constitute a structural limitation of the electronic device 600 . In other embodiments of the present application, the electronic device 600 may also adopt different interface connection methods in the above embodiments, or a combination of multiple interface connection methods.

The charge management module 640 is used to receive charging input from the charger. Among them, the charger can be a wireless charger or a wired charger. In some wired charging embodiments, the charging management module 640 may receive charging input from the wired charger through the USB interface 630 . In some wireless charging embodiments, the charging management module 640 may receive wireless charging input through the wireless charging coil of the electronic device 600 . While charging the battery 642, the charging management module 640 can also provide power to the electronic device through the power management module 641.

The power management module 641 is used to connect the battery 642, the charging management module 640 and the processor 610. The power management module 641 receives input from the battery 642 and/or the charging management module 640, and supplies power to the processor 610, internal memory 621, external memory, display screen 694, camera 693, wireless communication module 660, etc. The power management module 641 can also be used to detect battery capacity, battery cycle times, battery health status (leakage, impedance) and other parameters. In some other embodiments, the power management module 641 may also be provided in the processor 610. In other embodiments, the power management module 641 and the charging management module 640 can also be provided in the same device.

The wireless communication function of the electronic device 600 can be implemented through the antenna 1, the antenna 2, the mobile communication module 650, the wireless communication module 660, the modem processor and the baseband processor.

Antenna 1 and Antenna 2 are used to transmit and receive electromagnetic wave signals. Each antenna in electronic device 600 may be used to cover a single or multiple communication frequency bands. Different antennas can also be reused to improve antenna utilization. For example: Antenna 1 can be reused as a diversity antenna for a wireless LAN. In other embodiments, antennas may be used in conjunction with tuning switches.

The mobile communication module 650 can provide wireless communication solutions including 2G/3G/4G/5G applied to the electronic device 600 . The mobile communication module 650 may include at least one filter, switch, power amplifier, low noise amplifier (LNA), etc. The mobile communication module 650 can receive electromagnetic waves through the antenna 1, perform filtering, amplification and other processing on the received electromagnetic waves, and transmit them to the modem processor for demodulation. The mobile communication module 650 can also amplify the signal modulated by the modem processor and convert it into electromagnetic waves through the antenna 1 for radiation. In some embodiments, at least part of the functional modules of the mobile communication module 650 may be disposed in the processor 610 . In some embodiments, at least part of the functional modules of the mobile communication module 650 and at least part of the modules of the processor 610 may be provided in the same device.

A modem processor may include a modulator and a demodulator. Among them, the modulator is used to modulate the low-frequency baseband signal to be sent into a medium-high frequency signal. The demodulator is used to demodulate the received electromagnetic wave signal into a low-frequency baseband signal. The demodulator then transmits the demodulated low-frequency baseband signal to the baseband processor for processing. After the low-frequency baseband signal is processed by the baseband processor, it is passed to the application processor. The application processor outputs sound signals through audio devices (not limited to speaker 670A, receiver 670B, etc.), or displays images or videos through display screen 694. In some embodiments, the modem processor may be a stand-alone device. In other embodiments, the modem processor may be independent of the processor 610 and may be provided in the same device as the mobile communication module 650 or other functional modules.

The wireless communication module 660 can provide applications on the electronic device 600 including wireless local area networks (WLAN) (such as wireless fidelity (Wi-Fi) network), Bluetooth (bluetooth, BT), and global navigation satellites. System (global navigation satellite system, GNSS), frequency modulation (frequency modulation, FM), near field communication technology (near field communication, NFC), infrared technology (infrared, IR) and other wireless communication solutions. The wireless communication module 660 may be one or more devices integrating at least one communication processing module. The wireless communication module 660 receives electromagnetic waves through the antenna 2, frequency modulates and filters the electromagnetic wave signals, and sends the processed signals to the processor 610. The wireless communication module 660 can also receive the signal to be sent from the processor 610, frequency modulate it, amplify it, and convert it into electromagnetic waves through the antenna 2 for radiation.

In some embodiments, the antenna 1 of the electronic device 600 is coupled to the mobile communication module 650, and the antenna 2 is coupled to the wireless communication module 660, so that the electronic device 600 can communicate with the network and other devices through wireless communication technology. The wireless communication technology may include global system for mobile communications (GSM), general packet radio service (GPRS), code division multiple access (CDMA), broadband code division multiple access (wideband code division multiple access, WCDMA), time-division code division multiple access (TD-SCDMA), long term evolution (LTE), BT, GNSS, WLAN, NFC, FM, and /or IR technology, etc. The GNSS may include global positioning system (GPS), global navigation satellite system (GLONASS), Beidou navigation satellite system (BDS), quasi-zenith satellite system (quasi -zenith satellite system (QZSS) and/or satellite based augmentation systems (SBAS).

The electronic device 600 implements display functions through a GPU, a display screen 694, an application processor, and the like. The GPU is an image processing microprocessor and is connected to the display screen 694 and the application processor. GPUs are used to perform mathematical and geometric calculations for graphics rendering. Processor 610 may include one or more GPUs that execute program instructions to generate or alter display information.

The display screen 694 is used to display images, videos, etc. Display 694 includes a display panel. The display panel can use a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active matrix organic light emitting diode or an active matrix organic light emitting diode (active-matrix organic light emitting diode). emitting diode (AMOLED), flexible light-emitting diode (FLED), Miniled, MicroLed, Micro-oLed, quantum dot light emitting diode (QLED), etc. In some embodiments, the electronic device 600 may include 1 or N display screens 694, where N is a positive integer greater than 1.

The electronic device 600 can implement the shooting function through an ISP, a camera 693, a video codec, a GPU, a display screen 694, and an application processor.

The ISP is used to process the data fed back by the camera 693. For example, when taking a photo, the shutter is opened, the light is transmitted to the camera sensor through the lens, the optical signal is converted into an electrical signal, and the camera sensor passes the electrical signal to the ISP for processing, and converts it into an image visible to the naked eye. ISP can also perform algorithm optimization on image noise, brightness, and skin color. ISP can also optimize the exposure, color temperature and other parameters of the shooting scene. In some embodiments, the ISP may be provided in camera 693.

Camera 693 is used to capture still images or video. The object passes through the lens to produce an optical image that is projected onto the photosensitive element. The photosensitive element can be a charge coupled device (CCD) or a complementary metal-oxide-semiconductor (CMOS) phototransistor. The photosensitive element converts the optical signal into an electrical signal, and then passes the electrical signal to the ISP to convert it into a digital image signal. ISP outputs digital image signals to DSP for processing. DSP converts digital image signals into standard RGB, YUV and other format image signals. In some embodiments, the electronic device 600 may include 1 or N cameras 693, where N is a positive integer greater than 1.

Digital signal processors are used to process digital signals. In addition to digital image signals, they can also process other digital signals. For example, when the electronic device 600 selects a frequency point, the digital signal processor is used to perform Fourier transform on the frequency point energy.

Video codecs are used to compress or decompress digital video. Electronic device 600 may support one or more video codecs. In this way, the electronic device 600 can play or record videos in multiple encoding formats, such as: moving picture experts group (MPEG) 1, MPEG2, MPEG3, MPEG4, etc.

NPU is a neural network (NN) computing processor. By drawing on the structure of biological neural networks, such as the transmission mode between neurons in the human brain, it can quickly process input information and can continuously learn by itself. Intelligent cognitive applications of the electronic device 600 can be implemented through the NPU, such as image recognition, face recognition, speech recognition, text understanding, etc.

The external memory interface 620 can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the electronic device 600. The external memory card communicates with the processor 610 through the external memory interface 620 to implement the data storage function. Such as saving music, videos, etc. files in external memory card.

Internal memory 621 may be used to store computer executable program code, which includes instructions. The processor 610 executes instructions stored in the internal memory 621 to execute various functional applications and data processing of the electronic device 600 . The internal memory 621 may include a program storage area and a data storage area. Among them, the stored program area can store an operating system, at least one application program required for a function (such as a sound playback function, an image playback function, etc.). The storage data area may store data created during use of the electronic device 600 (such as audio data, phone book, etc.). In addition, the internal memory 621 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, universal flash storage (UFS), etc.

The electronic device 600 can implement audio functions through the audio module 670, the speaker 670A, the receiver 670B, the microphone 670C, the headphone interface 670D, and the application processor. Such as music playback, recording, etc.

The audio module 670 is used to convert digital audio information into analog audio signal output, and is also used to convert analog audio input into digital audio signals. Audio module 670 may also be used to encode and decode audio signals. In some embodiments, the audio module 670 may be disposed in the processor 610, or some functional modules of the audio module 670 may be disposed in the processor 610.

The following is a detailed introduction to the memory access method provided by the embodiment of the present application in conjunction with Figure 5 and Figures 8 to 11.

Exemplarily, FIG. 8 is a schematic flowchart of adding an exception handling component label according to an embodiment of the present application. Through this process, an exception handling component label is added to the virtual address space in advance to respond to page missing exceptions in subsequent memory accesses and implement memory access. As shown in Figure 8, this process can be applied to memory management services of electronic devices, which may include but is not limited to the following steps:

S801, allocate virtual address space.

The above-mentioned S801 is a similar step to the S301 in the embodiment of FIG. 3 of the present application, and the same parts will not be described again. For details, please refer to the description of the above-mentioned S301. The different parts will be described in detail below in conjunction with Figure 9. Figure 9 is an exemplary schematic diagram of a scenario of adding an exception handling component label provided by an embodiment of the present application. As shown in Figure 9, the memory management service in this embodiment may include but is not limited to a virtual memory allocation module (such as Virtual memory allocator), a label generation module (such as fault handler label gen), and a label addition module (such as PTE marker). The memory management service calls the virtual memory allocation module to execute S901 and apply for a virtual address space to achieve the effect of allocating the virtual address space. For example, the overall virtual address space includes virtual address space 0 and virtual address space 1. The memory management service calls the virtual memory allocation module to apply for virtual address space 1 from the operating system, thereby allocating the virtual address space to the target access request. Among them, the target access request is the access request that triggers the virtual address space allocation, that is, the access request for the memory access performed by this application.

Still referring to Figure 9, in an optional implementation, after applying for the virtual address space, the memory management service calls the label generation module to perform S902 to generate a label, and then calls the label adding module to perform S903 to add the label. For example, the label generated by the memory management service calling the label generation module is label 2. This label 2 can be added to the data structure used to record the exception handler label (such as the label "PTE"). The data structure can be, for example, a table. The exception handler label recorded in this table is label 1, for example. It can be understood that the execution steps of S902 and S901 are not limited, and S902 can also be executed before S901, or S902 can be executed at the same time as S901. S902 and S901 can be executed before S903.

For label generation, in an optional implementation, the way in which the label generation module generates the exception handler label may include: the label generation module obtains the component identification of the page missing exception handling component, which is the process identification (such as service id), based on This identifier determines the exception handler label to generate a page missing exception handler label with a uniform format for easy management. When the electronic device is a single running domain architecture, the label generation module may determine the component identifier as the exception handler label. For example, the exception handler label may be the label "file fault handler label". When the electronic device has an architecture of multiple operating domains, such as the architecture shown in Figure 6 of this application, the label generation module can also obtain the domain identification (such as domain id) of the operating domain targeted by the target access request, and combine the domain identification and The above component identifiers are fused, for example, spliced, to obtain the exception handler label. For example, the exception handler label can be the label "Running domain D1 file fault handler label (D1 file fault handler label)", or the label "Running domain D1 file fault handler label" Exception handling component label (domain1 file fault handler label)".

In an optional implementation, the above page fault exception handler tag can be used not only to determine the page fault exception handling service, but also to perform permission verification. The permission refers to establishing a mapping between the virtual address space and the physical address space. relationship permissions. For example, the IO memory page fault exception handling service (IO manager) initiates the establishment of an unauthorized mapping relationship: when establishing a mapping relationship between a virtual address space whose memory type is file memory and the corresponding physical address space, the memory access requester can use the page table to The page fault exception handler label corresponding to the virtual address space in the virtual address space rejects the establishment request of the IO memory page fault exception handling service. In this way, the stability of the operating system can be improved.

For label addition, the memory management service calls the label addition module to perform steps including but not limited to the following:

S802: Based on the allocation result, create a page table that records the mapping relationship between the virtual address space and the physical address space.

After the memory management service calls the label generation module to generate the exception handler label, it calls the label adding module to create a page table that records the mapping relationship between the virtual address space and the physical address space based on the allocation result. The page table is used in the operating system shown in Figure 1 to record the mapping relationship between the virtual address space and the physical address space. When the mapping relationship is not established, for example, when the physical address space is not allocated, there is a vacancy in the page table. Unused page table entries. For example, a row of page table entries includes page table entries that record virtual address space information (such as indexes), and page table entries that record physical address space information (such as indexes). Unused page table entries are: unallocated physical address space In the row of the virtual address space, the page table entry records the physical address space information (such as index). Based on this, after the memory management service of this application allocates the virtual address space, based on the allocation result, it creates a record of the virtual address space and The page table of the physical address space mapping relationship to write page fault exception handler tags to unused page table entries. In this way, this application can directly use the existing data structure of the microkernel: the page table to store the page missing exception handler label, thereby eliminating the need to introduce new complex data structures into the microkernel. While improving memory access efficiency, it can maintain Microkernel is simple enough.

Exemplarily, FIG. 10a is an exemplary structural diagram of a page table when mapping has been established. As shown in Figure 10a, each row of the Level0 Page Table can include two page table entries: the base address L0 Addr Base and the mapping entry Entry0. The base address L0 Addr Base is used to record the information of the virtual address space VA, and the mapping entry Entry0 is used to record the information of the physical address space PA. The microkernel can obtain the specified bits in the virtual address space VA, such as VA[47:39], as an index, and search for the base address L0 Addr Base in the first-level page table according to the index, thereby obtaining the corresponding physical address space PA[47: 39]. FIG. 10b is an exemplary structural diagram of the page table when mapping has been established. As shown in Figure 10b, in a scenario where multi-level page tables, such as three-level page tables, are used to improve memory access efficiency, the page tables can include: one-level page table Level0 Page Table, two-level page table Level1 Page Table, three-level page table Table Level2 Page Table and four-level page table Level3 Page Table. Each level page table is similar to the first-level page table in Figure 10a. The difference is that the page table entries from Level0 Page Table to Level2 Page Table: mapping entry Entry0 to mapping entry Entry2, the records may be used for the next level page table. The first address for the search, rather than the physical address space information of the final search result. For example, a microkernel can perform the following steps to find the final physical address space:

The microkernel obtains the specified bit in the virtual address space VA, such as VA[47:39], as an index, and searches the base address L0 Addr Base in the first-level page table according to the index, and obtains the corresponding first address of the second-level page table Level1 Page Table. . The microkernel obtains VA[38:30] from the first address of the second-level page table Level1 Page Table as an index, searches the base address L1 Addr Base in the second-level page table according to this index, and obtains the corresponding first address of the third-level page table Level2 Page Table. address. The microkernel obtains VA[29:21] from the first address of the third-level page table Level2 Page Table as an index, searches the base address L2 Addr Base in the third-level page table according to this index, and obtains the corresponding first address of the fourth-level page table Level3 Page Table. address. The microkernel obtains VA[20:12] from the first address of the fourth-level page table Level3 Page Table as an index, searches the base address L3 Addr Base in the fourth-level page table according to this index, and obtains the physical address space PA[47:12].

The page table established through S802 in the embodiment of the present application is similar to the page table shown in Figure 10a and Figure 10b. The difference is that the page table entry recording the mapping entry in the page table established through S802 is a free page table entry, that is, it is not used. page table entry. The same parts will not be described again here. For details, please refer to the description of Figure 10a and Figure 10b.

It can be understood from Figure 3 that the electronic device shown in Figure 1 creates a page table when handling a page missing exception, but this application creates a page table before handling a page missing exception, for example when virtual memory space is allocated. In this way, this application can use the page table to record the exception handler label, thereby using the exception handler label to handle page missing exceptions.

S803: Add the handler label of the corresponding virtual address space to the page table entry of the physical address space information of the page table.

After the memory management service calls the label adding module to create the above page table with unused page table entries, it continues to call the label adding module to add the processor label of the corresponding virtual address space in the page table entry of the physical address space information of the page table. Among them, the page table entries of the physical address space information of the page table are unused page table entries in the page table, for example, the unused page table entries in the last level page table in the multi-level page table in Figure 10b: mapping entry Entry3. For example, FIG. 10c is a structural diagram of a page table for recording tags provided by an embodiment of the present application. As shown in Figure 10c, the memory management module can call the label adding module to add the exception handler label in the mapping entry Entry0 of the first-level page table Level0. For example, the memory management module obtains VA[47:39] of the allocated virtual address space VA as an index, and adds the exception handler label Lablem to the first-level page table according to the index. Figure 10d is another structural diagram of a page table for recording tags according to an embodiment of the present application. As shown in Figure 10d, the memory management module can call the label adding module to add the exception handler label in the mapping entry Entry3 of the multi-level page table Level3. For example, the memory management module obtains VA[47:39] of the allocated virtual address space VA as an index. According to this index, it finds the mapping entry Entry3 in the four-level page table Level3 Page Table step by step, thereby changing the exception handler label Lablem to Level 3 Page Table. The search process for page table entries in the multi-level page table can be referred to the description in Figure 10b above, and will not be described again here.

The memory management service adds a page-fault exception handler label to the page table and stores the page table, thereby achieving the purpose of adding a page-fault exception handler label to the virtual address space. Page fault exception handler labels can be divided into multiple types according to the type of virtual address space. Each The number of page fault exception handler tags can be multiple. For example, when the memory type is file memory and there are multiple virtual address spaces, each virtual address space corresponds to one file fault handler label. That is to say, the number of file fault handler labels is multiple.

Exemplarily, FIG. 11 is a structural diagram of an exemplary page fault exception handling architecture. As shown in Figure 11, the page fault exception processing architecture, which is the architecture of the electronic device, includes: a label generation module and a label adding module in the user-mode memory management service of the system service layer. These two modules are the same as those in the embodiment of Figure 9. The same modules are the same modules to implement the page missing exception handler label adding process shown in Figure 8 of this application and the embodiment of the label generation scenario shown in Figure 9 . Correspondingly, S1101 includes: the user-mode memory management service calls the label adding module to add the exception handler label generated by the label generation module to the data structure recording the exception handler label. The system service layer may also include thread management services, IO management services, file management services and other services for handling page missing exceptions.

Based on the exception handling component tag added in the embodiment of Figure 8, Figure 12 is an exemplary flow chart of the memory access method provided by the embodiment of the present application. As shown in Figure 12, the memory access method may include but is not limited to the following steps:

S1201, the microkernel detects a page fault exception in the virtual address space.

The above-mentioned S1201 is the same step as the S302 in the embodiment of FIG. 3 of this application, and will not be described again. For details, please refer to the description of the above-mentioned S302.

S1202, the microkernel determines the page fault exception handling service based on the handler label of the virtual address space.

After detecting a page missing exception in the virtual address space, the microkernel can determine the page missing exception handling service based on the handler label of the virtual address space. Among them, the handler label of the virtual address space includes: an exception handling component label added to the virtual address space in advance according to the memory type of the virtual address space. For example, the exception handling component tag is added in advance through the method provided in the embodiment of FIG. 8 . Each exception handling component label is used to indicate the page fault exception handling service corresponding to the virtual address space of a memory type, that is, the exception handling component. For example, for a virtual address space whose memory type is a file type, that is to say, the memory corresponding to the virtual address space is the file memory shown in Figure 2, then the exception handling component label of the virtual address space is file memory page fault exception handling service. Label (such as file fault handler label).

On this basis, the microkernel determines the page fault exception handling service based on the handler label of the virtual address space. Specifically, the microkernel searches for the page fault exception handler of the virtual address space where the page fault exception exists from the pre-stored page table. Tag, determine the processing service information corresponding to the found tag from the pre-established correspondence relationship between tags and processing service information, and determine the page missing exception processing service based on the processing service information. The specific way in which the microkernel searches for the page fault exception handler label is similar to the process of searching the physical address space in the embodiments of Figure 10a and Figure 10b. Both of them traverse the page table. The difference is that the search results are different. The same parts will not be described again here. For details, please refer to the description of the embodiment in Figure 10a and Figure 10b.

In an optional implementation, the kernel layer of the electronic device shown in Figure 11 may include an exception handling registration module to establish the page missing exception handler label and page missing exception handler information generated by the user mode memory management service. (such as interaction portals, or calling interfaces, etc.). Among them, the kernel-state memory management service belongs to the microkernel, which can also include a Trusted Computing Base (TCB) module and an interactive communication module (such as an IPC module). It can be understood that the TCB module and the IPC module are only examples of modules in the microkernel. For specific functions and calling methods, please refer to the existing technologies of trusted computing and inter-process communication in the operating system, and will not be described again here.

Continuing to refer to Figure 11, the user-mode memory management service can call the label adding module to perform step S1102 and send a registration request to the exception handling registration module to establish the correspondence between the page missing exception handler label and the page missing exception handling entry (fault handler entry). Relationship, that is, registering the page missing exception handling entry. Exemplarily, FIG. 13 is an exemplary structural diagram of a page fault exception handling table. As shown in Figure 13, the corresponding relationship between the page fault exception handler label and the page fault exception processing entry can be a page fault exception handling table (fault handler table). The structure of the page fault exception handling table can be key-value pairs. In an optional implementation, the page-fault exception handling table may include a default page-fault exception handling entry (not shown in the figure) and several page-fault exception handling entries corresponding to specific exception handler tags.

For example, continue to refer to Figure 13. In an optional implementation, the establishment of the page-fault exception handling table complies with the following two constraints: The first constraint is: the content in the page-fault exception handling table entry cannot be empty, that is, the entry default label as the key There must be content in the table entry default fault handler entry as the value. The second constraint is: the contents of different table entries as keys, that is, the default labels of exception handlers, are different, and each default label corresponds to an exception handling entry, default fault handler entry. For example, label label1 corresponds to the entry fault handler entry1, label label2 corresponds to the entry fault handler entry2,..., label labelm corresponds to the entry fault handler entrym.

In an optional implementation, based on the page fault exception handling table, the exception handling registration module can abstract four primitives: fault_handler_table_init, fault_handler_table_register, fault_handler_table_dispatcher, and fault_handler_table_unregister. Among them, a primitive refers to a program segment composed of several instructions, which is used to implement a specific function and cannot be interrupted during execution. The following introduces the meaning of each primitive abstracted by the exception handling registration module:

fault_handler_table_init: Initialize the page fault exception handling table fault handler table, and specify the table item default label and table item default fault handler entry.

fault_handler_table_register: Receive the page fault exception handler label label and fault handler entry key-value pair sent by the label adding module, find the free entry in the page fault exception handling table, that is, the unused entry, and fill in the key-value pair.

fault_handler_table_dispatcher: Find the corresponding table entry based on the input label and return the entry fault handler entry in the table entry. It can be understood that this primitive is used to determine the page fault exception handler.

fault_handler_table_unregister: Find the corresponding table entry based on the input label and remove the corresponding table entry.

After determining the page-fault exception handler label, the kernel-mode memory management service in the microkernel calls the exception handling registration module to search the above-mentioned page-fault exception handling table and obtains the entry fault handler entry of the page-fault exception handler.

In an optional implementation, a default page-fault exception handler can be set, so that when determining that the page-fault exception handler fails, the default page-fault exception handler is used as the determined page-fault exception handler. Determining that the page fault exception handler failed may include but is not limited to: traversing the page table and failing to find a valid page fault exception handler label that meets the preset conditions. For example, the access request is a write operation to the virtual address space, but the lack of write permission will trigger a page missing exception. The page missing exception can be filled in by the page missing exception processing service or feedback the page missing such as no write permission. Exception handling. At this point, the physical address space has been allocated, and the mapping between the physical address space and the virtual address space can be established. The page fault exception handler label corresponding to the virtual address space will be overwritten by the physical address space, that is, it will be overwritten as The mapping relationship between the physical address space and the virtual address space instead of the valid page fault exception handler label, then the microkernel can send the page fault exception information to the default page fault exception handler, which will handle it This type of page fault exception occurs. The default page fault exception handler may be, for example, an anonymous memory page fault processing service. In this way, it can be applied to the scenario where there is no valid page fault exception handler label, which expands the scope of application of the present application.

Figure 14a is a structural diagram illustrating an exemplary page fault exception handling architecture. As shown in Figure 14a, based on the architecture shown in Figure 11, the electronic device can also include a hardware layer. The hardware layer can specifically include components such as CPU, memory, network card, disk, etc. Figure 14b is a structural diagram illustrating an exemplary page fault exception handling architecture. As shown in Figure 14b, for an electronic device with multiple operating domains, each operating domain may include the modules shown in Figure 12. The functions of each module can be seen in the description of Figure 11, and will not be described again here. For example, running domain D1 includes thread management service, IO management service, file management service and user-mode memory management service. The user-mode memory management service has a new label generation module and a label addition module. Running domain D2 includes thread management service, IO management service, file management service and user-mode memory management service. The user-mode memory management service has a new label generation module and label addition module. In an example, the architecture shown in Figure 14b may also include a hardware layer. For details, please refer to the hardware layer shown in Figure 14a.

It can be understood that the architectures described in Figure 11, Figure 14a and Figure 14b are all exemplary descriptions of the architecture of the electronic device that implements the embodiments of Figures 8 and 9. The electronic device may include more or Fewer parts, or combining some parts, or splitting some parts, or different parts arrangement. The components illustrated may be implemented in hardware, software, or a combination of software and hardware.

In this embodiment, the exception handling component label can be added according to the memory type of the virtual address space. Compared with the fixed division of the virtual address space range according to the memory type of the virtual address space, the flexible use of the virtual address space can be ensured and the fixed division can be avoided. Incompatibility issues in applicable scenarios.

S1203. The microkernel sends page fault information to the determined page fault exception handling service.

After the microkernel determines the exception handler label, it can send page fault information to the determined page fault exception handling service. For example, as shown in Figure 11, an exception handling calling module can also be added to the kernel-mode memory management service in the electronic device. Based on this, the kernel-mode memory management service in the microkernel can call the exception handling calling module to execute S1103, find the exception handling entry from the exception handling registration module, and the exception handling calling module executes S1204, and send the page fault information to the found exception handling entry. The indicated page fault exception handling service (such as file management service). As shown in Figure 14a, based on the architecture shown in Figure 11, the electronic device can also include a hardware layer. The hardware layer can specifically include components such as CPU, memory, network card, disk, etc. Figure 14b is a structural diagram illustrating an exemplary page fault exception handling architecture. As shown in Figure 14b, for an electronic device with multiple operating domains, each operating domain may include Figure 11 For the modules shown, the functions of each module can be found in the description in Figure 11 and will not be described again here.

In order to facilitate understanding of the interactions between different services involved in the page fault exception processing flow provided by the embodiment of this application, please refer to the following steps in Figure 5:

S501, microkernel search tag.

S502: The microkernel sends the page fault information to the page fault exception handling service corresponding to the tag.

The above-mentioned S501 to S502 are the same steps as the S1202 to S1203 in FIG. 12 and will not be described again here. For details, please refer to the description of S1202 to S1203 in the above-mentioned embodiment of FIG. 12 . Combined with the services involved in S501 to S502 in Figure 5, it can be seen that the processing of page missing exceptions in the memory access of this application avoids the inter-process communication between the memory management service and the page missing exception handling service in the system service layer, and the interaction between different services occurs. Between the kernel layer and the system service layer, there is no inter-process communication in the system service layer to handle page fault exceptions.

S1204, the page fault exception handling service allocates the physical address space based on the page fault information.

S1204 is the same step as S305 in the embodiment of FIG. 3 and will not be described again here. For details, please refer to the description of S305 in the embodiment of FIG. 3 .

S1205. The page fault exception handling service updates the page table entry of the physical address space information based on the mapping relationship between the virtual address space and the physical address space.

S1205 is a similar step to S307 in the embodiment of FIG. 3, and the same parts will not be described again here. For details, please refer to the description of S307 in the embodiment of FIG. 3. The difference is that when the page missing exception handling service executes S1205, there is a pre-stored page table for recording the page missing exception handler label that can be used directly. The page fault exception handling service can update the page table entries of the physical address space information based on the mapping relationship between the virtual address space and the physical address space, that is, the allocated physical address space will be allocated according to the mapping between the physical address space and the virtual address space. relationship, updated to the pre-stored page table. For example, the pre-stored page table can be the page table shown in Figure 10d, and the allocated physical address space is the physical address space PA[47:12]. The page fault exception handling service can be based on the mapping between the physical address space and the virtual address space VA. relationship, that is, you can find the index relationship of the exception handler label Lablem according to Figure 10d, update the exception handler label Lablem in the mapping entry Entry3 to the physical address space PA[47:12], and obtain the updated page table as shown in Figure 10b page table shown. That is to say, the page table before updating records the mapping relationship between the virtual address space and the exception handler tag, and the updated page table records the mapping relationship between the virtual address space and the allocated physical address space.

S1206, the page fault exception handling service sends exception handling feedback to the microkernel.

S1206 is the same step as S308 in the embodiment of FIG. 3 and will not be described again here. For details, please refer to the description of S308 in the embodiment of FIG. 3 .

In this way, the memory access requester can access the virtual address space based on the updated page table. The specific access of the memory access requester to the virtual address space is similar to the access of the memory access requester to the virtual address space in the embodiment of Figure 3. The same parts will not be described again here. For details, see the relevant description of the embodiment of Figure 3. The difference is that in the embodiment of FIG. 12, the memory access requester uses the updated page table instead of the page table created by the page fault exception handling service after allocating the physical address space.

In the embodiment of the present application, when the microkernel detects a page missing exception in the virtual address space corresponding to the access request, it can directly determine the page missing exception processing service based on the exception handling component label of the virtual address space, thereby directly communicating with the page missing exception. Handle service interactions and implement memory access. In this way, the inter-process interaction between the specific exception handler and the page fault exception handler can be avoided, thereby improving the efficiency of memory access. Among them, the processing component tag added according to the memory type of the virtual address space can directly indicate the page fault exception processing component of the memory type. Compared with the fixed division of the virtual address space range according to the memory type, the flexibility of the virtual address space can be guaranteed. Use to avoid incompatibility problems in application scenarios caused by fixed division of virtual address space ranges.

In one example, during the startup phase of the electronic device, the kernel-mode memory management service can call the fault_handler_table_init interface provided by the exception handling registration module to initialize the pre-stored page fault exception handling table. In an optional implementation, when S902 in FIG. 9 is executed before S901 or simultaneously with S901, S902 can be used as a step in the startup phase to generate a page missing exception handler label. In an optional implementation, S1102 can also be used as a step in the startup phase to realize the registration of the page missing exception handler entry.

In one example, the virtual memory allocation phase, that is, the phase in which the user-mode memory management service of the electronic device allocates the virtual address space, may include: the user-mode memory management service allocates the virtual address space, creates a page table, and based on the virtual address The memory type of the space determines the corresponding page fault exception tag, and the page fault exception tag is added to the page table type.

In one example, the page fault exception processing stage may include: the microkernel obtains the page fault exception label corresponding to the virtual address space where the page fault exception occurs by traversing the page table, and the kernel mode memory management service in the microkernel obtains the page fault exception label by calling the exception. The fault_handler_table_dispatcher interface provided by the processing registration module module finds the page fault exception processing entry corresponding to the page fault exception tag. The kernel state memory management service in the microkernel calls the exception processing calling module and sends the page fault exception information to the corresponding page fault exception processing entry according to the page fault exception processing entry. system server business processing.

After the page fault exception processing stage, the memory access stage can be entered. For details, please refer to the description of the memory access requester's access to the virtual address space in the above embodiment.

For ease of understanding, the following uses different page-fault exception handling components as examples to describe the processing of page-fault exceptions in the memory access method provided by embodiments of the present application.

Exemplarily, FIG. 15 is a schematic diagram of a processing scenario of a method for handling a page missing exception. As shown in Figure 15, the memory type of the allocated virtual address space may be anonymous memory, IO memory or file memory. The following describes the handling process of page fault exceptions triggered when accessing virtual address spaces of different memory types:

Handle page fault exceptions corresponding to virtual address spaces of IO memory or file memory types:

Take the page fault exception triggered by accessing the virtual address space of the IO memory type as an example. At the kernel layer, after a page missing exception occurs, the microkernel determines the page table entry corresponding to the virtual address space by traversing the page table (page walk), and obtains the page missing exception handler label, such as the IO type label "IO exception handler label ( io fault handler label)". The kernel-mode memory management service in the microkernel calls the exception handling registration module to find the exception handling entry (such as exception handling entry 1 (fault handler entry1)) from the page fault exception handling table according to the IO type label. The kernel-mode memory management service in the microkernel calls the fault_handler_table_dispatche interface of the exception handling calling module, and distributes the page missing exception to the IO memory page missing exception handling service (IO manager) of the system service layer for processing.

The process of handling the page missing exception corresponding to the virtual address space of the file memory type is similar to that of the IO memory type. The difference is that the specific exception handler label and exception handling service are respectively the file type label and the file memory page missing exception handling service. The same parts will not be repeated here. For details, see the above description of IO memory types.

Handle page fault exceptions corresponding to virtual address spaces of anonymous memory types:

The page missing exception corresponding to the virtual address space of the anonymous memory type is similar to that of the IO memory type. The difference is that the specific exception handler label and exception handling service are anonymous type label and anonymous memory page missing exception handling service respectively. The same parts will not be repeated here. For details, see the above description of IO memory types. In an optional implementation, the virtual address space of the anonymous memory type often occupies a relatively large area. For this reason, the user-mode memory management service may not be included in the physical address space page table entry corresponding to the virtual address space of the anonymous memory type. Add page missing exception handling label. For example, the physical address space page table entry can be empty, or can be "unlabeled" as shown in Figure 15, to streamline the page fault exception handling process and reduce storage space costs, thereby further improving the efficiency of memory access. At this time, the anonymous memory page fault processing service can be used as the default page fault exception handling service. In this way, when the tag is missing, the microkernel will forward the page fault exception information to the default page fault exception handler.

The page missing exception handling in the above embodiments of the present application refers to the page missing exception handling in the mapping attribute dimension, that is, the memory type dimension. It is understandable that page fault exception processing can be from another dimension. At this time, there are two page fault exceptions: ①Major Page Fault (Major Page Fault) is also called Hard Page Fault (Hard Page Fault), which refers to The memory that needs to be accessed is not in the virtual address space, nor in the physical address space, and needs to be loaded from a slow device. A slow device refers to an abnormal status end device (host or storage) in the Storage Area Network (SAN) network. The abnormal status is manifested in the fact that the end device (host or storage) cannot respond normally and quickly. ② Minor page fault (Minor Page Fault) is also called soft page fault (Soft Page Fault). It means that the memory that needs to be accessed is not in the virtual address space, but in the physical address space. Only the memory management service is required to establish the physical address space and The mapping relationship of the virtual address space is enough.

For the page missing exceptions in the above ① and ②, a method similar to the embodiment of the present application can be adopted to improve the efficiency of memory access. The difference is that in the above page missing exception handling scenarios in ① and ②, the page missing exception handler label can be divided according to the difference between ① and ②. Correspondingly, the page missing exception handling entry corresponding to the page missing exception handler label is ① And the page fault exception processing unit in ②. For specific processing units, please refer to relevant prior art and will not be described again here.

It should be understood that in order to implement the above functions, the electronic device includes corresponding hardware and/or software modules that perform each function. In conjunction with the algorithm steps of each example described in the embodiments disclosed herein, the embodiments of the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is performed by hardware or computer software driving the hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions in conjunction with the embodiments for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of the present application.

This embodiment can divide the electronic device into functional modules according to the above method examples. For example, each functional module can be divided corresponding to each function, or two or more functions can be integrated into one processing module. The above integrated modules can be hard Implemented in the form of software. It should be noted that the division of modules in this embodiment is schematic and is only a logical function division. In actual implementation, there may be other division methods.

In an example, FIG. 16 is an exemplary schematic block diagram of a device 1600 provided by an embodiment of the present application. As shown in FIG. 16, the device 1600 may include: a processor 1601 and a transceiver/transceiver pin 1602. Optionally, memory 1603 is also included.

The various components of device 1600 are coupled together by bus 1604, which includes a power bus, a control bus, and a status signal bus in addition to a data bus. However, for the sake of clarity, various buses are referred to as bus 1604 in the figure.

Optionally, the memory 1603 may be used for instructions in the foregoing method embodiments. The processor 1601 can be used to execute instructions in the memory 1603, and control the receiving pin to receive signals, and control the transmitting pin to send signals.

The device 1600 may be the electronic device or a chip of the electronic device in the above method embodiment.

All relevant content of each step involved in the above method embodiments can be quoted from the functional description of the corresponding functional module, and will not be described again here.

This embodiment also provides a computer storage medium. Computer instructions are stored in the computer storage medium. When the computer instructions are run on an electronic device, the electronic device causes the electronic device to execute the above related method steps to implement the large screen service in the above embodiment. Cross-device transfer control methods.

This embodiment also provides a computer program product. When the computer program product is run on a computer, it causes the computer to perform the above related steps to implement the cross-device flow control method of large-screen services in the above embodiment.

In addition, the embodiments of the present application also provide a device. This device may be a chip, a component or a module. The device may include a connected processor and a memory; where the memory is used to store computer execution instructions. When the device runs At this time, the processor can execute the computer execution instructions stored in the memory, so that the chip executes the cross-device flow control method of large-screen services in the above method embodiments.

Among them, the electronic equipment, computer storage media, computer program products or chips provided in this embodiment are all used to execute the corresponding methods provided above. Therefore, the beneficial effects they can achieve can be referred to the corresponding methods provided above. The beneficial effects of the method will not be repeated here.

Through the description of the above embodiments, those skilled in the art can understand that for the convenience and simplicity of description, only the division of the above functional modules is used as an example. In practical applications, the above functions can be allocated to different modules according to needs. The functional module is completed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above.

In the several embodiments provided in the embodiments of this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of modules or units is only a logical function division. In actual implementation, there may be other division methods, for example, multiple units or components may be combined or can be integrated into another device, or some features can be ignored, or not implemented. On the other hand, the coupling or direct coupling or communication connection between each other shown or discussed may be through some interfaces, and the indirect coupling or communication connection of the devices or units may be in electrical, mechanical or other forms.

A unit described as a separate component may or may not be physically separate. A component shown as a unit may be one physical unit or multiple physical units, that is, it may be located in one place, or it may be distributed to multiple different places. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above integrated units can be implemented in the form of hardware or software functional units.

Any contents of various embodiments of the embodiments of this application, as well as any contents of the same embodiment, can be freely combined. Any combination of the above contents is within the scope of the embodiments of the present application.

Integrated units may be stored in a readable storage medium if they are implemented in the form of software functional units and sold or used as independent products. Based on this understanding, the technical solutions of the embodiments of the present application are essentially or contribute to the existing technology, or all or part of the technical solution can be embodied in the form of a software product, and the software product is stored in a storage medium , including several instructions to cause a device (which can be a microcontroller, a chip, etc.) or a processor to execute all or part of the steps of the methods of various embodiments of the embodiments of this application. The aforementioned storage media include: U disk, mobile hard disk, read only memory (ROM), random access memory (RAM), magnetic disk or optical disk and other media that can store program code.

The embodiments of the present application have been described above in conjunction with the accompanying drawings, but the embodiments of the present application are not limited to the above specific implementations. The above-mentioned specific implementations are only illustrative and not restrictive. Those of ordinary skill in the art, inspired by the embodiments of the present application, can do so without departing from the spirit of the embodiments of the present application and the scope protected by the claims. Under the circumstances, many forms can also be made, all of which fall within the protection of the embodiments of this application.

Claims

A memory access method, characterized in that the method includes:

Obtain a first access request, the first access request is used to indicate access to the first virtual address space;

If a first page fault exception corresponding to the first virtual address space is detected, obtain a processing component label of the first virtual address space; wherein, the processing component label of the first virtual address space is used to identify the processing component label corresponding to the first virtual address space. the first processing component of the first virtual address space;

Based on the processing component label of the first virtual address space, the first processing component is instructed to perform exception processing on the first page fault exception.
The method according to claim 1, characterized in that said obtaining the processing component label of the first virtual address space includes:

According to the first virtual address space, the processing component label is searched from a page table; wherein the processing component label is included in the target page table entry of the page table of the first virtual address space; the page table It is established when the first virtual address space is pre-allocated; the target page table entry is a page table entry in the page table used to record the physical address space information corresponding to the first virtual address space.
The method according to claim 1 or 2, characterized in that the processing component label is generated according to the memory type of the first virtual address space and the component identification of the processing component corresponding to the memory type.
The method according to claim 2 or 3, characterized in that, after the processing component tag based on the first virtual address space instructs the first processing component to perform exception processing on the first page fault exception, The method also includes:

Obtain a second access request, the second access request is used to indicate access to the second virtual address space;

If a second page fault exception corresponding to the second virtual address space is detected, obtain the processing component label of the second virtual address space; wherein the processing component label of the second virtual address space is used to identify the processing component label corresponding to the second virtual address space. a second processing component of the second virtual address space;

Detect whether the processing component label of the second virtual address space meets preset conditions;

If the preset condition is not met, instruct the designated processing component to perform exception processing on the second page missing exception.
The method of claim 4, wherein the designated processing component is an anonymous page processing component; accordingly, if the memory type of the first virtual address space is an anonymous page type, the first virtual address The processing component label for space allocation is empty.
The method according to any one of claims 1 to 5, characterized in that the processing component tag based on the first virtual address space instructs the first processing component to handle the first page fault exception. Exception handling, including:

Determine the target processing component information based on the processing component label of the first virtual address space and the pre-established correspondence between the label and the processing component information;

Based on the target processing component information, the first processing component is instructed to perform exception processing on the first page fault exception.
The method according to claim 6, characterized in that if the first page fault exception corresponding to the first virtual address space is detected, before obtaining the processing component label of the first virtual address space, the method Also includes:

In response to the pre-assigned at least one processing component label, generate a key-value pair based on the at least one processing component label and the processing component information respectively corresponding to the at least one processing component label;

Create a page fault exception handling table that records the key-value pairs, and obtain the corresponding relationship between the pre-established tags and the processing component information.
A memory access device, characterized in that the device includes:

A request acquisition module configured to acquire a first access request, where the first access request is used to indicate access to the first virtual address space;

A label acquisition module configured to obtain a processing component label of the first virtual address space if a first page fault exception corresponding to the first virtual address space is detected; wherein, the processing component of the first virtual address space The component tag is used to identify the first processing component corresponding to the first virtual address space;

The exception handling module is configured to instruct the first processing component to perform exception handling on the first page fault exception based on the processing component label of the first virtual address space.
The device according to claim 8, wherein the tag acquisition module is further configured to:

According to the first virtual address space, the processing component label is searched from a page table; wherein the processing component label is included in the target page table entry of the page table of the first virtual address space; the page table It is established when the first virtual address space is pre-allocated; the target page table entry is a page table entry in the page table used to record the physical address space information corresponding to the first virtual address space.
The device according to claim 8 or 9, characterized in that the processing component label is generated according to the memory type of the first virtual address space and the component identifier of the processing component corresponding to the memory type.
The device according to any one of claims 9-10, characterized in that,

The request acquisition module is also configured to acquire a second access request, where the second access request is used to indicate access to the second virtual address space;

The label acquisition module is also configured to obtain the processing component label of the second virtual address space if a second page fault exception corresponding to the second virtual address space is detected; wherein, the second virtual address The processing component label of the space is used to identify the second processing component corresponding to the second virtual address space; detect whether the processing component label of the second virtual address space meets a preset condition;

The exception handling module is further configured to instruct a designated processing component to perform exception handling on the second page missing exception if the preset condition is not met.
The device according to claim 11, wherein the designated processing component is an anonymous page processing component; accordingly, if the memory type of the first virtual address space is an anonymous page type, the first virtual address The processing component label for space allocation is empty.
The device according to any one of claims 8-12, characterized in that the exception handling module is further configured to:

Determine the target processing component information based on the processing component label of the first virtual address space and the pre-established correspondence between the label and the processing component information;

Based on the target processing component information, the first processing component is instructed to perform exception processing on the first page fault exception.
The device according to claim 13, characterized in that the device further includes:

a registration module, configured to respond to the pre-assigned at least one processing component tag, generate a key-value pair based on the at least one processing component tag and the processing component information respectively corresponding to the at least one processing component tag; create a record The page fault exception handling table of the key-value pair obtains the corresponding relationship between the pre-established tags and the processing component information.
An electronic device, characterized by including:

processors and transceivers;

Memory, used to store one or more programs;

When the one or more programs are executed by the one or more processors, the one or more processors are caused to implement the method according to any one of claims 1 to 7.
A computer-readable storage medium, characterized in that it includes a computer program, characterized in that, when the computer program is run on a camera, it causes the camera to perform the method according to any one of claims 1 to 8. .
A chip, characterized in that it includes one or more interface circuits and one or more processors; the interface circuit is used to receive signals from a memory of an electronic device and send the signals to the processor, and the The signal includes computer instructions stored in the memory; when the processor executes the computer instructions, the electronic device is caused to perform the method of any one of claims 1 to 7.
A computer program product, characterized by comprising a computer program that, when executed by an electronic device, causes the electronic device to execute the method described in any one of claims 1 to 7.