JP2014026575A - Test device, test method, and test program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a test device and the like, in which a testing having a high randomness is performed.SOLUTION: A test device 1 includes: a selection part 2 for taking out a first instruction string randomly out of a plurality of instruction strings constituted by combining instructions 7 which can be processed by an information processing device 6; an insertion part 3 for performing first processing, when the first instruction string is constituted by plural ones of the instructions, in which the instruction string is selected randomly as an insertion instruction string, the insertion instruction string is inserted between the instructions constituting the first instruction string, and the inserted instruction string is set to a second instruction string, and for setting the first instruction string to the second instruction string when the first instruction string is constituted by one of the instructions; a generation part 4 for generating a third instruction string by aligning the second instruction strings; and an execution part 5 for instructing the information processing device to perform processing of the third instruction string. The insertion part 3 performs the first processing by one or more times.

Description

  The present invention relates to a test apparatus for testing an information processing apparatus.

  Patent Document 1 discloses an example of a method for testing an information processing apparatus (hereinafter also referred to as “test”). FIG. 22 shows a method of testing the information processing apparatus disclosed in Patent Document 1. As shown in FIG. 22, the test apparatus 32 disclosed in Patent Document 1 includes a suppression instruction specifying unit 28, a random test program generation unit 29, a test instruction execution unit 30, and an execution result determination unit 31.

  The inhibition instruction designating unit 28 stores an instruction to be excluded from the random test among instructions that can be processed by the information processing apparatus 6 (hereinafter also referred to as “executable instructions”). The random test program generation unit 29 selects a plurality of instructions that are not included in the instructions stored in the inhibition instruction specification unit 28 from the executable instructions, and generates an instruction sequence by combining the selected instruction sequences. The instruction sequence represents a program (hereinafter, referred to as “random test program”) that the information processing apparatus 6 processes in the random test. Next, the test instruction execution unit 30 instructs the information processing apparatus 6 to process the instruction sequence. Next, the execution result determination unit 31 receives information related to the execution result from the information processing device 6 and determines the state of the information processing device 6 according to the received information.

  However, executable instructions include pre-processing that performs predetermined instruction processing before executing the instruction, or instructions that require post-processing that performs predetermined instruction processing after executing the instruction (hereinafter referred to as “required processing instruction”). ")". Predetermined instruction processing is made up of an instruction sequence configured by sequentially arranging a plurality of instructions in advance (hereinafter, the instruction sequence constituting the pre-processing is referred to as “pre-processing instruction”, and the instruction sequence constituting the post-processing is defined as Represented as “post-processing instructions”). Since the pre-processing instruction and the post-processing instruction are predetermined instruction sequences, the randomness (also expressed as randomness, randomness, etc.) in the instruction sequence executed by the information processing device 6 is reduced.

  The information processing apparatus test method disclosed in Patent Document 2 is obtained by adding a new instruction between a required processing instruction and a preprocessing instruction or between a required processing instruction and a postprocessing instruction. The given command is output as a random test program. That is, in the information processing apparatus test method, the pre-processing instruction or the post-processing instruction is a predetermined instruction sequence. For this reason, randomness of a random test program that frequently requires processing instructions decreases.

  The logic verification method disclosed in Patent Document 3 combines a plurality of predetermined instruction sequences and outputs the combination as a test instruction sequence. In the logic verification method, a large-scale test instruction sequence is created by the method described above.

JP-A-62-100846 Japanese Patent Laid-Open No. 02-115940 JP 2002-157145 A

  A computer program for performing a random test (hereinafter simply referred to as “program”) includes a random number or a pseudo-random number generated by using a random number generation program (hereinafter referred to as “random number”. There is a method of selecting a plurality of instructions at random and executing the selected instructions. In order to execute a specific instruction, a pre-processing instruction for executing a predetermined instruction sequence or a post-processing instruction for executing a predetermined instruction sequence is required. However, since the pre-processing instruction and the post-processing instruction are processes including a predetermined instruction sequence, the instruction sequence constituting the random test is determined before and after the specific instruction. As a result, the randomness of the treatment decreases in the random test. For this reason, the purpose of the random test is not necessarily achieved.

  Therefore, a main object of the present invention is to provide a test apparatus or the like for performing a test with high randomness.

  In order to achieve the above object, a test apparatus according to the present invention has the following configuration.

That is, the test apparatus according to the present invention is
A selection unit that randomly extracts a first instruction sequence from a plurality of instruction sequences configured by combining instructions that can be processed by the information processing apparatus;
When the first instruction sequence is composed of a plurality of the instructions, the instruction sequence is randomly selected as an insertion instruction sequence, the insertion instruction sequence is inserted between the instructions constituting the first instruction sequence, Perform the first process with the inserted instruction sequence as the second instruction sequence,
When the first instruction sequence is composed of one instruction, an insertion unit that uses the first instruction sequence as the second instruction sequence;
A generator that creates a third instruction sequence by arranging the second instruction sequences;
An execution unit that instructs the information processing device to process the third instruction sequence;
The insertion unit performs the first process at least once.

As another aspect of the present invention, the test method according to the present invention includes:
When a first instruction sequence is randomly extracted from a plurality of instruction sequences configured by combining instructions that can be processed by the information processing apparatus, and the first instruction sequence includes a plurality of the instructions, random The instruction sequence is selected as an insertion instruction sequence, the insertion instruction sequence is inserted between the instructions constituting the first instruction sequence, and the inserted instruction sequence is processed as a second instruction sequence at least once. When the first instruction sequence is composed of one instruction, the first instruction sequence is used as the second instruction sequence, and a third instruction sequence is created by arranging the second instruction sequence, The information processing apparatus is instructed to process a third instruction sequence.

  According to the test apparatus and the like according to the present invention, a test having high randomness can be performed.

  Next, the best mode for carrying out the invention will be described in detail with reference to the drawings.

<First Embodiment>
The configuration of the test apparatus according to the first embodiment of the present invention and the processing performed by the test apparatus will be described in detail with reference to FIG. 1 and FIG. FIG. 1 is a block diagram showing a configuration of a test apparatus 1 according to the first embodiment of the present invention. FIG. 2 is a flowchart showing the flow of processing in the test apparatus 1 according to the first embodiment of the present invention.

  Referring to FIG. 1, the test apparatus 1 according to the first embodiment of the present invention includes a selection unit 2, an insertion unit 3, a generation unit 4, and an implementation unit 5. The test apparatus 1 is connected to an information processing apparatus 6 that is a target for performing a random test. The test apparatus 1 reads from the instruction 7 an instruction that can be executed by the information processing apparatus 6 (hereinafter also referred to as “executable instruction”).

  For example, the information processing apparatus 6 executes a command as shown in FIG. FIG. 3 is a conceptual diagram showing an executable instruction sequence that is an input of the test apparatus 1 according to the first embodiment of the present invention. The notations such as a1, a2, a3, a4, b1, b2, and b3 in FIG. 3 conceptually represent one instruction that can be executed in the information processing apparatus 6. In the first line in FIG. 3, there are four instructions “a1, a2, a3, a4”. The notation “a1, a2, a3, a4” indicates that the information processing apparatus 6 executes a1, then executes a2, then executes a3, and then executes a4. Hereinafter, when an instruction has one or more executable instructions, a series of instructions are collectively expressed as an instruction sequence (or “executable instruction sequence”).

  First, the selection unit 2 randomly selects one or more first instruction sequences from the instructions 7 (step S1). FIG. 4 is a conceptual diagram showing an instruction sequence selected by the selection unit 2 according to the first embodiment of the present invention. Referring to FIG. 4, for example, the selection unit 2 sequentially selects four first instruction sequences “b1, b2, b3”, “c1”, “d1, d2”, “a1, a2, a3, a4”. Choose.

  Next, the insertion unit 3 determines whether or not the first instruction sequence has two or more instructions (step S2). For example, in the example of FIG. 4, the insertion unit 3 determines that the first instruction sequence “b1, b2, b3” has three instructions “b1”, “b2”, and “b3” (step S2 Determined as YES). Further, the insertion unit 3 determines that the first instruction sequence “c1” has one instruction “c1” (determined NO in step S2).

  If the insertion unit 3 determines that the first instruction sequence has two or more instructions (YES in step S2), one or more randomly selected instruction sequences are inserted between the instructions in the first instruction sequence. By inserting, a second instruction sequence is created (step S3). When determining that the first instruction sequence does not include two or more instructions (determined as NO in step S2), the insertion unit 3 sets the first instruction sequence as the second instruction sequence (step S4).

  FIG. 5 is a conceptual diagram showing a second instruction sequence created by the insertion unit 3 according to the first embodiment of the present invention. An example of processing performed by the insertion unit 3 will be described with reference to FIGS. 4 and 5. For example, since the insertion unit 3 determines that the first instruction sequence “b1, b2, b3” has two or more instructions as described above, between “b1” and “b2”, “b2” One or more randomly selected instruction sequences are inserted between “b3” and “b3”. Referring to FIG. 5, for example, the insertion unit 3 inserts two instruction strings “c1” between “b1” and “b2”. Next, the insertion unit 3 inserts one instruction string “d1, d2” between “b2” and “b3”. Next, the insertion unit 3 creates a second instruction sequence “b1, c1, c1, b2, d1, d2, b3”. Further, the insertion unit 3 creates the second instruction sequence “c1” in order to determine that the first instruction sequence “c1” does not have two or more instructions.

  Next, the generation unit 4 creates a third instruction sequence by arranging the second instruction sequences (step S5). In the example of FIG. 5, the generation unit 4 arranges, for example, in order from the first row, “b1, c1, c1, b2, d1, d2, b3, c1, d1, a1, a2, a3, a4, c1, d2. , ... "is created. The generation unit 4 does not necessarily have to arrange the second instruction sequences created by the insertion unit 3 in order, may be rearranged randomly in units of the second instruction sequence, or may be arranged in the reverse order. Only the second instruction sequence of the part may be arranged. The arrangement method is not limited to the above-described example.

  Next, the execution unit 5 commands the information processing device 6 to process the third instruction sequence (step S6). For example, in the above-described example, the execution unit 5 issues the instruction “b1, c1, c1, b2, d1, d2, b3, c1, d1, a1, a2, a3, a4, c1, d2,. Commands the information processing device 6 for the column. Then, the information processing apparatus 6 processes an instruction string “b1, c1, c1, b2, d1, d2, b3, c1, d1, a1, a2, a3, a4, c1, d2,.

  The test devices disclosed in Patent Literature 1 to Patent Literature 3 include a series of instructions (hereinafter, referred to as “preprocessing instruction sequence”) executed before executing a certain instruction, and a series of instructions executed after executing a certain instruction ( Hereinafter, an instruction sequence for performing a random test is created by combining with “post-processing instruction sequence”. Therefore, the instructions processed by the information processing device 6 in the pre-processing instruction sequence or the post-processing instruction sequence are always the same. For this reason, the test devices disclosed in Patent Documents 1 to 3 create an instruction sequence in which a plurality of specific instruction sequences appear even though the test device is a device that performs a random test.

  On the other hand, the test apparatus 1 according to the first embodiment of the present invention inserts one or more randomly selected instruction sequences between each instruction in a series of instructions (instruction sequences) processed by the information processing device 6. . That is, the test apparatus 1 according to the first embodiment of the present invention converts a specific instruction sequence into an instruction sequence having a randomly selected instruction sequence. Therefore, according to the test apparatus 1 according to the first embodiment of the present invention, the frequency with which a specific instruction sequence appears can be reduced, and an instruction having high randomness can be created.

  That is, according to the test apparatus according to the first embodiment of the present invention, a test having high randomness can be performed.

<Second Embodiment>
Next, a second embodiment based on the above-described first embodiment will be described.

  In the following description, the characteristic part according to the present embodiment will be mainly described, and the same components as those in the first embodiment described above will be denoted by the same reference numerals, and redundant description will be omitted. To do.

  The test device 9 according to the second embodiment of the present invention and the processing performed by the test device will be described with reference to FIGS. FIG. 6 is a block diagram showing the configuration of the test apparatus 9 according to the second embodiment of the present invention. FIG. 7 is a flowchart showing the flow of processing in the test apparatus 9 according to the second embodiment of the present invention.

  Referring to FIG. 6, the test apparatus 9 further includes a reading unit 8. The test device 9 reads an executable instruction from the instruction 10. An example of the instruction 10 is shown in FIG. FIG. 8 is a conceptual diagram showing an instruction sequence read by the reading unit 8 according to the second embodiment of the present invention.

  Referring to FIG. 8, the instruction sequence includes an executable instruction, a pre-processing instruction sequence, and a post-processing instruction sequence. For example, the executable instruction “b2” is associated with the pre-processing instruction sequence “b1” and the post-processing instruction sequence “b3”. The executable instruction “d2” is associated with the pre-processing instruction sequence “d1”, but is not associated with the post-processing instruction sequence.

  The reading unit 8 reads an executable instruction, a pre-processing instruction sequence, and a post-processing instruction sequence from the instruction 10 (step S7). Next, the reading unit 8 creates an executable instruction sequence by arranging the read information in the order of a pre-processing instruction sequence, an executable instruction, and a post-processing instruction sequence (step S8). For example, the reading unit 8 reads the executable instruction “b2”, the pre-processing instruction sequence “b1”, and the post-processing instruction sequence “b3”, and arranges the read instructions as described above to obtain “b1, An instruction sequence “b2, b3” is created.

  The reading unit 8 enables the test apparatus 9 to perform the same processing as in the first embodiment even if the input is in a format different from the input in the first embodiment.

  That is, according to the test apparatus according to the second embodiment of the present invention, a test having high randomness can be performed.

<Third Embodiment>
Next, a third embodiment based on the above-described first embodiment will be described.

  In the following description, the characteristic part according to the present embodiment will be mainly described, and the same components as those in the first embodiment described above will be denoted by the same reference numerals, and redundant description will be omitted. To do.

  The configuration of the test apparatus 12 according to the third embodiment of the present invention and the processing performed by the test apparatus 12 will be described with reference to FIGS. 9 and 10. FIG. 9 is a block diagram showing the configuration of the test apparatus 12 according to the third embodiment of the present invention. FIG. 10 is a flowchart showing the flow of processing in the test apparatus 12 according to the third embodiment of the present invention.

  Referring to FIG. 9, the test apparatus 12 according to the third embodiment has an insertion part 11. If the insertion unit 11 determines that the first instruction sequence includes two or more instructions (determined as YES in step S2), the insertion unit 11 inserts an instruction sequence inserted between the instructions included in the first instruction sequence (hereinafter referred to as “insertion instruction sequence”). Are abbreviated as “)”, one or more instruction sequences are randomly selected (step S9).

  When the insertion unit 11 determines that each selected insertion instruction sequence includes two or more instructions (determined as YES in step S10), the insertion unit 11 includes, as instruction sequences to be inserted between the instructions included in the insertion instruction sequence, respectively. One or more instruction sequences are randomly selected. Next, the insertion unit 11 sets the instruction sequence obtained by inserting the newly selected instruction sequence between the instructions included in the inserted instruction sequence as the second insertion instruction sequence (step S11).

  If the insertion unit 11 determines that each selected insertion instruction sequence does not include two or more instructions (NO in step S10), the insertion instruction sequence is set as a second insertion instruction sequence (step S12). .

  Next, the insertion unit 11 inserts the second insertion instruction sequence created for each insertion instruction sequence between the instructions included in the first instruction sequence, and sets the obtained instruction sequence as the second instruction sequence (step S1). S13).

  For example, in the example illustrated in the second embodiment, it is assumed that the selection unit 2 selects the first instruction sequence “b1, b2, b3”. Next, the insertion unit 11 randomly selects the first A insertion instruction sequence to be inserted between “b1” and “b2” and the randomly selected first insertion sequence to be inserted between “b2” and “b3”. Select 1B insertion instruction sequence. It is assumed that the first A insertion instruction sequence is “c1” and the first B insertion instruction sequence is “d1, d2”. Since the insertion unit 11 determines that the selected first A insertion instruction sequence does not include two or more instructions with respect to “c1” that is the first A insertion instruction sequence, “c1” is used as the second insertion instruction sequence. .

  The insertion unit 11 determines that the selected 1B insertion instruction sequence includes two or more instructions for “d1, d2” that are insertion instruction sequences, and therefore, between “d1” and “d2”. Insert a randomly selected insertion instruction sequence. For example, if the selected insertion instruction sequence is “c1”, the insertion unit 11 sets “d1, c1, d2” as the second insertion instruction sequence.

  Next, the insertion unit 11 creates a second instruction sequence “b1, c1, b2, d1, c1, d2, b3” by inserting each second insertion instruction sequence into “b1, b2, b3”. To do.

  When the test apparatus 12 according to the third embodiment of the present invention determines that each selected insertion instruction sequence includes a plurality of instructions, the test apparatus 12 further selects a randomly selected instruction sequence between the instructions in the insertion instruction sequence. insert. By processing in this way, the instruction sequence to be created becomes more suitable for random testing.

  That is, according to the test apparatus according to the third embodiment of the present invention, a test having high randomness can be performed.

<Fourth Embodiment>
Next, a fourth embodiment based on the above-described third embodiment will be described.

  In the following description, characteristic parts according to the present embodiment will be mainly described, and the same components as those in the third embodiment described above will be denoted by the same reference numerals, and redundant description will be omitted. To do.

  The configuration of the test apparatus 14 according to the fourth embodiment of the present invention and the processing performed by the test apparatus 14 will be described with reference to FIGS. 11 and 12. FIG. 11 is a block diagram showing a configuration of a test apparatus 14 according to the fourth embodiment of the present invention. FIG. 12 is a flowchart showing the flow of processing in the test apparatus 14 according to the fourth embodiment of the present invention.

  Referring to FIG. 11, the test apparatus 14 according to the fourth embodiment has an insertion unit 13. When the insertion instruction sequence includes a plurality of instructions in the test apparatus according to the third embodiment of the present invention, the insertion unit 13 recursively repeats the process of inserting the instruction sequence between the plurality of instructions. .

  That is, the insertion unit 13 inserts one or more selected instruction sequences at random between instructions in the insertion instruction sequence (step S14). At that time, if the insertion unit 13 determines that the selected instruction sequence includes two or more instructions (determined as YES in step S15), the insertion unit 13 inserts each selected instruction sequence in the insertion instruction sequence, that is, in step S14. It is set as the process input (step S16).

  If the insertion unit 13 does not determine that the selected instruction sequence includes two or more instructions (NO in step S15), the insertion unit 13 determines whether all the processes for the selected instruction sequence have been completed. If the insertion unit 13 determines that all the processes for the selected instruction sequence have been completed (YES in step S17), the process ends. If the insertion unit 13 determines that the process for the selected instruction sequence has not been completed (NO in step S17), the insertion unit 13 performs the process of step S15 on the selected instruction sequence that has not been completed. .

  Since the test apparatus 14 according to the fourth embodiment of the present invention recursively repeats the process of inserting an instruction sequence, a test having higher randomness can be performed.

  That is, according to the test apparatus according to the fourth embodiment of the present invention, a test having high randomness can be performed.

<Fifth Embodiment>
Next, a fifth embodiment based on the first embodiment described above will be described.

  In the following description, the characteristic part according to the present embodiment will be mainly described, and the same components as those in the first embodiment described above will be denoted by the same reference numerals, and redundant description will be omitted. To do.

  The configuration of the test apparatus 17 according to the fifth embodiment of the present invention and the processing performed by the test apparatus 17 will be described with reference to FIGS. 13 and 14. FIG. 13 is a block diagram showing a configuration of a test apparatus 17 according to the fifth embodiment of the present invention. FIG. 14 is a flowchart showing the flow of processing in the test apparatus 17 according to the fifth embodiment of the present invention.

  Referring to FIG. 13, the test apparatus 17 according to the fifth embodiment includes a generation unit 15 and a creation unit 16. The generation unit 15 randomly selects data for the information processing device 6 to process the second instruction sequence created by the insertion unit 3 (step S18). For example, the generation unit 15 refers to an external storage device (not shown in FIG. 13) that stores data necessary for processing each instruction, and selects data required for each instruction in the second instruction sequence from among them. Also good. Alternatively, when each instruction in the second instruction sequence processes numerical data, the generation unit 15 may create numerical data at random. The method of selecting data at random is not limited to the method described above.

  Next, the creating unit 16 creates a third instruction sequence by associating the second instruction sequence with the data selected as described above (step S19).

  The test apparatus 17 according to the fifth embodiment of the present invention randomly selects data to be processed by the information processing apparatus 6. Since the test apparatus 17 creates different data even for instruction sequences that process the same instruction, according to the test apparatus 17 according to the fifth embodiment of the present invention, the test to be created is further a random test. It will be a suitable program.

  That is, according to the test apparatus according to the fifth embodiment of the present invention, a test having high randomness can be performed.

<Sixth Embodiment>
Next, a sixth embodiment based on the first embodiment described above will be described.

  In the following description, the characteristic part according to the present embodiment will be mainly described, and the same components as those in the first embodiment described above will be denoted by the same reference numerals, and redundant description will be omitted. To do.

  The configuration of the test apparatus 20 according to the sixth embodiment of the present invention and the processing performed by the test apparatus 20 will be described with reference to FIGS. 15 and 16. FIG. 15 is a block diagram showing a configuration of a test apparatus 20 according to the sixth embodiment of the present invention. FIG. 16 is a flowchart showing the flow of processing in the test apparatus 20 according to the sixth embodiment of the present invention.

  Referring to FIG. 15, the test apparatus 20 according to the sixth embodiment further includes an execution unit 18 and a determination unit 19. The execution unit 18 validates the advance control in the information processing device 6 (step S20), and then instructs the information processing device 6 to process the third instruction sequence generated by the generation unit 4 (step S21). Next, the information processing apparatus 6 sends a result obtained by executing the processing of the third instruction sequence to the execution unit 18. The implementation unit 18 receives the execution result transmitted by the information processing device 6 (step S22). The execution result includes a register value, a memory value accessed by the third instruction sequence, and the like.

  Next, the execution unit 18 invalidates the preceding control in the information processing device 6 (step S23), and then instructs the information processing device 6 to process the third instruction sequence generated by the generation unit 4 (step S24). The method of invalidating the advance control can be realized by generating an interrupt each time the information processing apparatus 6 executes each instruction of the third instruction sequence. Next, the information processing apparatus 6 sends the result obtained by executing the processing of the third instruction sequence to the execution unit 18. The implementation unit 18 receives the execution result transmitted by the information processing device 6 (step S25).

  Next, the determination unit 19 compares the two execution results described above in the implementation unit 18 and outputs error information when it is determined that the two execution results do not match (determined NO in step S26). (Step S27). If the determination unit 19 determines that the two execution results match (determined as YES in step S26), the determination unit 19 does not output error information.

  In the above-described example, the execution unit 18 receives the execution result after the information processing apparatus 6 executes each instruction of the third instruction sequence. However, the execution unit 18 may receive the execution result every time each instruction is executed. Can be realized. Alternatively, the execution unit 18 can receive the execution result after the information processing apparatus 6 executes a part of the instructions in the third instruction sequence.

  That is, according to the test apparatus according to the sixth embodiment of the present invention, a test having high randomness can be performed. Furthermore, according to the test apparatus of the sixth embodiment of the present invention, it is possible to detect an error that may occur when the information processing apparatus 6 processes the third instruction sequence.

<Seventh Embodiment>
Next, a seventh embodiment based on the above-described first embodiment will be described.

  In the following description, the characteristic part according to the present embodiment will be mainly described, and the same components as those in the first embodiment described above will be denoted by the same reference numerals, and redundant description will be omitted. To do.

  The configuration of the test apparatus 22 according to the seventh embodiment of the present invention and the processing performed by the test apparatus 22 will be described with reference to FIGS. 17 and 18. FIG. 17 is a block diagram showing a configuration of a test apparatus 22 according to the seventh embodiment of the present invention. FIG. 18 is a flowchart showing the flow of processing in the test apparatus 22 according to the seventh embodiment of the present invention.

  Referring to FIG. 17, the test apparatus 22 according to the seventh embodiment includes an end unit 21. When receiving the end signal (determined as YES in Step S28), the end unit 21 thereafter ends the processing in the first to sixth embodiments (Step S29). If the end unit 21 does not receive the end signal (determined as NO in step S28), the end unit 21 performs the processing in the first to sixth embodiments (step S34).

  According to the test apparatus 22 according to the seventh embodiment of the present invention, in addition to the effects obtained by the first to sixth embodiments, it is possible to control the execution of a random test from the outside.

  That is, according to the test apparatus according to the seventh embodiment of the present invention, a test having high randomness can be performed.

<Eighth Embodiment>
Next, an eighth embodiment based on the above-described first embodiment will be described.

  In the following description, the characteristic part according to the present embodiment will be mainly described, and the same components as those in the first embodiment described above will be denoted by the same reference numerals, and redundant description will be omitted. To do.

  The configuration of the test apparatus 27 according to the eighth embodiment of the present invention and the processing performed by the test apparatus 27 will be described with reference to FIGS. FIG. 19 is a block diagram showing a configuration of a test apparatus 27 according to the eighth embodiment of the present invention. FIG. 20 is a flowchart showing the flow of processing in the test apparatus 27 according to the eighth embodiment of the present invention.

  Referring to FIG. 19, the test apparatus 27 according to the eighth embodiment of the present invention includes a selection unit 23, an insertion unit 24, a generation unit 25, and a storage unit 26. First, the selection unit 23 selects a plurality of executable instruction sequences from the instruction 7 (step S30). Next, the insertion unit 24 performs the first process as described in the first embodiment of the present invention on each selected executable instruction sequence (step S31). Next, the insertion unit 24 stores the second instruction sequence created as described above in the storage unit 26 (step S32). Next, the generation unit 25 randomly extracts the second instruction sequence stored in the storage unit 26, and creates a third instruction sequence by arranging the extracted second instruction sequences (step S33).

  In the test apparatus 27 according to the eighth embodiment of the present invention, the insertion unit 24 stores the second instruction sequence in the storage unit 26 as described above, so that the first process is executed for one executable instruction sequence. There is no need. Therefore, according to the test apparatus 27 according to the eighth embodiment of the present invention, in addition to being able to reduce the first processing, the effect of the first embodiment of the present invention is maintained as it is.

  That is, according to the test apparatus according to the eighth embodiment of the present invention, a test having high randomness can be performed.

(Hardware configuration example)
FIG. 21 is a block diagram schematically showing a hardware configuration of a calculation processing apparatus capable of realizing the test apparatus according to each embodiment of the present invention.

  Next, a configuration example of hardware resources for realizing the above-described test apparatus according to each embodiment of the present invention using one calculation processing apparatus (information processing apparatus, computer) will be described. However, such a test apparatus may be realized using at least two calculation processing apparatuses physically or functionally. Further, such a test apparatus may be realized as a dedicated apparatus.

  FIG. 21 is a diagram schematically showing a hardware configuration of a calculation processing apparatus capable of realizing the test apparatus according to the first embodiment to the eighth embodiment of the present invention. The calculation processing device 33 includes a central processing unit (hereinafter referred to as “CPU”) 34, a memory 35, a disk 36, a nonvolatile recording medium 37, an input device 38, and an output device 39.

  The nonvolatile recording medium 37 refers to, for example, a compact disc, a digital versatile disc, a Blu-ray disc, a universal serial bus memory (USB memory), and the like. Even if it is not supplied, the program is retained and can be carried. The nonvolatile recording medium 37 is not limited to the above-described medium. Further, the program may be carried via a communication network instead of the nonvolatile recording medium 37.

  That is, the CPU 34 copies a software program (computer program: hereinafter simply referred to as “program”) stored in the disk 36 to the memory 35 at the time of execution, and executes arithmetic processing. The CPU 34 reads data necessary for program execution from the memory 35. When display is necessary, the CPU 34 displays the output result on the output device 39. When inputting a program from the outside, the CPU 34 reads the program from the input device 38. The CPU 34 interprets and executes the test program (FIGS. 2, 7, 10, 12, 14, 16, 18, and 20) in the memory 35. The CPU 34 sequentially performs the processes described in the above-described embodiments of the present invention.

  That is, in such a case, it can be understood that the present invention can also be realized by such a test program. Furthermore, it can be understood that the present invention can also be realized by a computer-readable recording medium on which such a test program is recorded.

1 is a block diagram illustrating a configuration of a test apparatus according to a first embodiment of the present invention. It is a flowchart which shows the flow of a process in the test apparatus which concerns on the 1st Embodiment of this invention. It is a conceptual diagram showing the executable instruction sequence used as the input of the test apparatus which concerns on the 1st Embodiment of this invention. It is a conceptual diagram showing the command sequence which the selection part concerning the 1st Embodiment of this invention selects. It is a conceptual diagram showing the 2nd command sequence which the insertion part which concerns on the 1st Embodiment of this invention produces. It is a block diagram which shows the structure of the test apparatus which concerns on the 2nd Embodiment of this invention. It is a flowchart which shows the flow of a process in the test apparatus which concerns on the 2nd Embodiment of this invention. It is a conceptual diagram showing the command sequence which the reading part concerning the 2nd Embodiment of this invention reads. It is a block diagram which shows the structure of the test apparatus which concerns on the 3rd Embodiment of this invention. It is a flowchart which shows the flow of a process in the test apparatus which concerns on the 3rd Embodiment of this invention. It is a block diagram which shows the structure of the test apparatus which concerns on the 4th Embodiment of this invention. It is a flowchart which shows the flow of a process in the test apparatus which concerns on the 4th Embodiment of this invention. It is a block diagram which shows the structure of the test apparatus which concerns on the 5th Embodiment of this invention. It is a flowchart which shows the flow of a process in the test apparatus which concerns on the 5th Embodiment of this invention. It is a block diagram which shows the structure of the test apparatus which concerns on the 6th Embodiment of this invention. It is a flowchart which shows the flow of a process in the test apparatus which concerns on the 6th Embodiment of this invention. It is a block diagram which shows the structure of the test apparatus which concerns on the 7th Embodiment of this invention. It is a flowchart which shows the flow of a process in the test apparatus which concerns on the 7th Embodiment of this invention. It is a block diagram which shows the structure of the test apparatus which concerns on the 8th Embodiment of this invention. It is a flowchart which shows the flow of a process in the test apparatus which concerns on the 8th Embodiment of this invention. It is a block diagram which shows roughly the hardware constitutions of the calculation processing apparatus which can implement | achieve the test apparatus which concerns on each embodiment of this invention. It is a block diagram which shows the structure of the test apparatus relevant to this invention.

DESCRIPTION OF SYMBOLS 1 Test apparatus 2 Selection part 3 Insertion part 4 Generation part 5 Execution part 6 Information processing apparatus 7 Instruction 8 Reading part 9 Test apparatus 10 Instruction 11 Insertion part 12 Test apparatus 13 Insertion part 14 Test apparatus 15 Generation part 16 Creation part 17 Test apparatus DESCRIPTION OF SYMBOLS 18 Execution part 19 Judgment part 20 Test apparatus 21 End part 22 Test apparatus 23 Selection part 24 Insertion part 25 Generation part 26 Storage part 27 Test apparatus 28 Suppression instruction designation part 29 Random test program generation part 30 Test instruction execution part 31 Execution result determination 31 Section 32 Test device 33 Calculation processing device 34 CPU
35 Memory 36 Disk 37 Non-volatile recording medium 38 Input device 39 Output device

Claims (10)

A selection unit that randomly extracts a first instruction sequence from a plurality of instruction sequences configured by combining instructions that can be processed by the information processing apparatus;
When the first instruction sequence is composed of a plurality of the instructions, the instruction sequence is randomly selected as an insertion instruction sequence, the insertion instruction sequence is inserted between the instructions constituting the first instruction sequence, Perform the first process with the inserted instruction sequence as the second instruction sequence,
When the first instruction sequence is composed of one instruction, an insertion unit that uses the first instruction sequence as the second instruction sequence;
A generator that creates a third instruction sequence by arranging the second instruction sequences;
An execution unit that instructs the information processing device to process the third instruction sequence;
The insertion unit is a test apparatus that performs the first process at least once. The instruction, a pre-processing instruction sequence performed before the information processing apparatus executes the instruction, and a post-processing instruction sequence performed after the information processing apparatus executes the instruction; The test apparatus according to claim 1, further comprising a reading unit that arranges the pre-processing instruction sequence and the post-processing instruction sequence to form the instruction sequence. The insertion part is
When it is determined that the insertion instruction sequence is composed of a plurality of the instructions, the instruction sequence is randomly selected as a new insertion instruction sequence, and the new insertion instruction sequence is selected as the instruction constituting the insertion instruction sequence. The instruction sequence obtained by inserting between them is the second insertion instruction sequence,
When it is determined that the insertion instruction sequence is composed of one instruction, a second process is performed in which the insertion instruction sequence is the second insertion instruction sequence.
3. The test apparatus according to claim 1, wherein the second instruction sequence is inserted into the first instruction sequence, and the inserted instruction sequence is the second instruction sequence. 4. When the insertion unit determines that the new insertion instruction sequence is composed of two or more instructions, the insertion unit repeatedly performs the second process using the new insertion instruction sequence as the insertion instruction sequence. Item 4. The test apparatus according to Item 3. A creation unit that randomly selects data for the second instruction sequence and creates the selected data as first data;
5. The test apparatus according to claim 1, wherein the generation unit combines the second instruction sequence and the first data to create the third instruction sequence. 6. The implementation unit enables the preceding control in the information processing device, receives the first result in response to causing the information processing device to execute the third instruction sequence, invalidates the preceding control in the information processing device, Receiving a second result in response to causing the information processing apparatus to execute the third instruction sequence;
2. The information processing apparatus according to claim 1, further comprising: a determination unit that compares the first result with the second result and outputs information regarding an error when determining that they do not match and outputs no information regarding the error when determining that they match. The test apparatus according to claim 5. An end unit that terminates the process upon receiving the end signal;
The test apparatus according to claim 6, wherein the selection unit, the insertion unit, the generation unit, the creation unit, the implementation unit, and the determination unit repeatedly perform processing until the termination unit receives the termination signal. A storage unit for storing the second instruction sequence;
The selection unit reads a plurality of the instruction sequences,
The insertion unit performs the first process on the plurality of instruction sequences, stores the second instruction sequence in the storage unit,
The test apparatus according to claim 1, wherein the generation unit reads the second instruction sequence randomly from the storage unit, and arranges the read second instruction sequences to form the third instruction sequence.   When a first instruction sequence is randomly extracted from a plurality of instruction sequences configured by combining instructions that can be processed by the information processing apparatus, and the first instruction sequence includes a plurality of the instructions, random The instruction sequence is selected as an insertion instruction sequence, the insertion instruction sequence is inserted between the instructions constituting the first instruction sequence, and the inserted instruction sequence is processed as a second instruction sequence at least once. When the first instruction sequence is composed of one instruction, the first instruction sequence is used as the second instruction sequence, and a third instruction sequence is created by arranging the second instruction sequence, A test method for instructing the information processing apparatus to process a third instruction sequence. A selection function for randomly extracting a first instruction sequence from a plurality of instruction sequences configured by combining instructions that can be processed by the information processing apparatus;
When the first instruction sequence is composed of a plurality of the instructions, the instruction sequence is randomly selected as an insertion instruction sequence, the insertion instruction sequence is inserted between the instructions constituting the first instruction sequence, Perform the process of setting the inserted instruction sequence as the second instruction sequence at least once,
In the case where the first instruction sequence is composed of one instruction, an insertion function that uses the first instruction sequence as the second instruction sequence;
A generation function for creating a third instruction sequence by arranging the second instruction sequences;
An execution function for instructing the information processing apparatus to process the third instruction sequence;
A test program implemented on a computer.

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