JP2014022534A - Electronic component mounting system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance the entire tact time in a dual lane system.SOLUTION: A storage unit for storing the information about mounting turn, and the information about a task where the processing operation for each electronic component being mounted in each mounting turn is one unit, is provided. The information about mounting turn includes sequence numbers indicating the order of mounting turns being set, respectively, for a first component mounting head and a second component mounting head, and set numbers being associated with the sequence numbers. If there is a set number associated with a sequence number related to a task being performed by one component mounting head 40(30), when the other component mounting head 30(40) starts operation, during operation of any one of a first component mounting head 30 or a second component mounting head 40 stored in the storage unit, control means determines the mounting sequence of the other component mounting head based on the set number.

Description

  The present invention relates to an electronic component mounting system.

  The mounting system according to the present invention has a component mounting head. The component mounting head is a device for mounting an electronic component on a substrate fixed to a preset mounting area. In recent years, a technique for improving efficiency by accessing a plurality of component mounting heads simultaneously or alternately on the same substrate is known. When a plurality of component mounting heads are accessed in parallel with respect to the same substrate, an area (overlapping area) where all the component mounting heads can enter is formed on the substrate. In order to prevent the component mounting heads from colliding with each other in this overlapping area, priority (priority to the overlapping area) is set so that one component mounting head can enter the overlapping area among the plurality of component mounting heads. It is necessary to prohibit the entry of the other component mounting head into the overlapping area, while giving the authority to enter and perform the component mounting work. However, by simply giving superiority or inferiority to a plurality of component mounting heads and restricting entry into the overlapping area, the waiting time of the component mounting heads without priority is increased, and the processing efficiency is lowered. Thus, techniques for reducing the tact time while regulating interference have been proposed.

  Here, an area that is determined based on the amount of movement of both the component mounting heads and in which both component mounting heads can interfere with each other in the overlapping area is referred to as an interference region. For example, in Patent Document 1 previously proposed by the applicant, the interference area is dynamically recalculated every time one component mounting head finishes the mounting operation of one component so that the interference area becomes narrower. Technology has been proposed. With this method, each time component mounting progresses, the interference area is dynamically recalculated and set narrower, increasing the opportunity for multiple component mounting heads to access the same board at the same time. It is possible to reduce the overall tact time while preventing the problem.

  Further, another patent document 2 previously proposed by the applicant of the present application discloses a technique for weighting the degree of interference in an overlapping area. In Patent Document 2, while one component mounting head is performing a component mounting operation in an overlapping area with the highest degree of interference, the other component mounting head assigns another coordinate capable of avoiding interference and the opportunity for parallel operation A method of ensuring is disclosed. Both component mounting heads are alternately given priority in an overlapping area with a high degree of interference. The component mounting head to which priority is given is completed in order from the work in the overlapping area where the degree of interference is high. Therefore, also in the method of Patent Document 2, the possibility of interference decreases as the mounting of components proceeds, and accordingly, the opportunity for both component mounting heads to simultaneously mount components on the same substrate increases. The overall tact time can be shortened while preventing interference.

  In the prior arts disclosed in Patent Documents 1 and 2, a plurality of component mounting heads are accessed on the same substrate, and component mounting is processed in parallel. Therefore, in principle, the mounting timing of the component mounting head does not deviate. Therefore, if a combination suitable for each board is set in a set of a plurality of component mounting heads, it is possible to increase the ratio of parallel work in avoiding interference and all component mounting work in a suitable mounting order. It was.

JP 2011-23616 A JP 2011-124357 A

  As described above, each of the prior arts disclosed in Patent Documents 1 and 2 presupposes that a plurality of component mounting heads are alternately given priority and components are mounted in a region having a high degree of interference. .

  On the other hand, in recent years, there is an increasing demand for a dual lane method in which a pair of lanes that are adjacent to each other in parallel and that individually transport a substrate are provided. In the dual lane method, a component mounting head is provided for each lane. In a part of the mounting area where each component mounting head mounts an electronic component, there is an overlapping area so that all the component mounting heads can enter. In this overlapping area, an interference area where each component mounting head can interfere is determined based on the amount of movement of the component mounting head.

  In a dual lane system, the timing at which a substrate is transported often varies between one lane and the other lane. For this reason, there is a possibility that the combination of the sequence (mounting sequence) for mounting the electronic components between the component mounting head to which priority is given and the component mounting head to which priority is not given may be out of order. As a result, even if the above-described prior art is adopted for the dual lane system, if the mounting sequence does not match, the tact time becomes long, and the processing efficiency may be lowered.

  The present invention has been made in view of the above-described problems, and in an installation in which two lanes are adjacent in parallel and a component mounting head is provided for each mounting area set in both lanes, the overall tact time is reduced. It is an object to provide an electronic component mounting system that can be improved.

  In order to solve the above problems, the present invention is provided in the first lane, the first lane and the second lane, which are installed in parallel and adjacent to each other, each of which individually carries a substrate, The board transported to the first lane is stopped, the first mounting area for mounting electronic components, and the board provided in the second lane and transported to the second lane are stopped to A second mounting area for mounting a component; a first component mounting head for mounting an electronic component picked up by a component suction operation on a substrate provided in the first lane and stopped in the first mounting area; A second component mounting head for mounting an electronic component picked up by a component suction operation on a board provided in the second lane and stopped in the second mounting area; the first component mounting head; and the second component mounting head Information on the mounting turn, which is the unit of operation from when one of the pickups picks up the electronic component to the mounting of the electronic component picked up on the board in the corresponding lane, and is mounted at each mounting turn Information relating to a task with a processing operation for each electronic component as a unit is stored in each of the first component mounting head and the second component mounting head, and information stored in the storage unit And a control means for controlling the order of the plurality of tasks assigned to the first component mounting head and the order of the plurality of tasks assigned to the second component mounting head as a mounting sequence, respectively. The information on the sheet indicates the order of the mounting turn set for each of the first component mounting head and the second component mounting head. And a set number associated with the sequence number, the task associated with the related sequence number is executed by one of the first component mounting head and the second component mounting head. Is the sequence number related to the task that can be executed in parallel by the other component mounting head, and the storage unit stores the sequence numbers related to all the tasks of the first component mounting head and the second component mounting head. And storing the set number with respect to at least a part of the sequence numbers, and the control means includes any one of the first component mounting head and the second component mounting head. When the other component mounting head starts operating when it is in operation, the one component mounting head is executing When there is a set number associated with a sequence number related to a task, the mounting sequence of the other component mounting head is determined based on the set number. is there. In this aspect, the first component mounting head mounts the electronic component picked up by the component suction operation on the substrate transported to the first mounting area. The second component mounting head mounts the electronic component picked up by the component suction operation on the substrate transported to the second mounting area. The mounting operation of the first component mounting head and the second component mounting head is controlled by the control means. The control means controls the mounting operation based on the information on the mounting turn stored in the storage unit and the information on the task with the processing operation for each electronic component mounted in each mounting turn as a unit. The information related to the mounting turn includes a sequence number indicating the order of mounting turn set for each of the first component mounting head and the second component mounting head, and a set number associated with this sequence number. The set number is a sequence number related to a task that can be executed in parallel with the task when the task related to a certain sequence number is being executed. Therefore, when there is a task that can be executed by the second component mounting head in parallel with the first component mounting head when the first component mounting head is executing a task related to a certain sequence number, control is performed. The means can refer to the sequence number related to the task as the set number. When there is a set number, the second component mounting head executes a task related to the set number associated with the sequence number related to the task of the first component mounting head. As a result, the second component mounting head can execute the component mounting operation in parallel with the first component mounting head. Similarly, when there is a task that can be executed by the first component mounting head in parallel with the second component mounting head when the second component mounting head is executing a task related to a sequence number, The control means can refer to the sequence number related to the task as the set number. When there is a set number, the first component mounting head executes a task related to the set number associated with the sequence number related to the task of the second component mounting head. As a result, the first component mounting head can execute the component mounting operation in parallel with the second component mounting head.

  In the mounting system according to a preferred aspect, the first mounting area and the second mounting area include an overlapping area that partially overlaps so that both the first component mounting head and the second component mounting head can enter, The set number is set to a sequence number that includes a task in which the component mounting head on the other side is closest to the overlapping area side with respect to the component mounting head that executes the sequence number associated with the set number. In this aspect, the range (interference area) in which the first and second component mounting heads operating in parallel can interfere with each other in the overlapping area can be set as narrow as possible. In other words, the area in which the first and second component mounting heads can operate without interference becomes as wide as possible. Therefore, in order to avoid interference, the necessity of waiting for one component mounting head can be reduced as much as possible. Further, even when it is necessary to stand by, the time for the preceding component mounting head to stay in the interference area is relatively shortened, so the waiting time is also shortened.

  In a preferred aspect, the control means determines, for each task, whether or not interference occurs in the overlapping area when the first component mounting head and the second component mounting head are operated in parallel. Based on the determination, interference between both component mounting heads in the overlapping area is avoided. In this aspect, it is possible to realize parallel work of the first component mounting head and the second component mounting head while avoiding interference in the overlapping area.

  In a preferred aspect, the storage unit includes, for each task related to the sequence number, a storage area that stores an overlapping area entry length in which a component mounting head that executes the task enters toward the overlapping area, and the control The means executes the determination based on the overlapping area approach length. In this aspect, the control means can avoid interference while referring to the overlap area entry length that is the length of entry into the overlap area for each task. Therefore, by verifying the degree of entry into the overlapping area for each task, it is possible to set the interference waiting time to be short, or to set the area (or distance) in which the interference occurs to be short. Become.

  In a preferred aspect, when the control unit cannot refer to the set number, the control unit selects a sequence number that is a candidate for parallel operation in a preset order, and for each task related to the selected sequence number. When the first component mounting head and the second component mounting head are operated in parallel, it is determined whether or not interference occurs in the overlapping area, and it is determined that interference does not occur in the overlapping area. In some cases, the task is executed. In this aspect, parallel operation can be dynamically assigned in a preset order with respect to unimplemented tasks. Therefore, even when the set number is not set or when re-mounting is executed, parallel operation can be realized as much as possible.

  In a preferred aspect, when the task related to the related sequence number is being executed by either one of the first component mounting head or the second component mounting head, the set number is The other component mounting head is set to a sequence number including a task that can be executed in parallel without interfering with the overlapping area. In this aspect, the set number is associated with the sequence number in a combination that can reliably avoid interference in the overlapping area. Therefore, the parallel operation of the first and second component mounting heads can be realized based on the set number.

  In the implementation system according to a preferred aspect, when the number of times the task is processed in the first lane is different from the number of times the task is processed in the second lane, the set number is set in the lane having the smaller number of times of processing. It is set as much as the implementation process ends. In this aspect, even when the number of processing times of tasks is different between the substrate in the first lane and the substrate in the second lane, a set of tasks that can be operated in parallel is configured in a portion where the processing times are common. Therefore, suitable parallel work can be realized for all the mounting sequences.

  In a mounting system according to a preferred aspect, the control means causes a mounting failure to occur in a task executed by one of the first component mounting head and the second component mounting head, and the electronic component related to the mounting failure. When re-mounting is performed immediately after completion of the task, when the other component mounting head executes the next task assigned to the other component mounting head, the one component mounting head re-mounts. The mounting sequence of the other component mounting head is controlled based on the set number associated with the sequence number of the task related to the electronic component. In this aspect, when a mounting failure occurs in the task executed by the first component mounting head, the first component mounting head executes remounting of the electronic component related to the mounting failure immediately after the task is finished. The same applies when a mounting failure occurs in the task executed by the second component mounting head. When the first component mounting head performs remounting and the second component mounting head performs a parallel operation, the second component mounting head performs the second operation based on the set number associated with the sequence number related to the task in which remounting has occurred. The task of the component mounting head is determined. When the second component mounting head performs remounting, when the first component mounting head performs a parallel operation, the first component mounting head performs first operation based on the set number associated with the sequence number related to the task in which remounting has occurred. The task of the component mounting head is determined. Therefore, it is possible to maintain the order of the sequence numbers respectively associated with one component mounting head and the other component mounting head. As a result, the mounting sequence after the reworking operation of one of the component mounting heads is maintained according to the optimal order stored in the storage unit in advance. Therefore, even if the redo work is occurring, it is possible to avoid the total tact time from being prolonged.

  In the mounting system according to a preferred aspect, the control means causes an electronic component related to the mounting failure when a mounting failure occurs in a task executed by one of the first component mounting head and the second component mounting head. In the case where the re-mounting is executed collectively after the completion of all tasks assigned to the one component mounting head, the next component mounting head is assigned to the other component mounting head. When executing this task, the mounting sequence of the other component mounting head is determined regardless of the set number set in the storage unit. In this aspect, so-called collective retry (when a mounting failure occurs, re-mounting of the electronic components related to the mounting failure is collectively performed at the end) is executed. Therefore, when a mounting failure occurs in the task executed by the first component mounting head, the first component mounting head re-mounts the electronic component related to the mounting failure after all tasks related to the substrate being mounted are completed. Execute. The same applies when a mounting failure occurs in the task executed by the second component mounting head. For this reason, when re-mounting occurs in one of the first and second mounting areas, there is a possibility that the waiting time in the other mounting area becomes longer in order to maintain the mounting sequence in the other mounting area. is there. Therefore, in this aspect, in the operation state where collective retry is being executed, the mounting sequence of the other component mounting head is determined regardless of the set number.

  As described above, according to the present invention, the first lane and the second lane are adjacent to each other in parallel, and the first and second component mounting heads are set for each of the first and second mounting areas set in both lanes. In the equipment provided with the above, there is a remarkable effect that it is possible to provide an electronic component mounting system capable of improving the overall tact time.

It is a figure which shows schematic structure of the component mounting system (an example of the mounting system of an electronic component) which concerns on one Embodiment of this invention, (A) is a plane schematic diagram, (B) is a side cross-sectional schematic diagram. It is a block diagram which shows schematic structure of the component mounting system which concerns on embodiment of FIG. FIG. 2 is an entity diagram (ER diagram) showing an example of the structure of data stored in data storage means of the component mounting system of FIG. 1. It is a schematic plan view schematically showing an example of a lane set. FIG. 5 is a view table showing a setting example of sequence numbers and lane numbers corresponding to the lane set of FIG. 4, (A) is a view table related to the sequence set table, and (B) is a view table related to the task table. It is a flowchart which shows the example of a setting of a mounting sequence. It is a flowchart which shows the example of control of the component mounting operation | work which concerns on embodiment of FIG. It is a flowchart which shows the mounting process subroutine in the flowchart of FIG. FIG. 8 is a schematic plan view schematically showing, as an example, a result when the flowchart of FIG. 7 is executed based on the settings of FIGS. It is a schematic plan view schematically showing another example of a lane set. 11 is a view table showing a setting example of sequence numbers and lane numbers corresponding to the lane set of FIG. 10. FIG. 12 is a schematic plan view schematically showing, as an example, a result when the flowchart of FIG. 7 is executed based on the setting of FIG. 11. FIG. 8 is a schematic plan view schematically showing, as an example, another result when the flowchart of FIG. 7 is executed based on the settings of FIGS. FIG. 8 is a schematic plan view schematically showing, as an example, still another result when the flowchart of FIG. 7 is executed based on the settings of FIGS. It is an entity relationship diagram (ER diagram) showing another example of the structure of data stored in the data storage means of the component mounting system of FIG. 16 is a view table showing a setting example of sequence numbers and lane numbers corresponding to the lane set of FIG. 11 based on the ER diagram of FIG. 15. FIG. 16 is a schematic plan view schematically showing, as an example, the result when the flowchart of FIG. 7 is executed based on the ER diagram of FIG. 15.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

  A component mounting system 10 shown in FIG. 1 is of a dual lane type including two sets of first and second mounting units UA and UB. The first and second mounting units UA and UB (see FIG. 2) are provided on a rectangular base 11 for each of two lanes 1 and 2 (first and second lanes). In the following description, the horizontal direction parallel to the lanes 1 and 2 is the X-axis direction, the horizontal direction orthogonal to the X-axis direction is the Y-axis direction, and the vertical direction is the Z-axis direction. Further, from one end in the X-axis direction (the right side in FIG. 1A) to the other end side (the left side in FIG. 1A) is assumed to be the substrate transport direction, and one end side in the Y-axis direction (below the lower side in FIG. 1A). Side) is assumed to be the front.

  The lanes 1 and 2 are embodied by the first and second substrate transfer devices 12 and 14. The first and second substrate transfer devices 12 and 14 include a pair of belt conveyors 12a, 14a, 12b, and 14b that are parallel to each other, a non-illustrated transfer motor, a transmission mechanism that transmits the power of the transfer motor, and the like. It has. By driving the conveyors 12a, 14a, 12b, and 14b synchronously, the first and second substrate transport devices 12 and 14 support the printed circuit board P while supporting the sides of the printed circuit board P. Transport in the direction. Further, a substrate stopping device (not shown) temporarily stops the conveyed printed board P in the mounting areas MA and MB shown in FIG. Electronic component mounting work is performed in the mounting areas MA and MB. In order to stop the printed circuit board P transported by the first and second substrate transport devices 12 and 14 in the mounting areas MA and MB, the above-mentioned substrate stop device is provided at a predetermined position inside the conveyors 12a, 14a, 12b and 14b. A stopper (not shown) is provided. This stopper can be displaced between a state of projecting on both conveyors 12a, 14a, 12b and 14b and a state of being immersed below both conveyors 12a, 14a, 12b and 14b. The stopper is driven by a stopper driving unit 16 (see FIG. 2) made of a cylinder or the like. Further, in the mounting areas MA and MB, a board holding device (not shown) including push-up pins for holding the printed board P stopped by the stopper from the first and second board transfer devices 12 and 14 is held. And the stopper and the substrate holding device constitute a substrate positioning device.

  The base 11 is a rectangular structure in plan view. In the central portion of the base 11, mounting areas MA and MB are set for each of the first and second mounting units UA and UB. Mounting areas MA and MB are areas (ranges) in which first and second component mounting heads 30 and 40 described later mount electronic components. In addition, an overlapping area OA that is set symmetrically about the center line along the X-axis direction is set in the central portion in the Y-axis direction where both mounting areas MA and MB are adjacent in the front-rear direction. The overlapping area OA is an area into which both first and second component mounting heads 30 and 40 described later can enter.

  The base 11 is provided with a component supply section (not shown) arranged on both sides of the corresponding first and second substrate transport apparatuses 12 and 14 for each of the first and second mounting units UA and UB. . The component supply unit includes multiple rows of tape feeders. Each tape feeder includes a tape that stores and holds electronic components such as an IC, a transistor, and a capacitor at predetermined intervals, a reel that carries the tape, and a ratchet-type feeding mechanism that feeds the reel. The tape is fed from the reel to the component take-out section. Further, the fed tape component is picked up by a suction operation of first and second component mounting heads 30 and 40 described later. The feeding mechanism intermittently feeds the tape as the electronic component is piped up.

  The base 11 is provided with a pair of structures 20 that face each other along the X-axis direction. The structure 20 is formed in a gate type including leg portions 21 erected at the four corners of the base 11 and beam portions 22 connecting the leg portions 21 along the Y-axis direction. A Y-axis rail 21 a is laid on the upper surface of each beam portion 22. Both Y-axis rails 21a are laid back and forth along the Y-axis direction. Both Y-axis rails 21a guide end portions of a pair of X beams 23 and 24 provided for the first and second mounting units UA and UB, respectively. The X beams 23 and 24 extend along the X-axis direction. One X beam 23 and 24 is provided for each lane 1 and 2. The respective X beams 23 and 24 are connected to the Y-axis rail 21a via sliders 23a and 24a. Further, the slider 23 a of one X beam 23 is provided with a damper 23 b facing the slider 24 a of the other X beam 24. The damper 23b is interposed between the sliders 23a and 24a when the two X beams 23 and 24 come close to each other, and restricts the X beams 23 and 24 from coming into contact with each other.

  The first and second mounting units UA and UB are provided with Y-axis servomotors 25 (see FIG. 2) for driving the corresponding X beams 23 and 24, respectively. One Y-axis servomotor 25 (see FIG. 2) is provided for each beam portion 22. Each Y-axis servomotor 25 (see FIG. 2) can reciprocate the corresponding X beams 23 and 24 back and forth.

  X-axis rails (not shown) are provided on the surfaces where the X beams 23 and 24 oppose each other in the front-rear direction. The first and second component mounting heads 30 and 40 are attached to each X-axis rail for each of the first and second mounting units UA and UB. Each X beam 23, 24 is provided with an X-axis servo motor 26 (see FIG. 2) for driving the corresponding first and second component mounting heads 30, 40 along the X-axis direction.

  In the present embodiment, the servo motors 25 and 26 described above constitute a drive mechanism that drives first and second component mounting heads 30 and 40 described below. By this drive mechanism, the first and second component mounting heads 30 and 40 move on a plane set at a substantially central portion of the base 11 along the X-axis direction and the Y-axis direction, and supply components (not shown). An electronic component can be picked up from the part and mounted on the printed circuit board P in the mounting areas MA and MB.

  The first and second component mounting heads 30 and 40 are provided with one or a plurality of suction nozzles 31 and 41 so as to be movable up and down. As shown in FIG. 2, the first and second component mounting heads 30 and 40 include a Z-axis servomotor 27 that raises and lowers the suction nozzles 31 and 41 and an R-axis servomotor 28 that rotates the suction nozzles 31 and 41. Are equipped. The first and second component mounting heads 30 and 40 pick up electronic components from the component supply unit, and mount the picked-up electronic components on the printed circuit board P in the corresponding mounting areas MA and MB. At this time, the first and second component mounting heads 30 and 40 pick up a plurality of electronic components at a time. The plurality of electronic components picked up are conveyed together and sequentially mounted on the printed circuit board P. This pickup to mounting is called mounting turn. In one mounting turn, a plurality of electronic components are picked up and mounted. In this specification, a processing unit for each electronic component is called a task.

  Next, as a stationary imaging means for imaging a specific part of the printed circuit board P from above when the printed circuit board P stops in the mounting areas MA and MB, a first substrate camera 61 (first camera) and a second substrate are used. A camera 62 (second camera) is suspended from a fixed position of the base 11 for each of the first and second mounting units UA and UB. The first board camera 61 is in a position where the downstream corner portion can be imaged when the printed board P is stopped in the mounting area MA, and the second board camera 62 is when the printed board P is stopped in the mounting area MA. Are arranged at positions where the middle part of the one side can be imaged.

  Each of the first and second mounting units UA and UB is equipped with a component recognition camera 63 on the base 11. The camera 63 images the suction component after component mounting by the first and second component mounting heads 30 and 40. Based on the image captured by the camera 63, the component mounting system 10 can check the shift of the component mounting position.

  Each of the first and second component mounting heads 30 and 40 is equipped with a moving camera 64 that captures fiducial marks (board recognition marks) attached to the printed circuit board P. The moving camera 64 is composed of a CCD or the like arranged downward on the side of the corresponding first and second component mounting heads 30 and 40, and moves together with the first and second component mounting heads 30 and 40. It is supposed to be.

  Similar to the known mounting machine, both the first and second mounting units UA and UB are provided with sensors (indicated generically as SN in FIG. 2) for detecting required parameters of the respective units.

  Next, the control unit 100 that controls both the first and second mounting units UA and UB in an integrated manner will be described.

  Referring to FIG. 2, control unit 100 is constituted by a CPU or the like, and includes an arithmetic processing unit 101 connected to an external display unit 110, and data storage means for storing various data for board transfer, component mounting, and the like. 102, a mounting program storage unit 103 that stores a mounting program, a motor control unit 104 that controls each motor, an external input / output unit 105, a server communication unit 106, and an image processing unit 107.

  The arithmetic processing unit 101 manages arithmetic processing for executing a mounting program necessary for mounting electronic components on the printed circuit board P.

  The data storage means 102 stores data necessary for executing the installed program, a data collection (referred to as a table), and the like.

  The installed program storage unit 103 stores an installed program executed by the arithmetic processing unit 101.

  The motor control unit 104 controls the motors 25 to 28 based on signals from encoders provided in the motors 25 to 28 and a target value given from the arithmetic processing unit 101.

  The external input / output unit 105 is connected to various sensors SN such as sensors for detecting the loading and unloading of the printed circuit board P as input elements, and to the stopper driving unit 16 as an output element. In addition to this, a conveyance drive mechanism, a conveyor interval adjustment drive mechanism, and the like, which are not shown, are also connected to the external input / output unit 105.

  The server communication unit 106 performs communication with a server that controls the plurality of component mounting systems 10, data update, and the like.

  The image processing unit 107 is connected to the first board camera 61, the second board camera 62, the component camera 63, and the moving camera 64, and takes in signals indicating images from these cameras 61 to 64 to obtain a predetermined image. Processing is performed, and the image data is sent to the arithmetic processing unit 101.

  The display unit 110 is provided with a pointing device such as a display and a keyboard, and the operator controls the control unit 100 based on the execution status of the programs of the first and second mounting units UA and UB or displayed information. On the other hand, it has a function that can be operated to input information such as various data and commands.

  Next, the details of the data stored in the data storage unit 102 will be described with reference to FIG.

  Referring to FIG. 3, the data storage unit 102 stores a database 120 as a storage area. The data in the database 120 is used for control of the control unit 100 by a database management system (DBMS).

  The database 120 stores various data. Hereinafter, these data will be described based on ER notation. The database 120 includes a component mounting head table 121 that stores information related to the first and second component mounting heads 30 and 40, a substrate table 122 that stores information related to the printed circuit board P, and the printed circuit board P transported to the lane 1. A lane set table 123 for managing information related to a combination of printed circuit boards P (hereinafter referred to as “lane sets”) conveyed to the lane 2, and a management sequence for each lane set set in the lane set table 123. A sequence set table 124 and a task table 125 for managing information on tasks set for each sequence set are included. The tables 121 to 125 are generally composed of columns called attributes (hereinafter, attributes are indicated by {}) and rows called tuples (hereinafter, tuple values are indicated by ""). Logically configured in a matrix. An attribute refers to an item (for example, {head number} {substrate product number} {overlapping area}, etc.) set in the tables 121 to 125 (see FIGS. 5A and 5B). A tuple refers to a collection of information (instances) for each row. In the figure, (PK) represents a primary key and (FK) represents a foreign key. The primary key is an attribute that uniquely identifies a row in the tables 121 to 125. The foreign key has the same value as the primary key, and is used to refer to data in the table having the primary key. Furthermore, the arrows in the figure indicate the relationship (relationship) between the tables, and indicate that the foreign key in the table on the end point side of the arrow refers to the primary key in the table on the start point side of the arrow. ing.

  The component mounting head table 121 is a table that stores information about the first and second component mounting heads 30 and 40. The component mounting head table 121 includes {head number} that uniquely identifies the first and second component mounting heads 30 and 40 as a main key. In {head number}, the model numbers of the first and second component mounting heads 30 and 40 (for example, “HD001” and “HD002” shown in FIG. 5A) are registered. In the component mounting head table 121, items for storing various parameters necessary for controlling the first and second component mounting heads 30 and 40 are set for each model number.

  The substrate table 122 is a table that stores information related to the printed circuit board P. The substrate table 122 includes {substrate product number} that uniquely identifies the printed circuit board P as a main key. In {substrate product number}, the product number of the printed circuit board P (for example, “BD00123”, “BD00456”, etc. shown in FIGS. 4, 5A and 5B) is registered. In the board table 122, items (in the example shown, {width, length}, etc.) for storing information related to boards necessary for mounting electronic components are set for each product number. In addition, an item {retry type identifier} is set in the substrate table 122. {Retry type identifier} is an item for storing information for identifying the type of the re-mounting method when the mounting process fails. The re-implementation method will be described later.

  Next, the lane set table 123 is a table that stores information on lane sets. As will be described later, in this embodiment, the mounting order is managed in units of tasks. The task is a first unit in which an operation from when the first and second component mounting heads 30 and 40 pick up an electronic component until the electronic component picked up on the printed circuit board P on the corresponding lane is mounted is a unit. The work of the second component mounting heads 30 and 40 is referred to. Tasks in this embodiment are managed by unique numbers across both the first component mounting head 30 and the second component mounting head 40. For this reason, in this embodiment, tasks are managed for each lane set. A lane set table 123 is provided to store information regarding the lane set.

  The lane set table 123 includes {lane 1 head number, lane 2 head number, lane 1 board product number, lane 2 board product number, overlapping area} and the like. In {lane 1 head number}, the head number of the first component mounting head 30 set in lane 1 is stored. In the lane 2 head number, the head number of the second component mounting head 40 set in lane 2 is stored. Further, in the lane 1 substrate product number, the substrate product number of the printed circuit board P transported to the lane 1 is stored. The lane 2 substrate product number stores the substrate product number of the printed circuit board P transported to the lane 2. As is clear from this table configuration, in this embodiment, various lane sets can be registered in the lane set table 123, and control parameters can be set for each lane set.

  FIG. 4 shows an example of a lane set. The printed circuit board P having the board part number “BD00123” is set in the lane 1 of FIG. 5, and the printed board P having the board part number “BD00456” is set in the lane 2 in the lane 2. The task is described as a unit from the path from the white circle described on the outside of the printed circuit board P to the first black circle, or the path from the black circle described outside the printed circuit board P to the next black circle. The white circles indicate the timing for each task when determining the driving situation (timing when determining step S41 in FIG. 7 described later). In the illustrated example, four tasks are set for each printed circuit board P. Of course, this is a simplified numerical value for convenience of explanation, and in practice, a task having a number of two or more digits is set. In lane 1, the first component mounting head 30 with the head number “HD001” is set. In the lane 2, the second component mounting head 40 with the head number “HD002” is set. In this way, it is possible to identify the first and second component mounting heads 30 and 40 for each lane set determined by {lane 1 substrate product number, lane 2 substrate product number}.

  Next, {overlapping area} of the lane set table 123 is an item for storing an overlapping area OA into which both the first and second component mounting heads 30 and 40 can enter. Although it is simplified in the figure, in practice, a plurality of items can be set so that the start point coordinates (X, Y) and end point coordinates (X, Y) of the overlap area A can be registered in two-dimensional coordinates. It has become. The same applies to {interference area} described later.

  As shown in FIG. 1A, an overlapping area OA is set in the mounting areas MA and MB in which the first and second component mounting heads 30 and 40 can move. In this overlapping area OA, it is necessary to avoid the collision between the first and second component mounting heads 30 and 40. On the other hand, the necessity for the first and second component mounting heads 30 and 40 to move to the overlapping area OA differs depending on the type of the printed circuit board P on which the electronic components are mounted. Therefore, in the lane set table 123 according to the present embodiment, information on the printed circuit board P on which electronic components are mounted in the lane 1 and information on the printed circuit board P on which electronic components are mounted on the lane 2 are respectively transmitted from the substrate table 122. The mounting sequence can be set according to the combination of both printed circuit boards P, that is, the lane set. By providing this {overlapping area} in the lane set table 123, the range of the overlapping area OA can be individually set according to the lane set. As a method of setting a value stored in {overlapping area}, a predetermined default value is determined as a range of overlapping area OA, and a common default value is set to {overlapping area} for all combinations of printed circuit boards P. You may make it preserve | save.

  Next, the sequence set table 124 is a table for storing a sequence number set for each lane set and a set number set for the sequence number. Here, the sequence number is a processing order determined with one mounting turn as one unit. Normally, a plurality of sequence numbers are set for each lane set. The sequence number is set to a value obtained by numbering the order of the entire mounting turn in order from the first using the printed circuit board P in lane 1 and the printed circuit board P in lane 2 as one printed circuit board.

  Referring to FIG. 4, the sequence numbers are set sequentially from No. 1 to No. 8, as indicated by circled numbers. In the example shown in FIG. 4, even-numbered sequence numbers are assigned to tasks executed by the first component mounting head 30. An odd sequence number is assigned to the task executed by the second component mounting head 40. In the present embodiment, {current lane 1 board product number, current lane 2 board product number, current sequence number} is set as the primary key of the sequence set table 124. All of the sequence number values set for each lane set are stored in {current sequence number} which is a part of the primary key.

  Next, the set number refers to a sequence number associated with the sequence number. The set number indicates that when the task related to the sequence number of the related destination is executed by either one of the first component mounting head 30 and the second component mounting head 40, the other component mounting head is one in the overlap area OA. The sequence number is set to a task that can be executed in parallel without interfering with the component mounting head. In order to set a set number for each sequence number, the sequence set table 124 includes {next lane 1 board product number, next lane 2 board product number, next sequence number, interference area}. The sequence number stored in {next sequence number} is associated with the sequence number stored in {current sequence number} in a one-to-one relationship. The sequence number set in this {next sequence number} is an example of the set number in this embodiment.

  Referring to FIG. 5A, in the illustrated example, lane 1 has a sequence number set in {current sequence number} as a task executed by second component mounting head 40 in lane 2. The second sequence number executed by the first component mounting head 30 is stored in {next sequence number} and associated therewith. This means that when the task related to the first sequence number is being executed by the second component mounting head 40 in lane 2, the task related to the second sequence number is executed by the first component mounting head 30 in lane 1 Even in this case, both component mounting heads 30 and 40 can execute tasks in parallel without interference in the overlapping area OA. Therefore, in the illustrated example, it is set that the task related to the second sequence number may be executed in parallel while the task related to the first sequence number is being executed. Similarly, for the sequence numbers 2, 3, 4, 5, 6, 6, 7, and 8 stored in {current sequence number}, 3, 4, 5, respectively. , 6th, 7th, 8th, 1st sequence numbers are stored in {next sequence number}. The sequence numbers stored in these {next sequence numbers} function as set numbers of the sequence numbers stored in the corresponding {current sequence number}. Note that {current lane 1 board product number, current lane 2 board product number, current sequence number} is a primary key, and {current sequence number} is not Null. On the other hand, {next lane 1 board product number, next lane 2 board product number, next sequence number} is an external key for storing the set number, and may be null (see FIG. 12). Further, as is apparent from the structure of the sequence set table 124, in the illustrated embodiment, only one set number is set for one sequence number.

  Next, referring to FIG. 4, {interference area} includes the first component mounting head 30 and the second component when the mounting turn related to the current sequence number is parallel to the mounting turn related to the next sequence number. This is an item for storing the interference area A where the mounting head 40 interferes. The interference area A is determined based on the overlapping area approach length described later. The value of {interference area} is recalculated and updated every time one component mounting head 30 (or 40) finishes one task so that the interference area A becomes narrower. Also good. In the present embodiment, the current sequence number and the next sequence number are determined so that the interference area A is as short as possible. As a result, an area in which the first component mounting head 30 and the second component mounting head 40 can operate in parallel increases, so that it is less necessary to wait to relatively avoid interference. In addition, when the first component mounting head 30 and the second component mounting head 40 are operated in parallel, even if it is necessary to stand by to avoid interference, the preceding component mounting head 40 ( Since 30) stays in the interference area A is relatively short, the waiting time can be shortened.

  Next, the task table 125 uses {task number} as a primary key together with {current lane 1 board part number, current lane 2 board part number, current sequence number} referring to the sequence numbers stored in the sequence set table 124. . The task table 125 includes {part number, overlap area entry length}. By providing the task table 125, as shown in FIG. 5B, it is possible to set the interference area entry length for each task included in the sequence number.

  {Task number} is an item for storing a number indicating the processing order of electronic components (that is, tasks) processed in the mounting turn related to the sequence number. In the illustrated embodiment, the part number of the electronic component mounted for each {task number} is stored in {part part number}.

  Next, {overlapping area entry length} is an item for storing the length (distance) at which the component mounting head 30 (40) executing the task related to the sequence number enters the overlapping area OA for each sequence number. It is. By providing this {overlapping area entry length} for each task, the control unit 100 operates the other component mounting head 30 (40) while the one component mounting head 40 (30) is operating. It becomes possible to determine for each task whether or not the interference between the component mounting heads 30 and 40 occurs in the overlapping area OA.

  Each of the above-described tables 121 to 125 shows a logical structure. Physically, a plurality of tables may be mounted on the same data file, or a plurality of one data table may be provided. It may be implemented in the data file. In addition to the tables 121 to 125 shown in FIG. 3, the data storage means 102 is provided with a table for managing transactions. In the transaction table, the processing results are stored for each task. Therefore, the control unit 100 can determine whether or not a task has been processed on a certain printed circuit board P by referring to the transaction table. In the following description, a sequence number related to an unprocessed task is also referred to as an “unimplemented sequence number”.

  Next, a processing method for determining values stored in the above-described lane set table 123 and sequence set table 124 will be described.

  Referring to FIG. 6, in the present embodiment, the entire printed circuit board P carried into lanes 1 and 2 is regarded as one printed circuit board, and the arrangement of components is determined for each combination of printed circuit boards P. (Step S1). Next, according to the specifications of the first and second component mounting heads 30 and 40 for mounting electronic components on the printed circuit board P, the heads are grouped for each task, and a mounting sequence is determined for each grouped task ( Step S2). Next, an operation time calculation (simulation) is executed based on the mounting sequence determined in step S2 (step S3). In this simulation, the next sequence number is the other component when the task related to the current sequence number is executed by one of the component mounting head 40 (30) and the other component mounting head 40 (30). The mounting head 30 (40) is set to have a sequence number related to a task that can be executed in parallel. Here, “parallel” means that the component mounting heads 30 and 40 are required to execute the mounting turn at the same time. When one task is executed in the process of executing each mounting turn, the other task is It does not exclude waiting. Needless to say, it is ideal that all tasks can be executed simultaneously. In the simulation in step S3, the current sequence number and the next sequence number are determined so that the interference area A is as short as possible based on the overlapping area approach length for each task. As a result, all tasks can be executed in parallel as much as possible, and the need to wait to avoid interference is reduced. Also, even if it is necessary to wait to avoid interference, the time for the preceding component mounting head 40 (30) to stay in the interference area A is relatively short. The waiting time can be shortened. Thereafter, the simulation result is verified to determine whether or not there is room for improvement (step S4). If there is room for improvement, the process returns to step S1 and the above-described processing is repeated. At this stage, when a mounting sequence that is considered to have no room for improvement is determined, a sequence number is set for each task, and the set values are stored in the sequence set table 124 {lane 1 board product number, lane 2 board product number. , The current sequence number} is stored (step S5). Next, a set number is set for each sequence number, and values relating to the set number are stored in {lane 1 board product number, lane 2 board product number, next sequence number} of the sequence set table 124 (step S6). The above setting processes S1 to S6 are performed manually by the operator, but a method of automatically calculating a predetermined argument as a parameter may be employed.

  Next, a specific example in the case where component mounting is performed in the present embodiment will be described with reference to FIGS. In the following description, based on the control shown in FIG. 7 and FIG. 8, the first component mounting head 30 is also referred to as its own device, and the second component mounting head 40 is also referred to as the counterpart. The relationship between the own machine and the other party is exactly the same when the first component mounting head 30 is the other party and the second component mounting head 40 is the own machine.

  First, referring to FIGS. 1, 3, and 7, the control unit 100, when the printed circuit board P is carried into the mounting area MA or MB of any mounting unit UA or UB, the sequence set table 124, etc. It is determined whether or not there is a component that needs to be mounted on the printed circuit board P (step S40). Here, if the mounting of all the electronic components has been completed, the mounting program shown in FIG. 7 is ended, and the unloading operation of the printed circuit board P is started.

  On the other hand, if there is an electronic component to be mounted on the printed circuit board P (or remains) in step S40, the control unit 100 determines, for example, the mounting sequence of the own device (first component mounting head 30). At this time, it is determined whether or not the other party (second component mounting head 40) is in operation (step S41).

  If it is determined in step S41 that the counterpart (second component mounting head 40) is in operation (YES in step S41), the control unit 100 performs a sequence related to the task of the counterpart (second component mounting head 40). The number is acquired as the current sequence number (step S42). Next, the control unit 100 searches the sequence set table 124 for the set number of the acquired current sequence number (that is, the value set in {next sequence number}) (step S43). Then, it is determined whether or not a set number has been searched (step S44). In this determination, when the set number is searched, the control unit 100 determines whether or not the own machine (first component mounting head 30) is executing a task corresponding to the set number (step S45).

  If the task corresponding to the set number has not been executed, the control unit 100 shifts to an operation for executing the task related to the set number (sequence number set in {next sequence number}), that is, implementation processing. (Step S50).

  Specifically, as shown in FIG. 8, the control unit 100 causes the own device (component mounting head 30) to execute component suction processing (step S501). Next, the control unit 100 recognizes the suction position of the component with the camera 63 for component recognition (step S502), and provides the recognition result to the process of correcting the misalignment at the time of mounting. Thereafter, the control unit 100 acquires the number Nc of electronic component mountings related to the sequence number (step S503). Next, the control unit 100 initializes the counter variable n to 1 (step S504). Furthermore, the control unit 100 reads the overlapping area approaching depth of the nth task number from {overlapping area approaching length} of the task table 125 (step S505). Thereafter, the control unit 100 determines whether or not interference occurs when executing the task (step S506). Various determination methods can be considered. For example, the value of the interference area A related to the current sequence number is read from {interference area} of the sequence set table 124, and based on the {overlapping area entry length} of the task table 125, the corresponding component mounting head 30 (40) This can be realized by determining whether or not to enter the interference area.

  If interference occurs, the task waits for the other component mounting head 40 (30) to finish the current task (steps S507 and S508). As described above, in the present embodiment, the current sequence number and the next sequence number are determined so that the interference area A is as short as possible based on the overlapping area approach length for each task. Therefore, the need to wait to avoid interference is very low. Further, even when it is necessary to wait to avoid interference, the waiting time for the preceding component mounting head 40 (30) to stay in the interference area A is relatively short. Is extremely short.

  When the counterpart component mounting head 40 (30) completes the current task (YES in step S508), or when it is determined in step S506 that no interference occurs, the control unit 100 determines that the own unit (component Thereafter, the mounting head 30) shifts to a component mounting process (step S509).

  Next, the control unit 100 increments the counter variable n (step S510). Thereafter, the control unit 100 compares the counter variable n with the number of mounting times Nc, and determines whether or not the electronic component having the task number related to the incremented counter variable n remains (step S511). If an electronic component related to an unprocessed task number remains (Nc ≧ n), the control unit 100 moves to step S505 and repeats the above-described processing. When there is no unprocessed electronic component (when Nc <n), the control unit 100 returns to the main routine.

  Referring to FIG. 7, after executing the mounting process subroutine of step S50, control unit 100 determines whether the mounting process is good, that is, whether re-mounting is necessary (step S60). If the mounting process is good, that is, if it is determined that re-mounting is unnecessary, the process proceeds to step S40 and the above-described process is repeated. On the other hand, when the mounting process is inappropriate, the control unit 100 executes the remounting process (step S70). As will be described in detail later, there are two types of re-mounting processing: a sequential processing type (see FIG. 13) and a batch processing type (see FIG. 14). In this embodiment, the sequential processing type and the batch processing type are identified based on the set value of {retry type identifier} of the substrate table 122. Based on the set value of {retry type identifier} in the board table 122, the control unit 100 executes the remounting process with a processing type preset for each board.

  When the remounting process in step S70 is completed, the control unit 100 proceeds to step S40 and repeats the above-described process.

  Further, if the counterpart (second component mounting head 40) is not operating in the determination in step S41 (NO in step S41), the set number is not set in the determination in step S44 ( In the case of NO in step S44), or in the determination in step S45, if the task related to the searched set number has been executed, the control unit 100 has not executed the own unit (component mounting head 30). Among the sequence numbers related to the task (“unmounted sequence number”), the sequence number with the smallest number is selected as a candidate unmounted sequence number (step S46). Next, the control unit 100 executes the above-described mounting process subroutine S50 of FIG. 8 based on the selected unmounted sequence number. Thereby, when there is an unimplemented sequence number, for example, it is determined whether or not parallel processing is possible in ascending order (the processing in step S46 may be in descending order). Regardless of the setting, it is possible to achieve parallel processing and improve the overall tact time.

  FIG. 9 shows execution processing when parallel processing based on the flowcharts of FIGS. 7 and 8 is executed in the lane set shown in FIGS. 4 and 5A and 5B. As shown in the figure, the task related to the first sequence number is first executed in lane 2. In parallel with this task, the task related to the second sequence number, which is the set number of the sequence number of Lane 2, is executed on Lane 1. Then, in order, in lane 2, tasks related to sequence numbers of sequence numbers 3, 5, and 7 are sequentially executed. In parallel with these tasks, in Lane 1, the tasks associated with sequence numbers 4, 6, and 8 are sequentially executed.

  By the way, the number of tasks required for the printed circuit board P in lane 1 is not necessarily the same as the number of tasks required for the printed circuit board P in lane 2.

  Referring to FIG. 10, in the illustrated example, the number of tasks in lane 1 is four, whereas the number of tasks in lane 2 is six. Therefore, as shown in FIG. 11, for the sequence numbers 9 and 11, the next sequence number as the set number is a missing number (Null). When the flowcharts of FIGS. 7 and 8 are executed in the mode as shown in FIG. 10, after the task related to the sequence number 8 of the first printed circuit board P is executed in the lane 1 as shown in FIG. In the next printed circuit board P, the task related to the second sequence number is executed. At this time, even in the case where the task related to the sequence number 9 of the first printed circuit board P is still being executed in lane 2, the first printed circuit board P is completed in lane 1 Instead of waiting, a task related to a sequence number that can be processed in parallel is selected based on the processing in step S46 in FIG. 7, and parallel processing is executed as much as possible. For example, in the example of FIG. 12, the task related to the second sequence number of the second printed circuit board P is executed in parallel with the task related to the ninth sequence number. Similarly, in parallel with the task related to the 11th sequence number, the task related to the 4th sequence number of the second printed circuit board P is executed in parallel. On the other hand, when the processing of the first printed circuit board P is completed in lane 2 and the processing of the second printed circuit board P is started, a sequence number of a suitable combination for the mounting processing in lane 1 Is selected. That is, in the example of FIG. 12, since the task related to the fourth sequence number is executed, the sequence number of the task to be executed first is not first but fifth. Even in the selection of the sequence number below, if there is a set number related to the unimplemented sequence number, the task of the sequence number related to the set number is executed, and if there is no set number related to the unimplemented sequence number, A task related to a sequence number that can be combined is executed. As described above, in this embodiment, as shown in FIG. 12, the component mounting work for lane 1 and lane 2 can be processed in parallel while avoiding interference for each task.

  Furthermore, as a practical problem, there is a problem when re-mounting processing (step S60 in FIG. 7) occurs. As already mentioned, there are two types of re-implementation processing: a sequential processing type and a batch processing type.

  Referring to FIG. 13, the sequential processing type is a method in which when a mounting failure occurs, re-mounting is executed immediately after the task where the mounting failure has occurred.

  Referring to FIG. 14, the batch processing type is a method in which when a mounting failure occurs, after all tasks are completed, electronic components related to the mounting failure are collectively mounted.

  In the sequential processing type of FIG. 13, it is more reasonable to maintain the relationship between the sequence number and the set number by maintaining the mounting sequence of lane 1 and lane 2 after waiting for re-mounting, and to improve efficiency. Therefore, in the illustrated embodiment, when step S42 of FIG. 7 is executed, in the sequential processing type, even if the other party (second component mounting head 40) is executing remounting, the remounting is performed. The current sequence number is acquired assuming that the task is being executed. That is, in the case of the example shown in FIG. 13, the counterpart (second component mounting head 40) performs remounting in the task related to the first sequence number. Accordingly, in this case, it is assumed that the task related to the first sequence number is executed, the second sequence number that is the first set number is selected as the set number, and the above-described processing is executed. As a result, as shown in FIG. 13, even if a retry occurs, parallel processing is executed while the relationship between the sequence number and the set number is generally maintained.

  On the other hand, in the case of the batch processing type of FIG. 14, since the possibility that the time until the end will increase when re-mounting is started increases, in that case, it is often more reasonable to cancel the pair. . Therefore, in the present embodiment, when executing step S42 of FIG. 7, in the batch processing type, if the counterpart (second component mounting head 40) is executing remounting, Null is returned. As a result, since the set number is not specified in the set number search in step S43, step S70 and subsequent steps are executed in the determination in step S44. Therefore, when the counterpart (second component mounting head 40) is executing remounting, the smallest number is selected from among the unmounted sequence numbers in the own device (first component mounting head 30) in step S70. The As a result, as shown in FIG. 14, when a retry occurs, the relationship between the sequence number and the set number is canceled, and parallel processing is executed within a range where interference does not occur.

  As described above, in the present embodiment, the first component mounting head 30 mounts the electronic component picked up by the component suction operation on the printed board P transported to the first mounting area MA. The second component mounting head 40 mounts an electronic component picked up by a component suction operation on the printed circuit board P transported to the second mounting area MB. The mounting operation of the first component mounting head 30 and the second component mounting head 40 is controlled by the control unit 100. The control unit 100 controls the mounting operation based on the information on the mounting turn stored in the data storage unit 102 and the information on the task with the processing operation for each electronic component mounted in each mounting turn as a unit. . The information regarding the mounting turn and the information regarding the task with the processing operation for each electronic component mounted in each mounting turn as a unit include the mounting turn set for each of the first component mounting head 30 and the second component mounting head 40. And a set number associated with the sequence number. The set number is a sequence number related to a task that can be executed in parallel with the task when the task related to a certain sequence number is being executed. Accordingly, when there is a task that can be executed by the second component mounting head 40 in parallel with the first component mounting head 30 when the first component mounting head 30 is executing a task related to a certain sequence number. The control unit 100 can refer to the sequence number related to the task as the set number. When there is a set number, the second component mounting head 40 executes a task related to the set number associated with the sequence number related to the task of the first component mounting head 30. As a result, the second component mounting head 40 can execute the component mounting operation in parallel with the first component mounting head 30 without interfering with the first component mounting head 30. Similarly, there is a task that can be executed by the first component mounting head 30 in parallel with the second component mounting head 40 when the second component mounting head 40 is executing a task related to a certain sequence number. When this is the case, the control unit 100 can refer to the sequence number related to the task as the set number. When there is a set number, the first component mounting head 30 executes a task related to the set number associated with the sequence number related to the task of the second component mounting head 40. As a result, the first component mounting head 30 can execute the component mounting operation in parallel with the second component mounting head 40 without interfering with the second component mounting head 40.

  In the mounting system according to the present embodiment, the first mounting area MA and the second mounting area MB partially overlap so that both the first component mounting head 30 and the second component mounting head 40 can enter. The overlap area OA is included. The set number is a sequence number that includes a task in which the component mounting head 30 (40) on the other side is closest to the overlap area OA side with respect to the component mounting head 40 (30) that executes the sequence number associated with the set number. Is set to For this reason, in this embodiment, the interference area A which is a range in which the first and second component mounting heads 30 and 40 operating in parallel can interfere with each other in the overlapping area can be set as narrow as possible. In other words, the area in which the first and second component mounting heads 30 and 40 can operate without interference becomes as wide as possible. Therefore, in order to avoid interference, the necessity of waiting for one component mounting head 30 (40) can be reduced as much as possible. Further, even when it is necessary to wait, the waiting time is shortened because the preceding component mounting head 40 (30) stays in the interference area A relatively.

  In the present embodiment, as shown in FIG. 8, the control unit 100 causes interference in the overlap area OA when the first component mounting head 30 and the second component mounting head 40 are operated in parallel for each task. It is determined whether or not there occurs, and interference between both component mounting heads 30 and 40 in the overlapping area OA is avoided based on this determination. For this reason, in this embodiment, it is possible to realize parallel work of the first component mounting head 30 and the second component mounting head 40 while avoiding interference in the overlapping area OA.

  In the present embodiment, the data storage unit 102 stores, for each task related to the sequence number, the overlapping area entry length that the component mounting head 40 (30) executing the task enters toward the overlapping area OA. As a storage area, the task table 125 is included, and the control unit 100 executes determination regarding interference based on the value stored in the {overlap area entry length} of the task table 125. For this reason, in this embodiment, the control unit 100 can avoid interference while referring to the overlap area entry length for each task. Therefore, by verifying the degree of entry into the overlapping area OA for each task, it is possible to set the interference waiting time to be short, or to set the area (or distance) in which the interference occurs to be short. It becomes.

  Further, in the present embodiment, when the control unit 100 cannot refer to the set number, the control unit 100 selects a sequence number that is a candidate for parallel operation in a preset order and relates to the selected sequence number. For each task, when the first component mounting head 30 and the second component mounting head 40 are operated in parallel, it is determined whether or not interference occurs in the overlapping area OA, and interference in the overlapping area OA does not occur. If it is determined, the task is executed. For this reason, in the present embodiment, for a task that is not mounted, for example, parallel operation can be dynamically assigned in ascending order of sequence numbers, and parallel operation can be executed while avoiding interference in the overlapping area OA. Therefore, even when the set number is not set or when re-mounting is executed, parallel operation can be realized as much as possible.

  Further, in the present embodiment, as for the set number, the task related to the related sequence number is executed by one of the first component mounting head 30 and the second component mounting head 40 (for example, the second component mounting head 40). The component mounting head 40 (30) is set to a sequence number that includes a task that can be executed in parallel without the other component mounting head 30 (40) interfering in the overlapping area OA. . For this reason, in the present embodiment, the set number is associated with the sequence number in a combination that can reliably avoid interference in the overlapping area OA. Therefore, the parallel operation of the first and second component mounting heads can be realized based on the set number. The “sequence number including a task that can be executed in parallel without the other component mounting head interfering in the overlapping area” is a component mounting head that follows the preceding component mounting head 40 (30). The task that can avoid interference when 30 (40) operates in parallel includes not only a part of the tasks but also all of them.

  In the mounting system according to the present embodiment, when the number of tasks processed in lane 1 is different from the number of tasks processed in lane 2, the set number is the mounting processing in the lane with the smaller number of processing. It is set for the amount of time that ends. For this reason, in the present embodiment, even if the number of times the task is processed is different between the printed circuit board P in lane 1 and the printed circuit board P in lane 2, tasks that can be operated in parallel are used in the portion where the number of processed processes is common. Therefore, it is possible to realize a suitable parallel operation for all the mounting sequences.

  In the mounting system according to the present embodiment, the control unit 100 causes the mounting failure in a task executed by any one of the first component mounting head 30 and the second component mounting head 40 (30). In the case where the re-mounting of the electronic component related to the mounting failure is executed immediately after the end of the task, the next component mounting head 30 (40) is assigned to the other component mounting head 30 (40). When a task is executed, the task is associated with the sequence number of the task related to the electronic component that is mounted again by any one of the first component mounting head 30 and the second component mounting head 40 (30). Based on the set number, the mounting sequence of the other component mounting head 30 (40) is controlled. For this reason, in the present embodiment, when a mounting failure occurs in the task executed by the first component mounting head 30, the first component mounting head 30 executes remounting of the electronic component related to the mounting failure immediately after the task is finished. To do. The same applies when a mounting failure occurs in the task executed by the second component mounting head 40. When the first component mounting head 30 performs remounting, when the second component mounting head 40 performs a parallel operation, based on the set number associated with the sequence number related to the task in which remounting has occurred, The task of the second component mounting head 40 is determined. When the second component mounting head 40 performs remounting, when the first component mounting head 30 performs a parallel operation, based on the set number associated with the sequence number related to the task in which remounting has occurred, The task of the first component mounting head 30 is determined. Accordingly, it is possible to maintain the order of the sequence numbers respectively associated with one component mounting head 40 (30) and the other component mounting head 30 (40). As a result, the mounting sequence after the reworking operation of one component mounting head 40 (30) is completed is maintained in the optimal order stored in the data storage unit 102 in advance. Therefore, even if the redo work is occurring, it is possible to avoid the total tact time from being prolonged.

  In the mounting system according to the present embodiment, the control unit 100 causes a mounting failure in a task executed by any one of the first component mounting head 30 and the second component mounting head 40 (30). All the tasks that occur and the remounting of the electronic component related to the mounting failure is assigned to one of the first component mounting head 30 and the second component mounting head 40 (30). When the other component mounting head 30 (40) executes the next task assigned to the other component mounting head 30 (40) in the case where the processing is executed in a lump after the end of the process, the data storage means 102 The mounting sequence of the other component mounting head 30 (40) is determined regardless of the set number set in (1). For this reason, in this embodiment, so-called collective retry (when a mounting failure occurs, re-mounting of electronic components related to the mounting failure is performed collectively at the end) is executed. Therefore, if a mounting failure occurs in the task executed by the first component mounting head 30, the first component mounting head 30 will not be able to perform the electronic operation related to the mounting failure after all tasks related to the printed circuit board P being mounted are completed. Perform component re-mounting. The same applies when a mounting failure occurs in the task executed by the second component mounting head 40. For this reason, when re-mounting occurs in one of the first and second mounting areas MA and MB, in order to maintain the mounting sequence in the other mounting area, the waiting time in the other mounting area becomes long. there is a possibility. Therefore, in this aspect, in the operation state where collective retry is being executed, the mounting sequence of the other component mounting head 30 (40) is determined regardless of the set number.

  As described above, according to the present embodiment, the dual lane method (lanes 1 and 2 are adjacent in parallel, and each of the first and second mounting areas MA and MB respectively set in both lanes 1 and 2 is used. In the equipment in which the first and second component mounting heads 40 are provided and the overlapping portions of the mounting areas MA and MB are the overlapping areas OA of the first and second component mounting heads 40, interference between the component mounting heads 30 and 40 occurs. In this way, it is possible to provide an electronic component mounting system that can improve the overall tact time while preventing the problem.

  The present invention is not limited to the embodiment described above.

  For example, the relationship between the sequence number and the set number is not limited to one-to-one, and may be a one-to-many relationship in which a plurality of set numbers are set for one sequence number.

  Referring to FIG. 15, in the sequence set table 124 shown in FIG. 15, items related to the next sequence number {next lane 1 board product number, next lane 2 board product number, next sequence number} are set to one set number in addition to the main key. A one-to-many relationship is established in which a plurality of sequence numbers are set. Further, in order to determine the rank of a plurality of set numbers (that is, the next sequence number), {set number serial number} is included in the item.

  When the table structure of FIG. 15 is adopted, as shown in FIGS. 16 and 17, for example, when the current sequence number is 2, the first sequence number is 3 according to {set number serial number} at first. The sequence number is set as the set number. On the other hand, if the task related to the third sequence number has already been executed, the eleventh sequence number can be selected as the next sequence number. Similarly, when the current sequence number is the first 8th, since the task related to the 9th sequence number still remains in lane 2, the 9th sequence number is the next according to {set number serial number}. Selected as a sequence number (set number). On the other hand, when the current sequence number is number 8 for the second time, all tasks have been completed in lane 2, so this time, the first sequence number is changed to the next sequence number (in accordance with {set number serial number}). Set number) can be selected.

  As described above, when the table structure of FIG. 15 is adopted, even when the printed circuit boards P having different task processing times are combined (for example, in the case of the example shown in FIG. 10), the set numbers are set for all sequence numbers. Can be set. Therefore, the hit rate in step S43 in FIG. 7 increases. Accordingly, the frequency at which step S46 is executed by step S44 is reduced. Therefore, the calculation speed can be increased.

  Further, in the flowchart of FIG. 7, when step S46 is executed, an unimplemented sequence number may be selected in order from the task that the aircraft enters most toward the overlap area OA, not based on the sequence number. Good. In that case, since the processing proceeds in order from the task that is difficult to perform parallel processing, the probability that the parallel work can be performed as the mounting work proceeds can be increased.

  In addition, it goes without saying that various modifications can be made without departing from the scope of the present invention.

1 lane (example of 1st lane)
2 lanes (example of 2nd lane)
DESCRIPTION OF SYMBOLS 10 Component mounting system 12 Board | substrate conveyance apparatus 30 1st component mounting head 40 2nd component mounting head 100 Control unit 102 Data storage means 103 Mounting program storage means 121 Component mounting head table 122 Board table 123 Lane set table 124 Sequence set table A Interference Area OA Overlap area MA 1st mounting area MB 2nd mounting area P Printed circuit board

Claims (9)

A first lane and a second lane installed in parallel and adjacent to each other to form a pair, each of which individually transports a substrate;
A first mounting area that is provided in the first lane and stops the board conveyed to the first lane to mount an electronic component;
A second mounting area provided in the second lane for stopping the board conveyed to the second lane and mounting an electronic component;
A first component mounting head for mounting an electronic component picked up by a component suction operation on a substrate provided in the first lane and stopped in the first mounting area;
A second component mounting head for mounting an electronic component picked up by a component suction operation on a substrate provided in the second lane and stopped in the second mounting area;
The operation from when one of the first component mounting head and the second component mounting head picks up the electronic component until the electronic component picked up on the substrate in the corresponding lane is mounted as one unit. A storage unit that stores information related to the mounting turn and information related to a task with a processing operation for each electronic component mounted in each mounting turn as a unit for each of the first component mounting head and the second component mounting head. When,
Based on the information stored in the storage unit, the order of a plurality of tasks assigned to the first component mounting head and the order of a plurality of tasks assigned to the second component mounting head are controlled as mounting sequences, respectively. And control means for
The information regarding the mounting turn includes a sequence number indicating the order of mounting turns set for each of the first component mounting head and the second component mounting head, and a set number associated with the sequence number. When the task related to the sequence number of the related destination is being executed by either one of the first component mounting head or the second component mounting head, the other component mounting head is related to a task that can be executed in parallel The sequence number,
The storage unit stores sequence numbers related to all tasks of the first component mounting head and the second component mounting head, and stores the set numbers for at least some of the sequence numbers.
The control means is configured such that when one of the first component mounting head and the second component mounting head is in operation, the other component mounting head starts operating. In the case where there is a set number associated with a sequence number related to a task being executed, the mounting sequence of the other component mounting head is determined based on the set number. Component mounting system. The electronic component mounting system according to claim 1,
The first mounting area and the second mounting area include an overlapping area that partially overlaps so that both the first component mounting head and the second component mounting head can enter,
The set number is set to a sequence number that includes a task in which the other component mounting head can be closest to the overlapping area side with respect to the component mounting head that executes the sequence number associated with the set number. Electronic component mounting system. The electronic component mounting system according to claim 2,
The control means determines, for each task, whether or not interference occurs in the overlap area when the first component mounting head and the second component mounting head are operated in parallel. An electronic component mounting system characterized by avoiding interference between both component mounting heads in the overlapping area. The electronic component mounting system according to claim 2 or 3,
The storage unit includes, for each task related to the sequence number, a storage area that stores an overlap area entry length in which a component mounting head that executes the task enters toward the overlap area,
The electronic component mounting system, wherein the control means performs the determination based on the overlapping area approach length. The electronic component mounting system according to claim 4,
When the control unit cannot refer to the set number, the control unit selects a sequence number that is a candidate for parallel operation in a preset order, and for each task related to the selected sequence number, When the component mounting head and the second component mounting head are operated in parallel, it is determined whether or not interference occurs in the overlapping area, and when it is determined that interference in the overlapping area does not occur, An electronic component mounting system characterized by that the task is executed. In the electronic component mounting system according to any one of claims 2 to 5,
The set number indicates that when a task related to a related sequence number is executed by one of the first component mounting head and the second component mounting head, the other component mounting is performed on the component mounting head. An electronic component mounting system, wherein the head is set to a sequence number including tasks that can be executed in parallel without interfering with each other in the overlapping area. In the electronic component mounting system according to any one of claims 1 to 6,
When the number of times the task is processed in the first lane is different from the number of times the task is processed in the second lane, the set number is the same as the amount of the mounting process in the lane with the smaller number of processes. An electronic component mounting system characterized by being set. In the electronic component mounting system according to any one of claims 1 to 7,
The control means causes a mounting failure to occur in a task executed by one of the first component mounting head and the second component mounting head, and completes re-mounting of the electronic component related to the mounting failure. When the other component mounting head executes the next task assigned to the other component mounting head in the case of executing immediately after that, the task related to the electronic component remounted by the one component mounting head is executed. An electronic component mounting system that controls a mounting sequence of the other component mounting head based on a set number associated with a sequence number. In the electronic component mounting system according to any one of claims 1 to 8,
The control means has a mounting failure in a task executed by one of the first component mounting head and the second component mounting head, and the electronic component relating to the mounting failure is remounted. When the other component mounting head executes the next task assigned to the other component mounting head when all tasks assigned to that component mounting head are executed at the same time. An electronic component mounting system characterized by determining a mounting sequence of the other component mounting head regardless of the set number set in the storage unit.

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